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Interrupts: Temas Selectos de Electrónica

Interrupts are events that stop the CPU's current task to process an external event outside of the normal instruction flow. There are two types of interrupts - maskable hardware interrupts and non-maskable software interrupts. The CPU handles interrupts by finishing its current instruction, acknowledging the interrupt source, saving context, executing the interrupt service routine, retrieving context and enabling interrupts again before continuing. Interrupt priority is determined either by a daisy chain or parallel priority decoder that provides the highest priority interrupt vector to the CPU.

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33 views10 pages

Interrupts: Temas Selectos de Electrónica

Interrupts are events that stop the CPU's current task to process an external event outside of the normal instruction flow. There are two types of interrupts - maskable hardware interrupts and non-maskable software interrupts. The CPU handles interrupts by finishing its current instruction, acknowledging the interrupt source, saving context, executing the interrupt service routine, retrieving context and enabling interrupts again before continuing. Interrupt priority is determined either by a daisy chain or parallel priority decoder that provides the highest priority interrupt vector to the CPU.

Uploaded by

Lilly Castillo
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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Interrupts

Temas Selectos de Electrnica

Definition
Exceptions that will stop CPU's current task in order to attend the interrupting event. Exceptions are events that require processing outside the normal flow of instruction execution.

Interrupt Types
Maskable(I, X*):
HW interrupts

Non-Maskable:
SW interrupts

Security Exceptions:
Reset Watchdog Illegal OPcode Each exception has an associated 16-bit vector, which points to the memory location where the routine that handles the exception is located.

CPU Interrupt Recognition Steps


IRQ request Finish current instruction (latency may vary due to CISC architecture) Acknowledge interrupt source Disable global Interrupts Save context Execute ISR (Interrupt Service Routine) Retrieve context Enable Global interrupts Execute next instruction

Interrupt Block Diagram


What if 2 interrupt happens at the same time?

Interrupt Priority
A hardware priority hierarchy determines which reset or interrupt is serviced first when simultaneous requests are made. Six sources are non-maskable. The remaining sources are maskable, and the device integration module typically can change the relative priorities of maskable interrupts

Priority decoder
The priority decoder evaluates all interrupts pending and determines their validity and priority. When the CPU requests an interrupt vector, the decoder will provide the vector for the highest priority interrupt request. There are 2 decoding configurations:
Daisy chain Parallel priority

Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the INT upon request by the CPU is shown in Table 4-1.

The I Maskable interrupt sources have default priorities that follow the address order of the interrupt vectors. The higher the vector address, the higher the priority of the interrupt. Typically, a device integration module incorporates logic that can give any one maskable source priority over other maskable sources.

Exception processing Flow


(refer to CPU chapter)

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