( An A u t o n o m o u s I n s t i t u t e u n d e r U G C A c t 1956)

DEPARTMENT OF ELECTRONICS ENGINEERING

G. H. RAISONI COLLEGE OF ENGINEERING

Name of course:M.Tech. Semester/Branch I/(VLSI) Digital System -I Name of subject Modelling of List of Experiments
Sr. Name of the Experiment No . 1. WRITE A VHDL CODE FOR DIFFERENT LOGIC GATES. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. DESIGN 4:1 MULTIPLEXER AND WRITE VHDL CODE FOR SAME. DESIGN ARITHMETIC AND LOGIC UNIT. DESIGN BCD TO SEVEN SEGMENT DECODER. TO DESIGN HALF ADDER AND FULL ADDER AND WRITE VHDL CODE FOR SAME. TO DESIGN 4:16 DECODER USING 3:8 DECODER USING STRUCTURAL STYLE OF MODELING. DESIGN FLIP FLOPS AND WRITE A VHDL CODE FOR SAME USING BEHAVIOUR STYLE OF MODELLING. DESIGN THREE BIT UP-DOWN COUNTER AND WRITE THE VHDL CODE FOR IT. DESIGN A4 BIT BARREL SHIFTER AND WRITE VHDL CODE FOR THE SAME. DESIGN OF FINITE STATE MACHINE TO DETECT A SEQUENCE 1110 USING MEALY MODEL AND WRITE VHDL CODE FOR THE SAME. MINI PROJECT.

EXPERIMENT NO.:- 1
AIM: Write a VHDL code for different logic gates. SOFTWARE: Xilinx Software.
1. AND GATE PROGRAM: Library IEEE; Use ieee.STD_LOGIC_1164.all; Use ieee.STD_LOGIC_ARITH.all; Use ieee.STD_LOGIC_UNSIGNED.all; entityand_gate is Port(A,B: in STD_LOGIC: C:out STD_LOGIC); endand_gate; Architecturebehavioural ofand_gate is begin C<=A and B; endbehavioral;

RTL SCHEMATIC:

SIMULATION:

2. OR GATE PROGRAM: Library IEEE; Use ieee.STD_LOGIC_1164.all; Use ieee.STD_LOGIC_ARITH.all; Use ieee.STD_LOGIC_UNSIGNED.all; entityor_gate is Port(A,B: in STD_LOGIC: C:out STD_LOGIC); endor_gate; Architecture behavioural of and_gate is begin C<=A or B; endbehavioral;

RTL SCHEMATIC

SIMULATION:

3. NOT GATE
PROGRAM: Library IEEE; Use ieee.STD_LOGIC_1164.all; Use ieee.STD_LOGIC_ARITH.all; Use ieee.STD_LOGIC_UNSIGNED.all; Entity not_gate is

Port(A: in STD_LOGIC: B:out STD_LOGIC); endnot_gate; Architecture behavioural of not_gate is begin B<= not(A) ; endbehavioral;

RTL SCHEMATIC:

SIMULATION:

4. NAND GATE
PROGRAM: Library IEEE;

Use ieee.STD_LOGIC_1164.all; Use ieee.STD_LOGIC_ARITH.all; Use ieee.STD_LOGIC_UNSIGNED.all; Entity nand_gate is Port(A,B: in STD_LOGIC: C:out STD_LOGIC); endnand_gate; Architecture behavioural of nand_gate is begin C<=A nand B; endbehavioral;

RTL SCHEMATIC:

SIMULATION:

5. NOR GATE
PROGRAM: Library IEEE; Use ieee.STD_LOGIC_1164.all; Use ieee.STD_LOGIC_ARITH.all; Use ieee.STD_LOGIC_UNSIGNED.all; Entity nor_gate is Port(A,B: in STD_LOGIC: C:out STD_LOGIC); endnor_gate; Architecture behavioural of nor_gate is begin C<=A nor B; endbehavioral;

RTL SCHEMATIC:

SIMULATION:

6. X-OR GATE
PROGRAM: Library IEEE; Use ieee.STD_LOGIC_1164.all; Use ieee.STD_LOGIC_ARITH.all; Use ieee.STD_LOGIC_UNSIGNED.all; Entity xor_gate is Port(A,B: in STD_LOGIC: C:out STD_LOGIC); endxor_gate;

Architecture behavioural of xor_gate is begin C<=A xor B; endbehavioral;

RTL SCHEMATIC:

SIMULATION:

7. X-NOR GATE
PROGRAM: Library IEEE; Use ieee.STD_LOGIC_1164.all; Use ieee.STD_LOGIC_ARITH.all; Use ieee.STD_LOGIC_UNSIGNED.all; Entity xnor_gate is

Port(A,B: in STD_LOGIC: C:out STD_LOGIC); endxnor_gate; Architecture behavioural of xnor_gate is begin C<=A xnor B; endbahavioral;

RTL SCHEMATIC:

SIMULATION:

RESULT: Thus VHDL code for all logic gates are written and their corresponding synthesis and simulations are done.

EXPERIMENT NO.:- 2
AIM: Design 4:1 multiplexer and write VHDL code for same. SOFTWARE: Xilinx Software. PROGRAM:
Library IEEE; Use ieee.STD_LOGIC_1164.all; Use ieee.STD_LOGIC_ARITH.all; Use ieee.STD_LOGIC_UNSIGNED.all;

entity mux_4_1 is Port(A,B,C,D: in STD_LOGIC: S:in STD_LOGIC_VECTOR(1 downto 0);

Y:out STD_LOGIC); end mux_4_1;

Architecture behavioural of mux_4_1 is begin Process (S) begin Case S is When 00 => Y <= A; When 01 => Y <= B; When 10 => Y <= C; When others => Y <= D; end case; end process; end behavioral;

RTL SCHEMATIC:

SIMULATION:

RESULT: Thus the 4:1 multiplexer is studied and VHDL code is written for same.

EXPERIMENT NO.:- 3
AIM: Design arithmetic and logic unit.

SOFTWARE:- Xilinx Software.

entityALU is Port(A,B: in STD_LOGIC: S:in STD_LOGIC_VECTOR(2 downto 0); Y:out STD_LOGIC); end ALU;

Architecture behavioural of ALU is begin Process (S) begin Case S is When 000 => Y <= A or B; When 001 => Y <= A and B; When 010 => Y <= A nand B; When 011 => Y <= A nor B; When 100 => Y <= A xor B; When 101 => Y <= A xnor B; When 110 => Y <= not A ; When 111 => Y <= not B; When others => null;

end case; end process endbehavioral;

RTL SCHEMATIC:

SIMULATION:

RESULT: Thus Arithmetic and logic unit is designed and code is written.

EXPERIMENT NO.:- 4
AIM: Design BCD to seven segment decoder. SOFTWARE: Xilinx Software.
PROGRAM: Library IEEE; Use ieee.STD_LOGIC_1164.all; Use ieee.STD_LOGIC_ARITH.all; Use ieee.STD_LOGIC_UNSIGNED.all;

Entity BCD_7 is Port(B: in STD_LOGIC_VECTOR(3 downto 0); S:out STD_LOGIC_VECTOR(6 to 0));

end BCD_7;

Architecture behavioural of BCD_7 is begin Process (B) begin Case B is When 0000 =>S <=0000000; When 0001 =>S <= 1001111; When 0010 => S <= 0010010; When 0011 => S <= 0000110; When 0100 => S <= 0101100; When 0101 => S <= 0100100; When 0110 => S<= 0100000; When 0111 => S <= 0001111; When 1000 => S <= 0000000; When 1001 => S <= 0000100; When others => S<= _______; end case; end process; endbehavioral;

RTL SCHEMATIC:

SIMULATION:

RESULT: Thus BCD to seven segment decoder is designed.

EXPERIMENT NO.:- 5

AIM: To Design half adder and full adder and write VHDL code for same. SOFTWARE: Xilinx Software.
1. HALF ADDER PROGRAM: Library IEEE; Use ieee.STD_LOGIC_1164.all; Use ieee.STD_LOGIC_ARITH.all; Use ieee.STD_LOGIC_UNSIGNED.all; entityhalf_add is Port(a,b: in STD_LOGIC: s,co:out STD_LOGIC); endhalf_add; Architecture behavioural of half_add is begin s<= a xor b; co<=a and b; endbehavioral;

RTL SCHEMATIC:

SIMULATION:

2. FULLADDER PROGRAM: Library IEEE; Use ieee.STD_LOGIC_1164.all; Use ieee.STD_LOGIC_ARITH.all; Use ieee.STD_LOGIC_UNSIGNED.all; entityfull_add is Port(a,b,ci: in STD_LOGIC: s,co:out STD_LOGIC); endfull_add; Architecture behavioural of full_add is begin s<= a xor bxor c; co<=(a and b) or (b and ci) or (a and ci); endbehavioral;

RTL SCHEMATIC:

SIMULATION:

RESULT: Thus half adder and full adder are designed and code for it is written.

EXPERIMENT NO.6
Aim: To design 4:16 decoder using 3:8 decoder using structural style of Modeling. Program: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DECODER is Port ( X : in STD_LOGIC_VECTOR (3 downto 0);

Z : out STD_LOGIC_VECTOR (15 downto 0)); end DECODER; architecture Behavioral of DECODER is COMPONENT DEC3_8 PORT(CS:IN STD_LOGIC; A:IN STD_LOGIC_VECTOR(2 DOWNTO 0); Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END COMPONENT; COMPONENT NOT_1 PORT( A:IN STD_LOGIC; B:OUT STD_LOGIC); END COMPONENT; SIGNAL S1:STD_LOGIC; begin D1: DEC3_8 PORT MAP(X(3),X(2 DOWNTO 0),Z(7 DOWNTO 0)); D2: DEC3_8 PORT MAP(S1,X(2 DOWNTO 0),Z(15 DOWNTO 8)); N : NOT_1 PORT MAP(X(3),S1); end Behavioral;

RTL SCHEMATIC:

SIMULATIONS:

RESULT: THUS 4 TO 16 DECODER IS DESIGNED USING 3 TO 8 DECODER AND VHDL CODE IS WRITTEN FOR SAME.

EXPERIMENT NO 7 AIM : DESIGN FLIP FLOPS AND WRITE A VHDL CODE FOR SAME USING BEHAVIOUR STYLE OF MODELLING.

D FLIP FLOP
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entityd_ff is Port ( reset : in STD_LOGIC; clk : in STD_LOGIC; d : in STD_LOGIC; q : out STD_LOGIC); endd_ff; architecture Behavioral of d_ff is begin process(reset,clk,) begin if reset='1' then q<='0'; elsifclkevent and clk=1 then q<=d; end if; end process; end Behavioral;

RTL SCHEMATIC:

SIMULATIONS:

T-FLIP FLOP:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entityt_ff is Port ( reset : in STD_LOGIC; clk : in STD_LOGIC; t : in STD_LOGIC; q : out STD_LOGIC qn: out STD_LOGIC); endt_ff; architecture Behavioral of t_ff is begin process(reset,clk,) begin if(reset='1') then q<='1'; qn<=0; elsifclkevent and clk=1 then q<=t; qn<=not t; end if; end process; end Behavioral;

RTL SCHEMATIC:

SIMULATIONS:

SR-FLIP FLOP:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entitysr_ff is Port ( reset : in STD_LOGIC; clk : in STD_LOGIC; s,r : in STD_LOGIC; q : out STD_LOGIC qn: out STD_LOGIC); endsr_ff; architecture Behavioral of sr_ff is signalff:STD_LOGIC; begin process(reset,clk) variablesr: STD_LOGIC_VECTOR(1 DOWNTO 0); begin if (reset='0') then ff<=0; elsifclkevent and clk=1 then sr:= s & r; casesr is when 01 =>ff<= 0; when 10 =>ff<= 1; when 11 =>ff<= not ff; when others =>ff<= ff; end case; end if; end process; q<= ff; qn<= not ff; end Behavioral;

RTL SCHEMATIC:

SIMULATIONS:

JK-FLIP FLOP:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entityjk_ff is Port ( reset : in STD_LOGIC; clk : in STD_LOGIC; j,k : in STD_LOGIC; q : out STD_LOGIC qn: out STD_LOGIC); endjk_ff; architecture Behavioral of jk_ff is signalff:STD_LOGIC; begin process(reset,clk) variablejk: STD_LOGIC_VECTOR(1 DOWNTO 0); begin if (reset='0') then ff<=0; elsifclkevent and clk=1 then jk:= j & k; casejk is when 01 =>ff<= 0; when 10 =>ff<= 1; when 11 =>ff<= not ff; when others =>ff<= ff; end case; end if; end process; end Behavioral;

RTL SCHEMATIC:

SIMULATIONS:

RESULT: THUS DESIGN OF ALL FLIP FLOPS IS DONE AND VHDL CODE IS WRITTEN FOR IT.

EXPERIMENT NO 8 AIM:DESIGN THREE BIT UP-DOWN COUNTER AND WRITE THE VHDL CODE FOR IT. DESIGN OF 3-BIT UPDOWN COUNTER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity COUNTER_S is Port ( CLK : in STD_LOGIC; CLR : in STD_LOGIC; UPDOWN : in STD_LOGIC; Y : out STD_LOGIC_VECTOR (2 downto 0)); end COUNTER_S;

architecture Behavioral of COUNTER_S is SIGNAL TEMP: STD_LOGIC_VECTOR(2 DOWNTO 0); begin PROCESS (CLK, CLR) BEGIN IF(CLR='1') THEN TEMP<="000"; ELSIF (CLK'EVENT AND CLK='1') THEN IF (UPDOWN='1') THEN TEMP<=TEMP+1; ELSE TEMP<=TEMP-1; END IF; END IF; END PROCESS; Y<=TEMP; end Behavioral;

RTL SCHEMATIC

SIMULATION

RESULT: THUS WE HAVE STUDIED THE VHDL CODE FOR THREE BIT UPDOWN COUNTER.

EXPERIMENT NO :9 AIM : DESIGN A4 BIT BARREL SHIFTER AND WRITE VHDL CODE FOR THE SAME.
4 BARREL SHIFTER CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity barrel shift is generic(N:positive:=4); port(data: IN std_logic_vector(N-1 downto 0); seleKt : in integer range 0 to N-1;

Barr_old: out std_logic_vector(N-1 docounto 0); end barrel shift; architecture Behavioral of barrel shift is begin process (select, date) variablevar_buf: std_logic_vector(N-1); begin VAR_BUF:= data; for K in 1 to select loop var_BUF:= VAR_BUF(N-2 downto 0)&var_BUF(N-1); end loop; Barr_out<= Var_BUF; endfor_loop_style; end process; end Behavioral;

RTL SHCEMATIC

SIMULATIONS:

RESULT : THUS WE HAVE STUDIED THE 4 BIT BARREL SHIFTER.

EXPERIMENT NO :10

AIM : DESIGN OF FINITE STATE MACHINE TO DETECT A SEQUENCE 1110 USING MEALY MODEL AND WRITE VHDL CODE FOR THE SAME. FSM CODE
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity last is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; x : in STD_LOGIC; z : out STD_LOGIC); end last; architectureBeh of last is typestate_type is(a,b,c,d); signal y:state_type; begin process(clk,rst) begin ifrst='0' then y<=a; elsifclk'event and clk='1' then case y is when a=> if x='0' then y<=b; else y<=a; end if; when b=> if x='0' then y<=b; else y<=c; end if;

when c=> if x='0' then y<=c;

else y<=a; end if; when d=> if x='0' then y<=d; else y<=c; end if; end case; end if; end process; process(y,x) begin case y is when a=> z<='0'; when b=> z<='0'; when c=> z<='0'; when d=> z<=x; end case; end process; endBehavioral;

RTL SCHEMATIC:

OUTPUT

RESULT : THUS WE HAVE STUDIED THE FINITE STATE MACHINE (FSM) USING MEALY MODEL & VHDL CODE FOR THE SAME.