Full adder

entity FULL ADDER is -----Initializing the Ports for input and out------------------port( SUM CO A B CI end FULLADD; -----Behavioural Describtion of a FULL ADDER--------------functionality-------architecture behav of FULL ADDER is --------programme begin---------begin process(A,B,CI) -----preferred code for arithmetic operators--variable sel : std_logic_vector(2 downto 0) ; begin sel := A&B&CI ; case sel is : out STD_LOGIC; ------SUM----: out STD_LOGIC; ------Carry Out--: in STD_LOGIC; -------Input A-----: in STD_LOGIC; -------Input B-----: in STD_LOGIC); ------Carry In-----

when "000" => CO <= '0' ; SUM <= '0' ; when "001" => CO <= '0' ; SUM <= '1' ; when "010" => CO <= '0' ; SUM <= '1' ; when "011" => CO <= '1' ; SUM <= '0' ; when "100" => CO <= '0' ; SUM <= '1' ; when "101" => CO <= '1' ; SUM <= '0' ; when "110" => CO <= '1' ; SUM <= '0' ; when "111" =>

CO <= '1' ; SUM <= '1' ; when others => CO <= 'X' ; SUM <= 'X' ; end case ; end process ; end behav ;

VHDL CODE FOR 8 BIT RIPPLE CARRY ADDER

entity carryrippleadder is -------n is set 0-7----generic(n:integer := 7 ); ----Declaration of input/output----port( AD_in : in std_logic_vector(n downto 0 ); BD_in : in std_logic_vector(n downto 0 ); S : out std_logic_vector(n downto 0 ); ------Carry In-----cin : in std_logic ; -------Auxilliary carry----ACY : out std_logic ; -----Carry out-------

cout : out std_logic ) ; end carryrippleadder ; -----Behavioural Describtion of a carry ripple adder --------architecture struct of carry ripple adder is -----Sub circuit Full adder used in in CRA----component FULL ADDER -------Description of input and output of FULL ADDER-----------port( S CO A B CI end component; ---Declare signal Data A-----signal AD_in_s :std_logic_vector(n downto 0 ); ----Declare signal Data B-----signal BD_in_s :std_logic_vector(n downto 0 ); -----Declare signal Sum-----signal S_s :std_logic_vector(n downto 0 ); -----Declare signal Carry in----signal cin_s :std_logic_vector(n downto 0 ); : out STD_LOGIC; : out STD_LOGIC; : in STD_LOGIC; : in STD_LOGIC; : in STD_LOGIC);

-----Declare signal Carry Out-----signal cout_s :std_logic_vector(n downto 0 ); begin cin_s(0) <= cin ; ADDER0: FULL ADDER port map ( S => S_s(0) , CO => cout_s(0) , A => AD_in_s(0) , B => BD_in_s(0) , CI => cin_s(0)) ; G1 : for s in n downto 1 generate ------S = sum-----ADDER1: FULL ADDER port map( S => S_s(s) , CO => cout_s(s) , A => AD_in_s(s) , B => BD_in_s(s) , CI => cout_s(s-1)) ; end generate ; SUM <= SUM_S ; cout <= cout_s(7) ; AD_in_s <= AD_in ; BD_in_s <= BD_in ; ACY <= cout_s(3) ;

end struct ;

A.3

VHDL CODE FOR ALU

entity alu is ---- n is set 0-7 ---generic ( n : integer := 7 ; ---- s is 3 ---s : integer := 3) ; --- Declaration of input/output D stands for data --port(D_a : in std_logic_vector(n downto 0); D_b : in std_logic_vector(n downto 0); D_out: out std_logic_vector(n downto 0); --- Carry out --cout : out std_logic; ---Auxiliary carry--ACY : out std_logic; SIGN : out std_logic; PARITY : out std_logic; S : out std_logic; --- Carry in --cin : in std_logic; --- operation select ---

operation_sel : in std_logic_vector(s downto 0)); end alu; -----Behavioural Describtion of alu ---------

architecture behav of alu is signal nd : std_logic_vector(n downto 0 ); signal AD_in_s : std_logic_vector(n downto 0 ); signal BD_in_s : std_logic_vector(n downto 0 ); signal D_b_n_s : std_logic_vector(n downto 0 ); signal D_a_n_s : std_logic_vector(n downto 0 ); signal B_in_s_r : std_logic_vector(n downto 0 ); signal A_in_s_r : std_logic_vector(n downto 0 ); signal S_s : std_logic_vector(n downto 0 );

signal cout_s : std_logic ; ---- component used in alu ---component carryrippleadder --- Declaration of input/output --port( A_in : in std_logic_vector(n downto 0 ); B_in : in std_logic_vector(n downto 0 ); S : out std_logic_vector(n downto 0 ); cin : in std_logic ; ACY : out std_logic ;

cout : out std_logic ) ; end component;

begin AD_in_s <= dat_a ; BD_in_s <= dat_b ; dat_b_n_s <= not(dat_b) ; dat_a_n_s <= not(dat_a) ; ---integrating CRA with ALU--CRA8_1 : carryrippleadder port map (AD_in => AD_in_s_r , BD_in => BD_in_s_r , S => S_s , cin => cin , ACY => ACY , cout => cout_s) ;

process(D_a,D_b,operation_sel,A_in_s,B_in_s,dat_b_n_s,S_s) variable D_xor_res:std_logic_vector(n downto 0) ; variable D_shr_res:std_logic_vector(n downto 0) ; variable D_xnor_res:std_logic_vector(n downto 0); variable D_and_res:std_logic_vector(n downto 0); variable D_nand_res:std_logic_vector(n downto 0);

variable D_or_res:std_logic_vector(n downto 0); variable D_nor_res:std_logic_vector(n downto 0); variable D_out_var:std_logic_vector(n downto 0); variable operation_sel_int : integer := 0 ; begin operation_sel_int := CONV_INTEGER(operation_sel);

--- behav of XOR operation --for i in n downto 0 loop D_xor_res(i) := D_a(i) xor D_b(i); end loop;

--- shift data A right --for i in n-1 downto 0 loop D_shr_res(i) := D_a(i+1) ; end loop; D_shr_res(7) := '0' ;

--- behav for xnor operation --for i in n downto 0 loop D_xnor_res(i) := not (D_a(i) xor D_b(i)); end loop;

--- behav for and operation --for i in n downto 0 loop D_and_res(i) := D_a(i) and D_b(i); end loop; --- behav for nand operation --for i in n downto 0 loop D_nand_res(i) := not (D_a(i) and D_b(i)); end loop; --- behave for or operation --for i in n downto 0 loop D_or_res(i) := D_a(i) or D_b(i); end loop; --- behav for nor operation--for i in n downto 0 loop D_nor_res(i) := not (D_a(i) or D_b(i)); end loop; case operation_sel_int is when 1 => D_out_var := D_xor_res ; BD_in_s_r <= BD_in_s ; AD_in_s_r <= AD_in_s ;

cout <= '0' ; when 2 => D_out_var := D_xnor_res ; BD_in_s_r <= BD_in_s ; AD_in_s_r <= AD_in_s ; cout <= '0' ; when 3 => D_out_var := D_and_res ; BD_in_s_r <= BD_in_s ; AD_in_s_r <= AD_in_s ; cout <= '0' ; when 4 => D_out_var := D_nand_res ; BD_in_s_r <= BD_in_s ; AD_in_s_r <= AD_in_s ; cout <= cout_s ; when 5 => D_out_var := D_or_res ; BD_in_s_r <= BD_in_s ; AD_in_s_r <= AD_in_s ; cout <= '0' ; when 6 =>

D_out_var := D_nor_res ; BD_in_s_r <= BD_in_s ; AD_in_s_r <= AD_in_s ; cout <= '0' ; --- addition A + B --when 0 => BD_in_s_r <= BD_in_s ; D_out_var := S_s ; AD_in_s_r <= AD_in_s ; cout <= cout_s ; --- subtraction A B --when 7 => BD_in_s_r <= D_b_n_s ; D_out_var := S_s ; AD_in_s_r <= AD_in_s ; cout <= cout_s ; --- not not(A) --when 8 => BD_in_s_r <= "00000000" ; D_out_var := S_s ; AD_in_s_r <= D_a_n_s ; cout <= cout_s ;

--- increment REG + 1 --when 9 => BD_in_s_r <= BD_in_s ; D_out_var := S_s ; AD_in_s_r <= "00000000" ; cout <= cout_s ; --- dcr REG 1 --when 10 => BD_in_s_r <= "11111110" ; D_out_var := S_s ; AD_in_s_r <= BD_in_s; cout <= cout_s ; --- shl A <- shl(A) --when 11 => BD_in_s_r <= AD_in_s ; D_out_var := S_s ; AD_in_s_r <= AD_in_s; cout <= cout_s ; --- SUM/clear --when 12 => BD_in_s_r <= "00000000" ; D_out_var := S_s ;

AD_in_s_r <= "00000000"; cout <= cout_s ; when 13 => -- SHIFT RIGHT(A) -D_out_var := D_shr_res ; BD_in_s_r <= BD_in_s ; AD_in_s_r <= AD_in_s ; cout <= cout_s ; when others => D_out_var := S_s ; BD_in_s_r <= "00000000" ; AD_in_s_r <= "00000000"; cout <= cout_s ; end case ; D_out <= D_out_var ; PARITY <= D_out_var(0) xor D_out_var(1) xor D_out_var(2) xor D_out_var(3) xor D_out_var(4) xor D_out_var(5) xor D_out_var(6) xor D_out_var(7) ; nd <= D_out_var ; end process; SUM <= not (nod(0) and nod(1) and nod(2) and nod(3) and nod(4) and nod(5) and nod(6) and nod(7)) ; SIGN <= nod(7) ; end behav;

VHDL CODE FOR 8-bit REGISTER

entity r8 is --- n is set 0-7--generic (n: integer:= 7); --- declaration of input/output --port(D_in : in std_logic_vector(n downto 0); E clear clock : in std_logic; : in std_logic; : in std_logic;

D_out : out std_logic_vector(n downto 0)); end r8; -----Behavioural Describtion of r8 --------architecture behav of r8 is begin process(clock,clear) variable D_out_all_1:std_logic_vector(n downto 0) ; variable D_out_sig:std_logic_vector(n downto 0) ; begin if(clear = '1') then -- +ive edge triggered -if(clock = '1') and (clock'event) then

if(E = '1')then D_out <= D_in ; end if; end if; -- for async reset -elsif(clear = '0') then D_out <= (others => '0') ; end if; end process; end behav ;

VHDL CODE FOR TRI-STATE BUFFER

entity tristate_buffer is port ( enable: in std_logic; d_in: in std_logic_vector ( 7 downto 0 ) ; d_out; out std_logic_vector (7 downto 0 )) ; end tristate_buffer; -----Behavioural Describtion of a tri state buffer --------architecture behavioral of tristate_buffer is begin process (enable, d_in) begin if (enable = 1 ) then

d_out <= d_in; else d_out <= (others => zzzzzzzzzz); end if; end process; end behavioral;

VHDL CODE FOR TRANSPARENT LATCH

entity transparentlatch is --- Declaration of input/output --port(in_D : in std_logic_vector(7 downto 0); E : in std_logic ; D_out: out std_logic_vector(7 downto 0)); end trans_latch ; -----Behavioural Describtion of a transparent latch --------architecture behav of transparentlatch is begin process(E) begin if(E = '1')then

D_out <= in_D; end if ; end process ; end behav ; VHDL CODE FOR 2-1 MULTIPLEXER entity multiplexer is port ( D_in_b, D_in, enable: in std_logic; D_out: out std_logic) ; end multiplexer; -----Behavioural Describtion of a multiplexer --------architecture behavioral of multiplexer is begin process (Enable, D_in_b, D_in) begin if (Enable= '0' ) then D_out <= D_in_b; else D_out <= D_in; end if; end process; end behavioral;

VHDL CODE FOR PROGRAM COUNTER

entity pch is --- n is set 0-7 --generic ( n : integer := 7 ); ---Declaration of input/output--port(point_next_add : out std_logic_vector(n downto 0) ; count_start : in std_logic ; clock clear : in std_logic ; : in std_logic ;

D_in : in std_logic_vector(n downto 0) ; E : in std_logic ); end pch ; -----Behavioural Describtion of pch --------architecture struct of pch is ---- component used in pch ---component ComPC ---Declaration of input/output--port( C : out std_logic; E, count_start, data_in, clear,

clock : in std_logic); end component ;

signal point_next_add_sig : std_logic_vector(n downto 0) ; signal count_start_sig : std_logic_vector(n downto 0) ; begin count_start_sig(0) <= count_start ; PC1: comPC port map( C E => E , count_start => count_start , data_in => D_in(0) , clear clock => clear , => clock ) ; => point_next_add_sig(0) ,

P1: for s in n downto 1 generate PC1: comPC port map( C E => E , count_start => count_start_sig(s) , data_in => D_in(s) , clear clock => clear , => clock ) ; => point_next_add_sig(s) ,

count_start_sig(s) <= point_next_add_sig(s-1) and count_start_sig(s-1) ; end generate ; point_next_add <= point_next_add_sig ; end struct ;

-----location in the computer file system where the package is stored--library ieee; --- Package used --use ieee.std_logic_1164.all;

--- Name --entity comPC is

---- Declaration of input/output ---port( C : out std_ulogic;

E :in std_logic ; count_start :in std_logic ; data_in :in std_logic ; clear clock :in std_logic ; :in std_logic );

end comPC;

-----Behavioural Describtion of comPC ---------

architecture behav of comPC is signal C_sig: std_logic ;

begin process(E,count_start,data_in,clear,clock) variable sel : std_logic_vector(1 downto 0) ; begin sel := E&count_start ; if(clear = '1') then C_sig <= '0' ; elsif(rising_edge(clock)) then case sel is when "00" => C_sig <= C_sig; when "01" => C_sig <= not(C_sig); when "10" => C_sig <= data_in; when "11" =>

C_sig <= not(C_sig); when others => null ; end case ; end if ; end process ; C <= C_sig ; end behav ;

VHDL CODE FOR STACK POINTER

entity STACKPOINTER is --- it enables count(up or down) --port(count_up_down : in std_logic ; clock : in std_logic ; hi : in std_logic ; lo : in std_logic ; clear : in std_logic ; D_in : in std_logic_vector(7 downto 0 ); -- parallel data SPLSB_OUT : out std_logic_vector(7 downto 0 ); SPMSB_OUT : out std_logic_vector(7 downto 0 )); end SP ;

------ Behavioural Describtion of STACKPOINTER ---------

architecture behav of STACKPOINTER is signal c_out_var : std_logic_vector(15 downto 0 ) ; begin process(clock,count_up_down,clear,hi,lo,D_in) variable toggle_bit_incr : std_logic_vector(15 downto 0 ) ; variable toggle_bit_decr : std_logic_vector(15 downto 0 ) ; variable sel begin if(clear = '0') then c_out_var <= "0000000000000000" ; else if(rising_edge(clock)) then toggle_bit_incr(0) := count_up_down ; toggle_bit_decr(0) := count_up_down ; for s in 1 to 15 loop toggle_bit_inr(s) := toggle_bit_inr(s-1) and c_out_var(s-1); toggle_bit_dcr(s) := toggle_bit_dcr(s-1) or c_out_var(s-1); end loop ; : std_logic_vector(2 downto 0 ) ;

for j in 0 to 15 loop if (toggle_bit_inr(s) = '1' or toggle_bit_dcr(s) = '0') then c_out_var(s) <= not (c_out_var(s));

end if ; end loop ; sel := hi&lo&count_up_down ; case sel is when "011" => for i in 7 downto 0 loop c_out_var(s) <= D_in(s) ; c_out_var(s+8) <= c_out_var(s+8) ; end loop ; when "101" => for i in 7 downto 0 loop c_out_var(s+8) <= D_in(s) ; c_out_var(s) <= c_out_var(s) ; end loop ; when "000" => c_out_var <= c_out_var ; when others => null ; end case ; end if ; end if ; end process ;

SPLSB_OUT <= c_out_var(7)&c_out_var(6)&c_out_var(5)&c_out_var(4)&c_out_var(3)&c_out_var(2)&c_out_var(1)&c_ out_var(0); SPMSB_OUT <= c_out_var(15)&c_out_var(14)&c_out_var(13)&c_out_var(12)&c_out_var(11)&c_out_var(10)&c_out_var (9)&c_out_var(8); end behav ;

VHDL CODE FOR ARRAY OF REGISTERS

entity REGISTERARRAY is --- n is set 0-7 --generic ( n : integer := 7 ; ---- s is 4 ---s : integer := 4); ---- Declaration of input/output ---port ( D_IN : in std_logic_vector(n downto 0) ; D_IN_FLAGS : in std_logic_vector(n downto 0) ; LOAD_FLAGS : in std_logic ; clear : in std_logic ; clock : in std_logic ;

INCR_PC : in std_logic ; DECR_SP : in std_logic ; Da_OUT : out std_logic_vector(n downto 0) ;

add_high_OUT : out std_logic_vector(n downto 0) ; A_OUT_r8 B_OUT_r8 C_OUT_r8 D_OUT_r8 E_OUT_r8 F_OUT_r8 H_OUT_r8 L_OUT_r8 : out std_logic_vector(n downto 0) ; : out std_logic_vector(n downto 0) ; : out std_logic_vector(n downto 0) ; : out std_logic_vector(n downto 0) ; : out std_logic_vector(n downto 0) ; : out std_logic_vector(n downto 0) ; : out std_logic_vector(n downto 0) ; : out std_logic_vector(n downto 0) ;

SPH_OUT : out std_logic_vector(n downto 0) ; REG_SEL_IN : in std_logic_vector(s downto 0) ; REG_SEL_OUT : in std_logic_vector(s downto 0)) ; end REG_ARR ; -----Behavioural Describtion of REGISTERARRAY --------architecture behav of REGISTERARRAY is ---- component used in REG_ARR ---component SP ---Declaration of input/output--port(count_up_down : in std_logic ; clock : in std_logic ; hi : in std_logic ; lo : in std_logic ;

clear : in std_logic ; D_in : in std_logic_vector(7 downto 0 ); SPLSB_OUT : out std_logic_vector(7 downto 0 ); SPMSB_OUT : out std_logic_vector(7 downto 0 )); end component ; ---- component used in REGISTERARRAY ---component r8 ---- n is 7 ---generic (n: integer:= 7); ---Declaration of input/output--port(D_in : in std_logic_vector(n downto 0); E clear clock : in std_logic; : in std_logic; : in std_logic;

D_out : out std_logic_vector(n downto 0)); end component ; ---- component used in REGISTER_ARRAY ---component pch ---- n is 7 ---generic( n : Integer := 7); ---Declaration of input/output--port( point_next_add : out std_logic_vector (7 downto 0);

count_start, clock, clear : in std_logic; D_in : in std_logic_vector (7 downto 0); E :in std_logic); end component; ---- component used in REGISTERARRAY ---component pcl ---- n is 7 ---generic ( n : integer := 7 ); ---Declaration of input/output--port(point_next_add : out std_logic_vector(n downto 0) ; OUT_to_PCH : out std_logic; count_start : in std_logic ; clock clear : in std_logic ; : in std_logic ;

D_in : in std_logic_vector(n downto 0) ; E : in std_logic ); end component ; ---- enter data A in regA ---signal enter_A : std_logic ; signal D_out_regA : std_logic_vector(n downto 0); ---- enter data F in regF ---signal enter_F : std_logic ; signal D_out_regF : std_logic_vector(n downto 0);

---- enter data B in regB ---signal enter_B : std_logic ; signal D_out_regB : std_logic_vector(n downto 0); ---- enter data C in regC ---signal enter_C : std_logic ; signal D_out_regC : std_logic_vector(n downto 0); ---- enter data D in regD ---signal enter_D : std_logic ; signal D_out_regD : std_logic_vector(n downto 0); ---- enter data E in regE ---signal enter_E : std_logic ; signal D_out_regE : std_logic_vector(n downto 0); ---- enter data H in regH ---signal enter_H : std_logic ; signal D_out_regH : std_logic_vector(n downto 0); ---- enter data L in regL ---signal enter_L : std_logic ; signal D_out_regL : std_logic_vector(n downto 0); ---- enter data SPL in regSPL ---signal enter_SPL : std_logic ; signal D_out_regSPL : std_logic_vector(n downto 0);

---- enter data SPH in regSPH ---signal enter_SPH : std_logic ; signal D_out_regSPH : std_logic_vector(n downto 0); ---- enter data PCL in regPCL ---signal enter_PCL : std_logic ; signal D_out_regPCL : std_logic_vector(n downto 0); ---- enter data PCH in regPCH ---signal enter_PCH : std_logic ; signal D_out_regPCH : std_logic_vector(n downto 0); ---- enter data W in regW ---signal enter_W : std_logic ; signal D_out_regW : std_logic_vector(n downto 0); ---- enter data Z in regZ ---signal enter_Z : std_logic ; signal D_out_regZ : std_logic_vector(n downto 0); --signal enter_VECTOR : std_logic_vector(13 downto 0); ---- signal increase in PCH ---signal INCR_PCH : std_logic ; ---- signal decrease in SPH -----signal DECR_SPH : std_logic ; begin

--- assign register number 1 --REG_A:r8 port map (D_in => D_IN, E => load_A , => clear , => clock ,

clear clock

D_out => dat_out_regA ) ;

--- assign register number 2 --REG_F:r8 port map (D_in => D_IN_FLAGS, E => load_FLAGS , => clear , => clock ,

clear clock

D_out => dat_out_regF ) ;

--- assign register number 3 --REG_B:r8 port map (D_in => D_IN, E => load_B , => clear , => clock ,

clear clock

D_out => dat_out_regB ) ;

--- assign register number 4 --REG_C:r8 port map (D_in => D_IN, E => load_C , => clear , => clock ,

clear clock

D_out => dat_out_regC ) ;

--- assign register number 5 --REG_D:r8 port map (D_in => D_IN, E => load_D , => clear , => clock ,

clear clock

D_out => dat_out_regD ) ;

--- assign register number 6 --REG_E:r8 port map (D_in => D_IN, E => load_E , => clear , => clock ,

clear clock

D_out => dat_out_regE ) ;

--- assign register number 7 ---

REG_H:r8 port map (D_in => D_IN, E => load_H , => clear , => clock ,

clear clock

D_out => dat_out_regH ) ;

--- assign register number 8 --REG_L:r8 port map (D_in => D_IN, E => load_L , => clear , => clock ,

clear clock

D_out => dat_out_regL ) ;

REG_SP : SP port map(count_up_down => DECR_SP , clock => clock ,

hi => load_SPH , lo => load_SPL , clear => clear , D_in => D_IN , SPLSB_OUT => dat_out_regSPL , SPMSB_OUT => dat_out_regSPH ) ;

--- assign register number 11 --REG_PCL:pcl port map (D_in => D_IN, OUT_to_PCH => INCR_PCH , E => load_PCL , count_start => INCR_PC , clear clock => clear , => clock ,

point_next_add => dat_out_regPCL ) ;

--- assign register number 11 --REG_PCH:pch port map (D_in => D_IN, E => load_PCH , count_start => INCR_PCH , clear clock => clear , => clock ,

point_next_add => dat_out_regPCH ) ;

--- assign register number 13 --REG_W:r8 port map (D_in => D_IN, E => load_W , => clear , => clock ,

clear clock

D_out => dat_out_regW ) ;

--- assign register number 14 --REG_Z:r8 port map (D_in => D_IN, E => load_Z , => clear , => clock ,

clear clock

D_out => dat_out_regZ ) ;

process(D_IN,INR_PC,REG_SEL_IN,REG_SEL_OUT,clock,clear) variable load_VECTOR : std_logic_vector(13 downto 0); variable DAT_OUT_var : std_logic_vector(n downto 0); variable REG_SEL_IN_INT : integer ;--:= 0 ; variable REG_SEL_OUT_INT : integer ;--:= 0 ; begin SEL_IN_INT := CONV_INTEGER(REG_SEL_IN); SEL_OUT_INT := CONV_INTEGER(REG_SEL_OUT); case SEL_IN_INT is when 0 => enter_VECTOR := "00000000000001" ;

when 1 =>

enter_VECTOR := "00000000000010" ;

when 2 => enter_VECTOR := "00000000000100" ;

when 3 => enter_VECTOR := "00000000001000" ; when 4 => enter_VECTOR := "00000000010000" ;

when 5 => enter_VECTOR := "00000000100000" ;

when 6 => enter_VECTOR := "00000001000000" ;

when 7 => enter_VECTOR := "00000010000000" ;

---

when 8 => enter_VECTOR := "00000100000000" ;

when 9 => enter_VECTOR := "00001000000000" ;

when 10 => enter_VECTOR := "00010000000000" ;

when 11 => enter_VECTOR := "00100000000000" ;

when 12 => enter_VECTOR := "01000000000000" ;

when 13 => enter_VECTOR := "10000000000000" ;

when 14 => enter_VECTOR := "00000000000000" ;

when others => enter_VECTOR := "00000000000000" ;

end case ;

case SEL_OUT_INT is when 7 => D_OUT_var := dat_out_regA ;

when 8 => D_OUT_var := dat_out_regF ;

when 0 => D_OUT_var := dat_out_regB ;

when 1 => D_OUT_var := dat_out_regC ;

when 2 => D_OUT_var := dat_out_regD ;

when 3 => D_OUT_var := dat_out_regE ;

when 4 => D_OUT_var := dat_out_regH ;

when 5 => D_OUT_var := dat_out_regL ;

when 9 => D_OUT_var := dat_out_regSPL ;

when 10 => D_OUT_var := dat_out_regSPH ;

when 11 => D_OUT_var := dat_out_regPCL ;

when 12 => D_OUT_var := dat_out_regPCH ;

when 13 => D_OUT_var := dat_out_regW ;

when 6 => D_OUT_var := dat_out_regZ ;

when others =>

D_OUT_var := dat_out_regPCL ;

end case ; enter_A <= load_VECTOR(7) ; --enter_F <= load_VECTOR(8) ; enter_B <= load_VECTOR(0) ; enter_C <= load_VECTOR(1) ; enter_D <= load_VECTOR(2) ; enter_E <= load_VECTOR(3) ; enter_H <= load_VECTOR(4) ; enter_L <= load_VECTOR(5) ; enter_SPL <= load_VECTOR(9) ; enter_SPH <= load_VECTOR(10) ; enter_PCL <= load_VECTOR(11) ; enter_PCH <= load_VECTOR(12) ; enter_W <= load_VECTOR(13) ; enter_Z <= load_VECTOR(6) ; D_OUT <= DAT_OUT_var ;

end process ;

add_high_OUT <= dat_out_regPCH ;

A_OUT_r8 B_OUT_r8 C_OUT_r8 D_OUT_r8 E_OUT_r8 F_OUT_r8 H_OUT_r8

<= dat_out_regA; <= dat_out_regB; <= dat_out_regC; <= dat_out_regD; <= dat_out_regE; <= dat_out_regF; <= dat_out_regH;

SPH_OUT <= dat_out_regSPH; L_OUT_r8 end behav ; <= dat_out_regL;

VHDL CODE FOR HIGH ORDER ADDRESS LATCH

entity highorderaddresslatch is --- n is set 0-7 --generic (n: integer:= 7); --- Declaration of input/output--port(D_pch : in std_logic_vector(7 downto 0) ; D_H : in std_logic_vector(7 downto 0) ; D_B : in std_logic_vector(7 downto 0) ; D_D : in std_logic_vector(7 downto 0) ; D_SPH : in std_logic_vector(7 downto 0) ; SEL clock : in std_logic_vector(2 downto 0) ; : in std_logic ;

clear : in std_logic ; E : in std_logic ; D_out : out std_logic_vector(7 downto 0) ); end highorderaddresslatch;

-----Behavioural Describtion of highorderaddresslatch ---------

architecture behav of add_latch_high is ---- component used in high order address latch ---component r8 ---- n is 7 ---generic (n: integer:= 7); ---Declaration of input/output--port(D_in : in std_logic_vector(n downto 0); E clear clock : in std_logic; : in std_logic; : in std_logic;

D_out : out std_logic_vector(n downto 0)); end component ;

signal data_reg8 :std_logic_vector(n downto 0) ; signal data_reg8_in :std_logic_vector(n downto 0) ;

begin

LATCH_1:r8 port map (D_in => data_reg8 , E => E , clear => clear , clock => clock ,

D_out => D_out );

process(clock,sel,D_pch,D_H,D_B,D_D) variable data_reg8_var : std_logic_vector(n downto 0);-- := "00000000"; begin case sel is when "000" => data_reg8_var := D_pch ;

when "001" => data_reg8_var := D_B ;

when "010" => data_reg8_var := D_D ;

when "011" => data_reg8_var := D_H ;

when "100" => data_reg8_var := D_SPH ;

when others => data_reg8_var := "00000000"; end case ; data_reg8 <= data_reg8_var ; end process ; end behav ;

VHDL CODE FOR COUNTER

entity COUNTER is ---- s is 4 ---generic ( s : integer := 4 ); ---- Declaration of input/output ---port(clock zero_reset c_start clear : in std_logic ; : in std_logic ; : in std_logic ; : in std_logic ; : out std_logic_vector(s downto 0));

T_states_OUT

end COUNTER ;

-----Behavioural Describtion of COUNTER -----

architecture behav of COUNTER is signal T_states_OUT_sig : std_logic_vector(s downto 0); begin process(c_start,zero_reset,clear,clock) variable toggle_bit_incr : std_logic_vector(s downto 0 ) ; begin if(clear = '0') then T_states_OUT_sig <= (others => '0') ; elsif(rising_edge(clock)) then toggle_bit_incr(0) := c_start ; for j in 1 to s loop toggle_bit_incr(j) := toggle_bit_incr(j-1) and T_states_OUT_sig(j-1); end loop ;

for j in 0 to s loop if (toggle_bit_incr(j) = '1') then T_states_OUT_sig(j) <= not (T_states_OUT_sig(j)) ; end if ;

end loop ; if(zero_reset = '1') then T_states_OUT_sig <= (others => '0') ; end if ; end if ; end process ; T_states_OUT <= T_states_OUT_sig ; end behav ; VHDL CODE FOR CONTROL UNIT entity cpu_control is --- Declaration of input/output --port( INSTRUCTION_OUT_S T_STATE_IN clock : in std_logic_vector(7 downto 0) ;

: in std_logic_vector(4 downto 0) ; : in std_logic ;

s0_8085 s1_8085 iomn_8085

: out std_logic ; : out std_logic ; : out std_logic ;

RESETOUT_8085 : out std_logic ; CLK_OUT_8085 : out std_logic ; SOD_8085 : in std_logic ;

SID_8085 HOLD_8085 HOLDA_8085 TRAP_8085 RST75_8085 RST65_8085 RST55_8085 INTR_8085 INTA_8085

: in std_logic ; : in std_logic ; : out std_logic ; : in std_logic ; : in std_logic ; : in std_logic ; : in std_logic ; : in std_logic ; : out std_logic ;

---- Auxiliary Carry ---ACY_8085 SIGN_8085 PARITY_8085 ZERO_8085 ---- Carry ---CY_8085 : in std_logic ; : in std_logic ; : in std_logic ; : in std_logic ; : in std_logic ;

---- Carry In ---CIN_8085 : out std_logic ;

---- Load 5 flags ---LOAD_FLAGS_8085 : out std_logic ; SEL_HI_ADD_8085 : out std_logic_vector(2 downto 0 ) ;

LATCH_LOW_ADD

: out std_logic ; : out std_logic ;

T_STATES_OUT_COUNTER ALE ---- Read ---RDn ---- Write ---WRn OP_SEL : out std_logic ;

: out std_logic ;

: out std_logic ; : out std_logic_vector(3 downto 0) ;

SEL_DATAOUT_ALU_OUT : out std_logic ; EN_FROM_OUT LOAD_REG_T LOAD_REG_ID INR_PC DCR_SP EN_OUT_BUS EN_IN_BUS ---- clock ---clkn REG_SEL_IN REG_SEL_OUT end cpu_control ; : out std_logic ; : out std_logic_vector(4 downto 0) ; : out std_logic_vector(4 downto 0)) ; : out std_logic ; : out std_logic ; : out std_logic ; : out std_logic ; : out std_logic ; : out std_logic ; : out std_logic ;

-----Behavioural Describtion of cpu_control -----

architecture behav of cpu_control is begin clkn <= not(clock) ; process(T_STATE_IN,INSTRUCTION_OUT_S) variable CONTROLWORD : std_logic_vector(35 downto 0) ; variable INTR_WORD : std_logic_vector(4 downto 0) ; begin INTR_WORD := TRAP_8085&RST75_8085&RST65_8085&RST55_8085&INTR_8085 ; case T_STATE_IN is when "00000" => case INSTRUCTION_OUT_S is

--- few instructions selected for experiment CALL & MOV --when "11001101" => -- CALL CONTROLWORD := "11001000111011000000011010110011010" ;

when others => CONTROLWORD := "110001000111001000000011111110101110" ; end case ;

when "00001" => CASE INTR_WORD is when "00001" => CONTROLWORD := "100000001110100110000011111110101110" ; when others => CONTROLWORD := "100001000110100110000001111110101110" ; end CASE ;

when "00010" => CASE INTR_WORD is when "00001" => CONTROLWORD := "100000001110000000000011111110101110" ; when others => CONTROLWORD := "100001000110000000000001111110101110" ; end CASE ;

--- 4th T STATE --when "00011" => case INSTRUCTION_OUT_S is ---Binary 01111111 is mov a,a--when "7F" => -- mov a,a CONTROL_WORD := "000001000110010000000011001110011111" ;

---Binary 01111000 is mov a, b--when "78" => -- mov a,b CONTROL_WORD := "000001000110010000000011001110000011" ; end case ;

DCR_SP

<= CONTROLWORD(35) ; <= CONTROLWORD(34) ;

LATCH_LOW_ADD

for i in 33 downto 31 loop SEL_HI_ADD_8085(i-31) end loop ; <= CONTROLWORD(i) ;

INTA_8085 LOAD_FLAGS_8085 CIN_8085 iomn_8085 s1_8085 s0_8085 ALE

<= CONTROLWORD(30) ; <= CONTROLWORD(29) ;

<= CONTROLWORD(28) ; <= CONTROLWORD(27) ; <= CONTROLWORD(26) ; <= CONTROLWORD(25) ; <= CONTROLWORD(24) ; <= CONTROLWORD(23) ; <= CONTROLWORD(22) ; <= CONTROLWORD(21) ; <= CONTROLWORD(20) ;

EN_FROM_OUT EN_IN_BUS EN_OUT_BUS INR_PC

ENTER_REG_ID ENTER_REG_T

<= CONTROLWORD(19) ; <= CONTROLWORD(18) ;

for i in 17 downto 14 loop OPERATION_SEL(i-14) end loop ; <= CONTROLWORD(i) ;

RDn

<= CONTROLWORD(13) ;

SEL_D_OUT_ALU_OUT <= CONTROLWORD(12) ;

for i in 11 downto 7 loop REG_SEL_IN(i-7) end loop ; <= CONTROLWORD(i) ;

for i in 6 downto 2 loop REG_SEL_OUT(i-2) end loop ; <= CONTROLWORD(i) ;

WRn

<= CONTROLWORD(1) ;

T_STATES_OUT_COUNTER <= CONTROLWORD(0) ; end process ; end behav ;