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Abstract

This document summarizes research on novel nanoscale semiconductor devices for VLSI circuit design. It describes several transistor designs including MOSFETs, FinFETs, single electron transistors, tunnel FETs, gate-all-around FETs, and carbon nanotube FETs. The research aims to analyze parameters like drain current, threshold voltage, and transconductance to improve efficiency by reducing channel length and leakage current while increasing drain current and speed. The goal is to enhance VLSI circuit performance through the study and analysis of these nanoscale semiconductor devices.

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Vivek Singh
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116 views2 pages

Abstract

This document summarizes research on novel nanoscale semiconductor devices for VLSI circuit design. It describes several transistor designs including MOSFETs, FinFETs, single electron transistors, tunnel FETs, gate-all-around FETs, and carbon nanotube FETs. The research aims to analyze parameters like drain current, threshold voltage, and transconductance to improve efficiency by reducing channel length and leakage current while increasing drain current and speed. The goal is to enhance VLSI circuit performance through the study and analysis of these nanoscale semiconductor devices.

Uploaded by

Vivek Singh
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Study and Analysis of Nanoscale Novel Semiconductor Devices for VLSI Circuits Design

Abstract: The metaloxidesemiconductor field-effect transistor (MOSFET, MOSFET, or MOS FET) is a transistor used for amplifying or switching electronic signals. Although the MOSFET is a four-terminal device with source (S), gate (G), drain (D), and body (B) terminals, the body (or substrate) of the MOSFET often is connected to the source terminal, making it a three-terminal device like other field-effect transistors. Because these two terminals are normally connected to each other (short-circuited) internally, only three terminals appear in electrical diagrams. The dual-gate MOSFET has a tetrode configuration, where both gates control the current in the device. It is commonly used for small-signal devices in radio frequency applications where biasing the drain-side gate at constant potential reduces the gain loss caused by Miller effect, replacing two separate transistors in cascode configuration. Other common uses in RF circuits include gain control and mixing (frequency conversion). The FinFET, is a double-gate silicon-on-insulator device, one of a number of geometries being introduced to mitigate the effects of short channels and reduce drain-induced barrier lowering. The "fin" refers to the narrow channel between source and drain. A thin insulating oxide layer on either side of the fin separates it from the gate. SOI FinFETs with a thick oxide on top of the fin are called double-gate and those with a thin oxide on top as well as on the sides are called triple-gate FinFETs. The Single Electron Transistor is a new type of switching device that uses controlled electron tunneling to amplify current. It consists of two electrodes known as the drain and the source, connected through tunnel junctions to one common electrode with a low self-capacitance, known as the island. The electrical potential of the island can be tuned by a third electrode, known as the gate, capacitively coupled to the island. Tunnel Field-Effect Transistor (FET) is a gated-diode operating based on band-to-band tunneling at the junction. Key device parameters are the bandgap of the source material, the gate-to-channel coupling, the gate dielectric thickness and permittivity and the junction profile including abruptness and doping level. Gate-All-Around FETs are similar in concept to FinFETs except that the gate material surrounds the channel region on all sides. Depending on design, gate-all-around FETs can have two or four effective gates. Gate-all-around FETs have been successfully built around a silicon nanowire and etched InGaAs nanowires.

A carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Carbon nanotubes are cylindrical sheets of one ore more concentric layers of carbon atoms. Single-wall carbon nanotubes show superior electrical properties and are considered promising candidates for future Nano electronic applications, either as interconnects or active devices. By analyzing the parameters & equations pertaining to the basic MOSFET, we can study the equations for Drain Current (ID), Gate-Source Voltage (VGS), Drain-Source Voltage (VDS), Threshold Voltage (VTH), Trans conductance (gm), Output Resistance (Rout), Channel Length(L), Width (W). We can also plot the ID vs VDS graph at different values of VGS By studying the equations obtained for the above design parameters we aim to improve the efficiency of the above FETs by 1) Reducing the length of the channel, which implies smaller area. 2) Reducing the leakage current, which in turn reduces the power dissipation. 3) Increasing the drain current to improve the switching which in turn enhances the speed. 4) Reducing the delay of the circuit.

Project Mentor: Eric Savio Sales De Andrade (09104079) Dr. Balwinder Raj Vivek Kumar Singh (09104097) Assistant Professor Department of Electronics & Communication NIT Jalandhar

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