Time Behavioral Model For Phase-Domain ADPLL Based Frequency Synthesizer
Time Behavioral Model For Phase-Domain ADPLL Based Frequency Synthesizer
Another essential remark is that the phase error in the where we take care of modulo effect resulting of the finite
PLL is directly proportionnal to this delay. width R of the reference phase accumulator.
Equation (2) is valid if TD,k remains constant during a Similarly, the undersampled output of the DCO phase
whole cycle of FREF. Let us define by Ni(k) the integer part accumulator, RV(k) of the finite width D can be written
of the ratio between the two periods defined above
φ D [k + 1] = (φ D [k ] + N [k ]) mod[2 D ] (9)
However this expression cannot be implemented without t
With the assumption that x = 2π∆f pp ∫ g (τ )dτ is small
knowledge of N(k). Thanks to our previous analysis, we are 0
here able to compute N(k) using (7) and, therefore enough so that sin( x) ≈ x , we obtain the first order
implement (9). approximation
The fractionnal phase error ε can be simply modelized as t
the quantified version of our previous τk+1, normalized to sˆ(t ) = cos(2π f 0t ) − 2π∆f pp sin(2π f 0t ) ∫ g (τ ) dτ (15)
TD , an averaged value of TD. 0
A more precise model can be derived from the analysis of after developing the cosine in (14).
the TDC in terms of quantified delay between rising and The Fourier Transform of sˆ(t ) is
falling edges preceding the rising edge of FREF. This model
∆f G( f − f0 ) G( f + f0 ) (16)
Sˆ ( f ) = (δ f 0 + δ − f 0 ) + pp
is not developped in this paper for sake of simplicity. 1
−
Other elements involved in the ADPLL are the phase 2 2 f − f0 f + f0
error computation, the loop filter and the DCO. They are
briefly described now. where G ( f ) = TF [g (t )] .
The phase error is not just realized by an arithmetic For f = ±f0, the weight can also be computed by
additionner, according to 1 tmax t
tmax ∫0 ∫0
1 2 − π ∆f pp g (τ )dτ dt.
φ E [k ] = φ R [k ] − φ D [k ] + ε [k ] (10)
Thereby, with (16), we can directly compute the PSD
but by an adder with a limited width that take into account transform of the instantaneous frequency using solely the
the binary-signed format and modulo effect. lowpass signal g(t). The analysis above is continuous, but a
The digital loop filter is implemented by its difference similar analysis can be done in the discrete case. For
equation. implementation of a simulator based on our behavioral
The DCO is modelized by equations given in [2]. For a model, care must be taken on spectral aliasing, and a zeroth-
small deviation ∆f, we can use simple linearized model order interpolation have to be used in order to increase the
sampling period.
f DCO (k ) = f 0 + ∆f (k ) = f 0 + OTW ( k ) K DCO (11)
20log|S(f)| [dB]
-40
0 X: 9.5e+4 X: 2.4e+6
Y: -80.66
(FDCO - f0)/FREF
-80 Y: -86.2
-1/200 -120
-1/100
300 500 700 900 300 500 700 900 -160
(a) t/Tref (b) -5 -2.5 0 2.5 5
f-f 0 [MHz]
Fig 5. Limit cycle comparison between new behavioral model (a)
and VHDL model (b) Fig 7. PSD of the locking sequence when PLL is settled
1/2
both the validity and the speed of this model.
0 Such a model will be used to analyse several aspects of
(b)
-1/2
(c) this ADPLL and select a set of parameters optimizing its
performance.
-1
0 2000 4000 6000 8000 10000 12000 14000 16000
t/Tref
REFERENCES
1/10 0
(b) (c) [1] R. B. Staszeswski and P. T. Balsara, “Phase-Domain All-
(FDCO - f0)/FREF
(FDCO - f0)/FREF