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Time Behavioral Model For Phase-Domain ADPLL Based Frequency Synthesizer

The document presents a time behavioral model for a phase-domain all-digital phase-locked loop (ADPLL) used in frequency synthesizers. The model can be easily implemented and used to simulate the ADPLL faster than conventional models by expressing outputs independently of internal rates. The model represents the key components, including the time-to-digital converter and resampled oscillator phase accumulator, as behaving like a dual modulus divider controlled by phase error. Simulations using the behavioral model illustrate its effectiveness compared to a conventional VHDL model.

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0% found this document useful (0 votes)
78 views4 pages

Time Behavioral Model For Phase-Domain ADPLL Based Frequency Synthesizer

The document presents a time behavioral model for a phase-domain all-digital phase-locked loop (ADPLL) used in frequency synthesizers. The model can be easily implemented and used to simulate the ADPLL faster than conventional models by expressing outputs independently of internal rates. The model represents the key components, including the time-to-digital converter and resampled oscillator phase accumulator, as behaving like a dual modulus divider controlled by phase error. Simulations using the behavioral model illustrate its effectiveness compared to a conventional VHDL model.

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jubidown
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© Attribution Non-Commercial (BY-NC)
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P1-17

Time Behavioral Model for Phase-Domain ADPLL based Frequency


Synthesizer
Cyril Joubert(1,2), Jean François Bercher(1), Geneviève Baudoin(1), Thierry Divel(2),
Serge Ramet(2), Philippe Level(2)
(1) ESIEE / ESYCOM, 2 Boulevard Blaise Pascal, 93160 Noisy-le-Grand, France.
(2) ST-MICROELECTRONICS, 12 Rue Jules Horowitz, B.P.217, 38019 Grenoble, France.
[email protected], [email protected], [email protected], [email protected],
[email protected], [email protected]

Abstract — In this paper, we present a Time Behavioral


achieved by oversampling the reference clock, FREF, by the
Model of a recently proposed Phase-Domain All-Digital Phase- oscillator clock, FDCO.
Locked Loop (ADPLL) for RF applications. This model can be Note that in Fig 1, index i and k do not refer to the same
easily implemented, and results in a versatile and fast ADPLL clock.
simulator that enables to study many aspects of the PLL, e.g. Higher ADPLL precision is obtained using fractionnal
transient responses, steady states, limit cycles, or to perform
phase error correction. One can show that this fractionnal
perturbation analysis. Moreover, we present a baseband
analysis that allows to compute the power spectral density phase error is proportionnal to a time delay. The Time to
from the instantaneous frequency obtained as the output of the Digital Converter (TDC) is used to convert the delay
behavioral model. Simulations illustrate the effectiveness of (phase) between the RF and reference clocks directly into a
this new behavioral model. digital quantity [3], with a time resolution, noted ∆TRES, that
Index Terms — Phase locked loops, modeling can be equal to the elementary propagation delay through an
inverter gate.
The Frequency Command Word (FCW) is given as input
I. INTRODUCTION to the reference phase accumulator (RPA), and enables to
Recently, a new All Digital Phase-Locked Loop based RF tune the output frequency of the DCO.
frequency synthesizer was presented by Staszeswski et al.
FDCO = FCW × FREF (1)
[1]. A block diagram of the proposed architecture is shown
in Fig 1. Designing a PLL requires a simulator in order to study
ΦR [k] + ΦE [k] the effect of varying parameters and optimize the PLL.
FDCO
FCW RPA + Loop
Filter
OTW
DCO Analysis and simulation of the ADPLL in Fig. 1, with a
+
− direct method requires a very high rate clock. Indeed, such a
ε [k]
clock must have a rate that is greater than the highest
ΦD [k] ΦD [i] frequency in the system. This requirement leads to an
TDC QD DPA 1 incredible simulation time and fantastic amounts of data.
The objective of this paper is to show that it is possible to
simulate such a PLL at much more reasonnable rate,
FS
FREF DQ without sacrifying accuracy. The limiting components are
the DCO phase accumulator (at FDCO rate), and the TDC
(with accuracy ∆TRES), because of they would need an
Fig 1. ADPLL based RF frequency synthesizer [1] extremely fast sampling frequency for a correct
representation. The key for developing new simulation
A digitally controlled oscillator (DCO) allows for this model is to express behavior of limiting components outputs
PLL to be implemented in a fully digital manner [2]. directly at rate FREF but independently of internal rate FDCO
Phase accumulators are used to count cycle periods of or time accuracy ∆TRES. This can be understood as a kind of
reference and feedback oscillators. A synchronous clock, carrier frequency suppression.
FS, undersamples the output of the DCO phase accumulator In section II we consider the analysis of the simplest
(DPA), so that comparison of the two phases can be phase comparator: a D flip-flop, and so doing we present
performed using the same clock. The retimed clock, FS, is the basics of our behavioral model. Then, in section III we
develop the closed loop model; expressions of TDC and N i ( k ) = TR TD ,k  (4)
resampled oscillator phase accumulator outputs are derived
using the analysis of section II. Next, we show how to In (2) we have either N(k) = Ni(k) or N(k) = Ni(k) +1.
derive the Power Spectral Density (PSD) from the Hence the behavior of the D flip-flop is equivalent to a Dual
instantaneous frequency obtained at the output of the DCO. Modulus Divider (DMD) controlled by the phase error (via
Finally, we show typical results obtained using the the delay τ) as shown in Fig 3. In an extented model taking
behavioral model and we make simulation comparison with into account possible variations of TD,k during FREF cycle,
a conventional VHDL model. we may represent N(k) by N(k) = Ni(k) + C(k) where C(k) is
a natural number.
II. PRINCIPLE OF BEHAVIORAL MODEL
FDCO DMD FS
In order to understand the principle of the behavioral Ni/Ni+1
model, we focus on simple D flip-flop. Indeed, this central control
element links asynchronous clocks FDCO and FREF because it FREF
τ
resynchronizes them.
Let us consider the waveform shown in Fig 2. In this
diagram two important parameters appear: the delay τk and Fig 3. Behavioral model of the D flip-flop by a DMD controlled
the integer value N(k). τk is defined as the difference by the phase error
between the kth reference rising edge and following
oscillator rising edge, and N(k) is the real-value count of the In the case where N(k) take only two values, computation
DCO clock periods TD,k for each cycle of the reference of N(k) proceeds as follows.
clock. First suppose that N(k)=Ni(k)+1, and compute τk+1 using
(2). Then, we have to check that (3) is satisfied. If it is, we
FREF FS keep N(k)=Ni(k)+1, otherwise N(k) = Ni(k).
D Q
FDCO This analysis results in the following equations:
τk τk+1 (Ni + 1)TD,k − TR + τ (k) if τ (k + 1) − TD,k < 0 (5)
TR τ (k +1) = 
 NiTD,k − TR + τ (k) otherwise .
FREF
TD,k TD,k+1 This can be further simplified into
FDCO τ ( k + 1) = τ ( k ) + ( N i ( k ) + 0,5 )TD , k − TR
N(k)TD,k (6)
− sgn (N i ( k )TD , k − TR + τ ( k ) )T D , k 2
FS
using sgn(x) the sign function: sgn(x)= –1 if x<0, and
sgn(x)= 1 otherwise.
Fig 2. Inputs/output of the D flip-flop with a representative set of
waveforms Similarly, equation (2) and condition (3) leads to
N ( k ) = N i ( k ) + 0 .5
(7)
− 0.5 sgn (τ ( k ) + N i ( k ) T D , k − T R ).
The exact relation between reference and oscillator
frequencies can be deduced from the waveform in Fig 2.
We obtain the following relashionship between τk+1 and τk

τ k +1 = τ k + N (k )TD , k − TR (2) III. CLOSED LOOP MODEL


For the closed loop model we need to compute the output
where TR is the period of the reference clock and TD,k is the of phase accumulators and fractionnal error correction ε.
DCO period during the kth FREF cycle. An important point is Expression of reference phase accumulator is simply given
that the time delay is bounded according to by the well-known relation
0 ≤ τ k +1 ≤ TD , k ∀k (3) φ R [k + 1] = (φ R [k ] + FCW ) mod[2 R ] (8)

Another essential remark is that the phase error in the where we take care of modulo effect resulting of the finite
PLL is directly proportionnal to this delay. width R of the reference phase accumulator.
Equation (2) is valid if TD,k remains constant during a Similarly, the undersampled output of the DCO phase
whole cycle of FREF. Let us define by Ni(k) the integer part accumulator, RV(k) of the finite width D can be written
of the ratio between the two periods defined above
φ D [k + 1] = (φ D [k ] + N [k ]) mod[2 D ] (9)
However this expression cannot be implemented without t
With the assumption that x = 2π∆f pp ∫ g (τ )dτ is small
knowledge of N(k). Thanks to our previous analysis, we are 0
here able to compute N(k) using (7) and, therefore enough so that sin( x) ≈ x , we obtain the first order
implement (9). approximation
The fractionnal phase error ε can be simply modelized as t
the quantified version of our previous τk+1, normalized to sˆ(t ) = cos(2π f 0t ) − 2π∆f pp sin(2π f 0t ) ∫ g (τ ) dτ (15)
TD , an averaged value of TD. 0

A more precise model can be derived from the analysis of after developing the cosine in (14).
the TDC in terms of quantified delay between rising and The Fourier Transform of sˆ(t ) is
falling edges preceding the rising edge of FREF. This model
∆f  G( f − f0 ) G( f + f0 )  (16)
Sˆ ( f ) = (δ f 0 + δ − f 0 ) + pp
is not developped in this paper for sake of simplicity. 1
 − 
Other elements involved in the ADPLL are the phase 2 2  f − f0 f + f0 
error computation, the loop filter and the DCO. They are
briefly described now. where G ( f ) = TF [g (t )] .
The phase error is not just realized by an arithmetic For f = ±f0, the weight can also be computed by
additionner, according to 1 tmax t
tmax ∫0 ∫0
1 2 − π ∆f pp g (τ )dτ dt.
φ E [k ] = φ R [k ] − φ D [k ] + ε [k ] (10)
Thereby, with (16), we can directly compute the PSD
but by an adder with a limited width that take into account transform of the instantaneous frequency using solely the
the binary-signed format and modulo effect. lowpass signal g(t). The analysis above is continuous, but a
The digital loop filter is implemented by its difference similar analysis can be done in the discrete case. For
equation. implementation of a simulator based on our behavioral
The DCO is modelized by equations given in [2]. For a model, care must be taken on spectral aliasing, and a zeroth-
small deviation ∆f, we can use simple linearized model order interpolation have to be used in order to increase the
sampling period.
f DCO (k ) = f 0 + ∆f (k ) = f 0 + OTW ( k ) K DCO (11)

where f0 is the central frequency, OTW is the oscillator V. SIMULATIONS


tuning word at the input of the DCO, and KDCO the gain of
the DCO. Note that the real output of our model is directly The new behavioral model was implemented in
the instantaneous frequency, delivered at rate FREF, and not MATLAB. Another conventional model was realized in
a time signal with that instantaneous frequency. However, VHDL and simulated in MODELSIM.
we may compute the PSD of such virtual signal as described Simulations were done with two objectives to achieve:
now. 1. Validation of the time behavioral model by comparison
with results obtained by the VHDL model.
2. Study of spectral spurs linked to limit cycles and noise
IV. SPECTRAL DENSITY COMPUTATION level due to quantization (TDC).
The objective of this section is to show how to compute Examples reported below are typical results obtained
the PSD from the instantaneous frequency given by the using the behavioral model. Statistical analysis of
output of the behavioral model. performances and sensibility of the PLL will be developed
Let us consider fi(t) the instantaneous frequency of an elsewhere.
oscillator A. Time behavioral model validation
fi (t ) = f 0 + ∆fi (t ) = f 0 + ∆f pp g (t ) (12) For both models with same set of parameters, we compare
the transient behavior of the DCO output frequency when
where f0 is the mean frequency, ∆fpp is the peak-to-peak we change the frequency command word.
deviation from f0 and g(t) is a normalized frequency
modulation pattern (-1<g(t)<1) with zero mean. Fig 4 show the transient reponse of the output frequency
We define the instantaneous phase by of the ADPLL, when FCW is out of synthesizable range of
t t the DCO (T1) and next (T2), when FCW changes between
θi (t ) = ∫ 2π fi (τ )dτ = 2π f 0t + 2π∆f pp ∫ g (τ )dτ . (13) minimum and maximum value of the DCO. We observe the
0 0
same behavior and settling time.
The output signal s(t) of the oscillator is given by In Fig 5, we show the ADPLL locked behavior for both
 t

models (with the same scale). We note the same general
s(t ) = cos (θi (t ) ) = cos  2π f 0t + 2π∆f pp ∫ g (τ )dτ  . (14) behavior (frequency deviation, patterns), but also observe
 0  small differences in the limit cycle sequence because of
TDC modelisation and accuracy limitation in the VHDL Different frequency steps and gains for the DCO
simulator (1 femtosecond). characterize these three modes.
The behavioral model enables to measure and analyse the
locking sequence: transient parts and fluctuations during
steady states as shown in Fig 6.
Moreover, comparison with same simulation time and
parameters shows that the new behavioral model is 20 times
(a)
faster than VHDL model with 1fs resolution.
T1 T2
C. Spectral density computation
(b)
With the spectral density computation analysis in section
IV, we easily compute the PSD of the instantaneous
frequency of the DCO.
Fig 4. Simulation comparison of instantaneous frequency between 0
new behavioral model (a) and VHDL model (b) X: 0
Y: -6.021

20log|S(f)| [dB]
-40

0 X: 9.5e+4 X: 2.4e+6
Y: -80.66
(FDCO - f0)/FREF

-80 Y: -86.2

-1/200 -120

-1/100
300 500 700 900 300 500 700 900 -160
(a) t/Tref (b) -5 -2.5 0 2.5 5
f-f 0 [MHz]
Fig 5. Limit cycle comparison between new behavioral model (a)
and VHDL model (b) Fig 7. PSD of the locking sequence when PLL is settled

In Fig 7, we show an example of PSD when the PLL is


B. ADPLL Locking sequence locked. We can note the amplitudes and frequencies of
Convergence of the ADPLL is achieved using three spurs, due to accuracy of TDC and precision of DCO.
different modes [2]: first, a calibration (CAL) mode initiates
the TDC and the central frequency of the PLL, VI. CONCLUSION
independantly of frequency command word. Second, an
acquisition (ACQ) mode acquires channel selected by FCW. We have presented a simple and effective behavioral
Third, a tracking (TRK) mode achieves the required model for an all-digital phase locked loop. This model,
performances (use of a Sigma Delta modulator can further based on a simple expression of the delay that is an image
refine this last mode). of phase error, enables simulating the PLL at low rate
(independently of carrier frequency) instead of conventional
1
CAL ACQ TRK high rate simulator.
(a)
Simulation comparisons with a VHDL simulator confirm
(FDCO - f0)/FREF

1/2
both the validity and the speed of this model.
0 Such a model will be used to analyse several aspects of
(b)
-1/2
(c) this ADPLL and select a set of parameters optimizing its
performance.
-1
0 2000 4000 6000 8000 10000 12000 14000 16000
t/Tref
REFERENCES
1/10 0
(b) (c) [1] R. B. Staszeswski and P. T. Balsara, “Phase-Domain All-
(FDCO - f0)/FREF
(FDCO - f0)/FREF

1/20 Digital Phase-Locked Loop,” IEEE trans. on circuits and


-1/80
System, vol. 52, no. 3, pp. 159-163, March 2005.
0 [2] R. B. Staszewski, C-M. Hung, D. Leipold and P. T. Balsara,
-1/40 -1/40
“A first Multigigahertz Digitally Controlled Oscillator for
1920 1940 1960 1980 4000 5000 6000 7000 8000
Wireless Applications,” IEEE Trans. on Microwave Theory
t/Tref t/Tref
and Techniques, vol. 51, no. 11, pp. 2154-2164, Nov 2003.
Fig 6. Locking sequence (a) and zoom (b, c) on transient at the [3] R. B. Staszewski, D. Leipold, C-M. Hung and P. T. Balsara,
modes shifts “TDC-Based Frequency Synthesizer for Wireless
Applications,” IEEE RFIC Symposium, pp. 215-218, 2004.

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