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VLSI System Design: 06-2757575 X 62371 Kjlee@mail - Ncku.edu - TW

This document outlines the course VLSI System Design taught by Professor KJ Lee at National Cheng Kung University. The course covers topics such as design methodology, Verilog hardware description language, combinational and sequential logic components, non-pipelined and pipelined CPU design, IP design, cache memory design, synthesis, simulation, verification, electronic system level design, and testing. Students will complete design homework assignments and a final project using EDA tools like Verilog simulators and synthesis tools on the university workstations. The class meets either from 6:10-9:00 PM or 7:10-10:00 PM on Mondays.

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333 views

VLSI System Design: 06-2757575 X 62371 Kjlee@mail - Ncku.edu - TW

This document outlines the course VLSI System Design taught by Professor KJ Lee at National Cheng Kung University. The course covers topics such as design methodology, Verilog hardware description language, combinational and sequential logic components, non-pipelined and pipelined CPU design, IP design, cache memory design, synthesis, simulation, verification, electronic system level design, and testing. Students will complete design homework assignments and a final project using EDA tools like Verilog simulators and synthesis tools on the university workstations. The class meets either from 6:10-9:00 PM or 7:10-10:00 PM on Mondays.

Uploaded by

sckid
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI System Design

06-2757575 X 62371 [email protected]


VLSI TEST LAB. NCKU-EE KJLEE

Fields in NCKU EE
Devices & Materials Design Simulation Verification Testing Debugging

VLSI/CAD
Communication
HDTV Wireless Personal comm. DSP Digital TV

Computer Power
Power IC Micro motors Powermanagement CPU Memory Peripheral Robotics Multimedia Fuzzy control CD-ROM Simulation- DVD engines TV-game

Control Instrument
Micro sensors Neural network Medical equipment
Class0.2

VLSI System Design

NCKUEE-KJLEE

Contents
Introduction Design Domain/Methodology/Flow Verilog Hardware Description Language Combinational & Sequential Logic Components Design of a Non-Pipelined CPU Design of a Pipelined CPU IP Design / Coding style Design of Cache Memory Synthesis / Optimization Simulation and Verification Electronic System Level Design Testing / Design for Testability
Class0.3

Introduction Design Method Verilog Logic NPL-CPU PL-CPU IP-design Cache Synthesis Simulation ESL Testing

VLSI System Design

NCKUEE-KJLEE

Reference Books
1. Digital Design and Synthesis with Verilog HDL, 1993 (?) by E. Sternheim, R. Singh, R. Madhavan, Y. Trivedi. 2. Computer Organization & Design: the Hardware/Software Interface, 2005, 3nd Edition, by D.A. Patterson & J.L. Hennessy. 3. The Verilog Hardware Description Language 4th Edition 1998, by Donald E. Thomas & Philip R. Moorby. 4. Verilog-XL Training Manual, 2006 or 2007, Edited by CIC. 5. Reuse Methodology Manual (RMM), 2002, 3rd Edition, by M. Keating & P. Bricaud. 6. Principles of CMOS VLSI Design, 2005, 3rd Edition, by N. Weste and D. Harris. 7. Any Verilog Handbook.

VLSI System Design

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NCKUEE-KJLEE

Class Requirements
Pre-requisite classes:
Basic Computer Concepts, Logic Systems Grading: (Tentative)
5~6 sets of design homework (20-30%) Midterm & final exams (40-50%) Final Project (group of 4-6) (30-35%)

Teaching Assistants:
To be announced.
(62400 2827 CM95502)

Web site: to be announced in class


VLSI System Design Class0.5 NCKUEE-KJLEE

Environment to Do Your Homework & Project


Workstation
Unix system How to use workstation?
CIC Training Classroom, 4F, EE building Connected to the workstations in the CIC training classroom with PCs in EE PC room
The software, xwin, is needed.

Personal computer
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VLSI System Design

NCKUEE-KJLEE

How to Use Workstation?(1/2)


For CIC training classroom Enter your account (will be announced) password:

VLSI System Design

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NCKUEE-KJLEE

How to Use Workstation?(2/2)

You can enter commands here

VLSI System Design

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NCKUEE-KJLEE

Related EDA (Electronic Design Automation) Tools


Verilog simulator Waveform viewer
verilogXL (Cadence) simvision (Cadence) or nWave (SpringSoft, ) debussy (SpringSoft)

HDL Debug & Analysis Logic synthesis Layout


dv (Design Vision, Synopsys) encounter (SOC Encounter, Cadence) calibre (Mentor Graphics )
Class0.9 NCKUEE-KJLEE

VLSI System Design

Verilog Code Writing

VLSI System Design

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Waveform

VLSI System Design

Class0.11

NCKUEE-KJLEE

Logic Synthesis

VLSI System Design

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Layout

VLSI System Design

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Discussion: Class Time


Original
8-A (4:10 P.M. to 7:00 P.M.) on Monday

Options
A-C (6:10 P.M. to 9:00 P.M.) on Monday B-D (7:10 P.M. to 10:00 P.M.) on Monday

VLSI System Design

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NCKUEE-KJLEE

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