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Lab Manual 7 Vlsi

The document introduces behavioral modeling in Verilog, describing behavioral models that model logic at a higher level compared to RTL and structural models, it discusses the different types of procedural blocks in Verilog including initial and always blocks, and provides an example of modeling a 4 to 1 multiplexer using case statements. The lab task asks students to model a 16 to 1 multiplexer using case statements based on a 2 bit input comparator example provided.

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62 views6 pages

Lab Manual 7 Vlsi

The document introduces behavioral modeling in Verilog, describing behavioral models that model logic at a higher level compared to RTL and structural models, it discusses the different types of procedural blocks in Verilog including initial and always blocks, and provides an example of modeling a 4 to 1 multiplexer using case statements. The lab task asks students to model a 16 to 1 multiplexer using case statements based on a 2 bit input comparator example provided.

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USMAN INSTITUTE OF TECHNOLOGY HAMDARD UNIVERSITY DEPARTMENT OF ELECTRONICS ENGINEERING

LAB MANUAL 7 FALL 2011

Engr Atif Fareed Engr Areeb Ahmed Engr Kashif Ali

EE-401-VLSI DESIGN
OBJECTIVE:

Introduction to Behavioral Modeling


STUDENT NAME: _____________________________________________________ SEMESTER: __________________________________________________________ ROLL NO: ___________________________________________________________ DATE OF EXPERIMENT: ______________________________________________ REPORT SUBMITTED ON: _____________________________________________

MARKS OBTAINED: ___________________________________________________ REMARKS IF ANY: ____________________________________________________ SIGNATURE: _________________________________________________________

Introduction To Behavioral Modeling


Behavioral Models : Higher level of modeling where behavior of logic is modeled. RTL Models : Logic is modeled at register level Structural Models : Logic is modeled at both register level and gate level.

Verilog behavioral code is inside procedure blocks, but there is an exception: some behavioral code also exist outside procedure blocks. We can see this in detail as we make progress. There are two types of procedural blocks in Verilog:

initial : initial blocks execute only once at time zero (start execution at time zero). always : always blocks loop to execute over and over again; in other words, as the name suggests, it executes always Procedural assignment statements assign values to reg, integer, real, or time variables and can not assign values to nets (wire data types). You can assign to a register (reg data type) the value of a net (wire), constant, another register, or a specific value.

The begin - end keywords


Group several statements together. Cause the statements to be evaluated sequentially (one at a time) o Any timing within the sequential groups is relative to the previous statement. o Delays in the sequence accumulate (each delay is added to the previous delay) o Block finishes after the last statement in the block.

Blocking assignments are executed in the order they are coded, hence they are sequential. Since they block the execution of next statment, till the current statement is executed, they are called blocking assignments. Assignment are made with "=" symbol. Example a = b; Nonblocking assignments are executed in parallel. Since the execution of next statement is not blocked due to execution of current statement, they are called nonblocking statement. Assignments are made with "<=" symbol. Example a <= b;

The Conditional Statement if-else The if - else statement controls the execution of other statements. In programming language like c, if - else controls the flow of program. When more than one statement needs to be executed for an if condition, then we need to use begin and end as seen in earlier examples. Syntax : if if (condition)

statements; Syntax : if-else if (condition) statements; else statements; Syntax : nested if-else-if if (condition) statements; else if (condition) statements; ................ ................ else statements;

Example-1:
module simple_if(); reg latch; wire enable,din; always @ (enable or din) if (enable) begin latch <= din; end endmodule

The Case Statement The case statement compares an expression to a series of cases and executes the statement or statement group associated with the first matching case:

case statement supports single or multiple statements. Group multiple statements using begin and end keywords.

Syntax of a case statement look as shown below. case () < case1 > : < statement > < case2 > : < statement > ..... default : < statement > endcase

The case statement can also act like a many-to-one multiplexer. To understand this, let us model the 4-to-1 multiplexer, using case statements. Notice that an 8-to-1 or 16-to-1 multiplexer can also be easily implemented by case statements.

Example-2 4-to-1 Multiplexer with Case Statement

Example-3

Lab Task-: Objective


Make a 16 to 1 multiplexer by using case statement

Hint (Given below coding is for 2-bit input comparator)


module comparator (a0,a1,b0,b1,G,E,L); input a0,a1,b0,b1; output G,E,L; reg begin L<={a1,a0}<{b1,b0}; // greater than if ({a1,a0}>{b1,b0}) G<= 1; else G<= 0; // equivalent to G={a1,a0}>{b1,b0}; E<={a1,a0}=={b1,b0}; //logical equality end endmodule // less than G,E,L; always@(a0 or a1 or b0 or b1)

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