CPS 104 Computer Organization and Programming Lecture- 29: Virtual Memory

March 29, 2004 Gershon Kedem http://kedem.duke.edu/cps104/Lectures

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Admin.

Homework-6: Is Due today. Homework -7: is posted, Due next Monday

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Virtual Memory

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Memory System Management Problems

Different Programs have different memory requirements. u How to manage program placement? Different machines have different amount of memory. u How to run the same program on many different machines? At any given time each machine runs a different set of programs. u How to fit the program mix into memory? Reclaiming unused memory? Moving code around? The amount of memory consumed by each program is dynamic (changes over time) u How to effect changes in memory location: add or subtract space? Program bugs can cause a program to generate reads and writes outside the program address space. u How to protect one program from another?

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Virtual Memory
Provides illusion of very large memory Sum of the memory of many jobs greater than physical memory Address space of each job larger than physical memory Allows available (fast and expensive) physical memory to be well utilized. Simplifies memory management: code and data movement, protection, ... (main reason today) Exploits memory hierarchy to keep average access time low. Involves at least two storage levels: main and secondary Virtual Address -- address used by the programmer Virtual Address Space -- collection of such addresses Memory Address -- address in physical memory also known as physical address or real address
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Review: A Simple Programs Memory 2n-1 Layout

Stack
5

What are the possible addresses generated by the program? How big is our DRAM? Is there more than one program running? If so, how do we allocate memory to each?

Data
3

Text
add r,s1,s2

Reserved

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Paged Virtual Memory: Main Idea

Divide memory (virtual and physical) into fixed size blocks (Pages, Frames).
u u

Pages in Virtual space. Frames in Physical space.

Make page size a power of 2: (page size = 2k) All pages in the virtual address space are contiguous. Pages can be mapped into physical Frames in any order. Some of the pages are in main memory (DRAM), some of the pages are on secodary memory (disk). All programs are written using Virtual Memory Address Space. The hardware does on-the-fly translation between virtual and physical address spaces. Use a Page Table to translate between Virtual and Physical addresses

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Basic Issues in Virtual Memory System Design

size of information blocks (pages)that are transferred from secondary to main storage (M) block of information brought into M, and M is full, then some region of M must be released to make room for the new block --> replacement policy which region of M is to hold the new block --> placement policy missing item fetched from secondary memory only on the occurrence of a fault --> demand load policy
cache reg

mem

disk

pages

frame Paging Organization virtual and physical address space partitioned into blocks of equal size frames pages
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Virtual and Physical Memories

Physical Memory Virtual Memory
Frame-0 Page-0 Frame-1 Page-1 Frame-2 Page-2 Frame-3 Page-3 Frame-4 Frame-5

Disk
Page -2

Page N-2 Page N-1 Page N

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Virtual to Physical Address translation

Page size: 4K

Virtual Address
31 Virtual Page Number 11 Page offset 0

Page Table

29 Physical Frame Number

11 Page offset

Physical Address
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Address Map
V = {0, 1, . . . , n - 1} virtual address space M = {0, 1, . . . , m - 1} physical address space MAP: V --> M U {0} address mapping function MAP(a) = a' if data at virtual address a is present in physical address a' and a' in M = 0 if data at virtual address a is not present in M missing item fault Processor Addr. Trans. Mechanism 0 a' physical address
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n>m

fault handler Main Memory Secondary Memory

OS performs this transfer

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The page table

Virtual Address
31 Virtual Page Number
Page table reg V D AC Frame number Access Control

1211 Page offset

Dirty bit 1 0

Valid bit

29 Physical Frame Number

11 Page offset

Physical Address
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Address Mapping Algorithm

If V = 1 then page is in main memory at frame address stored in table else address located page in secondary memory Access Control R = Read-only, R/W = read/write, X = execute only If kind of access not compatible with specified access rights, then protection_violation_fault If valid bit not set then page fault Protection Fault: access control violation; causes trap to hardware, or software fault handler Page Fault: page not resident in physical memory, also causes a trap; usually accompanied by a context switch: current process suspended while page is fetched from secondary storage e.g., VAX 11/780 each process sees a 4 gigabyte (232 bytes) virtual address space 1/2 for user regions, 1/2 for a system wide name space shared by all processes. page size is 512 bytes (too small)
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Optimal Page Size

Choose page size that minimizes fragmentation (partial use of pages) large page size => internal fragmentation more severe BUT decreases the # of pages / name space => smaller page tables In general, the trend is towards larger page sizes because -- Memories get larger as the price of RAM drops. -- The gap between processor speed and disk speed grow wider. -- Programmers demand larger virtual address spaces (larger program) -- Smaller page table. Most machines at 4K-8K byte pages today, with page sizes likely to increase

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Fragmentation
Page Table Fragmentation occurs when page tables become very large because of large virtual address spaces; linearly mapped page tables could take up sizable chunk of memory 21 9 EX: VAX Architecture (late 1970s) Disp XX Page Number NOTE: this implies that page table could require up to 2 ^21 entries, each on the order of 4 bytes long (8 M Bytes) Alternatives to linear page table: (1) Hardware associative mapping: requires one entry per page frame (O(|M|)) rather than per virtual page (O(|N|)) (2) "software" approach based on a hash table (inverted page table) page# disp Present Access Page# Phy Addr Page Table 00 P0 region of user process 01 P1 region of user process 10 system name space

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associative or hashed lookup on the page number field Spring 2004 GK

Page Replacement Algorithms

Just like cache block replacement! Least Recently Used: -- selects the least recently used page for replacement -- requires knowledge about past references, more difficult to implement (thread through page table entries from most recently referenced to least recently referenced; when a page is referenced it is placed at the head of the list; the end of the list is the page to replace) -- good performance, recognizes principle of locality

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Page Replacement (Continued)

Not Recently Used: Associated with each page is a reference flag such that ref flag = 1 if the page has been referenced in recent past = 0 otherwise -- if replacement is necessary, choose any page frame such that its reference bit is 0. This is a page that has not been referenced in the recent past -- clock implementation of NRU: 10 10 10 0 0 page table entry last replaced pointer (lrp) if replacement is to take place, advance lrp to next entry (mod table size) until one with a 0 bit is found; this is the target for replacement; As a side effect, all examined PTE's have their reference bits set to zero.

page table entry

ref bit An optimization is to search for a page that is both not recently referenced AND not dirty. Why?
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Virtual Address and a Cache

VA CPU Translation hit data PA Cache miss Main Memory

It takes an extra memory access to translate VA to PA This makes cache access very expensive, and this is the "innermost loop" that you want to go as fast as possible

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Translation Lookaside Buffer (TLB)

A way to speed up translation is to use a special cache of recently used page table entries -- this has many names, but the most frequently used is Translation Lookaside Buffer or TLB Virtual Address Physical Address Dirty Ref Valid Access

TLB access time comparable to cache access time (much less than main memory access time) Typical TLB is 64-256 entries fully associative cache with random replacement

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Translation Look-Aside Buffers

Just like any other cache, the TLB can be organized as fully associative, set associative, or direct mapped TLBs are usually small, typically not more than 128 - 256 entries even on high end machines. This permits fully associative lookup on these machines. Many mid-range machines use small n-way set associative organizations. VA CPU TLB Lookup miss Translation with a TLB Translation data 1/2 t
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hit PA Cache hit

miss Main Memory

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TLB Design

Must be fast, not increase critical path Must achieve high hit ratio Generally small highly associative (64-128 entries FA cache) Mapping change u page added/removed from physical memory u processor must invalidate the TLB entry (special instructions) PTE is per process entity u Multiple processes with same virtual addresses u Context Switches? Flush TLB Add ASID (PID) u part of processor state, must be set on context switch

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Hardware Managed TLBs CPU

TLB

Control

Hardware Handles TLB miss Dictates page table organization Complicated state machine to walk page table Exception only if access violation

Memory

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Software Managed TLBs CPU

TLB

Control

Memory

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Software Handles TLB miss u OS reads translations from Page Table and puts them in TLB u special instructions Flexible page table organization Simple Hardware to detect Hit or Miss GK Spring Exception if TLB miss 2004 or access violation

Choosing a Page Size

What if page is too small? Too many misses BIG page tables What if page is too big? Fragmentation u dont use all of the page, but cant use that DRAM for other pages u want to minimize fragmentation (get good utilization of physical memory) Smaller page tables

Trend it toward larger pages u increasing gap between CPU/DRAM/DISK

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Reducing Translation Time

Machines with TLBs go one step further to reduce # cycles/cache access They overlap the cache access with the TLB access Works because high order bits of the VA are used to look in the TLB while low order bits are used as index into cache

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Overlapped Cache & TLB Access

32

TLB

assoc lookup

index

Cache

PA

Hit/ Miss

12 20 page # disp =

PA

Data

Hit/ Miss

IF cache hit AND (cache tag = PA) then deliver data to CPU ELSE IF [cache miss OR (cache tag = PA)] and TLB hit THEN access memory with the PA from the TLB ELSE do standard VA translation
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Problems With Overlapped TLB Access

Overlapped access only works as long as the address bits used to index into the cache do not change as the result of VA translation This usually limits things to small caches, large page sizes, or high n-way set associative caches if you want a large cache Example: suppose everything the same except that the cache is increased to 8 K bytes instead of 4 K: 11 2
cache index

00 This bit is changed by VA translation, but is needed for cache lookup

20 virt page #

12 disp

Solutions: go to 8K byte page sizes; go to 2 way set associative cache; or SW guarantee VA[13]=PA[13] 1K 4 4 2 way set assoc. cache
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10
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More on Selecting a Page Size

Reasons for larger page size u Page table size is inversely proportional to the page size. u faster cache hit time when cache page size; bigger page => bigger cache (no aliasing problem). u Transferring larger pages to or from secondary storage, is more efficient (Higher bandwidth) u The number of TLB entries is restricted by clock cycle time, so a larger page size reduces TLB misses. Reasons for a smaller page size u dont waste storage; data must be contiguous within page. u quicker process start for small processes(?) Hybrid solution: multiple page sizes: Alpha, UltraSPARC: 8KB, 64KB, 512 KB, 4 MB pages

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Memory Protection

Paging Virtual memory provides protection by: u Each process (user or OS) has different virtual memory space. u The OS maintain the page tables for all processes. u A reference outside the process allocated space cause an exception that lets the OS decide what to do. u Memory sharing between processes is done via different Virtual spaces but common physical frames.

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Putting it together: The SparcStation 20:

The SparcStation 20 has the following memory system. Caches: Two level-1 caches: I-cache and D-cache

Parameter Organization Page size Line size Replacement

Instruction cache 20Kbyte 5-way SA 4K bytes 8 bytes Pseudo LRU

Data cache 16KB 4-way SA 4K bytes 4 bytes Pseudo LRU

TLB: 64 entry Fully Associative TLB, Random replacement t External Level-2 Cache: 1M-byte, Direct Map, 128 byte blocks, 32-byte sub-blocks.

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SparcStation 20 Data Access

Virtual Address
20 12 10 2 tag data

Data Cache
tag tag tag

4 bytes

1K

10

= Physical Address
To Memory 24 20

Data Select

TLB
= = =
tag0 tag1 tag2 To CPU

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SparcStation 20: Instruction Memory

Instruction Address
20 12 10 2 tag data

Instruction Cache
tag tag tag

4 bytes tag

1K

10

= Physical Address
36 To Memory 24 20

Instruction Select

TLB
= = =
tag0 tag1 tag2 To CPU (instruction register)

=
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