Intel Xeon Processor E5-1600/ E5-2600/E5-4600 Product Families

Datasheet - Volume One

May 2012

Reference Number: 326508, Revision: 002

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family, not across different processor families. See http://www.intel.com/products/processor%5Fnumber/ for details. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Intel, Xeon, Intel SpeedStep, Intel Core, and the Intel logo are trademarks of Intel Corporation in the U. S. and other countries. *Other names and brands may be claimed as the property of others. Copyright 2009-2012, Intel Corporation. All rights reserved.

Intel Xeon Processor E5-1600/ E5-2600/E5-4600 Product Families Datasheet Volume One

Contents
1 Overview ................................................................................................................. 13 1.1 Introduction ..................................................................................................... 13 1.1.1 Processor Feature Details ........................................................................ 14 1.1.2 Supported Technologies .......................................................................... 14 1.2 Interfaces ........................................................................................................ 15 1.2.1 System Memory Support ......................................................................... 15 1.2.2 PCI Express* ......................................................................................... 16 1.2.3 Direct Media Interface Gen 2 (DMI2)......................................................... 17 1.2.4 Intel QuickPath Interconnect (Intel QPI) .............................................. 18 1.2.5 Platform Environment Control Interface (PECI) ........................................... 18 1.3 Power Management Support ............................................................................... 19 1.3.1 Processor Package and Core States........................................................... 19 1.3.2 System States Support ........................................................................... 19 1.3.3 Memory Controller.................................................................................. 19 1.3.4 PCI Express ........................................................................................... 19 1.3.5 Intel QPI ............................................................................................... 19 1.4 Thermal Management Support ............................................................................ 19 1.5 Package Summary............................................................................................. 20 1.6 Terminology ..................................................................................................... 20 1.7 Related Documents ........................................................................................... 22 1.8 State of Data .................................................................................................... 23 Interfaces................................................................................................................ 25 2.1 System Memory Interface .................................................................................. 25 2.1.1 System Memory Technology Support ........................................................ 25 2.1.2 System Memory Timing Support............................................................... 25 2.2 PCI Express* Interface....................................................................................... 26 2.2.1 PCI Express* Architecture ....................................................................... 26 2.2.2 PCI Express* Configuration Mechanism ..................................................... 27 2.3 DMI2/PCI Express* Interface .............................................................................. 28 2.3.1 DMI2 Error Flow ..................................................................................... 28 2.3.2 Processor/PCH Compatibility Assumptions.................................................. 28 2.3.3 DMI2 Link Down..................................................................................... 28 2.4 Intel QuickPath Interconnect............................................................................... 28 2.5 Platform Environment Control Interface (PECI) ...................................................... 30 2.5.1 PECI Client Capabilities ........................................................................... 30 2.5.2 Client Command Suite ............................................................................ 31 2.5.3 Client Management................................................................................. 69 2.5.4 Multi-Domain Commands ........................................................................ 74 2.5.5 Client Responses .................................................................................... 75 2.5.6 Originator Responses .............................................................................. 76 2.5.7 DTS Temperature Data ........................................................................... 76 Technologies ........................................................................................................... 79 3.1 Intel Virtualization Technology (Intel VT) ........................................................ 79 3.1.1 Intel VT-x Objectives .............................................................................. 79 3.1.2 Intel VT-x Features................................................................................. 80 3.1.3 Intel VT-d Objectives .............................................................................. 80 3.1.4 Intel Virtualization Technology Processor Extensions ................................... 81 3.2 Security Technologies ........................................................................................ 81 3.2.1 Intel Trusted Execution Technology........................................................ 81 3.2.2 Intel Trusted Execution Technology Server Extensions .............................. 82 3.2.3 Intel Advanced Encryption Standard Instructions (Intel AES-NI).............. 82

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3.3 3.4 3.5 3.6 3.7 3.8 4

3.2.4 Execute Disable Bit .................................................................................83 Intel Hyper-Threading Technology .....................................................................83 Intel Turbo Boost Technology ...........................................................................83 3.4.1 Intel Turbo Boost Operating Frequency ...................................................83 Enhanced Intel SpeedStep Technology ...............................................................84 Intel Intelligent Power Technology.....................................................................84 Intel Advanced Vector Extensions (Intel AVX) ..................................................84 Intel Dynamic Power Technology .........................................................................85

Power Management .................................................................................................87 4.1 ACPI States Supported .......................................................................................87 4.1.1 System States........................................................................................87 4.1.2 Processor Package and Core States ...........................................................87 4.1.3 Integrated Memory Controller States .........................................................88 4.1.4 DMI2/PCI Express* Link States.................................................................89 4.1.5 Intel QuickPath Interconnect States ..........................................................89 4.1.6 G, S, and C State Combinations................................................................90 4.2 Processor Core/Package Power Management .........................................................90 4.2.1 Enhanced Intel SpeedStep Technology.......................................................90 4.2.2 Low-Power Idle States.............................................................................91 4.2.3 Requesting Low-Power Idle States ............................................................92 4.2.4 Core C-states .........................................................................................92 4.2.5 Package C-States ...................................................................................94 4.2.6 Package C-State Power Specifications........................................................97 4.3 System Memory Power Management ....................................................................98 4.3.1 CKE Power-Down ....................................................................................98 4.3.2 Self Refresh ...........................................................................................98 4.3.3 DRAM I/O Power Management ..................................................................99 4.4 DMI2/PCI Express* Power Management ................................................................99 Thermal Management Specifications ...................................................................... 101 5.1 Package Thermal Specifications ......................................................................... 101 5.1.1 Thermal Specifications........................................................................... 101 5.1.2 TCASE and DTS Based Thermal Specifications........................................... 103 5.1.3 Processor Thermal Profiles ..................................................................... 104 5.1.4 Embedded Server Processor Thermal Profiles............................................ 130 5.1.5 Thermal Metrology ................................................................................ 133 5.2 Processor Core Thermal Features ....................................................................... 135 5.2.1 Processor Temperature.......................................................................... 135 5.2.2 Adaptive Thermal Monitor ...................................................................... 135 5.2.3 On-Demand Mode ................................................................................. 137 5.2.4 PROCHOT_N Signal ............................................................................... 137 5.2.5 THERMTRIP_N Signal ............................................................................ 138 5.2.6 Integrated Memory Controller (IMC) Thermal Features............................... 138 Signal Descriptions ................................................................................................ 141 6.1 System Memory Interface Signals ...................................................................... 141 6.2 PCI Express* Based Interface Signals ................................................................. 142 6.3 DMI2/PCI Express* Port 0 Signals ...................................................................... 144 6.4 Intel QuickPath Interconnect Signals .................................................................. 144 6.5 PECI Signal ..................................................................................................... 145 6.6 System Reference Clock Signals ........................................................................ 145 6.7 JTAG and TAP Signals....................................................................................... 145 6.8 Serial VID Interface (SVID) Signals .................................................................... 146 6.9 Processor Asynchronous Sideband and Miscellaneous Signals................................. 146 6.10 Processor Power and Ground Supplies ................................................................ 149

Intel Xeon Processor E5-1600/ E5-2600/E5-4600 Product Families Datasheet Volume One

Electrical Specifications ......................................................................................... 151 7.1 Processor Signaling ......................................................................................... 151 7.1.1 System Memory Interface Signal Groups ................................................. 151 7.1.2 PCI Express* Signals ............................................................................ 151 7.1.3 DMI2/PCI Express* Signals.................................................................... 151 7.1.4 Intel QuickPath Interconnect (Intel QPI) .................................................. 151 7.1.5 Platform Environmental Control Interface (PECI) ...................................... 152 7.1.6 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN)....................... 152 7.1.7 JTAG and Test Access Port (TAP) Signals ................................................. 153 7.1.8 Processor Sideband Signals ................................................................... 153 7.1.9 Power, Ground and Sense Signals........................................................... 153 7.1.10 Reserved or Unused Signals................................................................... 158 7.2 Signal Group Summary .................................................................................... 158 7.3 Power-On Configuration (POC) Options............................................................... 162 7.4 Fault Resilient Booting (FRB)............................................................................. 163 7.5 Mixing Processors............................................................................................ 163 7.6 Flexible Motherboard Guidelines (FMB) ............................................................... 164 7.7 Absolute Maximum and Minimum Ratings ........................................................... 164 7.7.1 Storage Conditions Specifications ........................................................... 165 7.8 DC Specifications ............................................................................................ 166 7.8.1 Voltage and Current Specifications.......................................................... 167 7.8.2 Die Voltage Validation ........................................................................... 173 7.8.3 Signal DC Specifications ........................................................................ 174 7.9 Waveforms..................................................................................................... 180 7.10 Signal Quality ................................................................................................. 181 7.10.1 DDR3 Signal Quality Specifications ......................................................... 182 7.10.2 I/O Signal Quality Specifications............................................................. 182 7.10.3 Intel QuickPath Interconnect Signal Quality Specifications.......................... 182 7.10.4 Input Reference Clock Signal Quality Specifications................................... 182 7.10.5 Overshoot/Undershoot Tolerance............................................................ 182 Processor Land Listing........................................................................................... 187 8.1 Listing by Land Name ...................................................................................... 187 8.2 Listing by Land Number ................................................................................... 212 Package Mechanical Specifications ........................................................................ 237 9.1 Package Mechanical Drawing............................................................................. 237 9.2 Processor Component Keep-Out Zones ............................................................... 241 9.3 Package Loading Specifications ......................................................................... 241 9.4 Package Handling Guidelines............................................................................. 241 9.5 Package Insertion Specifications........................................................................ 241 9.6 Processor Mass Specification ............................................................................. 242 9.7 Processor Materials.......................................................................................... 242 9.8 Processor Markings.......................................................................................... 242 Boxed Processor Specifications ............................................................................. 243 10.1 Introduction ................................................................................................... 243 10.1.1 Available Boxed Thermal Solution Configurations ...................................... 243 10.1.2 Intel Thermal Solution STS200C (Passive/Active Combination Heat Sink Solution) ...................................... 243 10.1.3 Intel Thermal Solution STS200P and STS200PNRW (Boxed 25.5 mm Tall Passive Heat Sink Solutions).................................... 244 10.2 Mechanical Specifications ................................................................................. 245 10.2.1 Boxed Processor Heat Sink Dimensions and Baseboard Keepout Zones ........ 245 10.2.2 Boxed Processor Retention Mechanism and Heat Sink Support (ILM-RS) ...... 254 10.3 Fan Power Supply [STS200C]............................................................................ 254 10.3.1 Boxed Processor Cooling Requirements ................................................... 255 10.4 Boxed Processor Contents ................................................................................ 257

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Intel Xeon Processor E5-1600/ E5-2600/E5-4600 Product Families Datasheet Volume One

Figures
1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 2-32 2-33 2-34 2-35 2-36 2-37 2-38 2-39 2-40 2-41 2-42 2-43 2-44 2-45 2-46 Intel Xeon Processor E5-2600 Product Family on the 2 Socket Platform ...........................................................................................................14 PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2)...................17 PCI Express* Layering Diagram ...........................................................................26 Packet Flow through the Layers ...........................................................................27 Ping() ..............................................................................................................32 Ping() Example..................................................................................................32 GetDIB() ..........................................................................................................32 Device Info Field Definition .................................................................................33 Revision Number Definition .................................................................................33 GetTemp()........................................................................................................34 GetTemp() Example ...........................................................................................35 RdPkgConfig() ...................................................................................................36 WrPkgConfig()...................................................................................................37 DRAM Thermal Estimation Configuration Data........................................................40 DRAM Rank Temperature Write Data ....................................................................41 The Processor DIMM Temperature Read / Write .....................................................42 Ambient Temperature Reference Data ..................................................................42 Processor DRAM Channel Temperature .................................................................43 Accumulated DRAM Energy Data..........................................................................43 DRAM Power Info Read Data ...............................................................................44 DRAM Power Limit Data ......................................................................................45 DRAM Power Limit Performance Data....................................................................45 CPUID Data ......................................................................................................49 Platform ID Data ...............................................................................................49 PCU Device ID...................................................................................................49 Maximum Thread ID...........................................................................................50 Processor Microcode Revision ..............................................................................50 Machine Check Status ........................................................................................50 Package Power SKU Unit Data .............................................................................50 Package Power SKU Data ....................................................................................52 Package Temperature Read Data .........................................................................52 Temperature Target Read ...................................................................................53 Thermal Status Word .........................................................................................54 Thermal Averaging Constant Write / Read .............................................................54 Current Config Limit Read Data ...........................................................................55 Accumulated Energy Read Data ...........................................................................55 Power Limit Data for VCC Power Plane ..................................................................56 Package Turbo Power Limit Data ..........................................................................57 Package Power Limit Performance Data ................................................................57 Efficient Performance Indicator Read ....................................................................58 ACPI P-T Notify Data ..........................................................................................58 Caching Agent TOR Read Data.............................................................................59 DTS Thermal Margin Read...................................................................................59 Processor ID Construction Example ......................................................................61 RdIAMSR()........................................................................................................61 PCI Configuration Address...................................................................................64 RdPCIConfig() ...................................................................................................64 PCI Configuration Address for local accesses..........................................................66

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2-47 2-48 2-49 2-50 4-1 4-2 4-3 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9

RdPCIConfigLocal()............................................................................................ 66 WrPCIConfigLocal() ........................................................................................... 68 The Processor PECI Power-up Timeline() .............................................................. 70 Temperature Sensor Data Format........................................................................ 76 Idle Power Management Breakdown of the Processor Cores..................................... 91 Thread and Core C-State Entry and Exit ............................................................... 91 Package C-State Entry and Exit ........................................................................... 95 Tcase: 8-Core 150W Thermal Profile, Workstation Platform SKU Only ..................... 105 DTS: 8-Core 150W Thermal Profile, Workstation Platform SKU Only ....................... 105 Tcase: 8-Core 135W Thermal Profile 2U ............................................................. 107 DTS: 8-Core 135W Thermal Profile 2U................................................................ 108 Tcase: 8/6-Core 130W Thermal Profile 1U .......................................................... 110 DTS: 8-Core 130W Thermal Profile 1U................................................................ 110 DTS: 6-Core 130W Thermal Profile 1U................................................................ 111 Tcase: 6-Core 130W 1S WS Thermal Profile ........................................................ 112 DTS: 6-Core 130W 1S WS Thermal Profile .......................................................... 113 Tcase: 8-Core 115W Thermal Profile 1U ............................................................. 115 DTS: 8-Core 115W Thermal Profile 1U................................................................ 115 Tcase: 8/6-Core 95W Thermal Profile 1U ............................................................ 117 DTS: 8-Core 95W Thermal Profile 1U ................................................................. 117 DTS: 6-Core 95W Thermal Profile 1U ................................................................. 118 Tcase: 8-Core 70W Thermal Profile 1U ............................................................... 119 DTS: 8-Core 70W Thermal Profile 1U ................................................................. 120 Tcase: 6-Core 60W Thermal Profile 1U ............................................................... 121 DTS: 6-Core 60W Thermal Profile 1U ................................................................. 122 Tcase: 4-Core 130W Thermal Profile 2U ............................................................. 123 DTS: 4-Core 130W Thermal Profile 2U................................................................ 124 Tcase: 4-Core 130W 1S WS Thermal Profile ........................................................ 126 DTS: 4-Core 130W 1S WS Thermal Profile .......................................................... 126 Tcase: 4/2-Core 80W Thermal Profile 1U ............................................................ 128 DTS: 4-Core 80W Thermal Profile 1U ................................................................. 128 DTS: 2-Core 80W Thermal Profile 1U ................................................................. 129 Tcase: 8-Core LV95W Thermal Profile, Embedded Server SKU ............................... 131 Tcase: 8-Core LV70W Thermal Profile, Embedded Server SKU ............................... 132 Case Temperature (TCASE) Measurement Location .............................................. 134 Frequency and Voltage Ordering........................................................................ 136 Input Device Hysteresis ................................................................................... 152 VR Power-State Transitions............................................................................... 156 8/6-Core: VCC Static and Transient Tolerance Loadlines ....................................... 170 4/2-Core: Processor VCC Static and Transient Tolerance Loadlines ......................... 172 Load Current Versus Time ................................................................................ 173 VCC Overshoot Example Waveform.................................................................... 174 BCLK{0/1} Differential Clock Crosspoint Specification .......................................... 180 BCLK{0/1} Differential Clock Measurement Point for Ringback .............................. 180 BCLK{0/1} Single Ended Clock Measurement Points for Absolute Cross Point and Swing ...................................................................................................... 181 7-10 BCLK{0/1} Single Ended Clock Measurement Points for Delta Cross Point ............... 181 7-11 Maximum Acceptable Overshoot/Undershoot Waveform........................................ 185 9-1 Processor Package Assembly Sketch .................................................................. 237 9-2 Processor Package Drawing Sheet 1 of 2 ............................................................ 239 9-3 Processor Package Drawing Sheet 2 of 2 ............................................................ 240 9-4 Processor Top-Side Markings ........................................................................... 242

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10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12

STS200C Passive/Active Combination Heat Sink (with Removable Fan) ................... 244 STS200C Passive/Active Combination Heat Sink (with Fan Removed)...................... 244 STS200P and STS200PNRW 25.5 mm Tall Passive Heat Sinks ................................ 245 Boxed Processor Motherboard Keepout Zones (1 of 4) .......................................... 246 Boxed Processor Motherboard Keepout Zones (2 of 4) .......................................... 247 Boxed Processor Motherboard Keepout Zones (3 of 4) .......................................... 248 Boxed Processor Motherboard Keepout Zones (4 of 4) .......................................... 249 Boxed Processor Heat Sink Volumetric (1 of 2) .................................................... 250 Boxed Processor Heat Sink Volumetric (2 of 2) .................................................... 251 4-Pin Fan Cable Connector (For Active Heat Sink) ................................................ 252 4-Pin Base Baseboard Fan Header (For Active Heat Sink) ..................................... 253 Fan Cable Connector Pin Out For 4-Pin Active Thermal Solution............................. 255

Tables
1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 Referenced Documents .......................................................................................22 Summary of Processor-specific PECI Commands ....................................................30 Minor Revision Number Meaning ..........................................................................33 GetTemp() Response Definition ...........................................................................35 RdPkgConfig() Response Definition.......................................................................36 WrPkgConfig() Response Definition ......................................................................37 RdPkgConfig() & WrPkgConfig() DRAM Thermal and Power Optimization Services Summary .............................................................................................39 Channel & DIMM Index Decoding .........................................................................41 RdPkgConfig() & WrPkgConfig() CPU Thermal and Power Optimization Services Summary .............................................................................................46 Power Control Register Unit Calculations ...............................................................51 RdIAMSR() Response Definition ...........................................................................62 RdIAMSR() Services Summary.............................................................................62 RdPCIConfig() Response Definition .......................................................................65 RdPCIConfigLocal() Response Definition ................................................................67 WrPCIConfigLocal() Response Definition................................................................68 WrPCIConfigLocal() Memory Controller and IIO Device/Function Support...................69 PECI Client Response During Power-Up .................................................................69 SOCKET ID Strapping .........................................................................................71 Power Impact of PECI Commands vs. C-states.......................................................71 Domain ID Definition..........................................................................................74 Multi-Domain Command Code Reference...............................................................74 Completion Code Pass/Fail Mask ..........................................................................75 Device Specific Completion Code (CC) Definition ....................................................75 Originator Response Guidelines............................................................................76 Error Codes and Descriptions...............................................................................77 System States...................................................................................................87 Package C-State Support ....................................................................................87 Core C-State Support .........................................................................................88 System Memory Power States .............................................................................88 DMI2/PCI Express* Link States............................................................................89 Intel QPI States.................................................................................................89 G, S and C State Combinations............................................................................90 P_LVLx to MWAIT Conversion ..............................................................................92 Coordination of Core Power States at the Package Level..........................................95

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4-10 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 7-1 7-2 7-3 7-4 7-5 7-6 7-7

Package C-State Power Specifications .................................................................. 97 Processor SKU Summary Table ......................................................................... 104 Tcase: 8-Core 150W Thermal Specifications, Workstation Platform SKU Only........... 104 8-Core 150W Thermal Profile, Workstation Platform SKU Only ............................. 106 Tcase: 8-Core 135W Thermal Specifications 2U ................................................... 107 8-Core 135W Thermal Profile Table 2U ............................................................... 108 Tcase: 8/6-Core 130W Thermal Specifications, Workstation/Server Platform ........... 109 8/6-Core 130W Thermal Profile Table 1U ............................................................ 111 Tcase: 6-Core 130W 1S WS Thermal Specifications.............................................. 112 6-Core 130W 1S WS Thermal Profile Table.......................................................... 113 Tcase: 8-Core 115W Thermal Specifications 1U ................................................... 114 8-Core 115W Thermal Profile Table 1U ............................................................... 116 Tcase: 8/6-Core 95W Thermal Specifications, Workstation/Server Platform ............. 116 8/6-Core 95W Thermal Profile Table 1U.............................................................. 118 Tcase: 8-Core 70W Thermal Specifications 1U ..................................................... 119 8-Core 70W Thermal Profile Table 1U................................................................. 120 Tcase: 6-Core 60W Thermal Specifications 1U ..................................................... 121 6-Core 60W Thermal Profile Table 1U................................................................. 122 Tcase: 4-Core 130W Thermal Specifications 2U ................................................... 123 4-Core 130W Thermal Profile Table 2U ............................................................... 124 Tcase: 4-Core 130W 1S WS Thermal Specifications, Workstation/Server Platform .... 125 4-Core 130W 1S WS Thermal Profile Table.......................................................... 127 Tcase: 4/2-Core 80W Thermal Specifications 1U .................................................. 127 4/2-Core 80W Thermal Profile Table 1U.............................................................. 129 Embedded Server Processor Elevated Tcase SKU Summary Table .......................... 130 Tcase: 8-Core LV95W Thermal Specifications, Embedded Server SKU ..................... 130 8-Core LV95W Thermal Profile Table, Embedded Server SKU................................. 131 Tcase: 8-Core LV70W Thermal Specifications, Embedded Server SKU ..................... 132 8-Core LV70W Thermal Profile Table, Embedded Server SKU................................. 133 Memory Channel DDR0, DDR1, DDR2, DDR3....................................................... 141 Memory Channel Miscellaneous ......................................................................... 142 PCI Express* Port 1 Signals .............................................................................. 142 PCI Express* Port 2 Signals .............................................................................. 142 PCI Express* Port 3 Signals .............................................................................. 143 PCI Express* Miscellaneous Signals ................................................................... 143 DMI2 and PCI Express* Port 0 Signals................................................................ 144 Intel QPI Port 0 and 1 Signals ........................................................................... 144 Intel QPI Miscellaneous Signals ......................................................................... 144 PECI Signals ................................................................................................... 145 System Reference Clock (BCLK{0/1}) Signals ..................................................... 145 JTAG and TAP Signals ...................................................................................... 145 SVID Signals .................................................................................................. 146 Processor Asynchronous Sideband Signals .......................................................... 146 Miscellaneous Signals ...................................................................................... 148 Power and Ground Signals ................................................................................ 149 Power and Ground Lands.................................................................................. 154 SVID Address Usage ........................................................................................ 157 VR12.0 Reference Code Voltage Identification (VID) Table .................................... 157 Signal Description Buffer Types ......................................................................... 158 Signal Groups ................................................................................................. 159 Signals with On-Die Termination ....................................................................... 162 Power-On Configuration Option Lands ................................................................ 162

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7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 8-1 8-2 9-1 9-2 9-3 10-1 10-2 10-3

Fault Resilient Booting (Output Tri-State) Signals ................................................. 163 Processor Absolute Minimum and Maximum Ratings ............................................. 164 Storage Condition Ratings................................................................................. 165 Voltage Specification ........................................................................................ 167 Processor Current Specifications ........................................................................ 168 8/6 Core: Processor VCC Static and Transient Tolerance ....................................... 169 4/2-Core: Processor VCC Static and Transient Tolerance ....................................... 170 VCC Overshoot Specifications ............................................................................ 173 DDR3 and DDR3L Signal DC Specifications .......................................................... 174 PECI DC Specifications ..................................................................................... 176 System Reference Clock (BCLK{0/1}) DC Specifications........................................ 176 SMBus DC Specifications................................................................................... 176 JTAG and TAP Signals DC Specifications .............................................................. 177 Serial VID Interface (SVID) DC Specifications ...................................................... 177 Processor Asynchronous Sideband DC Specifications............................................. 178 Miscellaneous Signals DC Specifications .............................................................. 179 Processor I/O Overshoot/Undershoot Specifications .............................................. 182 Processor Sideband Signal Group Overshoot/Undershoot Tolerance ........................ 184 Land Name ..................................................................................................... 187 Land Number .................................................................................................. 212 Processor Loading Specifications ........................................................................ 241 Package Handling Guidelines ............................................................................. 241 Processor Materials .......................................................................................... 242 PWM Fan Frequency Specifications For 4-Pin Active Thermal Solution...................... 254 8 Core / 6 Core Server Thermal Solution Boundary Conditions ............................... 256 4 Core Server Thermal Solution Boundary Conditions ........................................... 256

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Intel Xeon Processor E5-1600/ E5-2600/E5-4600 Product Families Datasheet Volume One

Revision History
Revision Number 001 002 Initial Release Added Intel Xeon Processor E5-4600 Product Family Description Revision Date March 2012 May 2012

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1
1.1

Overview
Introduction
The Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One provides DC specifications, signal integrity, differential signaling specifications, land and signal definitions, and an overview of additional processor feature interfaces. The Intel Xeon processor E5-1600/E5-2600/E5-4600 product families are the next generation of 64-bit, multi-core enterprise processors built on 32-nanometer process technology. Throughout this document, the Intel Xeon processor E5-1600/E52600/E5-4600 product families may be referred to as simply the processor. Where information differs between the EP and EP 4S SKUs, this document uses specific Intel Xeon processor E5-1600 product family, Intel Xeon processor E5-2600 product family, and Intel Xeon processor E5-4600 product family notation.Based on the low-power/high performance 2nd Generation Intel Core Processor Family microarchitecture, the processor is designed for a two chip platform consisting of a processor and a Platform Controller Hub (PCH) enabling higher performance, easier validation, and improved x-y footprint. The Intel Xeon processor E5-1600 product family and the Intel Xeon processor E5-2600 product family are designed for Efficient Performance server, workstation and HPC platforms. The Intel Xeon processor E5-4600 product family processor supports scalable server and HPC platforms of two or more processors, including glueless 4-way platforms. Note: some processor features are not available on all platforms. These processors feature per socket, two Intel QuickPath Interconnect point-to-point links capable of up to 8.0 GT/s, up to 40 lanes of PCI Express* 3.0 links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express* 2.0 interface with a peak transfer rate of 5.0 GT/s. The processor supports up to 46 bits of physical address space and 48-bit of virtual address space. Included in this family of processors is an integrated memory controller (IMC) and integrated I/O (IIO) (such as PCI Express* and DMI2) on a single silicon die. This single die solution is known as a monolithic processor. Figure 1-1 and Figure 1-2, shows the processor 2-socket and 4-socket platform configuration. The Legacy CPU is the boot processor that is connected to the PCH component, this socket is set to NodeID[0]. In the 4-socket configuration, the Remote CPU is the processor which is not connected to the Legacy CPU.

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Figure 1-1.

Intel Xeon Processor E5-2600 Product Family on the 2 Socket Platform

Figure 1-2.

Intel Xeon Processor E5-4600 Product Family on the 4 Socket Platform

1.1.1

Processor Feature Details

Up to 8 execution cores Each core supports two threads (Intel Hyper-Threading Technology), up to 16 threads per socket

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46-bit physical addressing and 48-bit virtual addressing 1 GB large page support for server applications A 32-KB instruction and 32-KB data first-level cache (L1) for each core A 256-KB shared instruction/data mid-level (L2) cache for each core Up to 20 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level cache (LLC), shared among all cores The Intel Xeon processor E5-4600 product family supports Directory Mode, Route Through, and Node IDs to reduce unnecessary Intel QuickPath Interconnect traffic by tracking cache lines present in remote sockets.

1.1.2

Supported Technologies
Intel Virtualization Technology (Intel VT) Intel Virtualization Technology (Intel VT) for Directed I/O (Intel VT-d) Intel Virtualization Technology Processor Extensions Intel Trusted Execution Technology (Intel TXT) Intel Advanced Encryption Standard Instructions (Intel AES-NI) Intel 64 Architecture Intel Streaming SIMD Extensions 4.1 (Intel SSE4.1) Intel Streaming SIMD Extensions 4.2 (Intel SSE4.2) Intel Advanced Vector Extensions (Intel AVX) Intel Hyper-Threading Technology (Intel HT Technology) Execute Disable Bit Intel Turbo Boost Technology Intel Intelligent Power Technology Enhanced Intel SpeedStep Technology Intel Dynamic Power Technology (Intel DPT) (Memory Power Management)

1.2
1.2.1

Interfaces
System Memory Support
Intel Xeon processor E5-1600/E5-2600/E5-4600 product families supports 4 DDR3 channels Unbuffered DDR3 and registered DDR3 DIMMs LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher capacity memory subsystems Independent channel mode or lockstep mode Data burst length of eight cycles for all memory organization modes Memory DDR3 data transfer rates of 800, 1066, 1333, and 1600 MT/s 64-bit wide channels plus 8-bits of ECC support for each channel DDR3 standard I/O Voltage of 1.5 V and DDR3 Low Voltage of 1.35 V 1-Gb, 2-Gb and 4-Gb DDR3 DRAM technologies supported for these devices:

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UDIMMs x8, x16 RDIMMs x4, x8 LRDIMM x4, x8 (2-Gb and 4-Gb only) Up to 8 ranks supported per memory channel, 1, 2 or 4 ranks per DIMM Open with adaptive idle page close timer or closed page policy Per channel memory test and initialization engine can initialize DRAM to all logical zeros with valid ECC (with or without data scrambler) or a predefined test pattern Isochronous access support for Quality of Service (QoS), native 1 and 2 socket platforms - Intel Xeon processor E5-1600 and E5-2600 product families only Minimum memory configuration: independent channel support with 1 DIMM populated Integrated dual SMBus master controllers Command launch modes of 1n/2n RAS Support (including and not limited to): Rank Level Sparing and Device Tagging Demand and Patrol Scrubbing DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM device failure. Independent channel mode supports x4 SDDC. x8 SDDC requires lockstep mode Lockstep mode where channels 0 & 1 and channels 2 & 3 are operated in lockstep mode The combination of memory channel pair lockstep and memory mirroring is not supported Data scrambling with address to ease detection of write errors to an incorrect address. Error reporting via Machine Check Architecture Read Retry during CRC error handling checks by iMC Channel mirroring within a socket Channel Mirroring mode is supported on memory channels 0 & 1 and channels 2 & 3 Corrupt Data Containment MCA Recovery Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT) Memory thermal monitoring support for DIMM temperature via two memory signals, MEM_HOT_C{01/23}_N

1.2.2

PCI Express*
The PCI Express* port(s) are fully-compliant to the PCI Express* Base Specification, Revision 3.0 (PCIe* 3.0) Support for PCI Express* 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s) Up to 40 lanes of PCI Express* interconnect for general purpose PCI Express* devices at PCIe* 3.0 speeds that are configurable for up to 10 independent ports 4 lanes of PCI Express* at PCIe* 2.0 speeds when not using DMI2 port (Port 0), also can be downgraded to x2 or x1 Negotiating down to narrower widths is supported, see Figure 1-3:

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x16 port (Port 2 & Port 3) may negotiate down to x8, x4, x2, or x1. x8 port (Port 1) may negotiate down to x4, x2, or x1. x4 port (Port 0) may negotiate down to x2, or x1. When negotiating down to narrower widths, there are caveats as to how lane reversal is supported. Non-Transparent Bridge (NTB) is supported by PCIe* Port3a/IOU1. For more details on NTB mode operation refer to PCI Express Base Specification - Revision 3.0: x4 or x8 widths and at PCIe* 1.0, 2.0, 3.0 speeds Two usage models; NTB attached to a Root Port or NTB attached to another NTB Supports three 64-bit BARs Supports posted writes and non-posted memory read transactions across the NTB Supports INTx, MSI and MSI-X mechanisms for interrupts on both side of NTB in upstream direction only Address Translation Services (ATS) 1.0 support Hierarchical PCI-compliant configuration mechanism for downstream devices. Traditional PCI style traffic (asynchronous snooped, PCI ordering). PCI Express* extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space. PCI Express* Enhanced Access Mechanism. Accessing the device configuration space in a flat memory mapped fashion. Automatic discovery, negotiation, and training of link out of reset. Supports receiving and decoding 64 bits of address from PCI Express*. Memory transactions received from PCI Express* that go above the top of physical address space (when Intel VT-d is enabled, the check would be against the translated HPA (Host Physical Address) address) are reported as errors by the processor. Outbound access to PCI Express* will always have address bits 63 to 46 cleared. Re-issues Configuration cycles that have been previously completed with the Configuration Retry status. Power Management Event (PME) functions. Message Signaled Interrupt (MSI and MSI-X) messages Degraded Mode support and Lane Reversal support Static lane numbering reversal and polarity inversion support

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Figure 1-3.

PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2)
Port 0 DMI / PCIe Port 1 (IOU2) PCIe Port 2 (IOU0) PCIe Port 3 (IOU1) PCIe

Transaction

Transaction

Transaction

Transaction

Link Physical
03

Link Physical
03 47 03

Link Physical
47 811 12..15 03

Link Physical
47 811 12..15

X4 DMI

X4
Po rt 1a

X4
Po rt 1b

X4
Po rt 2a

X4
Po rt 2b

X4
Po rt 2c

X4
Po rt 2d

X4
Po rt 3a

X4
Po rt 3b

X4
Po rt 3c

X4
Po rt 3d

X8
Po rt 1a

X8
Po rt 2a

X8
Po rt 2c

X8
Po rt 3a

X8
Po rt 3c

X16
Po rt 2a

X16
Po rt 3a

1.2.3

Direct Media Interface Gen 2 (DMI2)

Serves as the chip-to-chip interface to the Intel C600 Chipset The DMI2 port supports x4 link width and only operates in a x4 mode when in DMI2 Operates at PCI Express* 1.0 or 2.0 speeds Transparent to software Processor and peer-to-peer writes and reads with 64-bit address support APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined End of Interrupt broadcast message when initiated by the processor. System Management Interrupt (SMI), SCI, and SERR error indication Static lane numbering reversal support Supports DMI2 virtual channels VC0, VC1, VCm, and VCp

1.2.4

Intel QuickPath Interconnect (Intel QPI)

Compliant with Intel QuickPath Interconnect v1.1 standard packet formats Implements two full width Intel QPI ports Full width port includes 20 data lanes and 1 clock lane 64 byte cache-lines Isochronous access support for Quality of Service (QoS), native 1 and 2 socket platforms - Intel Xeon processor E5-1600 and E5-2600 product families only

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Home snoop based coherency 3-bit Node ID 46-bit physical addressing support No Intel QuickPath Interconnect bifurcation support Differential signaling Forwarded clocking Up to 8.0 GT/s data rate (up to 16 GB/s direction peak bandwidth per port) All ports run at same operational frequency Reference Clock is 100 MHz Slow boot speed initialization at 50 MT/s Common reference clocking (same clock generator for both sender and receiver) Intel Interconnect Built-In-Self-Test (Intel IBIST) for high-speed testability Polarity and Lane reversal (Rx side only)

1.2.5

Platform Environment Control Interface (PECI)

The PECI is a one-wire interface that provides a communication channel between a PECI client (the processor) and a PECI master (the PCH). Supports operation at up to 2 Mbps data transfers Link layer improvements to support additional services and higher efficiency over PECI 2.0 generation Services include CPU thermal and estimated power information, control functions for power limiting, P-state and T-state control, and access for Machine Check Architecture registers and PCI configuration space (both within the processor package and downstream devices) PECI address determined by SOCKET_ID configuration Single domain (Domain 0) is supported

1.3
1.3.1

Power Management Support

Processor Package and Core States
ACPI C-states as implemented by the following processor C-states: Package: PC0, PC1/PC1E, PC2, PC3, PC6 (Package C7 is not supported) Core: CC0, CC1, CC1E, CC3, CC6, CC7 Enhanced Intel SpeedStep Technology

1.3.2

System States Support

S0, S1, S3, S4, S5

1.3.3

Memory Controller
Multiple CKE power down modes Multiple self-refresh modes

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Memory thermal monitoring via MEM_HOT_C01_N and MEM_HOT_C23_N Signals

1.3.4

PCI Express
L0s is not supported L1 ASPM power management capability

1.3.5

Intel QuickPath Interconnect

L0s is not supported L0p and L1 power management capabilities

1.4

Thermal Management Support

Digital Thermal Sensor with multiple on-die temperature zones Adaptive Thermal Monitor THERMTRIP_N and PROCHOT_N signal support On-Demand mode clock modulation Open and Closed Loop Thermal Throttling (OLTT/CLTT) support for system memory in addition to Hybrid OLTT/CLTT mode Fan speed control with DTS Two integrated SMBus masters for accessing thermal data from DIMMs New Memory Thermal Throttling features via MEM_HOT_C{01/23}_N signals Running Average Power Limit (RAPL), Processor and DRAM Thermal and Power Optimization Capabilities

1.5 1.6

Package Summary
The processor socket is a 52.5 x 45 mm FCLGA package (LGA2011-0 land FCLGA10).

Terminology
Term ASPM BMC Cbo DDR3 DMA DMI DMI2 DTS ECC Active State Power Management Baseboard Management Controllers Cache and Core Box. It is a term used for internal logic providing ring interface to LLC and Core. Third generation Double Data Rate SDRAM memory technology that is the successor to DDR2 SDRAM Direct Memory Access Direct Media Interface Direct Media Interface Gen 2 Digital Thermal Sensor Error Correction Code Description

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Term Enhanced Intel SpeedStep Technology Execute Disable Bit

Description Allows the operating system to reduce power consumption when performance is not needed. The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel 64 and IA-32 Architectures Software Developer's Manuals for more detailed information. Flow Control Unit. The Intel QPI Link layers unit of transfer; 1 Flit = 80-bits. Refers to the normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical, and thermal, are satisfied. The Integrated Memory Controller. A Memory Controller that is integrated in the processor die. The Integrated I/O Controller. An I/O controller that is integrated in the processor die. Intel Management Engine (Intel ME) Intel QuickData Technology is a platform solution designed to maximize the throughput of server data traffic across a broader range of configurations and server environments to achieve faster, scalable, and more reliable I/O. A cache-coherent, link-based Interconnect specification for Intel processors, chipsets, and I/O bridge components. 64-bit memory extensions to the IA-32 architecture. Further details on Intel 64 architecture and programming model can be found at http://developer.intel.com/technology/intel64/. Intel Turbo Boost Technology is a way to automatically run the processor core faster than the marked frequency if the part is operating under power, temperature, and current specifications limits of the Thermal Design Power (TDP). This results in increased performance of both single and multi-threaded applications. Intel Trusted Execution Technology Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform. Intel Virtualization Technology (Intel VT) for Directed I/O. Intel VT-d is a hardware assist, under system software (Virtual Machine Manager or OS) control, for enabling I/O device virtualization. Intel VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping, a key feature of Intel VT-d. Intels 32-nm processor design, follow-on to the 32-nm 2nd Generation Intel Core Processor Family design. It is the first processor for use in Intel Xeon processor E5-1600 and E5-2600 product families-based platforms. Intel Xeon processor E5-1600 product family and Intel Xeon processor E5-2600 product family supports Efficient Performance server, workstation and HPC platforms Intels 32-nm processor design, follow-on to the 32-nm processor design. It is the first processor for use in Intel Xeon processor E5-4600 product familybased platforms. Intel Xeon processor E5-4600 product family supports scalable server and HPC platforms for two or more processors, including glueless four-way platforms. A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface. Any timing variation of a transition edge or edges from the defined Unit Interval (UI). I/O Virtualization The processor mates with the system board through this surface mount, LGA2011-0 land FCLGA10 contact socket, for the Intel Xeon processor E5 product family-based platform.

Flit Functional Operation

IMC IIO Intel ME Intel QuickData Technology Intel QuickPath Interconnect (Intel QPI) Intel 64 Technology

Intel Turbo Boost Technology

Intel TXT Intel Virtualization Technology (Intel VT) Intel VT-d

Intel Xeon processor E5-1600 product family and Intel Xeon processor E5-2600 product family Intel Xeon processor E5-4600 product family

Integrated Heat Spreader (IHS) Jitter IOV LGA2011-0 land FCLGA10 Socket

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Term LLC LRDIMM NCTF Last Level Cache

Description

Load Reduced Dual In-line Memory Module Non-Critical to Function: NCTF locations are typically redundant ground or noncritical reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality. Network Equipment Building System. NEBS is the most common set of environmental design guidelines applied to telecommunications equipment in the United States. Platform Controller Hub (Intel C600 Chipset). The next generation chipset with centralized platform capabilities including the main I/O interfaces along with display connectivity, audio features, power management, manageability, security and storage features. Power Control Unit The third generation PCI Express* specification that operates at twice the speed of PCI Express* 2.0 (8 Gb/s); however, PCI Express* 3.0 is completely backward compatible with PCI Express* 1.0 and 2.0. PCI Express* Generation 3.0 PCI Express* Generation 2.0 PCI Express* Generation 2.0/3.0 Platform Environment Control Interface Physical Unit. An Intel QPI terminology defining units of transfer at the physical layer. 1 Phit is equal to 20 bits in full width mode and 10 bits in half width mode The 64-bit, single-core or multi-core component (package) The term processor core refers to silicon die itself which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and 256-KB L2 cache. All execution cores share the L3 cache. All DC and signal integrity specifications are measured at the processor die (pads), unless otherwise noted. Registered Dual In-line Memory Module A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a DDR3 DIMM. Intel Xeon processor E5 product family-based platform targeted for scalable designs using third party Node Controller chip. In these designs, Node Controller is used to scale the design beyond one/two/four sockets. System Control Interrupt. Used in ACPI protocol. Intel Streaming SIMD Extensions (Intel SSE) A processor Stock Keeping Unit (SKU) to be installed in either server or workstation platforms. Electrical, power and thermal specifications for these SKUs are based on specific use condition assumptions. Server processors may be further categorized as Efficient Performance server, workstation and HPC SKUs. For further details on use condition assumptions, please refer to the latest Product Release Qualification (PRQ) Report available via your Customer Quality Engineer (CQE) contact. System Management Bus. A two-wire interface through which simple system and power management related devices can communicate with the rest of the system. It is based on the principals of the operation of the I2C* two-wire serial bus from Philips Semiconductor. A non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to free air (i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. Thermal Averaging Constant

NEBS

PCH

PCU PCI Express* 3.0

PCI Express* 3 PCI Express* 2 PCI Express* PECI Phit

Processor Processor Core

RDIMM Rank

Scalable-2S

SCI SSE SKU

SMBus

Storage Conditions

TAC

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Term TDP TSOD UDIMM Uncore Unit Interval Thermal Design Power Thermal Sensor on DIMM Unbuffered Dual In-line Module

Description

The portion of the processor comprising the shared cache, IMC, HA, PCU, UBox, and Intel QPI link interface. Signaling convention that is binary and unidirectional. In this binary signaling, one bit is sent for every edge of the forwarded clock, whether it be a rising edge or a falling edge. If a number of edges are collected at instances t1, t2, tn,...., tk then the UI at instance n is defined as: UI n = t n - t n - 1 Processor core power supply Processor ground Variable power supply for the processor system memory interface. VCCD is the generic term for VCCD_01, VCCD_23. Refers to a Link or Port with one Physical Lane Refers to a Link or Port with four Physical Lanes Refers to a Link or Port with eight Physical Lanes Refers to a Link or Port with sixteen Physical Lanes

VCC VSS VCCD_01, VCCD_23 x1 x4 x8 x16

1.7
Table 1-1.

Related Documents
Refer to the following documents for additional information. Referenced Documents (Sheet 1 of 2)
Document Intel Xeon Processor E5 Product Family Datasheet Volume Two Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families BSDL (Boundary Scan Description Language) Intel C600 Series Chipset Data Sheet Intel 64 and IA-32 Architectures Software Developers Manual (SDM) Volumes 1, 2, and 3 Advanced Configuration and Power Interface Specification 3.0 PCI Local Bus Specification 3.0 PCI Express Base Specification - Revision 2.1 and 1.1 PCI Express Base Specification - Revision 3.0 System Management Bus (SMBus) Specification DDR3 SDRAM Specification Low (JESD22-A119) and High (JESD-A103) Temperature Storage Life Specifications Intel 64 and IA-32 Architectures Software Developer's Manuals Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide Intel 64 and IA-32 Architectures Optimization Reference Manual Location http://www.intel.com http://www.intel.com http://www.intel.com http://www.intel.com http://www.intel.com http://www.acpi.info http://www.pcisig.com/specifications http://www.pcisig.com http://smbus.org/ http://www.jedec.org http://www.jedec.org

http://www.intel.com/products/proce ssor/manuals/index.htm

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Table 1-1.

Referenced Documents (Sheet 2 of 2)

Document Intel Virtualization Technology Specification for Directed I/O Architecture Specification Intel Trusted Execution Technology Software Development Guide Location http://download.intel.com/technolog y/computing/vptech/Intel(r)_VT_for_ Direct_IO.pdf http://www.intel.com/technology/sec urity/

1.8

State of Data
The data contained within this document is the most accurate information available by the publication date of this document.

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Interfaces
This chapter describes the interfaces supported by the processor.

2.1
2.1.1

System Memory Interface

System Memory Technology Support
The Integrated Memory Controller (IMC) supports DDR3 protocols with four independent 64-bit memory channels with 8 bits of ECC for each channel (total of 72-bits) and supports 1 to 3 DIMMs per channel depending on the type of memory installed. The type of memory supported by the processor is dependent on the target platform: Intel Xeon processor E5 product family-based platforms support: ECC registered DIMMs: with a maximum of three DIMMs per channel allowing up to eight device ranks per channel. ECC and non-ECC unbuffered DIMMs: with a maximum of two DIMMs per channel thus allowing up to four device ranks per channel. Support for mixed non-ECC with ECC un-buffered DIMM configurations.

2.1.2

System Memory Timing Support

The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and command signal mode timings on the main memory interface: tCL = CAS Latency tRCD = Activate Command to READ or WRITE Command delay tRP = PRECHARGE Command Period CWL = CAS Write Latency Command Signal modes = 1n indicates a new command may be issued every clock and 2n indicates a new command may be issued every 2 clocks. Command launch mode programming depends on the transfer rate and memory configuration.

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2.2

PCI Express* Interface

This section describes the PCI Express* 3.0 interface capabilities of the processor. See the PCI Express* Base Specification for details of PCI Express* 3.0.

2.2.1

PCI Express* Architecture

Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged. The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification. The PCI Express* architecture is specified in three layers: Transaction Layer, Data Link Layer, and Physical Layer. The partitioning in the component is not necessarily along these same boundaries. Refer to Figure 2-1 for the PCI Express* Layering Diagram.

Figure 2-1.

PCI Express* Layering Diagram

Transaction Data Link Physical

Logical Sub-Block

Transaction Data Link Physical

Logical Sub-Block

Electrical Sub-Block

Electrical Sub-Block

RX

TX

RX

TX

PCI Express* uses packets to communicate information between components. Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers. At the receiving side, the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device.

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Figure 2-2.

Packet Flow through the Layers

Framing

Sequence Number

Header

Data

ECRC

LCRC

Framing

Transaction Layer Data Link Layer Physical Layer

2.2.1.1 Transaction Layer
The upper layer of the PCI Express* architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events. The Transaction Layer also manages flow control of TLPs.

2.2.1.2

Data Link Layer

The middle layer in the PCI Express* stack, the Data Link Layer, serves as an intermediate stage between the Transaction Layer and the Physical Layer. Responsibilities of Data Link Layer include link management, error detection, and error correction. The transmission side of the Data Link Layer accepts TLPs assembled by the Transaction Layer, calculates and applies data protection code and TLP sequence number, and submits them to Physical Layer for transmission across the Link. The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the Transaction Layer for further processing. On detection of TLP error(s), this layer is responsible for requesting retransmission of TLPs until information is correctly received, or the Link is determined to have failed. The Data Link Layer also generates and consumes packets which are used for Link management functions.

2.2.1.3

Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance matching circuitry. It also includes logical functions related to interface initialization and maintenance. The Physical Layer exchanges data with the Data Link Layer in an implementation-specific format, and is responsible for converting this to an appropriate serialized format and transmitting it across the PCI Express* Link at a frequency and width compatible with the remote device.

2.2.2

PCI Express* Configuration Mechanism

The PCI Express* link is mapped through a PCI-to-PCI bridge structure. PCI Express* extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express* configuration space is divided into a PCI-compatible region (which consists of the first

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256 bytes of a logical device's configuration space) and an extended PCI Express* region (which consists of the remaining configuration space). The PCI-compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express* configuration access mechanism described in the PCI Express* Enhanced Configuration Mechanism section. The PCI Express* Host Bridge is required to translate the memory-mapped PCI Express* configuration space accesses from the host processor to PCI Express* configuration cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is recommended that system software access the enhanced configuration space using 32-bit operations (32-bit aligned) only. See the PCI Express* Base Specification for details of both the PCI-compatible and PCI Express* Enhanced configuration mechanisms and transaction rules.

2.3

DMI2/PCI Express* Interface

Direct Media Interface 2 (DMI2) connects the processor to the Platform Controller Hub (PCH). DMI2 is similar to a four-lane PCI Express* supporting a speed of 5 GT/s per lane. This interface can be configured at power-on to serve as a x4 PCI Express* link based on the setting of the SOCKET_ID[1:0] and FRMAGENT signal for processors not connected to a PCH.

Note:

Only DMI2 x4 configuration is supported.

2.3.1

DMI2 Error Flow

DMI2 can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or GPE. Any DMI2 related SERR activity is associated with Device 0.

2.3.2

Processor/PCH Compatibility Assumptions

The processor is compatible with the PCH and is not compatible with any previous MCH or ICH products.

2.3.3

DMI2 Link Down

The DMI2 link going down is a fatal, unrecoverable error. If the DMI2 data link goes to data link down, after the link was up, then the DMI2 link hangs the system by not allowing the link to retrain to prevent data corruption. This is controlled by the PCH. Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal. No completions from downstream, non-posted transactions are returned upstream over the DMI2 link after a link down event.

2.4

Intel QuickPath Interconnect

The Intel QuickPath Interconnect is a high speed, packetized, point-to-point interconnect used in the 2nd Generation Intel(r) Core(TM) Processor Family. The narrow high-speed links stitch together processors in distributed shared memory and integrated I/O platform architecture. It offers much higher bandwidth with low latency. The Intel QuickPath Interconnect has an efficient architecture allowing more interconnect performance to be achieved in real systems. It has a snoop protocol

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Interfaces

optimized for low latency and high scalability, as well as packet and lane structures enabling quick completions of transactions. Reliability, availability, and serviceability features (RAS) are built into the architecture. The physical connectivity of each interconnect link is made up of twenty differential signal pairs plus a differential forwarded clock. Each port supports a link pair consisting of two uni-directional links to complete the connection between two components. This supports traffic in both directions simultaneously. To facilitate flexibility and longevity, the interconnect is defined as having five layers: Physical, Link, Routing, Transport, and Protocol. The Physical layer consists of the actual wires carrying the signals, as well as circuitry and logic to support ancillary features required in the transmission and receipt of the 1s and 0s. The unit of transfer at the Physical layer is 20-bits, which is called a Phit (for Physical unit). The Link layer is responsible for reliable transmission and flow control. The Link layers unit of transfer is 80-bits, which is called a Flit (for Flow control unit). The Routing layer provides the framework for directing packets through the fabric. The Transport layer is an architecturally defined layer (not implemented in the initial products) providing advanced routing capability for reliable end-to-end transmission. The Protocol layer is the high-level set of rules for exchanging packets of data between devices. A packet is comprised of an integral number of Flits. The Intel QuickPath Interconnect includes a cache coherency protocol to keep the distributed memory and caching structures coherent during system operation. It supports both low-latency source snooping and a scalable home snoop behavior. The coherency protocol provides for direct cache-to-cache transfers for optimal latency.

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2.5

Platform Environment Control Interface (PECI)

The Platform Environment Control Interface (PECI) uses a single wire for self-clocking and data transfer. The bus requires no additional control lines. The physical layer is a self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle level near zero volts. The duration of the signal driven high depends on whether the bit value is a logic 0 or logic 1. PECI also includes variable data transfer rate established with every message. In this way, it is highly flexible even though underlying logic is simple. The interface design was optimized for interfacing to Intel processor and chipset components in both single processor and multiple processor environments. The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components. Bus speed, error checking, and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information. The PECI bus offers: A wide speed range from 2 Kbps to 2 Mbps CRC check byte used to efficiently and atomically confirm accurate data delivery Synchronization at the beginning of every message minimizes device timing accuracy requirements

Note:

The PECI commands described in this document apply primarily to the Intel Xeon processor E5-1600/E5-2600/E5-4600 product families. The processors utilizes the capabilities described in this document to indicate support for four memory channels. Refer to Table 2-1 for the list of PECI commands supported by the processors. Summary of Processor-specific PECI Commands
Command Ping() GetDIB() GetTemp() RdPkgConfig() WrPkgConfig() RdIAMSR() WrIAMSR() RdPCIConfig() WrPCIConfig() RdPCIConfigLocal() WrPCIConfigLocal() Supported on the Processor Yes Yes Yes Yes Yes Yes No Yes No Yes Yes

Table 2-1.

2.5.1

PECI Client Capabilities

The processor PECI client is designed to support the following sideband functions: Processor and DRAM thermal management Platform manageability functions including thermal, power, and error monitoring The platform power management includes monitoring and control for both the processor and DRAM subsystem to assist with data center power limiting. Processor interface tuning and diagnostics capabilities (Intel Interconnect BIST).

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2.5.1.1

Thermal Management
Processor fan speed control is managed by comparing Digital Thermal Sensor (DTS) thermal readings acquired via PECI against the processor-specific fan speed control reference point, or TCONTROL. Both TCONTROL and DTS thermal readings are accessible via the processor PECI client. These variables are referenced to a common temperature, the TCC activation point, and are both defined as negative offsets from that reference. PECI-based access to the processor package configuration space provides a means for Baseboard Management Controllers (BMCs) or other platform management devices to actively manage the processor and memory power and thermal features. Details on the list of available power and thermal optimization services can be found in Section 2.5.2.6.

2.5.1.2

Platform Manageability
PECI allows read access to certain error registers in the processor MSR space and status monitoring registers in the PCI configuration space within the processor and downstream devices. Details are covered in subsequent sections. PECI permits writes to certain Memory Controller RAS-related registers in the processor PCI configuration space. Details are covered in Section 2.5.2.10.

2.5.1.3

Processor Interface Tuning and Diagnostics

The processor Intel Interconnect Built In Self Test (Intel IBIST) allows for in-field diagnostic capabilities in the Intel QPI and memory controller interfaces. PECI provides a port to execute these diagnostics via its PCI Configuration read and write capabilities in the BMC INIT mode. Refer to Section 2.5.3.7 for more details.

2.5.2

Client Command Suite

PECI command requires at least one frame check sequence (FCS) byte to ensure reliable data exchange between originator and client. The PECI message protocol defines two FCS bytes that are returned by the client to the message originator. The first FCS byte covers the client address byte, the Read and Write Length bytes, and all bytes in the write data block. The second FCS byte covers the read response data returned by the PECI client. The FCS byte is the result of a cyclic redundancy check (CRC) of each data block.

2.5.2.1

Ping()
Ping() is a required message for all PECI devices. This message is used to enumerate devices or determine if a device has been removed, been powered-off, etc. A Ping() sent to a device address always returns a non-zero Write FCS if the device at the targeted address is able to respond.

2.5.2.1.1

Command Format The Ping() format is as follows: Write Length: 0x00 Read Length: 0x00

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Figure 2-3.

Ping()
Byte # Byte Definition 0 Client Address 1 Write Length 0x00 2 Read Length 0x00 3 FCS

An example Ping() command to PECI device address 0x30 is shown below. Figure 2-4. Ping() Example
Byte # Byte Definition 0 0x30 1 0x00 2 0x00 3 0xe1

2.5.2.2

GetDIB()
The processor PECI client implementation of GetDIB() includes an 8-byte response and provides information regarding client revision number and the number of supported domains. All processor PECI clients support the GetDIB() command.

2.5.2.2.1

Command Format The GetDIB() format is as follows: Write Length: 0x01 Read Length: 0x08 Command: 0xf7

Figure 2-5.

GetDIB()

Byte # Byte Definition

0 Client Address 5 Device Info

1 Write Length 0x01 6 Revision Number

2 Read Length 0x08 7 Reserved

3 Cmd Code 0xf7 8 Reserved

4 FCS 9 Reserved

10 Reserved

11 Reserved

12 Reserved

13 FCS

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2.5.2.2.2

Device Info The Device Info byte gives details regarding the PECI client configuration. At a minimum, all clients supporting GetDIB will return the number of domains inside the package via this field. With any client, at least one domain (Domain 0) must exist. Therefore, the Number of Domains reported is defined as the number of domains in addition to Domain 0. For example, if bit 2 of the Device Info byte returns a 1, that would indicate that the PECI client supports two domains.

Figure 2-6.

Device Info Field Definition

Byte# 5
7 6 5 4 3 2 1 0

Reserved # of Domains Reserved

2.5.2.2.3 Revision Number All clients that support the GetDIB command also support Revision Number reporting. The revision number may be used by a host or originator to manage different command suites or response codes from the client. Revision Number is always reported in the second byte of the GetDIB() response. The Major Revision number in Figure 2-7 always maps to the revision number of the PECI specification that the PECI client processor is designed to. The Minor Revision number value depends on the exact command suite supported by the PECI client as defined in Table 2-2. Figure 2-7. Revision Number Definition

Byte# 6
7 4 3 0

Major Revision# Minor Revision#

Table 2-2. Minor Revision Number Meaning
Minor Revision 0 1 2 3 4 Supported Command Suite Ping(), GetDIB(), GetTemp() Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig() Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig(), RdIAMSR() Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig(), RdIAMSR(), RdPCIConfigLocal(), WrPCIConfigLocal() Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig(), RdIAMSR(), RdPCIConfigLocal(), WrPCIConfigLocal(), RdPCIConfig()

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Table 2-2.

Minor Revision Number Meaning

Minor Revision 5 6 Supported Command Suite Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig(), RdIAMSR(), RdPCIConfigLocal(), WrPCIConfigLocal(), RdPCIConfig(), WrPCIConfig() Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig(), RdIAMSR(), RdPCIConfigLocal(), WrPCIConfigLocal(), RdPCIConfig(), WrPCIConfig(), WrIAMSR()

For the processor PECI client the Revision Number will return 0011 0100b.

2.5.2.3

GetTemp()
The GetTemp() command is used to retrieve the maximum die temperature from a target PECI address. The temperature is used by the external thermal management system to regulate the temperature on the die. The data is returned as a negative value representing the number of degrees centigrade below the maximum processor junction temperature (Tjmax). The maximum PECI temperature value of zero corresponds to the processor Tjmax. This also represents the default temperature at which the processor Thermal Control Circuit activates. The actual value that the thermal management system uses as a control set point (TCONTROL) is also defined as a negative number below Tjmax. TCONTROL may be extracted from the processor by issuing a PECI RdPkgConfig() command as described in Section 2.5.2.4 or using a RDMSR instruction. TCONTROL application to fan speed control management is defined in the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/ Mechanical Design Guide. Please refer to Section 2.5.7 for details regarding PECI temperature data formatting.

2.5.2.3.1

Command Format The GetTemp() format is as follows: Write Length: 0x01 Read Length: 0x02 Command: 0x01 Description: Returns the highest die temperature for addressed processor PECI client.

Figure 2-8.

GetTemp()
Byte # Byte Definition 0 Client Address 1 Write Length 0x01 2 Read Length 0x02 3 Cmd Code 0x01

4 FCS

5 Temp[7:0]

6 Temp[15:8]

7 FCS

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Example bus transaction for a thermal sensor device located at address 0x30 returning a value of negative 10 counts is show in Figure 2-9. Figure 2-9. GetTemp() Example
Byte # Byte Definition 0 0x30 4 0xef 1 0x01 5 0x80 2 0x02 6 0xfd 3 0x01 7 0x4b

2.5.2.3.2

Supported Responses The typical client response is a passing FCS and valid thermal data. Under some conditions, the clients response will indicate a failure. GetTemp() response definitions are listed in Table 2-3. Refer to Section 2.5.7.4 for more details on sensor errors.

Table 2-3.

GetTemp() Response Definition

Response General Sensor Error (GSE)1 Bad Write FCS Abort FCS 0x00001 All other data Meaning Thermal scan did not complete in time. Retry is appropriate. Electrical error Illegal command formatting (mismatched RL/WL/Command Code) Processor is running at its maximum temperature or is currently being reset. Valid temperature reading, reported as a negative offset from the processor Tjmax.

Notes: 1. This response will be reflected in Bytes 5 & 6 in Figure 2-9.

2.5.2.4

RdPkgConfig()
The RdPkgConfig() command provides read access to the package configuration space (PCS) within the processor, including various power and thermal management functions. Typical PCS read services supported by the processor may include access to temperature data, energy status, run time information, DIMM temperatures and so on. Refer to Section 2.5.2.6 for more details on processor-specific services supported through this command.

2.5.2.4.1

Command Format The RdPkgConfig() format is as follows: Write Length: 0x05 Read Length: 0x05 (dword) Command: 0xa1 Description: Returns the data maintained in the processor package configuration space for the PCS entry as specified by the index and parameter fields. The index field contains the encoding for the requested service and is used in conjunction with the parameter field to specify the exact data being requested. The Read Length dictates the desired data return size. This command supports only dword responses on the

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processor PECI clients. All command responses are prepended with a completion code that contains additional pass/fail status information. Refer to Section 2.5.5.2 for details regarding completion codes. Figure 2-10. RdPkgConfig()

Note:

The 2-byte parameter field and 4-byte read data field defined in Figure 2-10 are sent in standard PECI ordering with LSB first and MSB last.

2.5.2.4.2

Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the clients response will indicate a failure.

Table 2-4.

RdPkgConfig() Response Definition

Response Bad Write FCS Abort FCS CC: 0x40 CC: 0x80 CC: 0x81 CC: 0x90 CC: 0x91 Electrical error Illegal command formatting (mismatched RL/WL/Command Code) Command passed, data is valid. Response timeout. The processor is not able to generate the required response in a timely fashion. Retry is appropriate. Response timeout. The processor is not able to allocate resources for servicing this command at this time. Retry is appropriate. Unknown/Invalid/Illegal Request PECI control hardware, firmware or associated logic error. The processor is unable to process the request. Meaning

2.5.2.5

WrPkgConfig()
The WrPkgConfig() command provides write access to the package configuration space (PCS) within the processor, including various power and thermal management functions. Typical PCS write services supported by the processor may include power limiting, thermal averaging constant programming and so on. Refer to Section 2.5.2.6 for more details on processor-specific services supported through this command.

2.5.2.5.1

Command Format The WrPkgConfig() format is as follows: Write Length: 0x0a(dword)

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Read Length: 0x01 Command: 0xa5 AW FCS Support: Yes Description: Writes data to the processor PCS entry as specified by the index and parameter fields. This command supports only dword data writes on the processor PECI clients. All command responses include a completion code that provides additional pass/fail status information. Refer to Section 2.5.5.2 for details regarding completion codes. The Assured Write FCS (AW FCS) support provides the processor client a high degree of confidence that the data it received from the host is correct. This is especially critical where the consumption of bad data might result in improper or non-recoverable operation. Figure 2-11. WrPkgConfig()

Note:

The 2-byte parameter field and 4-byte write data field defined in Figure 2-11 are sent in standard PECI ordering with LSB first and MSB last.

2.5.2.5.2

Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the clients response will indicate a failure.

Table 2-5.

WrPkgConfig() Response Definition (Sheet 1 of 2)

Response Bad Write FCS Abort FCS CC: 0x40 Electrical error or AW FCS failure Illegal command formatting (mismatched RL/WL/Command Code) Command passed, data is valid. Meaning

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Table 2-5.

WrPkgConfig() Response Definition (Sheet 2 of 2)

Response CC: 0x80 CC: 0x81 CC: 0x90 CC: 0x91 Meaning Response timeout. The processor was not able to generate the required response in a timely fashion. Retry is appropriate. Response timeout. The processor is not able to allocate resources for servicing this command at this time. Retry is appropriate. Unknown/Invalid/Illegal Request PECI control hardware, firmware or associated logic error. The processor is unable to process the request.

2.5.2.6

Package Configuration Capabilities

Table 2-6 combines both read and write services. Any service listed as a read would use the RdPkgConfig() command and a service listed as a write would use the WrPkgConfig() command. PECI requests for memory temperature or other data generated outside the processor package do not trigger special polling cycles on the processor memory or SMBus interfaces to procure the required information.

2.5.2.6.1

DRAM Thermal and Power Optimization Capabilities DRAM thermal and power optimization (also known as RAPL or Running Average Power Limit) services provide a way for platform thermal management solutions to program and access DRAM power, energy and temperature parameters. Memory temperature information is typically used to regulate fan speeds, tune refresh rates and throttle the memory subsystem as appropriate. Memory temperature data may be derived from a variety of sources including on-die or on-board DIMM sensors, DRAM activity information or a combination of the two. Though memory temperature data is a byte long, range of actual temperature values are determined by the DIMM specifications and operating range.

Note:

DRAM related PECI services described in this section apply only to the memory connected to the specific processor PECI client in question and not the overall platform memory in general. For estimating DRAM thermal information in closed loop throttling mode, a dedicated SMBus is required between the CPU and the DIMMs. The processor PCU requires access to the VR12 voltage regulator for reading average output current information through the SVID bus for initial DRAM RAPL related power tuning. Table 2-6 provides a summary of the DRAM power and thermal optimization capabilities that can be accessed over PECI on the processor. The Index values referenced in Table 2-6 are in decimal format. Table 2-6 also provides information on alternate inband mechanisms to access similar or equivalent information through register reads and writes where applicable. The user should consult the Intel 64 and IA-32 Architectures Software Developers Manual (SDM) Volumes 1, 2, and 3 or Intel Xeon Processor E5 Product Family Datasheet Volume Two for details on MSR and CSR register contents.

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Table 2-6.

RdPkgConfig() & WrPkgConfig() DRAM Thermal and Power Optimization Services Summary (Sheet 1 of 2)
Index Value (decimal) Parameter Value (word) Channel Index & DIMM Index RdPkgConfig() Data (dword) WrPkgConfig() Data (dword) Absolute temperature in Degrees Celsius for ranks 0, 1, 2 &3 Description Alternate Inband MSR or CSR Access

Service DRAM Rank Temperature Write

18

N/A

Write temperature for each rank within a single DIMM. Read temperature of each DIMM within a channel. Write ambient temperature reference for activity-based rank temperature estimation. Read ambient temperature reference for activity-based rank temperature estimation. Read the maximum DRAM channel temperature. Read the DRAM energy consumed by all the DIMMs in all the channels or all the DIMMs within a specified channel. Read DRAM power settings info to be used by power limiting entity. Read DRAM power settings info to be used by power limiting entity

N/A

DIMM Temperature Read

14

Channel Index

Absolute temperature in Degrees Celsius for DIMMs 0, 1, & 2

N/A

CSR: DIMMTEMPSTAT_[0:2]

DIMM Ambient Temperature Write / Read

19

0x0000

N/A

Absolute temperature in Degrees C to be used as ambient temperature reference

N/A

DIMM Ambient Temperature Write / Read

19

0x0000

Absolute temperature in Degrees C to be used as ambient temperature reference Maximum of all rank temperatures for each channel in Degrees Celsius

N/A

N/A

DRAM Channel Temperature Read Accumulated DRAM Energy Read

22

0x0000

N/A

N/A

04

Channel Index 0x00FF - All Channels

DRAM energy consumed by the DIMMs

N/A

MSR 619h: DRAM_ENERGY_STATUS CSR: DRAM_ENERGY_STATUS CSR: DRAM_ENERGY_STATUS_C H[0:3] 1

DRAM Power Info Read

35

0x0000

Typical and minimum DRAM power settings

N/A

MSR 61Ch: DRAM_POWER_INFO CSR: DRAM_POWER_INFO

DRAM Power Info Read

36

0x0000

Maximum DRAM power settings & maximum time window

N/A

MSR 61Ch: DRAM_POWER_INFO CSR: DRAM_POWER_INFO

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Table 2-6.

RdPkgConfig() & WrPkgConfig() DRAM Thermal and Power Optimization Services Summary (Sheet 2 of 2)
Index Value (decimal) Parameter Value (word) RdPkgConfig() Data (dword) WrPkgConfig() Data (dword) Description Alternate Inband MSR or CSR Access

Service DRAM Power Limit Data Write / Read

34

0x0000

N/A

MSR 618h: DRAM_POWER_LIMIT DRAM Plane Write DRAM CSR: Power Limit Data Power Limit Data DRAM_PLANE_POWER_LIM IT MSR 618h: DRAM_POWER_LIMIT Read DRAM CSR: Power Limit Data DRAM_PLANE_POWER_LIM IT Read sum of all time durations for which each DIMM has been throttled

DRAM Power Limit Data Write / Read

34

0x0000

DRAM Plane Power Limit Data

N/A

DRAM Power Limit Performance Status Read

38

0x0000

Accumulated DRAM throttle time

N/A

CSR: DRAM_RAPL_PERF_STATUS

Notes: 1. Time, energy and power units should be assumed, where applicable, to be based on values returned by a read of the PACKAGE_POWER_SKU_UNIT MSR or through the Package Power SKU Unit PCS read service.

2.5.2.6.2

DRAM Thermal Estimation Configuration Data Read/Write This feature is relevant only when activity-based DRAM temperature estimation methods are being utilized and would apply to all the DIMMs on all the memory channels. The write allows the PECI host to configure the and variables in Figure 2-12 for DRAM channel temperature filtering as per the equation below: TN = TN-1 + Energy TN and TN-1 are the current and previous DRAM temperature estimates respectively in degrees Celsius, is the DRAM temperature decay factor, Energy is the energy difference between the current and previous memory transactions as determined by the processor power control unit and is the DRAM energy-to-temperature translation coefficient. The default value of is 0x3FF. is defined by the equation: = (1 - ) (Thermal Resistance) (Scaling Factor) The Thermal Resistance serves as a multiplier for translation of DRAM energy changes to corresponding temperature changes and may be derived from actual platform characterization data. The Scaling Factor is used to convert memory transaction information to energy units in Joules and can be derived from system/memory configuration information. Refer to the Intel 64 and IA-32 Architectures Software Developers Manual (SDM) Volumes 1, 2, and 3 for methods to program and access Scaling Factor information.

Figure 2-12. DRAM Thermal Estimation Configuration Data

31 RESERVED 20 19 THETA VARIABLE Memory Thermal Estimation Configuration Data 10 9 BETA VARIABLE 0

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2.5.2.6.3

DRAM Rank Temperature Write This feature allows the PECI host to program into the processor, the temperature for all the ranks within a DIMM up to a maximum of four ranks as shown in Figure 2-13. The DIMM index and Channel index are specified through the parameter field as shown in Table 2-7. This write is relevant in platforms that do not have on-die or on-board DIMM thermal sensors to provide memory temperature information or if the processor does not have direct access to the DIMM thermal sensors. This temperature information is used by the processor in conjunction with the activity-based DRAM temperature estimations.

Table 2-7.

Channel & DIMM Index Decoding

Index Encoding 000 001 010 011 Physical Channel# 0 1 2 3 Physical DIMM# 0 1 2 Reserved

Figure 2-13. DRAM Rank Temperature Write Data

31 24 23 Rank# 3 Absolute Temp (in Degrees C) 16 15 Rank# 1 Absolute Temp (in Degrees C) 8 7 Rank# 0 Absolute Temp (in Degrees C) 0

Rank# 2 Absolute Temp (in Degrees C)

Rank Temperature Data 15 Reserved 6 5 DIMM Index Parameter format 3 2 Channel Index 0

2.5.2.6.4

DIMM Temperature Read This feature allows the PECI host to read the temperature of all the DIMMs within a channel up to a maximum of three DIMMs. This read is not limited to platforms using a particular memory temperature source or temperature estimation method. For platforms using DRAM thermal estimation, the PCU will provide the estimated temperatures. Otherwise, the data represents the latest DIMM temperature provided by the TSOD or on-board DIMM sensor and requires that CLTT (closed loop throttling mode) be enabled and OLTT (open loop throttling mode) be disabled. Refer to Table 2-7 for channel index encodings.

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Figure 2-14. The Processor DIMM Temperature Read / Write

31 Reserved 24 23 16 15 DIMM# 1 Absolute Temp (in Degrees C) 8 7 DIMM# 0 Absolute Temp (in Degrees C) 0

DIMM# 2 Absolute Temp (in Degrees C)

DIMM Temperature Data 15 Reserved Parameter format 3 2 Channel Index 0

2.5.2.6.5

DIMM Ambient Temperature Write / Read This feature allows the PECI host to provide an ambient temperature reference to be used by the processor for activity-based DRAM temperature estimation. This write is used only when no DIMM temperature information is available from on-board or on-die DIMM thermal sensors. It is also possible for the PECI host controller to read back the DIMM ambient reference temperature. Since the ambient temperature may vary over time within a system, it is recommended that systems monitoring and updating the ambient temperature at a fast rate use the maximum temperature value while those updating the ambient temperature at a slow rate use an average value. The ambient temperature assumes a single value for all memory channel/DIMM locations and does not account for possible temperature variations based on DIMM location.

Figure 2-15. Ambient Temperature Reference Data

31 Reserved Ambient Temperature Reference Data 8 7 Ambient Temperature (in Degrees C) 0

2.5.2.6.6

DRAM Channel Temperature Read This feature enables a PECI host read of the maximum temperature of each channel. This would include all the DIMMs within the channel and all the ranks within each of the DIMMs. Channels that are not populated will return the ambient temperature on systems using activity-based temperature estimations or alternatively return a zero for systems using sensor-based temperatures.

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Figure 2-16. Processor DRAM Channel Temperature

31
Channel 3 Maximum Temperature (in Degrees C)

24 23
Channel 2 Maximum Temperature (in Degrees C)

16 15
Channel 1 Maximum Temperature (in Degrees C)

8 7
Channel 0 Maximum Temperature (in Degrees C)

Channel Temperature Data

2.5.2.6.7

Accumulated DRAM Energy Read This feature allows the PECI host to read the DRAM energy consumed by all the DIMMs within all the channels or all the DIMMs within just a specified channel. The parameter field is used to specify the channel index. Units used are defined as per the Package Power SKU Unit read described in Section 2.5.2.6.11. This information is tracked by a 32-bit counter that wraps around. The channel index in Figure 2-17 is specified as per the index encoding described in Table 2-7. A channel index of 0x00FF is used to specify the all channels case. While Intel requires reading the accumulated energy data at least once every 16 seconds to ensure functional correctness, a more realistic polling rate recommendation is once every 100 mS for better accuracy. This feature assumes a 200W memory capacity. In general, as the power capability decreases, so will the minimum polling rate requirement. When determining energy changes by subtracting energy values between successive reads, Intel advocates using the 2s complement method to account for counter wraparounds. Alternatively, adding all Fs (0xFFFFFFFF) to a negative result from the subtraction will accomplish the same goal.

Figure 2-17. Accumulated DRAM Energy Data

31 Accumulated DRAM Energy Accumulated DRAM Energy Data 15 Reserved Parameter format 3 2 Channel Index 0 0

2.5.2.6.8

DRAM Power Info Read This read returns the minimum, typical and maximum DRAM power settings and the maximum time window over which the power can be sustained for the entire DRAM domain and is inclusive of all the DIMMs within all the memory channels. Any power values specified by the power limiting entity that is outside of the range specified through these settings cannot be guaranteed. Since this data is 64 bits wide, PECI facilitates access to this register by allowing two requests to read the lower 32 bits and upper 32 bits separately as shown in Table 2-6. Power and time units for this read are defined as per the Package Power SKU Unit settings described in Section 2.5.2.6.11.

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The minimum DRAM power in Figure 2-18 corresponds to a minimum bandwidth setting of the memory interface. It does not correspond to a processor IDLE or memory self-refresh state. The time window in Figure 2-18 is representative of the rate at which the power control unit (PCU) samples the DRAM energy consumption information and reactively takes the necessary measures to meet the imposed power limits. Programming too small a time window may not give the PCU enough time to sample energy information and enforce the limit while too large a time window runs the risk of the PCU not being able to monitor and take timely action on energy excursions. While the DRAM power setting in Figure 2-18 provides a maximum value for the time window (typically a few seconds), the minimum value may be assumed to be ~100 mS. The PCU programs the DRAM power settings described in Figure 2-18 when DRAM characterization has been completed by the memory reference code (MRC) during boot as indicated by the setting of the RST_CPL bit of the BIOS_RESET_CPL register. The DRAM power settings will be programmed during boot independent of the DRAM Power Limit Enable bit setting. Please refer to the Intel Xeon Processor E5 Product Family Datasheet Volume Two for information on memory energy estimation methods and energy tuning options used by BIOS and other utilities for determining the range specified in the DRAM power settings. In general, any tuning of the power settings is done by polling the voltage regulators supplying the DIMMs. Figure 2-18. DRAM Power Info Read Data
63 Reserved 55 54 Maximum Time Window 48 47 Reserved 46 Maximum DRAM Power 32

DRAM_POWER_INFO (upper bits)

31 Reserved

30 Minimum DRAM Power

16

15 Reserved

14 TDP DRAM Power (Typical Value)

DRAM_POWER_INFO (lower bits)

2.5.2.6.9

DRAM Power Limit Data Write / Read This feature allows the PECI host to program the power limit over a specified time or control window for the entire DRAM domain covering all the DIMMs within all the memory channels. Actual values are chosen based on DRAM power consumption characteristics. The units for the DRAM Power Limit and Control Time Window are determined as per the Package Power SKU Unit settings described in Section 2.5.2.6.11. The DRAM Power Limit Enable bit in Figure 2-19 should be set to activate this feature. Exact DRAM power limit values are largely determined by platform memory configuration. As such, this feature is disabled by default and there are no defaults associated with the DRAM power limit values. The PECI host may be used to enable and initialize the power limit fields for the purposes of DRAM power budgeting. Alternatively, this can also be accomplished through inband writes to the appropriate registers. Both power limit enabling and initialization of power limit values can be done in the same command cycle. All RAPL parameter values including the power limit value, control time window, and enable bit will have to be specified correctly even if the intent is to change just one parameter value when programming over PECI.

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The following conversion formula should be used for encoding or programming the Control Time Window in bits [23:17]. Control Time Window (in seconds) = ([1 + 0.25 * x] * 2y) * z where x = integer value of bits[23:22] y = integer value of bits[21:17] z = Package Power SKU Time Unit[19:16] (see Section 2.5.2.6.13 for details on Package Power SKU Unit) For example, using this formula, a control time value of 0x0A will correspond to a 1-second time window. A valid range for the value of the Control Time Window in Figure 2-19 that can be programmed into bits [23:17] is 250 mS - 40 seconds. From a DRAM power management standpoint, all post-boot DRAM power management activities (also referred to as DRAM RAPL or DRAM Running Average Power Limit) should be managed exclusively through a single interface like PECI or alternatively an inband mechanism. If PECI is being used to manage DRAM power budgeting activities, BIOS should lock out all subsequent inband DRAM power limiting accesses by setting bit 31 of the DRAM_POWER_LIMIT MSR or DRAM_PLANE_POWER_LIMIT CSR to 1. Figure 2-19. DRAM Power Limit Data
31 R ES ER VED 24 2 3 C o ntrol Tim e W in dow 17 16 R ES ER V ED 15 DRAM Pow er Lim it Enable 14 D R A M Pow er Lim it 0

D R A M _ PO W ER _ LIM IT D ata

2.5.2.6.10

DRAM Power Limit Performance Status Read This service allows the PECI host to assess the performance impact of the currently active DRAM power limiting modes. The read return data contains the sum of all the time durations for which each of the DIMMs has been operating in a low power state. This information is tracked by a 32-bit counter that wraps around. The unit for time is determined as per the Package Power SKU Unit settings described in Section 2.5.2.6.11. The DRAM performance data does not account for stalls on the memory interface. In general, for the purposes of DRAM RAPL, the DRAM power management entity should use PECI accesses to DRAM energy and performance status in conjunction with the power limiting feature to budget power between the various memory sub-systems in the server system.

Figure 2-20. DRAM Power Limit Performance Data

31 Accumulated DRAM Throttle Time DRAM Power Limit Performance

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2.5.2.6.11

CPU Thermal and Power Optimization Capabilities Table 2-8 provides a summary of the processor power and thermal optimization capabilities that can be accessed over PECI.

Note:

The Index values referenced in Table 2-8 are in decimal format. Table 2-8 also provides information on alternate inband mechanisms to access similar or equivalent information for register reads and writes where applicable. The user should consult the appropriate Intel 64 and IA-32 Architectures Software Developers Manual (SDM) Volumes 1, 2, and 3 or Intel Xeon Processor E5 Product Family Datasheet Volume Two for exact details on MSR or CSR register content.

Table 2-8.

RdPkgConfig() & WrPkgConfig() CPU Thermal and Power Optimization Services Summary (Sheet 1 of 3)
Parameter RdPkgConfig() Index WrPkgConfig() Value Value Data (dword) Data (dword) (decimal) (word) Description Alternate Inband MSR or CSR Access

Service

0x0000

CPUID Information

Returns processorspecific information Execute CPUID instruction to get including CPU family, processor signature model and stepping information. Used to ensure microcode update compatibility with processor.

0x0001

Platform ID

MSR 17h: IA32_PLATFORM_ID

Package Identifier Read

00

0x0002

PCU Device ID

Returns the Device ID information for CSR: DID the processor Power Control Unit. Returns the MSR: RESOLVED_CORES_MASK maximum Thread ID value supported CSR: RESOLVED_CORES_MASK by the processor. Returns processor microcode and PCU firmware revision information. Returns the MCA Error Source Log Read units for power, energy and time used in power control registers. Returns Thermal Design Power and minimum package power values for the processor SKU. Returns the maximum package power value for the processor SKU and the maximum time interval for which it can be sustained.

0x0003

Max Thread ID

0x0004

CPU Microcode Update Revision MCA Error Source Log Time, Energy N/A and Power Units

MSR 8Bh: IA32_BIOS_SIGN_ID

0x0005

CSR: MCA_ERR_SRC_LOG MSR 606h: PACKAGE_POWER_SKU_UNIT CSR: PACKAGE_POWER_SKU_UNIT MSR 614h: PACKAGE_POWER_SKU CSR: PACKAGE_POWER_SKU

Package Power SKU Unit Read

30

0x0000

Package Power SKU Read

28

0x0000

Package Power SKU[31:0]

N/A

Package Power SKU Read

29

0x0000

Package Power SKU[64:32]

N/A

MSR 614h: PACKAGE_POWER_SKU CSR: PACKAGE_POWER_SKU

Wake on PECI Mode Bit Write / Read

05

0x0001 - Set 0x0000 Reset

N/A

Enables package pop-up to C2 to Wake on PECI service PECI mode bit PCIConfig() accesses if appropriate.

N/A

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Table 2-8.

RdPkgConfig() & WrPkgConfig() CPU Thermal and Power Optimization Services Summary (Sheet 2 of 3)
Parameter RdPkgConfig() Index WrPkgConfig() Value Value Data (dword) Data (dword) (decimal) (word) Description Alternate Inband MSR or CSR Access

Service

Wake on PECI Mode Bit Write / Read Accumulated Run Time Read Package Temperature Read

05

0x0000

Wake on PECI mode bit Total reference time Processor package Temperature

N/A

Read status of Wake on PECI mode bit Returns the total run time.

N/A MSR 10h: IA32_TIME_STAMP_COUNTER

31

0x0000

N/A

02

0x00FF

N/A

Returns the maximum processor MSR 1B1h: die temperature in IA32_PACKAGE_THERM_STATUS PECI format. Read the maximum DTS temperature of a particular core or the System Agent MSR 19Ch: IA32_THERM_STATUS within the processor die in relative PECI temperature format Returns the maximum processor junction temperature and processor TCONTROL. MSR 1A2h: TEMPERATURE_TARGET CSR: TEMPERATURE_TARGET

Per Core DTS Temperature Read

09

0x00000x0007 (cores 0-7) 0x00FF System Agent

Per core DTS maximum temperature

N/A

Temperature Target Read

16

0x0000

Processor Tjmax and TCONTROL

N/A

Package Thermal Status Read / Clear

20

0x0000

Thermal Status Register

N/A

Read the thermal status register and optionally clear any log bits. The register includes status and MSR 1B1h: log bits for TCC IA32_PACKAGE_THERM_STATUS activation, PROCHOT_N assertion and Critical Temperature. Reads the Thermal Averaging Constant

Thermal Averaging Constant Write / Read Thermal Averaging Constant Write / Read

21

0x0000

Thermal Averaging Constant

N/A

N/A

21

0x0000

N/A

Thermal Averaging Constant

Writes the Thermal Averaging Constant Read the time for which the processor has been operating in a lowered power state due to internal TCC activation. Reads the current limit on the VCC power plane Returns the value of the energy consumed by just the VCC power plane or entire CPU package.

N/A

Thermally Constrained Time Read

32

0x0000

Thermally Constrained Time

N/A

N/A

Current Limit Read

17

0x0000

Current Limit per power plane

N/A

CSR: PRIMARY_PLANE_CURRENT_ CONFIG_CONTROL MSR 639h: PP0_ENERGY_ STATUS CSR: PP0_ENERGY_STATUS MSR 611h: PACKAGE_ENERGY_STATUS CSR: PACKAG_ENERGY_STATUS MSR 638h: PP0_POWER_LIMIT CSR: PP0_POWER_LIMIT

Accumulated Energy Status Read

03

0x0000 VCC 0x00FF - CPU package

Accumulated CPU energy

N/A

Power Limit for the VCC Power Plane Write / Read

25

0x0000

N/A

Power Limit Data

Program power limit for VCC power plane

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Table 2-8.

RdPkgConfig() & WrPkgConfig() CPU Thermal and Power Optimization Services Summary (Sheet 3 of 3)
Parameter RdPkgConfig() Index WrPkgConfig() Value Value Data (dword) Data (dword) (decimal) (word) Description Alternate Inband MSR or CSR Access

Service

Power Limit for the VCC Power Plane Write / Read Package Power Limits For Multiple Turbo Modes Package Power Limits For Multiple Turbo Modes Package Power Limits For Multiple Turbo Modes Package Power Limits For Multiple Turbo Modes Package Power Limit Performance Status Read Efficient Performance Indicator Read

25

0x0000

Power Limit Data

N/A

Read power limit data for VCC power plane Write power limit data 1 in multiple turbo mode. Write power limit data 2 in multiple turbo mode. Read power limit 1 data in multiple turbo mode. Read power limit 2 data in multiple turbo mode. Read the total time for which the processor package was throttled due to power limiting. Read number of productive cycles for power budgeting purposes.

MSR 638h: PP0_POWER_LIMIT CSR: PP0_POWER_LIMIT MSR 610h: PACKAGE_POWER_LIMIT CSR: PACKAGE_POWER_LIMIT MSR 610h: PACKAGE_POWER_LIMIT CSR: PACKAGE_POWER_LIMIT MSR 610h: PACKAGE_POWER_LIMIT CSR: PACKAGE_POWER_LIMIT MSR 610h: PACKAGE_POWER_LIMIT CSR: PACKAGE_POWER_LIMIT

26

0x0000

N/A

Power Limit 1 Data

27

0x0000

N/A

Power Limit 2 Data

26

0x0000

Power Limit 1 Data

N/A

27

0x0000

Power Limit 2 Data

N/A

08

0x00FF - CPU package

Accumulated CPU throttle time

N/A

CSR: PACKAGE_RAPL_PERF_STATUS

06

0x0000

Number of productive processor cycles

N/A

N/A

ACPI P-T Notify Write & Read

33

0x0000

N/A

Notify the processor New p-state PCU of the new pequivalent of P1 state that is one used in state below the conjunction with turbo frequency as package power specified through the limiting last ACPI Notify Read the processor PCU to determine the p-state that is one state below the turbo frequency as specified through the last ACPI Notify Read the Cbo TOR data for all enabled cores in the event of a 3-strike timeout. Can alternatively be used to read Core ID data to confirm that IERR was caused by a core timeout Read margin to processor thermal load line

N/A

ACPI P-T Notify Write & Read

33

0x0000

New p-state equivalent of P1 used in conjunction with package power limiting

N/A

N/A

Caching Agent TOR Read

39

Cbo Index, TOR Index, Bank#; Read Mode

Caching Agent (Cbo) Table of Requests (TOR) data; Core ID & associated valid bit Thermal margin to processor thermal profile or load line

N/A

N/A

Thermal Margin Read

10

0x0000

N/A

N/A

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2.5.2.6.12

Package Identifier Read This feature enables the PECI host to uniquely identify the PECI client processor. The parameter field encodings shown in Table 2-8 allow the PECI host to access the relevant processor information as described below. CPUID data: This is the equivalent of data that can be accessed through the CPUID instruction execution. It contains processor type, stepping, model and family ID information as shown in Figure 2-21.

Figure 2-21. CPUID Data

31 RESERVED 28 27 20 19 16 15 13 12 Processor Type 11 8 7 Model 4 3 0

Extended Family ID

Extended Model

RESERVED

Family ID

Stepping ID

CPU ID Data

Platform ID data: The Platform ID data can be used to ensure processor microcode updates are compatible with the processor. The value of the Platform ID or Processor Flag[2:0] as shown in Figure 2-22 is typically unique to the platform type and processor stepping. Refer to the Intel 64 and IA-32 Architectures Software Developers Manual (SDM) Volumes 1, 2, and 3 for more information. Figure 2-22. Platform ID Data
31 Reserved Platform ID Data 3 2 0

Processor Flag

PCU Device ID: This information can be used to uniquely identify the processor power control unit (PCU) device when combined with the Vendor Identification register content and remains constant across all SKUs. Refer to the appropriate register description for the exact processor PCU Device ID value. Figure 2-23. PCU Device ID
31 RESERVED PCU Device ID Data 16 15 PCU Device ID 0

Max Thread ID: The maximum Thread ID data provides the number of supported processor threads. This value is dependent on the number of cores within the processor as determined by the processor SKU and is independent of whether certain cores or corresponding threads are enabled or disabled.

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Figure 2-24. Maximum Thread ID

31 Reserved Maximum Thread ID Data 4 3 Max Thread ID 0

CPU Microcode Update Revision: Reflects the revision number for the microcode update and power control unit firmware updates on the processor sample. The revision data is a unique 32-bit identifier that reflects a combination of specific versions of the processor microcode and PCU control firmware. Figure 2-25. Processor Microcode Revision
31 CPU microcode and PCU firmware revision CPU code patch revision 0

Machine Check Status: Returns error information as logged by the MCA Error Source Log register. See Figure 2-26 for details. The power control unit will assert the relevant bit when the error condition represented by the bit occurs. For example, bit 29 will be set if the package asserted MCERR, bit 30 is set if the package asserted IERR and bit 31 is set if the package asserted CAT_ERR_N. The CAT_ERR_N may be used to signal the occurrence of a MCERR or IERR. Figure 2-26. Machine Check Status
31 CATERR 30 IERR 29 MCERR 28 Reserved MCA Error Source Log 0

2.5.2.6.13

Package Power SKU Unit Read This feature enables the PECI host to read the units of time, energy and power used in the processor and DRAM power control registers for calculating power and timing parameters. In Figure 2-27, the default value of the power unit field [3:0] is 0011b, energy unit [12:8] is 10000b and the time unit [19:16] is 1010b. Actual unit values are calculated as shown in Table 2-9.

Figure 2-27. Package Power SKU Unit Data

31 Reserved 20 19 16 15 13 12 8 7 4 3 0

Time Unit

Reserved

Energy Unit

Reserved

Power Unit

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Table 2-9.

Power Control Register Unit Calculations

Unit Field Value Calculation Default Value

Time Energy Power

1s /

2TIME UNIT

1s / 210 = 976 s 1J / 216 = 15.3 J 1W / 23 = 1/8 W

1J / 2ENERGY UNIT 1W / 2
POWER UNIT

2.5.2.6.14

Package Power SKU Read This read allows the PECI host to access the minimum, Thermal Design Power and maximum power settings for the processor package SKU. It also returns the maximum time interval or window over which the power can be sustained. If the power limiting entity specifies a power limit value outside of the range specified through these settings, power regulation cannot be guaranteed. Since this data is 64 bits wide, PECI facilitates access to this register by allowing two requests to read the lower 32 bits and upper 32 bits separately as shown in Table 2-8. Power units for this read are determined as per the Package Power SKU Unit settings described in Section 2.5.2.6.13. Package Power SKU data is programmed by the PCU firmware during boot time based on SKU dependent power-on default values set during manufacturing. The TDP package power specified through bits [14:0] in Figure 2-28 is the maximum value of the Power Limit1 field in Section 2.5.2.6.26 while the maximum package power in bits [46:32] is the maximum value of the Power Limit2 field. The minimum package power in bits [30:16] is applicable to both the Power Limit1 & Power Limit2 fields and corresponds to a mode when all the cores are operational and in their lowest frequency mode. Attempts to program the power limit below the minimum power value may not be effective since BIOS/OS, and not the PCU, controls disabling of cores and core activity. The maximum time window in bits [54:48] is representative of the maximum rate at which the power control unit (PCU) can sample the package energy consumption and reactively take the necessary measures to meet the imposed power limits. Programming too large a time window runs the risk of the PCU not being able to monitor and take timely action on package energy excursions. On the other hand, programming too small a time window may not give the PCU enough time to sample energy information and enforce the limit. The minimum value of the time window can be obtained by reading bits [21:15] of the PWR_LIMIT_MISC_INFO CSR using the PECI RdPCIConfigLocal() command.

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Figure 2-28. Package Power SKU Data

63 Reserved 55 54 Maximum Time Window 48 47 Reserved 46 Maximum Package Power 32

Package Power SKU (upper bits)

31 Reserved

30 Minimum Package Power

16

15 Reserved

14 TDP Package Power

Package Power SKU (lower bits)

2.5.2.6.15

Wake on PECI Mode Bit Write / Read Setting the Wake on PECI mode bit enables successful completion of the WrPCIConfigLocal(), RdPCIConfigLocal(), WrPCIConfig() and RdPCIConfig() PECI commands by forcing a package pop-up to the C2 state to service these commands if the processor is in a low-power state. The exact power impact of such a pop-up is determined by the product SKU, the C-state from which the pop-up is initiated and the negotiated PECI bit rate. A reset or clear of this bit or simply not setting the Wake on PECI mode bit could result in a timeout response (completion code of 0x82) from the processor indicating that the resources required to service the command are in a low power state. Alternatively, this mode bit can also be read to determine PECI behavior in package states C3 or deeper.

2.5.2.6.16

Accumulated Run Time Read This read returns the total time for which the processor has been executing with a resolution of 1 mS per count. This is tracked by a 32-bit counter that rolls over on reaching the maximum value. This counter activates and starts counting for the first time at RESET_N de-assertion.

2.5.2.6.17

Package Temperature Read This read returns the maximum processor die temperature in 16-bit PECI format. The upper 16 bits of the response data are reserved. The PECI temperature data returned by this read is the instantaneous value and not the average value as returned by the PECI GetTemp() described in Section 2.5.2.3.

Figure 2-29. Package Temperature Read Data

31 RESERVED 16 15 Sign Bit 14 PECI Temperature (Integer Value) 6 5 PECI Temperature (Fractional Value) 0

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2.5.2.6.18

Per Core DTS Temperature Read This feature enables the PECI host to read the maximum value of the DTS temperature for any specific core within the processor. Alternatively, this service can be used to read the System Agent temperature. Temperature is returned in the same format as the Package Temperature Read described in Section 2.5.2.6.17. Data is returned in relative PECI temperature format. Reads to a parameter value outside the supported range will return an error as indicated by a completion code of 0x90. The supported range of parameter values can vary depending on the number of cores within the processor. The temperature data returned through this feature is the instantaneous value and not an averaged value. It is updated once every 1 mS.

2.5.2.6.19

Temperature Target Read The Temperature Target Read allows the PECI host to access the maximum processor junction temperature (Tjmax) in degrees Celsius. This is also the default temperature value at which the processor thermal control circuit activates. The Tjmax value may vary from processor part to part to reflect manufacturing process variations. The Temperature Target read also returns the processor TCONTROL value. TCONTROL is returned in standard PECI temperature format and represents the threshold temperature used by the thermal management system for fan speed control.

Figure 2-30. Temperature Target Read

31 RESERVED 24 23 Processor Tjmax 16 15 TCONTROL 8 7 RESERVED 0

2.5.2.6.20

Package Thermal Status Read / Clear The Thermal Status Read provides information on package level thermal status. Data includes: Thermal Control Circuit (TCC) activation Bidirectional PROCHOT_N signal assertion Critical Temperature Both status and sticky log bits are managed in this status word. All sticky log bits are set upon a rising edge of the associated status bit and the log bits are cleared only by Thermal Status reads or a processor reset. A read of the Thermal Status word always includes a log bit clear mask that allows the host to clear any or all of the log bits that it is interested in tracking. A bit set to 0 in the log bit clear mask will result in clearing the associated log bit. If a mask bit is set to 0 and that bit is not a legal mask, a failing completion code will be returned. A bit set to 1 is ignored and results in no change to any sticky log bits. For example, to clear the TCC Activation Log bit and retain all other log bits, the Thermal Status Read should send a mask of 0xFFFFFFFD.

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Figure 2-31. Thermal Status Word

31 6 5 4 3 2 1 0

Reserved

Critical Temperature Log Critical Temperature Status Bidirectional PROCHOT# Log Bidirectional PROCHOT# Status TCC Activation Log TCC Activation Status
2.5.2.6.21 Thermal Averaging Constant Write / Read This feature allows the PECI host to control the window over which the estimated processor PECI temperature is filtered. The host may configure this window as a power of two. For example, programming a value of 5 results in a filtering window of 25 or 32 samples. The maximum programmable value is 8 or 256 samples. Programming a value of zero would disable the PECI temperature averaging feature. The default value of the thermal averaging constant is 4 which translates to an averaging window size of 24 or 16 samples. More details on the PECI temperature filtering function can be found in Section 2.5.7.3. Figure 2-32. Thermal Averaging Constant Write / Read
31 RESERVED Thermal Averaging Constant 4 3 PECI Temperature Averaging Constant 0

2.5.2.6.22

Thermally Constrained Time Read This features allows the PECI host to access the total time for which the processor has been operating in a lowered power state due to TCC activation. The returned data includes the time required to ramp back up to the original P-state target after TCC activation expires. This timer does not include TCC activation as a result of an external assertion of PROCHOT_N. This is tracked by a 32-bit counter with a resolution of 1mS per count that rolls over or wraps around. On the processor PECI clients, the only logic that can be thermally constrained is that supplied by VCC.

2.5.2.6.23

Current Limit Read This read returns the current limit for the processor VCC power plane in 1/8A increments. Actual current limit data is contained only in the lower 13 bits of the response data. The default return value of 0x438 corresponds to a current limit value of 135A.

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Figure 2-33. Current Config Limit Read Data

31 RESERVED

13

12 Current Limit for processor VCC

Current Config Limit Data

2.5.2.6.24

Accumulated Energy Status Read This service can return the value of the total energy consumed by the entire processor package or just the logic supplied by the VCC power plane as specified through the parameter field in Table 2-8. This information is tracked by a 32-bit counter that wraps around and continues counting on reaching its limit. Energy units for this read are determined as per the Package Power SKU Unit settings described in Section 2.5.2.6.13. While Intel requires reading the accumulated energy data at least once every 16 seconds to ensure functional correctness, a more realistic polling rate recommendation is once every 100mS for better accuracy. This feature assumes a 150W processor. In general, as the power capability decreases, so will the minimum polling rate requirement. When determining energy changes by subtracting energy values between successive reads, Intel advocates using the 2s complement method to account for counter wraparounds. Alternatively, adding all Fs (0xFFFFFFFF) to a negative result from the subtraction will accomplish the same goal.

Figure 2-34. Accumulated Energy Read Data

31 Accumulated CPU Energy Accumulated Energy Status 0

2.5.2.6.25

Power Limit for the VCC Power Plane Write / Read This feature allows the PECI host to program the power limit over a specified time or control window for the processor logic supplied by the VCC power plane. This typically includes all the cores, home agent and last level cache. The processor does not support power limiting on a per-core basis. Actual power limit values are chosen based on the external VR (voltage regulator) capabilities. The units for the Power Limit and Control Time Window are determined as per the Package Power SKU Unit settings described in Section 2.5.2.6.13. Since the exact VCC plane power limit value is a function of the platform VR, this feature is not enabled by default and there are no default values associated with the power limit value or the control time window. The Power Limit Enable bit in Figure 2-35 should be set to activate this feature. The Clamp Mode bit is also required to be set to allow the cores to go into power states below what the operating system originally requested. In general, this feature provides an improved mechanism for VR protection

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compared to the input PROCHOT_N signal assertion method. Both power limit enabling and initialization of power limit values can be done in the same command cycle. Setting a power limit for the VCC plane enables turbo modes for associated logic. External VR protection is guaranteed during boot through operation at safe voltage and frequency. All RAPL parameter values including the power limit value, control time window, clamp mode and enable bit will have to be specified correctly even if the intent is to change just one parameter value when programming over PECI. The usefulness of the VCC power plane RAPL may be somewhat limited if the platform has a fully compliant external voltage regulator. However, platforms using lower cost voltage regulators may find this feature useful. The VCC RAPL value is generally expected to be a static value after initialization and there may not be any use cases for dynamic control of VCC plane power limit values during run time. BIOS may be ideally used to read the VR (and associated heat sink) capabilities and program the PCU with the power limit information during boot. No matter what the method is, Intel recommends exclusive use of just one entity or interface, PECI for instance, to manage VCC plane power limiting needs. If PECI is being used to manage VCC plane power limiting activities, BIOS should lock out all subsequent inband VCC plane power limiting accesses by setting bit 31 of the PP0_POWER_LIMIT MSR and CSR to 1. The same conversion formula used for DRAM Power Limiting (see Section 2.5.2.6.9) should be applied for encoding or programming the Control Time Window in bits [23:17]. Figure 2-35. Power Limit Data for VCC Power Plane
31 RESERVED 24 23 Control Time Window 17 16 Clamp Mode 15 Power Limit Enable 14 VCC Plane Power Limit 0

VCC Power Plane Power Limit Data

2.5.2.6.26

Package Power Limits For Multiple Turbo Modes This feature allows the PECI host to program two power limit values to support multiple turbo modes. The operating systems and drivers can balance the power budget using these two limits. Two separate PECI requests are available to program the lower and upper 32 bits of the power limit data shown in Figure 2-36. The units for the Power Limit and Control Time Window are determined as per the Package Power SKU Unit settings described in Section 2.5.2.6.13 while the valid range for power limit values are determined by the Package Power SKU settings described in Section 2.5.2.6.14. Setting the Clamp Mode bits is required to allow the cores to go into power states below what the operating system originally requested. The Power Limit Enable bits should be set to enable the power limiting function. Power limit values, enable and clamp mode bits can all be set in the same command cycle. All RAPL parameter values including the power limit value, control time window, clamp mode and enable bit will have to be specified correctly even if the intent is to change just one parameter value when programming over PECI. Intel recommends exclusive use of just one entity or interface, PECI for instance, to manage all processor package power limiting and budgeting needs. If PECI is being used to manage package power limiting activities, BIOS should lock out all subsequent inband package power limiting accesses by setting bit 31 of the PACKAGE_POWER_LIMIT MSR and CSR to 1. The power limit 1 is intended to limit processor power consumption to any reasonable value below TDP and defaults to TDP.

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Power Limit 1 values may be impacted by the processor heat sinks and system air flow. Processor power limit 2 can be used as appropriate to limit the current drawn by the processor to prevent any external power supply unit issues. The Power Limit 2 should always be programmed to a value (typically 20%) higher than Power Limit 1 and has no default value associated with it. Though this feature is disabled by default and external programming is required to enable, initialize and control package power limit values and time windows, the processor package will still turbo to TDP if Power Limit 1 is not enabled or initialized. Control Time Window#1 (Power_Limit_1_Time also known as Tau) values may be programmed to be within a range of 250 mS-40 seconds. Control Time Window#2 (Power_Limit_2_Time) values should be in the range 3 mS-10 mS. The same conversion formula used for the DRAM Power Limiting feature (see Section 2.5.2.6.9) should be applied when programming the Control Time Window bits [23:17] for power limit 1 in Figure 2-36. The Control Time Window for power limit 2 can be directly programmed into bits [55:49] in units of mS without the aid of any conversion formulas. Figure 2-36. Package Turbo Power Limit Data
63 RESERVED 56 55 Control Time Window #2 49 48 Clamp Mode #2 47 Power Limit Enable #2 46 Power Limit # 2 32

Package Power Limit 2 31 RESERVED 24 23 Control Time Window #1 17 16 Clamp Mode #1 15 Power Limit Enable #1 14 Power Limit # 1 0

Package Power Limit 1

2.5.2.6.27

Package Power Limit Performance Status Read This service allows the PECI host to assess the performance impact of the currently active power limiting modes. The read return data contains the total amount of time for which the entire processor package has been operating in a power state that is lower than what the operating system originally requested. This information is tracked by a 32-bit counter that wraps around. The unit for time is determined as per the Package Power SKU Unit settings described in Section 2.5.2.6.13.

Figure 2-37. Package Power Limit Performance Data

31 Accumulated CPU Throttle Time Accumulated CPU Throttle Time 0

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2.5.2.6.28

Efficient Performance Indicator Read The Efficient Performance Indicator (EPI) Read provides an indication of the total number of productive cycles. Specifically, these are the cycles when the processor is engaged in any activity to retire instructions and as a result, consuming energy. Any power management entity monitoring this indicator should sample it at least once every 4 seconds to enable detection of wraparounds. Refer to the processor Intel 64 and IA-32 Architectures Software Developers Manual (SDM) Volumes 1, 2, and 3, for details on programming the Energy/Performance Bias (MSR_MISC_PWR_MGMT) register to set the Energy Efficiency policy of the processor.

Figure 2-38. Efficient Performance Indicator Read

31 Efficient Performance Cycles Efficient Performance Indicator Data 0

2.5.2.6.29

ACPI P-T Notify Write & Read This feature enables the processor turbo capability when used in conjunction with the PECI package RAPL or power limit. When the BMC sets the package power limit to a value below TDP, it also determines a new corresponding turbo frequency and notifies the OS using the ACPI Notify mechanism as supported by the _PPC or performance present capabilities object. The BMC then notifies the processor PCU using the PECI ACPI P-T Notify service by programming a new state that is one p-state below the turbo frequency sent to the OS via the _PPC method. When the OS requests a p-state higher than what is specified in bits [7:0] of the PECI ACPI P-T Notify data field, the CPU will treat it as request for P0 or turbo. The PCU will use the IA32_ENERGY_PERFORMANCE_BIAS register settings to determine the exact extent of turbo. Any OS p-state request that is equal to or below what is specified in the PECI ACPI P-T Notify will be granted as long as the RAPL power limit does not impose a lower p-state. However, turbo will not be enabled in this instance even if there is headroom between the processor energy consumption and the RAPL power limit. This feature does not affect the Thermal Monitor behavior of the processor nor is it impacted by the setting of the power limit clamp mode bit.

Figure 2-39. ACPI P-T Notify Data

31 Reserved ACPI P-T Notify Data 8 7 0

New P1 state

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2.5.2.6.30

Caching Agent TOR Read This feature allows the PECI host to read the Caching Agent (Cbo) Table of Requests (TOR). This information is useful for debug in the event of a 3-strike timeout that results in a processor IERR assertion. The 16-bit parameter field is used to specify the Cbo index, TOR array index and bank number according to the following bit assignments. Bits [1:0] - Bank Number - legal values from 0 to 2 Bits [6:2] - TOR Array Index - legal values from 0 to 19 Bits [10:7] - Cbo Index - legal values from 0 to 7 Bit [11] - Read Mode - should be set to 0 for TOR reads Bits [15:12] - Reserved Bit[11] is the Read Mode bit and should be set to 0 for TOR reads. The Read Mode bit can alternatively be set to 1 to read the Core ID (with associated valid bit as shown in Figure 2-40) that points to the first core that asserted the IERR. In this case bits [10:0] of the parameter field are ignored. The Core ID read may not return valid data until at least 1 mS after the IERR assertion.

Figure 2-40. Caching Agent TOR Read Data

31 Cbo TOR Data Read Mode (bit 11) = 0 31 RESERVED Read Mode (bit 11) = 1 4 3 Valid bit 2 Core ID

Note:

Reads to caching agents that are not enabled will return all zeroes. Refer to the debug handbook for details on methods to interpret the crash dump results using the Cbo TOR data shown in Figure 2-40.

2.5.2.6.31

Thermal Margin Read This service allows the PECI host to read the margin to the processor thermal profile or load line. Thermal margin data is returned in the format shown in Figure 2-41 with a sign bit, an integer part and a fractional part. A negative thermal margin value implies that the processor is operating in violation of its thermal load line and may be indicative of a need for more aggressive cooling mechanisms through a fan speed increase or other means. This PECI service will continue to return valid margin values even when the processor die temperature exceeds Tjmax.

Figure 2-41. DTS Thermal Margin Read

31 RESERVED 16 15 Sign Bit 14 Thermal Margin (Integer Value) 6 5 Therm al Margin (Fractional Value) 0

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2.5.2.7

RdIAMSR()
The RdIAMSR() PECI command provides read access to Model Specific Registers (MSRs) defined in the processors Intel Architecture (IA). MSR definitions may be found in the Intel 64 and IA-32 Architectures Software Developers Manual (SDM) Volumes 1, 2, and 3. Refer to Table 2-11 for the exact listing of processor registers accessible through this command.

2.5.2.7.1

Command Format The RdIAMSR() format is as follows: Write Length: 0x05 Read Length: 0x09 (qword) Command: 0xb1 Description: Returns the data maintained in the processor IA MSR space as specified by the Processor ID and MSR Address fields. The Read Length dictates the desired data return size. This command supports only qword responses. All command responses are prepended with a completion code that contains additional pass/fail status information. Refer to Section 2.5.5.2 for details regarding completion codes.

2.5.2.7.2

Processor ID Enumeration The Processor ID field that is used to address the IA MSR space refers to a specific logical processor within the CPU. The Processor ID always refers to the same physical location in the processor silicon regardless of configuration as shown in the example in Figure 2-42. For example, if certain logical processors are disabled by BIOS, the Processor ID mapping will not change. The total number of Processor IDs on a CPU is product-specific. Processor ID enumeration involves discovering the logical processors enabled within the CPU package. This can be accomplished by reading the Max Thread ID value through the RdPkgConfig() command (Index 0, Parameter 3) described in Section 2.5.2.6.12 and subsequently querying each of the supported processor threads. Unavailable processor threads will return a completion code of 0x90. Alternatively, this information may be obtained from the RESOLVED_CORES_MASK register readable through the RdPCIConfigLocal() PECI command described in Section 2.5.2.9 or other means. Bits [7:0] and [9:8] of this register contain the Core Mask and Thread Mask information respectively. The Thread Mask applies to all the enabled cores within the processor package as indicated by the Core Mask. For the processor PECI clients, the Processor ID may take on values in the range 0 through 15.

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Figure 2-42. Processor ID Construction Example

Cores 0,1.2...7

C7 T1 T0

C6 T1 13 T0 12

C5 T1 11 T0 10

C4 T1 9 T0 8 T1 7

C3 T0 6

C2 T1 5 T0 4

C1 T1 3 T0 2

C0 T1 1 T0 0 Processor ID (0..15)

15 14

Thread (0,1) Mask for Core4

Figure 2-43. RdIAMSR()

Note:

The 2-byte MSR Address field and read data field defined in Figure 2-43 are sent in standard PECI ordering with LSB first and MSB last.

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2.5.2.7.3

Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the clients response will indicate a failure.

Table 2-10. RdIAMSR() Response Definition

Response Meaning

Bad FCS Abort FCS CC: 0x40 CC: 0x80 CC: 0x81 CC: 0x82 CC: 0x90 CC: 0x91

Electrical error Illegal command formatting (mismatched RL/WL/Command Code) Command passed, data is valid. Response timeout. The processor was not able to generate the required response in a timely fashion. Retry is appropriate. Response timeout. The processor is not able to allocate resources for servicing this command at this time. Retry is appropriate. The processor hardware resources required to service this command are in a low power state. Retry may be appropriate after modification of PECI wake mode behavior if appropriate. Unknown/Invalid/Illegal Request PECI control hardware, firmware or associated logic error. The processor is unable to process the request.

2.5.2.7.4

RdIAMSR() Capabilities The processor PECI client allows PECI RdIAMSR() access to the registers listed in Table 2-11. These registers pertain to the processor core and uncore error banks (machine check banks 0 through 19). Information on the exact number of accessible banks for the processor device may be obtained by reading the IA32_MCG_CAP[7:0] MSR (0x0179). This register may be alternatively read using a RDMSR BIOS instruction. Please consult the Intel 64 and IA-32 Architectures Software Developers Manual (SDM) Volumes 1, 2, and 3 for more information on the exact number of cores supported by a particular processor SKU. Any attempt to read processor MSRs that are not accessible over PECI or simply not implemented will result in a completion code of 0x90. PECI access to these registers is expected only when in-band access mechanisms are not available.

Table 2-11. RdIAMSR() Services Summary (Sheet 1 of 2)

Process MSR or ID Address (byte) (dword) Meaning Process or ID (byte) MSR Address (dword) Meaning Proces sor ID (byte) MSR Address (dword) Meaning

0x0-0xF 0x0400 0x0-0xF 0x0280 0x0-0xF 0x0401 0x0-0xF 0x0402 0x0-0xF 0x0403 0x0-0xF 0x0404 0x0-0xF 0x0281 0x0-0xF 0x0405 0x0-0xF 0x0406 0x0-0xF 0x0407 0x0-0xF 0x0408

IA32_MC0_CTL IA32_MC0_CTL2 IA32_MC0_STATUS IA32_MC0_ADDR IA32_MC0_MISC IA32_MC1_CTL IA32_MC1_CTL2 IA32_MC1_STATUS IA32_MC1_ADDR IA32_MC1_MISC IA32_MC2_CTL2
1

0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF

0x041B 0x041C 0x0287 0x041D 0x041E 0x041F 0x0420 0x0288 0x0421 0x0422 0x0423

IA32_MC6_MISC IA32_MC7_CTL IA32_MC7_CTL2 IA32_MC7_STATUS IA32_MC7_ADDR IA32_MC7_MISC IA32_MC8_CTL IA32_MC8_CTL2 IA32_MC8_STATUS IA32_MC8_ADDR IA32_MC8_MISC

0x0-0xF 0x0436 0x0-0xF 0x0437 0x0-0xF 0x0438 0x0-0xF 0x028E 0x0-0xF 0x0439 0x0-0xF 0x043A 0x0-0xF 0x043B 0x0-0xF 0x043C 0x0-0xF 0x028F 0x0-0xF 0x043D 0x0-0xF 0x043E

IA32_MC13_ADDR IA32_MC13_MISC IA32_MC14_CTL IA32_MC14_CTL2 IA32_MC14_STATUS IA32_MC14_ADDR IA32_MC14_MISC IA32_MC15_CTL IA32_MC15_CTL2 IA32_MC15_STATUS IA32_MC15_ADDR

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Table 2-11. RdIAMSR() Services Summary (Sheet 2 of 2)

Process MSR or ID Address (byte) (dword) Meaning Process or ID (byte) MSR Address (dword) Meaning Proces sor ID (byte) MSR Address (dword) Meaning

0x0-0xF 0x0282 0x0-0xF 0x0409 0x0-0xF 0x040A 0x0-0xF 0x040B 0x0-0xF 0x040C 0x0-0xF 0x0283 0x0-0xF 0x040D 0x0-0xF 0x040E 0x0-0xF 0x040F 0x0-0xF 0x0410 0x0-0xF 0x0284 0x0-0xF 0x0411 0x0-0xF 0x0412 0x0-0xF 0x0413 0x0-0xF 0x0414 0x0-0xF 0x0285 0x0-0xF 0x0415 0x0-0xF 0x0416 0x0-0xF 0x0417 0x0-0xF 0x0418 0x0-0xF 0x0286 0x0-0xF 0x0419 0x0-0xF 0x041A

IA32_MC2_CTL2 IA32_MC2_STATUS IA32_MC2_ADDR2 IA32_MC2_MISC2 IA32_MC3_CTL IA32_MC3_CTL2 IA32_MC3_STATUS IA32_MC3_ADDR IA32_MC3_MISC IA32_MC4_CTL IA32_MC4_CTL2 IA32_MC4_STATUS IA32_MC4_ADDR2 IA32_MC4_MISC2 IA32_MC5_CTL IA32_MC5_CTL2 IA32_MC5_STATUS IA32_MC5_ADDR IA32_MC5_MISC IA32_MC6_CTL IA32_MC6_CTL2 IA32_MC6_STATUS IA32_MC6_ADDR

0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF 0x0-0xF

0x0424 0x0289 0x0425 0x0426 0x0427 0x0428 0x028A 0x0429 0x042A 0x042B 0x042C 0x028B 0x042D 0x042E 0x042F 0x0430 0x028C 0x0431 0x0432 0x0433 0x0434 0x028D 0x0435

IA32_MC9_CTL IA32_MC9_CTL2 IA32_MC9_STATUS IA32_MC9_ADDR IA32_MC9_MISC IA32_MC10_CTL IA32_MC10_CTL2

0x0-0xF 0x043F 0x0-0xF 0x0440 0x0-0xF 0x0290 0x0-0xF 0x0441 0x0-0xF 0x0442 0x0-0xF 0x0443 0x0-0xF 0x0444

IA32_MC15_MISC IA32_MC16_CTL IA32_MC16_CTL2 IA32_MC16_STATUS IA32_MC16_ADDR IA32_MC16_MISC IA32_MC17_CTL IA32_MC17_CTL2 IA32_MC17_STATUS IA32_MC17_ADDR IA32_MC17_MISC IA32_MC18_CTL IA32_MC18_CTL2 IA32_MC18_STATUS IA32_MC18_ADDR IA32_MC18_MISC IA32_MC19_CTL IA32_MC19_CTL2 IA32_MC19_STATUS IA32_MC19_ADDR IA32_MCG_CAP IA32_MCG_STATUS IA32_MCG_CONTAIN

IA32_MC10_STATUS 0x0-0xF 0x0291 IA32_MC10_ADDR IA32_MC10_MISC IA32_MC11_CTL IA32_MC11_CTL2 0x0-0xF 0x0445 0x0-0xF 0x0446 0x0-0xF 0x0447 0x0-0xF 0x0448

IA32_MC11_STATUS 0x0-0xF 0x0292 IA32_MC11_ADDR IA32_MC11_MISC IA32_MC12_CTL IA32_MC12_CTL2 0x0-0xF 0x0449 0x0-0xF 0x044A 0x0-0xF 0x044B 0x0-0xF 0x044C

IA32_MC12_STATUS 0x0-0xF 0x0293 IA32_MC12_ADDR IA32_MC12_MISC IA32_MC13_CTL IA32_MC13_CTL2 0x0-0xF 0x044D 0x0-0xF 0x044E 0x0-0xF 0x0179 0x0-0xF 0x017A

IA32_MC13_STATUS 0x0-0xF 0x0178

Notes: 1. The IA32_MC0_MISC register details will be available upon implementation in a future processor stepping. 2. The MCi_ADDR and MCi_MISC registers for machine check banks 2 & 4 are not implemented on the processors. The MCi_CTL register for machine check bank 2 is also not implemented. 3. The PECI host must determine the total number of machine check banks and the validity of the MCi_ADDR and MCi_MISC register contents prior to issuing a read to the machine check bank similar to standard machine check architecture enumeration and accesses. 4. The information presented in Table 2-11 is applicable to the processor only. No association between bank numbers and logical functions should be assumed for any other processor devices (past, present or future) based on the information presented in Table 2-11. 5. The processor machine check banks 4 through 19 reside in the processor uncore and hence will return the same value independent of the processor ID used to access these banks. 6. The IA32_MCG_STATUS, IA32_MCG_CONTAIN and IA32_MCG_CAP are located in the uncore and will return the same value independent of the processor ID used to access them. 7. The processor machine check banks 0 through 3 are core-specific. Since the processor ID is thread-specific and not corespecific, machine check banks 0 through 3 will return the same value for a particular core independent of the thread referenced by the processor ID. 8. PECI accesses to the machine check banks may not be possible in the event of a core hang. A warm reset of the processor may be required to read any sticky machine check banks. 9. Valid processor ID values may be obtained by using the enumeration methods described in Section 2.5.2.7.2. 10. Reads to a machine check bank within a core or thread that is disabled will return all zeroes with a completion code of 0x90. 11. For SKUs where Intel QPI is disabled or absent, reads to the corresponding machine check banks will return all zeros with a completion code of 0x40.

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2.5.2.8

RdPCIConfig()
The RdPCIConfig() command provides sideband read access to the PCI configuration space maintained in downstream devices external to the processor. PECI originators may conduct a device/function/register enumeration sweep of this space by issuing reads in the same manner that the BIOS would. A response of all 1s may indicate that the device/function/register is unimplemented even with a passing completion code. Alternatively, reads to unimplemented registers may return a completion code of 0x90 indicating an invalid request. Responses will follow normal PCI protocol. PCI configuration addresses are constructed as shown in Figure 2-44. Under normal inband procedures, the Bus number would be used to direct a read or write to the proper device. Actual PCI bus numbers for all PCI devices including the PCH are programmable by BIOS. The bus number for PCH devices may be obtained by reading the CPUBUSNO CSR. Refer to the Intel Xeon Processor E5 Product Family Datasheet Volume Two document for details on this register.

Figure 2-44. PCI Configuration Address

31 28 27 20 19 15 14 12 11 0

Reserved

Bus

Device

Function

Register

PCI configuration reads may be issued in byte, word or dword granularities. 2.5.2.8.1 Command Format The RdPCIConfig() format is as follows: Write Length: 0x06 Read Length: 0x05 (dword) Command: 0x61 Description: Returns the data maintained in the PCI configuration space at the requested PCI configuration address. The Read Length dictates the desired data return size. This command supports only dword responses with a completion code on the processor PECI clients. All command responses are prepended with a completion code that includes additional pass/fail status information. Refer to Section 2.5.5.2 for details regarding completion codes. Figure 2-45. RdPCIConfig()

Note:

The 4-byte PCI configuration address and read data field defined in Figure 2-45 are sent in standard PECI ordering with LSB first and MSB last.

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2.5.2.8.2

Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the clients response will indicate a failure. The PECI client response can also vary depending on the address and data. It will respond with a passing completion code if it successfully submits the request to the appropriate location and gets a response.

Table 2-12. RdPCIConfig() Response Definition

Response Meaning

Bad FCS Abort FCS CC: 0x40 CC: 0x80 CC: 0x81 CC: 0x82

Electrical error Illegal command formatting (mismatched RL/WL/Command Code) Command passed, data is valid. Response timeout. The processor was not able to generate the required response in a timely fashion. Retry is appropriate. Response timeout. The processor is not able to allocate resources for servicing this command at this time. Retry is appropriate. The processor hardware resources required to service this command are in a low power state. Retry may be appropriate after modification of PECI wake mode behavior if appropriate. Unknown/Invalid/Illegal Request PECI control hardware, firmware or associated logic error. The processor is unable to process the request.

CC: 0x90 CC: 0x91

2.5.2.9

RdPCIConfigLocal()
The RdPCIConfigLocal() command provides sideband read access to the PCI configuration space that resides within the processor. This includes all processor IIO and uncore registers within the PCI configuration space as described in the Intel Xeon Processor E5 Product Family Datasheet Volume Two document. PECI originators may conduct a device/function enumeration sweep of this space by issuing reads in the same manner that the BIOS would. A response of all 1s may indicate that the device/function/register is unimplemented even with a passing completion code. Alternatively, reads to unimplemented or hidden registers may return a completion code of 0x90 indicating an invalid request. It is also possible that reads to function 0 of non-existent IIO devices issued prior to BIOS POST may return all 0s with a passing completion code. PECI originators can access this space even prior to BIOS enumeration of the system buses. There is no read restriction on accesses to locked registers. PCI configuration addresses are constructed as shown in Figure 2-46. Under normal inband procedures, the Bus number would be used to direct a read or write to the proper device. PECI reads to the processor IIO devices should specify a bus number of 0000 and reads to the rest of the processor uncore should specify a bus number of 0001 for bits [23:20] in Figure 2-46. Any request made with a bad Bus number is ignored and the client will respond with all 0s and a passing completion code.

Figure 2-46. PCI Configuration Address for local accesses

23 20 19 15 14 12 11 0

Bus

Device

Function

Register

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Command Format The RdPCIConfigLocal() format is as follows: Write Length: 0x05 Read Length: 0x02 (byte), 0x03 (word), 0x05 (dword) Command: 0xe1 Description: Returns the data maintained in the PCI configuration space within the processor at the requested PCI configuration address. The Read Length dictates the desired data return size. This command supports byte, word and dword responses as well as a completion code. All command responses are prepended with a completion code that includes additional pass/fail status information. Refer to Section 2.5.5.2 for details regarding completion codes.

Figure 2-47. RdPCIConfigLocal()

Byte # Byte Definition 0 Client Address 1 Write Length 0x05 2 Read Length {0x02,0x03,0x05} 3 Cmd Code 0xe1

4 Host ID[7:1] & Retry[0] LSB

6 PCI Configuration Address

7 MSB

8 FCS

9 Completion Code
Note:

10 LSB

11 Data (1, 2 or 4 bytes)

12

13 MSB

14 FCS

The 3-byte PCI configuration address and read data field defined in Figure 2-47 are sent in standard PECI ordering with LSB first and MSB last.

2.5.2.9.2

Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the clients response will indicate a failure. The PECI client response can also vary depending on the address and data. It will respond with a passing completion code if it successfully submits the request to the appropriate location and gets a response.

Table 2-13. RdPCIConfigLocal() Response Definition (Sheet 1 of 2)

Response Meaning

Bad FCS Abort FCS CC: 0x40 CC: 0x80 CC: 0x81

Electrical error Illegal command formatting (mismatched RL/WL/Command Code) Command passed, data is valid. Response timeout. The processor was not able to generate the required response in a timely fashion. Retry is appropriate. Response timeout. The processor is not able to allocate resources for servicing this command at this time. Retry is appropriate.

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Table 2-13. RdPCIConfigLocal() Response Definition (Sheet 2 of 2)

Response Meaning

CC: 0x82

The processor hardware resources required to service this command are in a low power state. Retry may be appropriate after modification of PECI wake mode behavior if appropriate. Unknown/Invalid/Illegal Request PECI control hardware, firmware or associated logic error. The processor is unable to process the request.

CC: 0x90 CC: 0x91

2.5.2.10

WrPCIConfigLocal()
The WrPCIConfigLocal() command provides sideband write access to the PCI configuration space that resides within the processor. PECI originators can access this space even before BIOS enumeration of the system buses. The exact listing of supported devices and functions for writes using this command on the processor is defined in Table 2-19. The write accesses to registers that are locked will not take effect but will still return a completion code of 0x40. However, write accesses to registers that are hidden will return a completion code of 0x90. Because a WrPCIConfigLocal() command results in an update to potentially critical registers inside the processor, it includes an Assured Write FCS (AW FCS) byte as part of the write data payload. In the event that the AW FCS mismatches with the client-calculated FCS, the client will abort the write and will always respond with a bad write FCS. PCI Configuration addresses are constructed as shown in Figure 2-46. The write command is subject to the same address configuration rules as defined in Section 2.5.2.9. PCI configuration writes may be issued in byte, word or dword granularity.

2.5.2.10.1

Command Format The WrPCIConfigLocal() format is as follows: Write Length: 0x07 (byte), 0x08 (word), 0x0a (dword) Read Length: 0x01 Command: 0xe5 AW FCS Support: Yes Description: Writes the data sent to the requested register address. Write Length dictates the desired write granularity. The command always returns a completion code indicating pass/fail status. Refer to Section 2.5.5.2 for details on completion codes.

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Figure 2-48. WrPCIConfigLocal()

Byte # Byte Definition 0 Client Address 1 Write Length {0x07, 0x08, 0x0a} 4 Host ID[7:1] & Retry[0] 8 LSB LSB 5 2 Read Length 0x01 6 PCI Configuration Address 3 Cmd Code 0xe5 7 MSB

9 Data (1, 2 or 4 bytes)

10

11 MSB

12 AW FCS

13 FCS

14 Completion Code

15 FCS

Note:

The 3-byte PCI configuration address and write data field defined in Figure 2-48 are sent in standard PECI ordering with LSB first and MSB last.

2.5.2.10.2

Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the clients response will indicate a failure. The PECI client response can also vary depending on the address and data. It will respond with a passing completion code if it successfully submits the request to the appropriate location and gets a response.

Table 2-14. WrPCIConfigLocal() Response Definition

Response Meaning

Bad FCS Abort FCS CC: 0x40 CC: 0x80 CC: 0x81 CC: 0x82

Electrical error or AW FCS failure Illegal command formatting (mismatched RL/WL/Command Code) Command passed, data is valid. Response timeout. The processor was not able to generate the required response in a timely fashion. Retry is appropriate. Response timeout. The processor is not able to allocate resources for servicing this command at this time. Retry is appropriate. The processor hardware resources required to service this command are in a low power state. Retry may be appropriate after modification of PECI wake mode behavior if appropriate. Unknown/Invalid/Illegal Request PECI control hardware, firmware or associated logic error. The processor is unable to process the request.

CC: 0x90 CC: 0x91

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WrPCIConfigLocal() Capabilities On the processor PECI clients, the PECI WrPCIConfigLocal() command provides a method for programming certain integrated memory controller and IIO functions as described in Table 2-15. Refer to the Intel Xeon Processor E5 Product Family Datasheet Volume Two for more details on specific register definitions. It also enables writing to processor REUT (Robust Electrical Unified Test) registers associated with the Intel QPI, PCIe* and DDR3 functions.

Table 2-15. WrPCIConfigLocal() Memory Controller and IIO Device/Function Support

Bus Device Function Offset Range Description

0000 0001 0001 0001 0001 0001

0-5 15 15 15 16 16

0-7 0 0 1 0, 1, 4, 5 2, 3, 6, 7

000-FFFh 104h-127h 180h-1AFh 080h-0CFh 104h-18Bh 1F4h-1FFh 104h-147h

Integrated I/O (IIO) Configuration Registers Integrated Memory Controller MemHot Registers Integrated Memory Controller SMBus Registers Integrated Memory Controller RAS Registers (Scrub/Spare) Integrated Memory Controller Thermal Control Registers Integrated Memory Controller Error Registers

2.5.3
2.5.3.1

Client Management
Power-up Sequencing
The PECI client will not be available when the PWRGOOD signal is de-asserted. Any transactions on the bus during this time will be completely ignored, and the host will read the response from the client as all zeroes. PECI client initialization is completed approximately 100 S after the PWRGOOD assertion. This is represented by the start of the PECI Client Data Not Ready (DNR) phase in Figure 2-49. While in this phase, the PECI client will respond normally to the Ping() and GetDIB() commands and return the highest processor die temperature of 0x0000 to the GetTemp() command. All other commands will get a Response Timeout completion in the DNR phase as shown in Table 2-16. All PECI services with the exception of core MSR space accesses become available ~500 S after RESET_N de-assertion as shown in Figure 2-49. PECI will be fully functional with all services including core accesses being available when the core comes out of reset upon completion of the RESET microcode execution. In the event of the occurrence of a fatal or catastrophic error, all PECI services with the exception of core MSR space accesses will be available during the DNR phase to facilitate debug through configuration space accesses.

Table 2-16. PECI Client Response During Power-Up (Sheet 1 of 2)

Command Response During Data Not Ready Response During Available Except Core Services

Ping() GetDIB() GetTemp() RdPkgConfig() WrPkgConfig() RdIAMSR()

Fully functional Fully functional Client responds with a hot reading or 0x0000 Client responds with a timeout completion code of 0x81 Client responds with a timeout completion code of 0x81 Client responds with a timeout completion code of 0x81

Fully functional Fully functional Fully functional Fully functional Fully functional Client responds with a timeout completion code of 0x81

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Table 2-16. PECI Client Response During Power-Up (Sheet 2 of 2)

Command Response During Data Not Ready Response During Available Except Core Services

RdPCIConfigLocal() WrPCIConfigLocal() RdPCIConfig()

Client responds with a timeout completion code of 0x81 Client responds with a timeout completion code of 0x81 Client responds with a timeout completion code of 0x81

Fully functional Fully functional Fully functional

In the event that the processor is tri-stated using power-on-configuration controls, the PECI client will also be tri-stated. Processor tri-state controls are described in Section 7.3, Power-On Configuration (POC) Options. Figure 2-49. The Processor PECI Power-up Timeline()

PWRGOOD RESET_N Core execution PECI Client Status SOCKET_ID[1:0] In Reset In Reset X
Data Not Ready

idle Reset uCode

Available except core services

running Boot BIOS Fully Operational

SOCKET ID Valid

2.5.3.2

Device Discovery
The PECI client is available on all processors. The presence of a PECI enabled processor in a CPU socket can be confirmed by using the Ping() command described in Section 2.5.2.1. Positive identification of the PECI revision number can be achieved by issuing the GetDIB() command. The revision number acts as a reference to the PECI specification document applicable to the processor client definition. Please refer to Section 2.5.2.2 for details on GetDIB response formatting.

2.5.3.3

Client Addressing
The PECI client assumes a default address of 0x30. The PECI client address for the processor is configured through the settings of the SOCKET_ID[1:0] signals. Each processor socket in the system requires that the two SOCKET_ID signals be configured to a different PECI addresses. Strapping the SOCKET_ID[1:0] pins results in the client addresses shown in Table 2-17. These package strap(s) are evaluated at the assertion of PWRGOOD (as depicted in Figure 2-49). Refer to the appropriate Platform Design Guide (PDG) for recommended resistor values for establishing non-default SOCKET_ID settings.

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The client address may not be changed after PWRGOOD assertion, until the next power cycle on the processor. Removal of a processor from its socket or tri-stating a processor will have no impact to the remaining non-tri-stated PECI client addresses. Since each socket in the system should have a unique PECI address, the SOCKET_ID strapping is required to be unique for each socket. Table 2-17. SOCKET ID Strapping
SOCKET_ID[1] Strap SOCKET_ID[0] Strap PECI Client Address

Ground Ground VTT VTT

Ground VTT Ground VTT

0x30 0x31 0x32 0x33

2.5.3.4

C-states
The processor PECI client may be fully functional in most core and package C-states. The Ping(), GetDIB(), GetTemp(), RdPkgConfig() and WrPkgConfig() commands have no measurable impact on CPU power in any of the core or package C-states. The RdIAMSR() command will complete normally unless the targeted core is in a Cstate that is C3 or deeper. The PECI client will respond with a completion code of 0x82 (see Table 2-22 for definition) for RdIAMSR() accesses in core C-states that are C3 or deeper. The RdPCIConfigLocal(), WrPCIConfigLocal(), and RdPCIConfig() commands will not impact the core C-states but may have a measurable impact on the package Cstate. The PECI client will successfully return data without impacting package Cstate if the resources needed to service the command are not in a low power state. If the resources required to service the command are in a low power state, the PECI client will respond with a completion code of 0x82 (see Table 2-22 for definition). If this is the case, setting the Wake on PECI mode bit as described in Section 2.5.2.6 can cause a package pop-up to the C2 state and enable successful completion of the command. The exact power impact of a pop-up to C2 will vary by product SKU, the C-state from which the pop-up is initiated and the negotiated PECI bit rate.

Table 2-18. Power Impact of PECI Commands vs. C-states

Command Power Impact

Ping() GetDIB() GetTemp() RdPkgConfig() WrPkgConfig() RdIAMSR() RdPCIConfigLocal() WrPCIConfigLocal() RdPCIConfig()

Not measurable Not measurable Not measurable Not measurable Not measurable Not measurable. PECI client will not return valid data in core C-state that is C3 or deeper May require package pop-up to C2 state May require package pop-up to C2 state May require package pop-up to C2 state

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S-states
The processor PECI client is always guaranteed to be operational in the S0 sleep state. The Ping(), GetDIB(), GetTemp(), RdPkgConfig(), WrPkgConfig(), RdPCIConfigLocal() and WrPCIConfigLocal() will be fully operational in S0 and S1. Responses in S3 or deeper states are dependent on POWERGOOD assertion status. The RdPCIConfig() and RdIAMSR() responses are guaranteed in S0 only. Behavior in S1 or deeper states is indeterminate. PECI behavior is indeterminate in the S3, S4 and S5 states and responses to PECI originator requests when the PECI client is in these states cannot be guaranteed.

2.5.3.6

Processor Reset
The processor PECI client is fully reset on all RESET_N assertions. Upon deassertion of RESET_N where power is maintained to the processor (otherwise known as a warm reset), the following are true: The PECI client assumes a bus Idle state. The Thermal Filtering Constant is retained. PECI SOCKET_ID is retained. GetTemp() reading resets to 0x0000. Any transaction in progress is aborted by the client (as measured by the client no longer participating in the response). The processor client is otherwise reset to a default configuration. The assertion of the CPU_ONLY_RESET signal does not reset the processor PECI client. As such, it will have no impact on the basic PECI commands, namely the Ping(), GetTemp() and GetDIB(). However, it is likely that other PECI commands that utilize processor resources being reset will receive a resource unavailable response till the reset sequence is completed.

2.5.3.7

System Service Processor (SSP) Mode Support

Sockets in SSP mode have limited PECI command support. Only the following PECI commands will be supported while in SSP mode. Other PECI commands are not guaranteed to complete in this mode. Ping RdPCIConfigLocal WrPCIConfigLocal (all uncore and IIO CSRs within the processor PCI configuration space will be accessible) RdPkgConfig (Index 0 only) Sockets remain in SSP mode until the "Go" handshake is received. This is applicable to the following SSP modes.

2.5.3.7.1

BMC INIT Mode The BMC INIT boot mode is used to provide a quick and efficient means to transfer responsibility for uncore configuration to a service processor like the BMC. In this mode, the socket performs a minimal amount of internal configuration and then waits for the BMC or service processor to complete the initialization.

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Link Init Mode In cases where the socket is not one Intel QPI hop away from the Firmware Agent socket, or a working link to the Firmware Agent socket cannot be resolved, the socket is placed in Link Init mode. The socket performs a minimal amount of internal configuration and waits for complete configuration by BIOS.

2.5.3.8

Processor Error Handling

Availability of PECI services may be affected by the processor PECI client error status. Server manageability requirements place a strong emphasis on continued availability of PECI services to facilitate logging and debug of the error condition. Most processor PECI client services are available in the event of a CAT_ERR_N assertion though they cannot be guaranteed. The Ping(), GetDIB(), GetTemp(), RdPkgConfig() and WrPkgConfig() commands will be serviced if the source of the CAT_ERR_N assertion is not in the processor power control unit hardware, firmware or associated register logic. Additionally, the RdPCIConfigLocal() and WrPCIConfigLocal() commands may also be serviced in this case. It is recommended that the PECI originator read Index 0/Parameter 5 using the RdPkgConfig() command to debug the CAT_ERR_N assertion. The PECI client will return the 0x91 completion code if the CAT_ERR_N assertion is caused by the PCU hardware, firmware or associated logic errors. In such an event, only the Ping(), GetTemp() and GetDIB() PECI commands may be serviced. All other processor PECI services will be unavailable and further debug of the processor error status will not be possible. If the PECI client returns a passing completion code, the originator should use the response data to determine the cause of the CAT_ERR_N assertion. In such an event, it is also recommended that the PECI originator determine the exact suite of available PECI client services by issuing each of the PECI commands. The processor will issue timeout responses for those services that may not be available. If the PECI client continues to return the 0x81 completion code in response to multiple retries of the RdPkgConfig() command, no PECI services, with the exception of the Ping(), GetTemp() and GetDIB(), will be guaranteed. The RdIAMSR() command may be serviced during a CAT_ERR_N assertion though it cannot be guaranteed.

2.5.3.9

Originator Retry and Timeout Policy

The PECI originator may need to retry a command if the processor PECI client responds with a response timeout completion code or a bad Read FCS. In each instance, the processor PECI client may have started the operation but not completed it yet. When the 'retry' bit is set, the PECI client will ignore a new request if it exactly matches a previous valid request. The processor PECI client will not clear the semaphore that was acquired to service the request until the originator sends the retry request in a timely fashion to successfully retrieve the response data. In the absence of any automatic timeouts, this could tie up shared resources and result in artificial bandwidth conflicts.

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Enumerating PECI Client Capabilities

The PECI host originator should be designed to support all optional but desirable features from all processors of interest. Each feature has a discovery method and response code that indicates availability on the destination PECI client. The first step in the enumeration process would be for the PECI host to confirm the Revision Number through the use of the GetDIB() command. The revision number returned by the PECI client processor always maps to the revision number of the PECI specification that it is designed to. The Minor Revision Number as described in Table 2-2 may be used to identify the subset of PECI commands that the processor in question supports for any major PECI revision. The next step in the enumeration process is to utilize the desired command suite in a real execution context. If the Write FCS response is an Abort FCS or if the data returned includes an Unknown/Invalid/Illegal Request completion code (0x90), then the command is unsupported. Enumerating known commands without real, execution context data, or attempting undefined commands, is dangerous because a write command could result in unexpected behavior if the data is not properly formatted. Methods for enumerating write commands using carefully constructed and innocuous data are possible, but are not guaranteed by the PECI client definition. This enumeration procedure is not robust enough to detect differences in bit definitions or data interpretation in the message payload or client response. Instead, it is only designed to enumerate discrete features.

2.5.4

Multi-Domain Commands
The processor does not support multiple domains, but it is possible that future products will, and the following tables are included as a reference for domain-specific definitions.

Table 2-19. Domain ID Definition

Domain ID 0b01 Domain Number 0

0b10

Table 2-20. Multi-Domain Command Code Reference

Command Name Domain 0 Code 0x01 0xa1 0xa5 0xb1 0x61 0xe1 0xe5 Domain 1 Code

GetTemp() RdPkgConfig() WrPkgConfig() RdIAMSR() RdPCIConfig() RdPCIConfigLocal() WrPCIConfigLocal()

0x02 0xa2 0xa6 0xb2 0x62 0xe2 0xe6

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2.5.5.1

Client Responses
Abort FCS
The Client responds with an Abort FCS under the following conditions: The decoded command is not understood or not supported on this processor (this includes good command codes with bad Read Length or Write Length bytes). Assured Write FCS (AW FCS) failure. Under most circumstances, an Assured Write failure will appear as a bad FCS. However, when an originator issues a poorly formatted command with a miscalculated AW FCS, the client will intentionally abort the FCS in order to guarantee originator notification.

2.5.5.2

Completion Codes
Some PECI commands respond with a completion code byte. These codes are designed to communicate the pass/fail status of the command and may also provide more detailed information regarding the class of pass or fail. For all commands listed in Section 2.5.2 that support completion codes, the definition in the following table applies. Throughout this document, a completion code reference may be abbreviated with CC. An originator that is decoding these commands can apply a simple mask as shown in Table 2-21 to determine a pass or fail. Bit 7 is always set on a command that did not complete successfully and is cleared on a passing command.

Table 2-21. Completion Code Pass/Fail Mask

0xxx xxxxb 1xxx xxxxb Command passed Command failed

Table 2-22. Device Specific Completion Code (CC) Definition

Completion Code Description

0x40 CC: 0x80 CC: 0x81 CC: 0x82

Command Passed Response timeout. The processor was not able to generate the required response in a timely fashion. Retry is appropriate. Response timeout. The processor was not able to allocate resources for servicing this command. Retry is appropriate. The processor hardware resources required to service this command are in a low power state. Retry may be appropriate after modification of PECI wake mode behavior if appropriate. Reserved Unknown/Invalid/Illegal Request PECI control hardware, firmware or associated logic error. The processor is unable to process the request. Reserved

CC: 0x83-8F CC: 0x90 CC: 0x91 CC: 0x92-9F

Note:

The codes explicitly defined in Table 2-22 may be useful in PECI originator response algorithms. Reserved or undefined codes may also be generated by a PECI client device, and the originating agent must be capable of tolerating any code. The Pass/Fail mask defined in Table 2-21 applies to all codes, and general response policies may be based on this information. Refer to Section 2.5.6 for originator response policies and recommendations.

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2.5.6

Originator Responses
The simplest policy that an originator may employ in response to receipt of a failing completion code is to retry the request. However, certain completion codes or FCS responses are indicative of an error in command encoding and a retry will not result in a different response from the client. Furthermore, the message originator must have a response policy in the event of successive failure responses. Refer to Table 2-22 for originator response guidelines. Refer to the definition of each command in Section 2.5.2 for a specific definition of possible command codes or FCS responses for a given command. The following response policy definition is generic, and more advanced response policies may be employed at the discretion of the originator developer.

Table 2-23. Originator Response Guidelines

Response After 1 Attempt After 3 Attempts

Bad FCS Abort FCS CC: 0x8x CC: 0x9x

Retry Retry Retry Abandon any further attempts and notify application layer Force bus idle (drive low) for 1 mS and retry Pass Pass

Fail with PECI client device error. Fail with PECI client device error if command was not illegal or malformed. The PECI client has failed in its attempts to generate a response. Notify application layer. N/A

None (all 0s) CC: 0x4x Good FCS

Fail with PECI client device error. Client may not be alive or may be otherwise unresponsive (for example, it could be in RESET). N/A N/A

2.5.7
2.5.7.1

DTS Temperature Data

Format
The temperature is formatted in a 16-bit, 2s complement value representing a number of 1/64 degrees centigrade. This format allows temperatures in a range of 512 C to be reported to approximately a 0.016 C resolution.

Figure 2-50. Temperature Sensor Data Format MSB Upper nibble

S Sign x x x

MSB Lower nibble

x x x x Integer Value (0-511)

LSB Upper nibble

x x x x

LSB Lower nibble

x x x x Fractional Value (~0.016)

2.5.7.2

Interpretation
The resolution of the processors Digital Thermal Sensor (DTS) is approximately 1C, which can be confirmed by a RDMSR from the IA32_THERM_STATUS MSR where it is architecturally defined. The MSR read will return only bits [13:6] of the PECI temperature sensor data defined in Figure 2-50. PECI temperatures are sent through a configurable low-pass filter prior to delivery in the GetTemp() response data. The output of this filter produces temperatures at the full 1/64C resolution even though the DTS itself is not this accurate.

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Temperature readings from the processor are always negative in a 2s complement format, and imply an offset from the processor Tjmax (PECI = 0). For example, if the processor Tjmax is 100C, a PECI thermal reading of -10 implies that the processor is running at approximately 10C below Tjmax or at 90C. PECI temperature readings are not reliable at temperatures above Tjmax since the processor is outside its operating range and hence, PECI temperature readings are never positive. The changes in PECI data counts are approximately linear in relation to changes in temperature in degrees centigrade. A change of 1 in the PECI count represents roughly a temperature change of 1 degree centigrade. This linearity is approximate and cannot be guaranteed over the entire range of PECI temperatures, especially as the offset from the maximum PECI temperature (zero) increases.

2.5.7.3

Temperature Filtering
The processor digital thermal sensor (DTS) provides an improved capability to monitor device hot spots, which inherently leads to more varying temperature readings over short time intervals. Coupled with the fact that typical fan speed controllers may only read temperatures at 4Hz, it is necessary for the thermal readings to reflect thermal trends and not instantaneous readings. Therefore, PECI supports a configurable lowpass temperature filtering function that is expressed by the equation:

TN = (1-) * TN-1 + * TSAMPLE

where TN and TN-1 are the current and previous averaged PECI temperature values respectively, TSAMPLE is the current PECI temperature sample value and the variable = 1/2X, where X is the Thermal Averaging Constant that is programmable as described in Section 2.5.2.6.21.

2.5.7.4

Reserved Values
Several values well out of the operational range are reserved to signal temperature sensor errors. These are summarized in Table 2-24.

Table 2-24. Error Codes and Descriptions

Error Code Description

0x8000 0x8001 0x8002 0x8003-0x81ff

General Sensor Error (GSE) Reserved Sensor is operational, but has detected a temperature below its operational range (underflow) Reserved

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3
3.1

Technologies
Intel Virtualization Technology (Intel VT)
Intel Virtualization Technology (Intel VT) makes a single system appear as multiple independent systems to software. This allows multiple, independent operating systems to run simultaneously on a single system. Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets. Intel Virtualization Technology (Intel VT) for Intel 64 and IA-32 Intel Architecture (Intel VT-x) adds hardware support in the processor to improve the virtualization performance and robustness. Intel VT-x specifications and functional descriptions are included in the Intel 64 and IA-32 Architectures Software Developers Manual, Volume 3B and is available at http://www.intel.com/ products/processor/manuals/index.htm Intel Virtualization Technology (Intel VT) for Directed I/O (Intel VT-d) adds processor and uncore implementations to support and improve I/O virtualization performance and robustness. The Intel VT-d spec and other Intel VT documents can be referenced at http://www.intel.com/technology/ virtualization/index.htm.

3.1.1

Intel VT-x Objectives

Intel VT-x provides hardware acceleration for virtualization of IA platforms. Virtual Machine Monitor (VMM) can use Intel VT-x features to provide improved reliable virtualized platform. By using Intel VT-x, a VMM is: Robust: VMMs no longer need to use para-virtualization or binary translation. This means that they will be able to run off-the-shelf OSs and applications without any special steps. Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA x86 processors. More reliable: Due to the hardware support, VMMs can now be smaller, less complex, and more efficient. This improves reliability and availability and reduces the potential for software conflicts. More secure: The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system.

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3.1.2

Intel VT-x Features

The processor core supports the following Intel VT-x features: Extended Page Tables (EPT) hardware assisted page table virtualization eliminates VM exits from guest OS to the VMM for shadow page-table maintenance Virtual Processor IDs (VPID) Ability to assign a VM ID to tag processor core hardware structures (for example, TLBs) This avoids flushes on VM transitions to give a lower-cost VM transition time and an overall reduction in virtualization overhead. Guest Preemption Timer Mechanism for a VMM to preempt the execution of a guest OS after an amount of time specified by the VMM. The VMM sets a timer value before entering a guest The feature aids VMM developers in flexibility and Quality of Service (QoS) guarantees Descriptor-Table Exiting Descriptor-table exiting allows a VMM to protect a guest OS from internal (malicious software based) attack by preventing relocation of key system data structures like IDT (interrupt descriptor table), GDT (global descriptor table), LDT (local descriptor table), and TSS (task segment selector). A VMM using this feature can intercept (by a VM exit) attempts to relocate these data structures and prevent them from being tampered by malicious software. Pause Loop Exiting (PLE) PLE aims to improve virtualization performance and enhance the scaling of virtual machines with multiple virtual processors PLE attempts to detect lock-holder preemption in a VM and helps the VMM to make better scheduling decisions

3.1.3

Intel VT-d Objectives

The key Intel VT-d objectives are domain-based isolation and hardware-based virtualization. A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated. Virtualization allows for the creation of one or more partitions on a single system. This could be multiple partitions in the same operating system, or there can be multiple operating system instances running on the same system offering benefits such as system consolidation, legacy migration, activity partitioning or security.

3.1.3.1

Intel VT-d Features Supported

The processor supports the following Intel VT-d features: Root entry, context entry, and default context Support for 4-K page sizes only Support for register-based fault recording only (for single entry only) and support for MSI interrupts for faults

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Support for fault collapsing based on Requester ID Support for both leaf and non-leaf caching Support for boot protection of default page table Support for non-caching of invalid page table entries Support for hardware based flushing of translated but pending writes and pending reads upon IOTLB invalidation. Support for page-selective IOTLB invalidation. Support for ARI (Alternative Requester ID - a PCI SIG ECR for increasing the function number count in a PCIe* device) to support IOV devices. Improved invalidation architecture End point caching support (ATS) Interrupt remapping

3.1.4

Intel Virtualization Technology Processor Extensions

The processor supports the following Intel VT Processor Extensions features: Large Intel VT-d Pages Adds 2 MB and 1 GB page sizes to Intel VT-d implementations Matches current support for Extended Page Tables (EPT) Ability to share CPU's EPT page-table (with super-pages) with Intel VT-d Benefits: Less memory foot-print for I/O page-tables when using super-pages Potential for improved performance - Due to shorter page-walks, allows hardware optimization for IOTLB Transition latency reductions expected to improve virtualization performance without the need for VMM enabling. This reduces the VMM overheads further and increase virtualization performance.

3.2
3.2.1

Security Technologies
Intel Trusted Execution Technology
Intel Trusted Execution Technology (Intel TXT) defines platform-level enhancements that provide the building blocks for creating trusted platforms. The Intel TXT platform helps to provide the authenticity of the controlling environment such that those wishing to rely on the platform can make an appropriate trust decision. The Intel TXT platform determines the identity of the controlling environment by accurately measuring and verifying the controlling software. Another aspect of the trust decision is the ability of the platform to resist attempts to change the controlling environment. The Intel TXT platform will resist attempts by software processes to change the controlling environment or bypass the bounds set by the controlling environment. Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute.

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These extensions enhance two areas: The launching of the Measured Launched Environment (MLE). The protection of the MLE from potential corruption. The enhanced platform provides these launch and control interfaces using Safer Mode Extensions (SMX). The SMX interface includes the following functions: Measured/Verified launch of the MLE. Mechanisms to ensure the above measurement is protected and stored in a secure location. Protection mechanisms that allow the MLE to control attempts to modify itself. For more information refer to the Intel Trusted Execution Technology Software Development Guide. For more information on Intel Trusted Execution Technology, see http://www.intel.com/technology/security/

3.2.2

Intel Trusted Execution Technology Server Extensions

Software binary compatible with Intel Trusted Execution Technology Server Extensions Provides measurement of runtime firmware, including SMM Enables run-time firmware in trusted session: BIOS and SSP Covers support for existing and expected future Server RAS features Only requires portions of BIOS to be trusted, for example, Option ROMs need not be trusted Supports S3 State without teardown: Since BIOS is part of the trust chain

3.2.3

Intel Advanced Encryption Standard Instructions (Intel AES-NI)

These instructions enable fast and secure data encryption and decryption, using the Intel AES New Instructions (Intel AES-NI), which is defined by FIPS Publication number 197. Since Intel AES-NI is the dominant block cipher, and it is deployed in various protocols, the new instructions will be valuable for a wide range of applications. The architecture consists of six instructions that offer full hardware support for Intel AES-NI. Four instructions support the Intel AES-NI encryption and decryption, and the other two instructions support the Intel AES-NI key expansion. Together, they offer a significant increase in performance compared to pure software implementations. The Intel AES-NI instructions have the flexibility to support all three standard Intel AES-NI key lengths, all standard modes of operation, and even some nonstandard or future variants. Beyond improving performance, the Intel AES-NI instructions provide important security benefits. Since the instructions run in data-independent time and do not use lookup tables, they help in eliminating the major timing and cache-based attacks that threaten table-based software implementations of Intel AES-NI. In addition, these instructions make AES simple to implement, with reduced code size. This helps reducing the risk of inadvertent introduction of security flaws, such as difficult-todetect side channel leaks.

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3.2.4

Execute Disable Bit

Intel's Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system. Allows the processor to classify areas in memory by where application code can execute and where it cannot. When a malicious worm attempts to insert code in the buffer, the processor disables code execution, preventing damage and worm propagation.

3.3

Intel Hyper-Threading Technology

The processor supports Intel Hyper-Threading Technology (Intel HT Technology), which allows an execution core to function as two logical processors. While some execution resources such as caches, execution units, and buses are shared, each logical processor has its own architectural state with its own set of general-purpose registers and control registers. This feature must be enabled via the BIOS and requires operating system support. For more information on Intel Hyper-Threading Technology, see http://www.intel.com/products/ht/hyperthreading_more.htm.

3.4

Intel Turbo Boost Technology

Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating frequency if it is operating below power, temperature, and current limits. The result is increased performance in multi-threaded and single threaded workloads. It should be enabled in the BIOS for the processor to operate with maximum performance.

3.4.1

Intel Turbo Boost Operating Frequency

The processors rated frequency assumes that all execution cores are running an application at the thermal design power (TDP). However, under typical operation, not all cores are active. Therefore most applications are consuming less than the TDP at the rated frequency. To take advantage of the available TDP headroom, the active cores can increase their operating frequency. To determine the highest performance frequency amongst active cores, the processor takes the following into consideration: The number of cores operating in the C0 state. The estimated current consumption. The estimated power consumption. The die temperature. Any of these factors can affect the maximum frequency for a given workload. If the power, current, or thermal limit is reached, the processor will automatically reduce the frequency to stay with its TDP limit.

Note:

Intel Turbo Boost Technology is only active if the operating system is requesting the P0 state. For more information on P-states and C-states refer to Section 4, Power Management.

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3.5

Enhanced Intel SpeedStep Technology

The processor supports Enhanced Intel SpeedStep Technology as an advanced means of enabling very high performance while also meeting the power-conservation needs of the platform. Enhanced Intel SpeedStep Technology builds upon that architecture using design strategies that include the following: Separation between Voltage and Frequency Changes. By stepping voltage up and down in small increments separately from frequency changes, the processor is able to reduce periods of system unavailability (which occur during frequency change). Thus, the system is able to transition between voltage and frequency states more often, providing improved power/performance balance. Clock Partitioning and Recovery. The bus clock continues running during state transition, even when the core clock and Phase-Locked Loop are stopped, which allows logic to remain active. The core clock is also able to restart more quickly under Enhanced Intel SpeedStep Technology. For additional information on Enhanced Intel SpeedStep Technology see Section 4.2.1.

3.6

Intel Intelligent Power Technology

Intel Intelligent Power Technology conserves power while delivering advanced powermanagement capabilities at the rack, group, and data center level. Providing the highest system-level performance per watt with Automated Low Power States and Integrated Power Gates. Improvements to this processor generation are: Intel Network Power Management Technology Intel Power Tuning Technology For more information on Intel Intelligent Power Technology, see this link http:// www.intel.com/technology/intelligentpower/.

3.7

Intel Advanced Vector Extensions (Intel AVX)

Intel Advanced Vector Extensions (Intel AVX) is a new 256-bit vector SIMD extension of Intel Architecture. The introduction of Intel AVX starts with the 2nd Generation Intel(r) Core(TM) Processor Family. Intel AVX accelerates the trend of parallel computation in general purpose applications like image, video, and audio processing, engineering applications such as 3D modeling and analysis, scientific simulation, and financial analysts. Intel AVX is a comprehensive ISA extension of the Intel 64 Architecture. The main elements of Intel AVX are: Support for wider vector data (up to 256-bit) for floating-point computation. Efficient instruction encoding scheme that supports 3 operand syntax and headroom for future extensions. Flexibility in programming environment, ranging from branch handling to relaxed memory alignment requirements. New data manipulation and arithmetic compute primitives, including broadcast, permute, fused-multiply-add, and so forth.

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The key advantages of Intel AVX are: Performance - Intel AVX can accelerate application performance via data parallelism and scalable hardware infrastructure across existing and new application domains: 256-bit vector data sets can be processed up to twice the throughput of 128-bit data sets. Application performance can scale up with number of hardware threads and number of cores. Application domain can scale out with advanced platform interconnect fabrics, such as Intel QPI. Power Efficiency - Intel AVX is extremely power efficient. Incremental power is insignificant when the instructions are unused or scarcely used. Combined with the high performance that it can deliver, applications that lend themselves heavily to using Intel AVX can be much more energy efficient and realize a higher performance-per-watt. Extensibility - Intel AVX has built-in extensibility for the future vector extensions: OS context management for vector-widths beyond 256 bits is streamlined. Efficient instruction encoding allows unlimited functional enhancements: Vector width support beyond 256 bits 256-bit Vector Integer processing Additional computational and/or data manipulation primitives. Compatibility - Intel AVX is backward compatible with previous ISA extensions including Intel SSE4: Existing Intel SSE applications/library can: Run unmodified and benefit from processor enhancements Recompile existing Intel SSE intrinsic using compilers that generate Intel AVX code Inter-operate with library ported to Intel AVX Applications compiled with Intel AVX can inter-operate with existing Intel SSE libraries.

3.8

Intel Dynamic Power Technology (Intel DPT)

Intel Dynamic Power Technology (Intel DPT) (Memory Power Management) is a platform feature with the ability to transition memory components into various low power states based on workload requirements. The Intel Xeon processor E5-1600/ E5-2600/E5-4600 product families platform supports Dynamic CKE (hardware assisted) and Memory Self Refresh (software assisted). For further details refer to the ACPI Specifications for Memory Power Management document.

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Power Management
This chapter provides information on the following power management topics: ACPI States System States Processor Core/Package States Integrated Memory Controller (IMC) and System Memory States Direct Media Interface Gen 2 (DMI2)/PCI Express* Link States Intel QuickPath Interconnect States

4.1
4.1.1
Table 4-1.

ACPI States Supported

The ACPI states supported by the processor are described in this section.

System States
System States
State Description

G0/S0 G1/S3-Cold G1/S4 G2/S5 G3

Full On Suspend-to-RAM (STR). Context saved to memory Suspend-to-Disk (STD). All power lost (except wakeup on PCH). Soft off. All power lost (except wakeup on PCH). Total reboot. Mechanical off. All power removed from system.

4.1.2

Processor Package and Core States

Table 4-2 lists the package C-state support as: 1) the shallowest core C-state that allows entry into the package C-state, 2) the additional factors that will restrict the state from going any deeper, and 3) the actions taken with respect to the Ring Vcc, PLL state and LLC. Table 4-3 lists the processor core C-states support.

Table 4-2.

Package C-State Support (Sheet 1 of 2)

Package CState Core States Limiting Factors Retention and PLL-Off LLC Fully Flushed Notes1

PC0 - Active

CC0

N/A PCIe/PCH and Remote Socket Snoops PCIe/PCH and Remote Socket Accesses Interrupt response time requirement DMI Sidebands Configuration Constraints

No VccMin Freq = MinFreq PLL = ON

No

PC2 Snoopable Idle

CC3-CC7

No

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Table 4-2.

Package C-State Support (Sheet 2 of 2)

Package CState Core States Limiting Factors Retention and PLL-Off LLC Fully Flushed Notes1

PC3 - Light Retention

at least one Core in C3

Core C-state Snoop Response Time Interrupt Response Time Non Snoop Response Time LLC ways open Snoop Response Time Non Snoop Response Time Interrupt Response Time

Vcc = retention PLL = OFF

No

2,3,4

PC6 - Deeper Retention

CC6-CC7

Vcc = retention PLL = OFF

No

2,3,4

Notes: 1. Package C7 is not supported. 2. All package states are defined to be "E" states - such that they always exit back into the LFM point upon execution resume 3. The mapping of actions for PC3, and PC6 are suggestions - microcode will dynamically determine which actions should be taken based on the desired exit latency parameters. 4. CC3/CC6 will all use a voltage below the VccMin operational point; The exact voltage selected will be a function of the snoop and interrupt response time requirements made by the devices (PCIe* and DMI) and the operating system.

Table 4-3.

Core C-State Support

Core C-State Global Clock PLL L1/L2 Cache Core VCC Context

CC0 CC1 CC1E CC3 CC6 CC7

Running Stopped Stopped Stopped Stopped Stopped

On On On On Off Off

Coherent Coherent Coherent Flushed to LLC Flushed to LLC Flushed to LLC

Active Active Request LFM Request Retention Power Gate Power Gate

Maintained Maintained Maintained Maintained Flushed to LLC Flushed to LLC

4.1.3
Table 4-4.

Integrated Memory Controller States

System Memory Power States (Sheet 1 of 2)
State Description

Power Up/Normal Operation CKE Power Down

CKE asserted. Active Mode, highest power consumption. Opportunistic, per rank control after idle time: Active Power Down (APD) (default mode) CKE de-asserted. Power savings in this mode, relative to active idle state is about 55% of the memory power. Exiting this mode takes 3 5 DCLK cycles. Pre-charge Power Down Fast Exit (PPDF) CKE de-asserted. DLL-On. Also known as Fast CKE. Power savings in this mode, relative to active idle state is about 60% of the memory power. Exiting this mode takes 3 5 DCLK cycles. Pre-charge Power Down Slow Exit (PPDS) CKE de-asserted. DLL-Off. Also known as Slow CKE. Power savings in this mode, relative to active idle state is about 87% of the memory power. Exiting this mode takes 3 5 DCLK cycles until the first command is allowed and 16 cycles until first data is allowed. Register CKE Power Down: IBT-ON mode: Both CKEs are de-asserted, the Input Buffer Terminators (IBTs) are left on. IBT-OFF mode: Both CKEs are de-asserted, the Input Buffer Terminators (IBTs) are turned off.

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Table 4-4.

System Memory Power States (Sheet 2 of 2)

State Description

Self-Refresh

CKE de-asserted. In this mode, no transactions are executed and the system memory consumes the minimum possible power. Self refresh modes apply to all memory channels for the processor. IO-MDLL Off: Option that sets the IO master DLL off when self refresh occurs. PLL Off: Option that sets the PLL off when self refresh occurs. In addition, the register component found on registered DIMMs (RDIMMs) is complemented with the following power down states: Clock Stopped Power Down with IBT-On Clock Stopped Power Down with IBT-Off

4.1.4
Table 4-5.

DMI2/PCI Express Link States

DMI2/PCI Express* Link States
State Description

L0 L1
Note:

Full on Active transfer state. Lowest Active State Power Management (ASPM) - Longer exit latency. L1 is only supported when the DMI2/PCI Express* port is operating as a PCI Express* port.

4.1.5
Table 4-6.

Intel QuickPath Interconnect States

Intel QPI States
State Description

L0 L0p L1

Link on. This is the power on active working state, A lower power state from L0 that reduces the link from full width to half width A low power state with longer latency and lower power than L0s and is activated in conjunction with package C-states below C0.

4.1.6
Table 4-7.

G, S, and C State Combinations

G, S and C State Combinations
Global (G) State Sleep (S) State Processor Core (C) State Processor State System Clocks Description

G0 G0 G0 G0 G1 G1 G2 G3

S0 S0 S0 S0 S3 S4 S5 N/A

C0 C1/C1E C3 C6/C7 Power off Power off Power off Power off

Full On Auto-Halt Deep Sleep Deep Power Down

On On On On Off, except RTC Off, except RTC Off, except RTC Power off

Full On Auto-Halt Deep Sleep Deep Power Down Suspend to RAM Suspend to Disk Soft Off Hard off

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4.2

Processor Core/Package Power Management

While executing code, Enhanced Intel SpeedStep Technology optimizes the processors frequency and core voltage based on workload. Each frequency and voltage operating point is defined by ACPI as a P-state. When the processor is not executing code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power C-states have longer entry and exit latencies.

4.2.1

Enhanced Intel SpeedStep Technology

The following are the key features of Enhanced Intel SpeedStep Technology: Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states. Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on temperature, leakage, power delivery loadline and dynamic capacitance. If the target frequency is higher than the current frequency, VCC is ramped up to an optimized voltage. This voltage is signaled by the SVID Bus to the voltage regulator. Once the voltage is established, the PLL locks on to the target frequency. If the target frequency is lower than the current frequency, the PLL locks to the target frequency, then transitions to a lower voltage by signaling the target voltage on the SVID Bus. All active processor cores share the same frequency and voltage. In a multicore processor, the highest frequency P-state requested amongst all active cores is selected. Software-requested transitions are accepted at any time. The processor has a new capability from the previous processor generation, it can preempt the previous transition and complete the new request without waiting for this request to complete. The processor controls voltage ramp rates internally to ensure glitch-free transitions. Because there is low transition latency between P-states, a significant number of transitions per second are possible.

4.2.2

Low-Power Idle States

When the processor is idle, low-power idle states (C-states) are used to save power. More power savings actions are taken for numerically higher C-states. However, higher C-states have longer exit and entry latencies. Resolution of C-states occurs at the thread, processor core, and processor package level. Thread level C-states are available if Hyper-Threading Technology is enabled. Entry and exit of the C-States at the thread and core level are shown in Figure 4-2.

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Figure 4-1.

Idle Power Management Breakdown of the Processor Cores

T h re a d 0

T h re a d 1

T h re a d 0

T h re a d 1

C o r e 0 S ta te

C o r e N S ta te

P r o c e s s o r P a c k a g e S ta te

Figure 4-2.

Thread and Core C-State Entry and Exit

C0
MWAIT(C1), HLT MWAIT(C1), HLT (C1E Enabled) MWAIT(C7), P_LVL4 I/O Read

MWAIT(C3), P_LVL2 I/O Read

MWAIT(C6), P_LVL3 I/O Read

C1

C1E

C3

C6

C7

While individual threads can request low power C-states, power saving actions only take place once the core C-state is resolved. Core C-states are automatically resolved by the processor. For thread and core C-states, a transition to and from C0 is required before entering any other C-state.

4.2.3

Requesting Low-Power Idle States

The core C-state will be C1E if all actives cores have also resolved a core C1 state or higher. The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E). However, software may make C-state requests using the legacy method of I/O reads from the ACPI-defined processor clock control registers, referred to as P_LVLx. This method of requesting C-states provides legacy support for operating systems that initiate C-state transitions via I/O reads.

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For legacy operating systems, P_LVLx I/O reads are converted within the processor to the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in I/O reads to the system. The feature, known as I/O MWAIT redirection, must be enabled in the BIOS. To enable it, refer to the Intel 64 and IA-32 Architectures Software Developers Manual (SDM) Volumes 1, 2, and 3.
Note:

The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as follows. P_LVLx to MWAIT Conversion
P_LVLx MWAIT(Cx) Notes

Table 4-8.

P_LVL2

MWAIT(C3)

The P_LVL2 base address is defined in the PMG_IO_CAPTURE MSR, described in the Intel 64 and IA-32 Architectures Software Developers Manual (SDM) Volumes 1, 2, and 3. C6. No sub-states allowed. C7. No sub-states allowed.

P_LVL3 P_LVL4

MWAIT(C6) MWAIT(C7)

The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict the range of I/O addresses that are trapped and emulate MWAIT like functionality. Any P_LVLx reads outside of this range does not cause an I/O redirection to MWAIT(Cx) like request. They fall through like a normal I/O instruction.
Note:

When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The MWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O redirections enable the MWAIT 'break on EFLAGS.IF feature which triggers a wakeup on an interrupt even if interrupts are masked by EFLAGS.IF.

4.2.4

Core C-states
The following are general rules for all core C-states, unless specified otherwise: A core C-State is determined by the lowest numerical thread state (for example, Thread 0 requests C1E while Thread 1 requests C3, resulting in a core C1E state). See Table 4-7. A core transitions to C0 state when: an interrupt occurs. there is an access to the monitored address if the state was entered via an MWAIT instruction. For core C1/C1E, and core C3, an interrupt directed toward a single thread wakes only that thread. However, since both threads are no longer at the same core C-state, the core resolves to C0. An interrupt only wakes the target thread for both C3 and C6 states. Any interrupt coming into the processor package may wake any core.

4.2.4.1

Core C0 State
The normal operating state of a core where code is being executed.

4.2.4.2

Core C1/C1E State

C1/C1E is a low power state entered when all threads within a core execute a HLT or MWAIT(C1/C1E) instruction.

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A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state. See the Intel 64 and IA-32 Architectures Software Developers Manual (SDM) Volumes 1, 2, and 3 for more information. While a core is in C1/C1E state, it processes bus snoops and snoops from other threads. For more information on C1E, see Section 4.2.5.2, Package C1/C1E.

4.2.4.3

Core C3 State
Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while maintaining its architectural state. All core clocks are stopped at this point. Because the cores caches are flushed, the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory.

4.2.4.4

Core C6 State
Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an MWAIT(C6) instruction. Before entering core C6, the core will save its architectural state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts. In addition to flushing core caches core architecture state is saved to the uncore. Once the core state save is completed, core voltage is reduced to zero. During exit, the core is powered on and its architectural state is restored.

4.2.4.5

Core C7 State
Individual threads of a core can enter the C7 state by initiating a P_LVL4 I/O read to the P_BLK or by an MWAIT(C7) instruction. Core C7 and core C7 substate are the same as Core C6. The processor does not support LLC flush under any condition.

4.2.4.6

C-State Auto-Demotion
In general, deeper C-states such as C6 or C7 have long latencies and have higher energy entry/exit costs. The resulting performance and energy penalties become significant when the entry/exit frequency of a deeper C-state is high. In order to increase residency in deeper C-states, the processor supports C-state auto-demotion. There are two C-State auto-demotion options: C6/C7 to C3 C3/C6/C7 To C1 The decision to demote a core from C6/C7 to C3 or C3/C6/C7 to C1 is based on each cores immediate residency history. Upon each core C6/C7 request, the core C-state is demoted to C3 or C1 until a sufficient amount of residency has been established. At that point, a core is allowed to go into C3/C6 or C7. Each option can be run concurrently or individually. This feature is disabled by default. BIOS must enable it in the PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by this register. See the Intel 64 and IA-32 Architectures Software Developers Manual (SDM) Volumes 1, 2, and 3 for C-state configurations.

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4.2.5

Package C-States
The processor supports C0, C1/C1E, C2, C3, and C6 power states. The following is a summary of the general rules for package C-state entry. These apply to all package C-states unless specified otherwise: A package C-state request is determined by the lowest numerical core C-state amongst all cores. A package C-state is automatically resolved by the processor depending on the core idle power states and the status of the platform components. Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C-state. The platform may allow additional power savings to be realized in the processor. For package C-states, the processor is not required to enter C0 before entering any other C-state. The processor exits a package C-state when a break event is detected. Depending on the type of break event, the processor does the following: If a core break event is received, the target core is activated and the break event message is forwarded to the target core. If the break event is not masked, the target core enters the core C0 state and the processor enters package C0. If the break event is masked, the processor attempts to re-enter its previous package state. If the break event was due to a memory access or snoop request. But the platform did not request to keep the processor in a higher package C-state, the package returns to its previous C-state. And the platform requests a higher power C-state, the memory access or snoop request is serviced and the package remains in the higher power C-state. The package C-states fall into two categories: independent and coordinated. C0/C1/ C1E are independent, while C2/C3/C6 are coordinated. Starting with the 2nd Generation Intel(r) Core(TM) Processor Family, package C-states are based on exit latency requirements which are accumulated from the PCIe* devices, PCH, and software sources. The level of power savings that can be achieved is a function of the exit latency requirement from the platform. As a result, there is no fixed relationship between the coordinated C-state of a package, and the power savings that will be obtained from the state. Coordinated package C-states offer a range of power savings which is a function of the guaranteed exit latency requirement from the platform. There is also a concept of Execution Allowed (EA), when EA status is 0, the cores in a socket are in C3 or a deeper state, a socket initiates a request to enter a coordinated package C-state. The coordination is across all sockets and the PCH. Table 4-9 shows an example of a dual-core processor package C-state resolution. Figure 4-3 summarizes package C-state transitions with package C2 as the interim between PC0 and PC1 prior to PC3 and PC6.

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Table 4-9.

Coordination of Core Power States at the Package Level

Core 1 Package C-State C0 C0 Core 0 C1 C3 C6 Notes: C1 C3 C6

C0 C0 C0 C0

C0 C11 C11 C11

C0 C11 C3 C3

C0 C11 C3 C6

1. The package C-state will be C1E if all actives cores have resolved a core C1 state or higher.

Figure 4-3.

Package C-State Entry and Exit

C0

C1

C2

C3

C6

4.2.5.1

Package C0
The normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state. Individual cores may be in lower power idle states while the package is in C0.

4.2.5.2

Package C1/C1E
No additional power reduction actions are taken in the package C1 state. However, if the C1E substate is enabled, the processor automatically transitions to the lowest supported core clock frequency, followed by a reduction in voltage. Autonomous power reduction actions which are based on idle timers, can trigger depending on the activity in the system. The package enters the C1 low power state when:

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At least one core is in the C1 state. The other cores are in a C1 or lower power state. The package enters the C1E state when: All cores have directly requested C1E via MWAIT(C1) with a C1E sub-state hint. All cores are in a power state lower that C1/C1E but the package low power state is limited to C1/C1E via the PMG_CST_CONFIG_CONTROL MSR. All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is enabled in POWER_CTL. No notification to the system occurs upon entry to C1/C1E.

4.2.5.3

Package C2 State
Package C2 state is an intermediate state which represents the point at which the system level coordination is in progress. The package cannot reach this state unless all cores are in at least C3. The package will remain in C2 when: it is awaiting for a coordinated response the coordinated exit latency requirements are too stringent for the package to take any power saving actions If the exit latency requirements are high enough the package will transition to C3 or C6 depending on the state of the cores.

4.2.5.4

Package C3 State
A processor enters the package C3 low power state when: At least one core is in the C3 state. The other cores are in a C3 or lower power state, and the processor has been granted permission by the platform. L3 shared cache retains context and becomes inaccessible in this state. Additional power savings actions, as allowed by the exit latency requirements, include putting Intel QPI and PCIe* links in L1, the uncore is not available, further voltage reduction can be taken. In package C3, the ring will be off and as a result no accesses to the LLC are possible. The content of the LLC is preserved.

4.2.5.5

Package C6 State
A processor enters the package C6 low power state when: At least one core is in the C6 state. The other cores are in a C6 or lower power state, and the processor has been granted permission by the platform. L3 shared cache retains context and becomes inaccessible in this state.

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Additional power savings actions, as allowed by the exit latency requirements, include putting Intel QPI and PCIe* links in L1, the uncore is not available, further voltage reduction can be taken. In package C6 state, all cores have saved their architectural state and have had their core voltages reduced to zero volts. The LLC retains context, but no accesses can be made to the LLC in this state, the cores must break out to the internal state package C2 for snoops to occur.

4.2.6

Package C-State Power Specifications

The table below lists the processor package C-state power specifications for various processor SKUs.

Table 4-10. Package C-State Power Specifications

TDP SKUs 8-Core / 6-Core C1E (W) C3 (W) C6 (W)

150W (8-core) 135W (8-core) 130W (8-core) 130W (6-core) 130W (6-core 1S WS) 115W (8-core) 95W (8-core) 95W (6-core) 70W (8-core) 60W (6-core) LV95W-8C (8-core) LV70W-8C (8-core)
4-Core / 2-Core

58 47 47 53 53 47 47 48 39 38 47 39

27 22 22 35 35 22 22 35 (E5-2660) 22 35 (E5-2620) 20 20 22 20

15 15 15 21 21 15 15 15 21 (E5-2620) 14 14 15 14

130W (4-core) 130W (4-Core 1S WS) 95W (4-core) 80W (4-core) 80W (2-core)

53 53 47 42 42

28 28 22 21 30 (E5-2603) 30

16 16 15 16 21

Notes: 1. Package C1E power specified at Tcase = 60C. 2. Package C3/C6 power specified at Tcase = 50C.

4.3

System Memory Power Management

The DDR3 power states can be summarized as the following: Normal operation (highest power consumption).

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CKE Power-Down: Opportunistic, per rank control after idle time. There may be different levels. Active Power-Down. Precharge Power-Down with Fast Exit. Precharge power Down with Slow Exit. Self Refresh: In this mode no transaction is executed. The DDR consumes the minimum possible power.

4.3.1

CKE Power-Down
The CKE input land is used to enter and exit different power-down modes. The memory controller has a configurable activity timeout for each rank. Whenever no reads are present to a given rank for the configured interval, the memory controller will transition the rank to power-down mode. The memory controller transitions the DRAM to power-down by de-asserting CKE and driving a NOP command. The memory controller will tri-state all DDR interface lands except CKE (de-asserted) and ODT while in power-down. The memory controller will transition the DRAM out of power-down state by synchronously asserting CKE and driving a NOP command. When CKE is off the internal DDR clock is disabled and the DDR power is significantly reduced. The DDR defines three levels of power-down: Active power-down. Precharge power-down fast exit. Precharge power-down slow exit.

4.3.2

Self Refresh
The Power Control Unit (PCU) may request the memory controller to place the DRAMs in self refresh state. Self refresh per channel is supported. The BIOS can put the channel in self-refresh if software remaps memory to use a subset of all channels. Also processor channels can enter self refresh autonomously without PCU instruction when the package is in a package C0 state.

4.3.2.1

Self Refresh Entry

Self refresh entrance can be either disabled or triggered by an idle counter. The idle counter always clears with any access to the memory controller and remains clear as long as the memory controller is not drained. As soon as the memory controller is drained, the counter starts counting, and when it reaches the idle-count, the memory controller will place the DRAMs in self refresh state. Power may be removed from the memory controller core at this point. But VCCD supply (1.5 V or 1.35 V) to the DDR IO must be maintained.

4.3.2.2

Self Refresh Exit

Self refresh exit can be either a message from an external unit or as reaction for an incoming transaction.

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4.3.2.3

DLL and PLL Shutdown

Self refresh, according to configuration, may be a trigger for master DLL shut-down and PLL shut-down. The master DLL shut-down is issued by the memory controller after the DRAMs have entered self refresh. The PLL shut-down and wake-up is issued by the PCU. The memory controller gets a signal from PLL indicating that the memory controller can start working again.

4.3.3

DRAM I/O Power Management

Unused signals are tristated to save power. This includes all signals associated with an unused memory channel. The I/O buffer for an unused signal should be tristated (output driver disabled), the input receiver (differential sense-amp) should be disabled. The input path must be gated to prevent spurious results due to noise on the unused signals (typically handled automatically when input receiver is disabled).

4.4

DMI2/PCI Express* Power Management

Active State Power Management (ASPM) support using L1 state, L0s is not supported.

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5
5.1

Thermal Management Specifications

Package Thermal Specifications
The processor requires a thermal solution to maintain temperatures within operating limits. Any attempt to operate the processor outside these limits may result in permanent damage to the processor and potentially other components within the system, see Section 7.7.1, Storage Conditions Specifications. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting. This section provides data necessary for developing a complete thermal solution. For more information on designing a component level thermal solution, refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide.

5.1.1

Thermal Specifications
To allow optimal operation and long-term reliability of Intel processor-based systems, the processor must remain within the minimum and maximum case temperature (TCASE) specifications as defined by the applicable thermal profile. Thermal solutions not designed to provide sufficient thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, please refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/ Mechanical Design Guide. The processors implement a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and to assure processor reliability. Selection of the appropriate fan speed is based on the relative temperature data reported by the processors Platform Environment Control Interface (PECI) as described in Section 2.5, Platform Environment Control Interface (PECI). If the DTS value is less than TCONTROL, then the case temperature is permitted to exceed the Thermal Profile, but the DTS value must remain at or below TCONTROL. For TCASE implementations, if DTS is greater than TCONTROL, then the case temperature must meet the TCASE based Thermal Profiles. For DTS implementations: TCASE thermal profile can be ignored during processor run time. If DTS is greater than Tcontrol then follow DTS thermal profile specifications for fan speed optimization.

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The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT_N (see Section 7, Electrical Specifications). Systems that implement fan speed control must be designed to use this data. Systems that do not alter the fan speed need to guarantee the case temperature meets the thermal profile specifications. Some processor SKUs support two thermal profiles; refer to Table 5-1for a summary of the planned SKUs and their supported thermal profiles. Both ensure adherence to Intel reliability requirements. Thermal Profile 2U is representative of a volumetrically unconstrained thermal solution (that is, industry enabled 2U heatsink). With single thermal profile, it is expected that the Thermal Control Circuit (TCC) would be activated for very brief periods of time when running the most power intensive applications. Thermal Profile 1U is indicative of a constrained thermal environment (that is, 1U form factor). Because of the reduced cooling capability represented by this thermal solution, the probability of TCC activation and performance loss is increased. Additionally, utilization of a thermal solution that does not meet Thermal Profile 1U will violate the thermal specifications and may result in permanent damage to the processor. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/ Mechanical Design Guide for details on system thermal solution design, thermal profiles and environmental considerations. The upper point of the thermal profile consists of the Thermal Design Power (TDP) and the associated TCASE value. It should be noted that the upper point associated with Thermal Profile 1U. (x = TDP and y = TCASE_MAX_B @ TDP) represents a thermal solution design point. In actuality the processor case temperature will not reach this value due to TCC activation. For Embedded Servers, Communications and storage markets Intel has plan SKUs that support Thermal Profiles with nominal and short-term conditions designed to meet NEBS level 3 compliance. For these SKUs operation at either the nominal or short-term thermal profiles should result in virtually no TCC activation. Thermal Profiles for these SKUs are found in Table 5-1. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP). The Adaptive Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period. To ensure maximum flexibility for future requirements, systems should be designed to the Flexible Motherboard (FMB) guidelines, even if a processor with lower power dissipation is currently planned. The Adaptive Thermal Monitor feature must be enabled for the processor to remain within its specifications.

5.1.2

TCASE and DTS Based Thermal Specifications

To simplify compliance to thermal specifications at processor run time, the processor has added a Digital Thermal Sensor (DTS) based thermal specification. Digital Thermal Sensor reports a relative die temperature as an offset from TCC activation temperature. TCASE thermal based specifications are used for heat sink sizing and DTS based specs are used for acoustic and fan speed optimizations. For the processor family, firmware (for example, BMC or other platform management devices) will have DTS based specifications for all SKUs programmed by the customer. 8-core and 6-core SKUs may share TCASE thermal profiles but they will have separate TDTS based thermal profiles. See Table 5-1 for the TCASE and DTS SKU summary. The processor fan speed control is managed by comparing DTS thermal readings via PECI against the processor-specific fan speed control reference point, or Tcontrol. Both Tcontrol and DTS thermal readings are accessible via the processor PECI client. At a one time readout only, the Fan Speed Control firmware will read the following:

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TEMPERATURE_TARGET MSR Tcontrol via PECI - RdPkgConfig() TDP via PECI - RdPkgConfig() Core Count - RdPCIConfigLocal() DTS PECI commands will also support DTS temperature data readings. Please see Section 2.5.7, DTS Temperature Data for PECI command details. Also, refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for details on DTS based thermal solution design considerations.

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5.1.3
Table 5-1.

Processor Thermal Profiles

Processor SKU Summary Table
Thermal Profile TDP SKUs Tcase 8-Core / 6-Core DTS

150W (8-core) 135W (8-core) 130W (8-core) 130W (6-core) 130W (6-core 1S WS) 115W (8-core) 95W (8-core) 95W (6-core) 70W (8-core) 60W (6-core)
4-Core / 2-Core

Figure 5-1 Figure 5-3 Figure 5-5 Figure 5-5 Figure 5-8 Figure 5-10 Figure 5-12 Figure 5-12 Figure 5-15 Figure 5-17

Figure 5-2 Figure 5-4 Figure 5-6 Figure 5-7 Figure 5-9 Figure 5-11 Figure 5-13 Figure 5-14 Figure 5-16 Figure 5-18

130W (4-core) 130W (4-core 1S WS) 95W (4-core)

1

Figure 5-19 Figure 5-21 Figure 5-23 Figure 5-25 Figure 5-25

Figure 5-20 Figure 5-22 Figure 5-24 Figure 5-26 Figure 5-27

80W (4-core) 80W (2-core) 1.

Applies only to Intel Xeon Processor E5-4600 Product Family.

5.1.3.1
Table 5-2.

8-Core 150W Thermal Specifications

Tcase: 8-Core 150W Thermal Specifications, Workstation Platform SKU Only
Core Frequency Thermal Design Power (W) Minimum TCASE (C) Maximum TCASE (C) Notes

Launch to FMB

150

See Figure 5-1 and Table 5-3

1, 2, 3, 4, 5, 6

Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Please refer to the electrical loadline specifications in Section 7.8.1. 2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. 3. These specifications are based on final silicon characterization. 4. Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements. 6. The 150W TDP SKU is intended for the dual processor workstations only and uses workstation specific use conditions for reliability assumptions.

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Figure 5-1.

Tcase: 8-Core 150W Thermal Profile, Workstation Platform SKU Only

Notes: 1. This Thermal Profile is representative of a volumetrically unconstrained platform. Please refer to Table 5-3 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Figure 5-2.

DTS: 8-Core 150W Thermal Profile, Workstation Platform SKU Only

Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP.

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2. 3.

This Thermal Profile is representative of a volumetrically unconstrained platform. Please refer to Table 5-3 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Table 5-3.

8-Core 150W Thermal Profile, Workstation Platform SKU Only

Power (W) Maximum TCASE (C) Maximum DTS(C)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150

38.9 39.8 40.8 41.7 42.6 43.6 44.5 45.4 46.4 47.3 48.3 49.2 50.1 51.1 52.0 52.9 53.9 54.8 55.7 56.7 57.6 58.5 59.5 60.4 61.3 62.3 63.2 64.1 65.1 66.0 67.0

38.9 40.4 42.0 43.5 45.0 46.6 48.1 49.6 51.1 52.7 54.2 55.7 57.3 58.8 60.3 61.9 63.4 64.9 66.4 68.0 69.5 71.0 72.6 74.1 75.6 77.2 78.7 80.2 81.7 83.3 84.8

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5.1.3.2
Table 5-4.

8-Core 135W Thermal Specifications

Tcase: 8-Core 135W Thermal Specifications 2U
Core Frequency Thermal Design Power (W) Minimum TCASE (C) Maximum TCASE (C) Notes

Launch to FMB

135

See Figure 5-3 and Table 5-5

1, 2, 3, 4, 5

Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Please refer to the electrical loadline specifications in Section 7.8.1. 2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. 3. These specifications are based on final silicon characterization. 4. Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements.

Figure 5-3.

Tcase: 8-Core 135W Thermal Profile 2U

Notes: 1. This Thermal Profile is representative of a volumetrically unconstrained platform. Please refer to Table 5-5 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

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Figure 5-4.

DTS: 8-Core 135W Thermal Profile 2U

Notes: 1. Some of the processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. This Thermal Profile is representative of a volumetrically unconstrained platform. Please refer to Table 5-5 for discrete points that constitute the thermal profile. 3. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Table 5-5.

8-Core 135W Thermal Profile Table 2U (Sheet 1 of 2)

Power (W) Maximum TCASE (C) Maximum DTS (C)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75

50.3 51.1 51.9 52.7 53.5 54.3 55.1 55.9 56.7 57.5 58.4 59.2 60.0 60.8 61.6 62.4

50.3 51.7 53.1 54.5 55.9 57.3 58.7 60.1 61.5 62.4 64.4 65.8 67.2 68.6 70.0 71.4

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Table 5-5.

8-Core 135W Thermal Profile Table 2U (Sheet 2 of 2)

Power (W) Maximum TCASE (C) Maximum DTS (C)

80 85 90 95 100 105 110 115 120 125 130 135

63.2 64.0 64.8 65.6 66.4 67.2 68.0 68.8 69.6 70.4 71.2 72.0

72.8 74.2 75.6 77.0 78.4 79.8 81.2 82.6 84.0 85.4 86.8 88.2

5.1.3.3
Table 5-6.

8/6-Core 130W Thermal Specifications

Tcase: 8/6-Core 130W Thermal Specifications, Workstation/Server Platform
Core Frequency Thermal Design Power (W) Minimum TCASE (C) Maximum TCASE (C) Notes

Launch to FMB

130

See Figure 5-5 and Table 5-7.

1, 2, 3, 4, 5

Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Please refer to the electrical loadline specifications in Section 7.8.1. 2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. 3. These specifications are based on final silicon characterization. 4. Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements.

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Figure 5-5.

Tcase: 8/6-Core 130W Thermal Profile 1U

Notes: 1. Please refer to Table 5-7 for discrete points that constitute this thermal profile. 2. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Figure 5-6.

DTS: 8-Core 130W Thermal Profile 1U

Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 5-7 for discrete points that constitute the thermal profile. 3. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

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Figure 5-7.

DTS: 6-Core 130W Thermal Profile 1U

Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 5-7 for discrete points that constitute the thermal profile. 3. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Table 5-7.

8/6-Core 130W Thermal Profile Table 1U (Sheet 1 of 2)

Power (W) Maximum TCASE (C) 8/6-core Maximum DTS (C) 8-core 6-Core

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95

56.7 57.8 58.9 60.0 61.1 62.2 63.2 64.3 65.4 66.5 67.6 68.7 69.8 70.9 72.0 73.1 74.1 75.2 76.3 77.4

56.7 58.4 60.0 61.7 63.4 65.0 66.7 68.4 70.0 71.7 73.4 75.0 76.7 78.3 80.0 81.7 83.3 85.0 86.7 88.3

56.7 58.5 60.4 62.2 64.0 65.9 67.7 69.5 71.4 72.5 75.1 76.9 78.7 80.6 82.4 84.2 86.1 87.9 89.7 91.6

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Table 5-7.

8/6-Core 130W Thermal Profile Table 1U (Sheet 2 of 2)

Power (W) Maximum TCASE (C) 8/6-core Maximum DTS (C) 8-core 6-Core

100 105 110 115 120 125 130

78.5 79.6 80.7 81.8 82.9 84.0 85.0

90.0 91.7 93.3 95.0 96.7 98.3 100.0

93.4 95.2 97.1 98.9 100.7 102.6 104.4

5.1.3.4
Table 5-8.

6-Core 130W 1S WS Thermal Specifications

Tcase: 6-Core 130W 1S WS Thermal Specifications
Core Frequency Thermal Design Power (W) Minimum TCASE (C) Maximum TCASE (C) Notes

Launch to FMB

130

See Figure 5-8 and Table 5-9

1, 2, 3, 4, 5

Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Please refer to the electrical loadline specifications in Section 7.8.1. 2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. 3. These specifications are based on final silicon characterization. 4. Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements.

Figure 5-8.

Tcase: 6-Core 130W 1S WS Thermal Profile

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Notes: 1. This Thermal Profile is representative of a volumetrically unconstrained platform. Please refer to Table 5-9 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Figure 5-9.

DTS: 6-Core 130W 1S WS Thermal Profile

Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. This Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 5-9 for discrete points that constitute this thermal profile. 3. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Table 5-9.

6-Core 130W 1S WS Thermal Profile Table (Sheet 1 of 2)

Power (W) Maximum TCASE (C) Maximum DTS (C)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

41.5 42.4 43.2 44.1 45.0 45.8 46.7 47.6 48.4 49.3 50.2 51.0 51.9 52.7 53.6 54.5 55.3

41.5 43.1 44.7 46.3 47.9 49.6 51.2 52.8 54.4 55.3 57.6 59.2 60.8 62.4 64.0 65.7 67.3

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Table 5-9.

6-Core 130W 1S WS Thermal Profile Table (Sheet 2 of 2)

Power (W) Maximum TCASE (C) Maximum DTS (C)

85 90 95 100 105 110 115 120 125 130

56.2 57.1 57.9 58.8 59.7 60.5 61.4 62.3 63.1 64.0

68.9 70.5 72.1 73.7 75.3 76.9 78.5 80.1 81.8 83.4

5.1.3.5

8-Core 115W Thermal Specifications

Table 5-10. Tcase: 8-Core 115W Thermal Specifications 1U

Core Frequency Thermal Design Power (W) Minimum TCASE (C) Maximum TCASE (C) Notes

Launch to FMB

115

See Figure 5-10 and Table 5-11

1, 2, 3, 4, 5

Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Please refer to the electrical loadline specifications in Section 7.8.1. 2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. 3. These specifications are based on final silicon characterization. 4. Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements.

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Figure 5-10. Tcase: 8-Core 115W Thermal Profile 1U

Notes: 1. Please refer to Table 5-11 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Figure 5-11. DTS: 8-Core 115W Thermal Profile 1U

Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 5-11 for discrete points that constitute this thermal profile.

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3.

Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Table 5-11. 8-Core 115W Thermal Profile Table 1U

Power (W) Maximum TCASE (C) Maximum DTS (C)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115

55.0 56.1 57.2 58.3 59.3 60.4 61.5 62.6 63.7 64.8 65.9 66.9 68.0 69.1 70.2 71.3 72.4 73.4 74.5 75.6 76.7 77.8 78.9 80.0

55.0 56.7 58.3 60.0 61.7 63.3 65.0 66.7 68.3 69.3 71.7 73.3 75.0 76.6 78.3 80.0 81.6 83.3 85.0 86.6 88.3 90.0 91.6 93.3

5.1.3.6

8/6-Core 95W Thermal Specifications

Table 5-12. Tcase: 8/6-Core 95W Thermal Specifications, Workstation/Server Platform

Core Frequency Thermal Design Power (W) Minimum TCASE (C) Maximum TCASE (C) Notes

Launch to FMB

95

See Figure 5-12 and Table 5-13

1, 2, 3, 4, 5

Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Please refer to the electrical loadline specifications in Section 7.8.1. 2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. 3. These specifications are based on final silicon characterization. 4. Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements.

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Figure 5-12. Tcase: 8/6-Core 95W Thermal Profile 1U

Notes: 1. Please refer to Table 5-13 for discrete points that constitute this thermal profile. 2. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Figure 5-13. DTS: 8-Core 95W Thermal Profile 1U

Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 5-13 for discrete points that constitute this thermal profile. 3. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

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Figure 5-14. DTS: 6-Core 95W Thermal Profile 1U

Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 5-13 for discrete points that constitute this thermal profile. 3. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Table 5-13. 8/6-Core 95W Thermal Profile Table 1U (Sheet 1 of 2)

Power (W) Maximum TCASE (C) 8/6-core 8-core Maximum DTS (C) 6-core

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

52.2 53.3 54.4 55.5 56.6 57.7 58.8 59.9 61.0 62.1 63.2 64.2 65.3 66.4 67.5 68.6 69.7

52.2 53.9 55.5 57.2 58.9 60.6 62.2 63.9 65.6 67.2 68.9 70.6 72.2 73.9 75.6 77.3 78.9

52.2 53.9 55.7 57.4 59.1 60.8 62.6 64.3 66.0 67.7 69.5 71.2 72.9 74.6 76.4 78.1 79.8

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Table 5-13. 8/6-Core 95W Thermal Profile Table 1U (Sheet 2 of 2)

Power (W) Maximum TCASE (C) 8/6-core 8-core Maximum DTS (C) 6-core

85 90 95

70.8 71.9 73.0

80.6 82.3 83.9

81.5 83.3 85.0

5.1.3.7

8-Core 70W Thermal Specifications

Table 5-14. Tcase: 8-Core 70W Thermal Specifications 1U

Core Frequency Thermal Design Power (W) Minimum TCASE (C) Maximum TCASE (C) Notes

Launch to FMB

70

See Figure 5-15 and Table 5-15

1, 2, 3, 4, 5

Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Please refer to the electrical loadline specifications in Section 7.8.1. 2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. 3. These specifications are based on final silicon characterization. 4. Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements.

Figure 5-15. Tcase: 8-Core 70W Thermal Profile 1U

Notes: 1. Please refer to Table 5-15 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

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Figure 5-16. DTS: 8-Core 70W Thermal Profile 1U

Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 5-15 for discrete points that constitute the thermal profile. 3. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Table 5-15. 8-Core 70W Thermal Profile Table 1U

Power (W) Maximum TCASE (C) Maximum DTS (C)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

48.9 50.0 51.1 52.1 53.2 54.3 55.4 56.4 57.5 58.6 59.7 60.7 61.8 62.9 64.0

48.9 50.5 52.0 53.6 55.2 56.8 58.3 59.9 61.5 63.0 64.6 66.2 67.7 69.3 70.9

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5.1.3.8

6-Core 60W Thermal Specifications

Table 5-16. Tcase: 6-Core 60W Thermal Specifications 1U

Core Frequency Thermal Design Power (W) Minimum TCASE (C) Maximum TCASE (C) Notes

Launch to FMB

60

See Figure 5-17 and Table 5-17

1, 2, 3, 4, 5

Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Please refer to the electrical loadline specifications in Section 7.8.1. 2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. 3. These specifications are based on final silicon characterization. 4. Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements.

Figure 5-17. Tcase: 6-Core 60W Thermal Profile 1U

Notes: 1. Please refer to Table 5-17 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

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Figure 5-18. DTS: 6-Core 60W Thermal Profile 1U

Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 5-17 for discrete points that constitute the thermal profile. 3. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Table 5-17. 6-Core 60W Thermal Profile Table 1U

Power (W) Maximum TCASE (C) Maximum DTS (C)

0 5 10 15 20 25 30 35 40 45 50 55 60

47.1 48.2 49.3 50.3 51.4 52.5 53.6 54.6 55.7 56.8 57.9 58.9 60.0

47.1 48.8 50.5 52.1 53.8 55.5 57.2 58.8 60.5 62.2 63.9 65.5 67.2

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5.1.3.9

4-Core 130W Thermal Specifications

Table 5-18. Tcase: 4-Core 130W Thermal Specifications 2U

Core Frequency Thermal Design Power (W) Minimum TCASE (C) Maximum TCASE (C) Notes

Launch to FMB

130

See Figure 5-19 and Table 5-19

1, 2, 3, 4, 5

Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Please refer to the electrical loadline specifications in Section 7.8.1. 2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. 3. These specifications are based on final silicon characterization. 4. Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements.

Figure 5-19. Tcase: 4-Core 130W Thermal Profile 2U

Notes: 1. This Thermal Profile is representative of a volumetrically unconstrained platform. Please refer to Table 5-19 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

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Figure 5-20. DTS: 4-Core 130W Thermal Profile 2U

Notes: 1. Some of the processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. This Thermal Profile is representative of a volumetrically unconstrained platform. Please refer to Table 5-19 for discrete points that constitute the thermal profile. 3. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Table 5-19. 4-Core 130W Thermal Profile Table 2U (Sheet 1 of 2)

Power (W) Maximum TCASE (C) Maximum DTS (C)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

49.7 50.6 51.5 52.4 53.3 54.2 55.1 56.0 56.9 57.8 58.7 59.5 60.4 61.3 62.2 63.1 64.0

49.7 51.5 53.3 55.0 56.8 58.6 60.4 62.2 63.9 65.0 67.5 69.3 71.1 72.8 74.6 76.4 78.2

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Table 5-19. 4-Core 130W Thermal Profile Table 2U (Sheet 2 of 2)

Power (W) Maximum TCASE (C) Maximum DTS (C)

85 90 95 100 105 110 115 120 125 130

64.9 65.8 66.7 67.6 68.5 69.4 70.3 71.2 72.1 73.0

80.0 81.7 83.5 85.3 87.1 88.9 90.6 92.4 94.2 96.0

5.1.3.10

4-Core 130W 1S WS Thermal Specifications

Table 5-20. Tcase: 4-Core 130W 1S WS Thermal Specifications, Workstation/Server Platform

Core Frequency Thermal Design Power (W) Minimum TCASE (C) Maximum TCASE (C) Notes

Launch to FMB

130

See Figure 5-21 and Table 5-21

1, 2, 3, 4, 5

Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Please refer to the electrical loadline specifications in Section 7.8.1. 2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. 3. These specifications are based on final silicon characterization. 4. Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements.

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Figure 5-21. Tcase: 4-Core 130W 1S WS Thermal Profile

Notes: 1. This Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 5-21 for discrete points that constitute this thermal profile. 2. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Figure 5-22. DTS: 4-Core 130W 1S WS Thermal Profile

Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP.

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2. 3.

This Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 5-21 for discrete points that constitute thermal profile. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Table 5-21. 4-Core 130W 1S WS Thermal Profile Table

Power (W) Maximum TCASE (C) Maximum DTS (C)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130

42.4 43.3 44.3 45.2 46.2 47.1 48.1 49.0 50.0 50.9 51.9 52.8 53.7 54.7 55.6 56.6 57.5 58.5 59.4 60.4 61.3 62.2 63.2 64.1 65.1 66.0 67.0

42.4 44.2 46.1 47.9 49.7 51.6 53.4 55.2 57.0 58.1 60.7 62.5 64.4 66.2 68.0 69.9 71.7 73.5 75.3 77.2 79.0 80.8 82.7 84.5 86.3 88.2 90.0

5.1.3.11

4-Core 95W Thermal Specifications

The 4-Core 95W thermal specifications only applies to the Intel Xeon Processor E54600 Product Family.

Table 5-22. Tcase: 4-Core 95W Thermal Specifications 1U

Core Frequency Thermal Design Power (W) Minimum TCASE (C) Maximum TCASE (C) Notes

Launch to FMB

95

See Figure 5-23 and Table 5-23

1, 2, 3, 4, 5

Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Please refer to the electrical loadline specifications in Section 7.8.1.

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2. 3. 4. 5.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. These specifications are based on final silicon characterization. Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements.

Figure 5-23. Tcase: 4-Core 95W Thermal Profile 1U

1. 2.

Please refer to Table 5-23 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Figure 5-24. DTS: 4-Core 95W Thermal Profile 1U

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1. 2. 3.

Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. Please refer to Table 5-23 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Table 5-23. 4-Core 95W Thermal Profile Table 1U

Power (W) Maximum TCASE (C) 4-core Maximum DTS (C) 4-core

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95

52.7 53.9 55.1 56.2 57.4 58.6 59.8 60.9 62.1 63.3 64.5 65.6 66.8 68.0 69.2 70.3 71.5 72.7 73.9 75.0

52.7 54.7 56.7 58.8 60.8 62.8 64.8 66.8 68.9 70.1 72.9 74.9 76.9 79.0 81.0 83.0 85.0 87.0 89.1 91.1

5.1.3.12

4/2-Core 80W Thermal Specifications

Table 5-24. Tcase: 4/2-Core 80W Thermal Specifications 1U

Core Frequency Thermal Design Power (W) Minimum TCASE (C) Maximum TCASE (C) Notes

Launch to FMB

80

See Figure 5-25 and Table 5-25

1, 2, 3, 4, 5

Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Please refer to the electrical loadline specifications in Section 7.8.1. 2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. 3. These specifications are based on final silicon characterization. 4. Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements.

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Figure 5-25. Tcase: 4/2-Core 80W Thermal Profile 1U

Notes: 1. Please refer to Table 5-25 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Figure 5-26. DTS: 4-Core 80W Thermal Profile 1U

Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 5-25 for discrete points that constitute the thermal profile. 3. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

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Figure 5-27. DTS: 2-Core 80W Thermal Profile 1U

Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 5-25 for discrete points that constitute the thermal profile. 3. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.

Table 5-25. 4/2-Core 80W Thermal Profile Table 1U (Sheet 1 of 2)

Power (W) Maximum TCASE (C) 4-core Maximum DTS (C) 4-core 2-core

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

50.6 51.8 53.0 54.2 55.4 56.7 57.9 59.1 60.3 61.5 62.7 63.9 65.1 66.3 67.5

50.6 52.6 54.7 56.7 58.7 60.7 62.8 64.8 66.8 68.8 70.9 72.9 74.9 76.9 79.0

50.6 52.7 54.8 57.0 59.1 61.2 63.3 65.4 67.6 69.7 71.8 73.9 76.0 78.2 80.3

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Table 5-25. 4/2-Core 80W Thermal Profile Table 1U (Sheet 2 of 2)

Power (W) Maximum TCASE (C) 4-core Maximum DTS (C) 4-core 2-core

75 80

68.8 70.0

81.0 83.0

82.4 84.5

5.1.4

Embedded Server Processor Thermal Profiles

Embedded server SKUs target operation at higher case temperatures and/or NEBS thermal profiles for embedded communications server form factors. The thermal profiles in this section pertain only to those specific SKUs. Network Equipment Building System (NEBS) is the most common set of environmental design guidelines applied to telecommunications equipment in the United States. Digital Thermal Sensor (DTS) based thermal profiles are also provided for each Embedded server SKU. The thermal solution is expected to be developed in accordance with the Tcase thermal profile. Operational compliance monitoring of thermal specifications and fan speed modulation may be done via the DTS based thermal profile. The slope of a DTS profile assumes full fan speed which is not required over much of the power range. At most power levels on embedded SKUs, temperatures of the nominal profile are less than Tcontrol as indicated by the blue shaded region in each DTS profile graph. As a further simplification, operation at DTS temperatures up to Tcontrol is permitted at all power levels. Compliance to the DTS profile is required for any temperatures exceeding Tcontrol.

Table 5-26. Embedded Server Processor Elevated Tcase SKU Summary Table
TDP SKU Tcase Spec DTS Spec

LV95W-8C (8-core) LV70W-8C (8-core)

Figure 5-28 Figure 5-30

Figure 5-29 Figure 5-31

5.1.4.1

8-Core LV95W Thermal Specifications

Table 5-27. Tcase: 8-Core LV95W Thermal Specifications, Embedded Server SKU
Core Frequency Thermal Design Power (W) Minimum TCASE (C) Maximum TCASE (C) Notes

Launch to FMB

95

See Figure 5-28 and Table 5-28

1, 2, 3, 4, 5

Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Please refer to the electrical loadline specifications in Section 7.8.1. 2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. 3. These specifications are based on final silicon characterization. 4. Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements.

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Figure 5-28. Tcase: 8-Core LV95W Thermal Profile, Embedded Server SKU

Notes: 1. This Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 5-28 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. 3. The Nominal Thermal Profile must be used for all normal operating conditions or for products that do not require NEBS Level 3 compliance. 4. The Short-Term Thermal Profile may only be used for short-term excursions to higher ambient operating temperatures, not to exceed 96 hours per instance, 360 hours per year, and a maximum of 15 instances per year, as compliant with NEBS Level 3. Operation at the Short-Term Thermal Profile for durations exceeding 360 hours per year violate the processor thermal specifications and may result in permanent damage to the processor.

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Figure 5-29. DTS: 8-Core LV95W Thermal Profile, Embedded Server SKU

Notes: 1. This Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 5-28 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. 3. The Nominal Thermal Profile must be used for all normal operating conditions or for products that do not require NEBS Level 3 compliance. As indicated by the blue shaded region, operation at DTS temperatures up to Tcontrol is permitted at all power levels. 4. The Short-Term Thermal Profile may only be used for short-term excursions to higher ambient operating temperatures, not to exceed 96 hours per instance, 360 hours per year, and a maximum of 15 instances per year, as compliant with NEBS Level 3. Operation at the Short-Term Thermal Profile for durations exceeding 360 hours per year violate the processor thermal specifications and may result in permanent damage to the processor.

Table 5-28. 8-Core LV95W Thermal Profiles, Embedded Server SKU (Sheet 1 of 2)
Maximum TCASE (C) Power (W) Long Term Short Term Maximum DTS (C) Long Term Short Term

0 5 10 15 20 25 30 35 40 45 50 55 60

52.6 53.7 54.8 55.8 56.9 58.0 59.1 60.1 61.2 62.3 63.4 64.4 65.5

67.6 68.7 69.8 70.8 71.9 73.0 74.1 75.1 76.2 77.3 78.4 79.4 80.5

52 54 55 57 59 60 62 64 65 67 69 70 72

67 69 70 72 74 75 77 79 80 82 84 85 87

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Table 5-28. 8-Core LV95W Thermal Profiles, Embedded Server SKU (Sheet 2 of 2)
Maximum TCASE (C) Power (W) Long Term Short Term Maximum DTS (C) Long Term Short Term

65 70 75 80 85 90 95

66.6 67.7 68.7 69.8 70.9 72.0 73.0

81.6 82.7 83.7 84.8 85.9 87.0 88.0

74 75 77 79 80 82 84

89 90 92 94 95 97 99

5.1.4.2

8-Core LV70W Thermal Specifications

Table 5-29. Tcase: 8-Core LV70W Thermal Specifications, Embedded Server SKU
Core Frequency Thermal Design Power (W) Minimum TCASE (C) Maximum TCASE (C) Notes

Launch to FMB

70

See Figure 5-30 and Table 5-30

1, 2, 3, 4, 5

Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Please refer to the electrical loadline specifications in Section 7.8.1. 2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. 3. These specifications are based on initial final silicon simulations, which will be updated as further characterization data becomes available. 4. Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency. 5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements.

Figure 5-30. Tcase: 8-Core LV70W Thermal Profile, Embedded Server SKU

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Notes: 1. This Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 5-30 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. 3. The Nominal Thermal Profile must be used for all normal operating conditions or for products that do not require NEBS Level 3 compliance. 4. The Short-Term Thermal Profile may only be used for short-term excursions to higher ambient operating temperatures, not to exceed 96 hours per instance, 360 hours per year, and a maximum of 15 instances per year, as compliant with NEBS Level 3. Operation at the Short-Term Thermal Profile for durations exceeding 360 hours per year violate the processor thermal specifications and may result in permanent damage to the processor.

Figure 5-31. DTS: 8-Core LV70W Thermal Profile, Embedded Server SKU

Notes: 1. This Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 5-28 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. 3. The Nominal Thermal Profile must be used for all normal operating conditions or for products that do not require NEBS Level 3 compliance. As indicated by the blue shaded region, operation at DTS temperatures up to Tcontrol is permitted at all power levels. 4. The Short-Term Thermal Profile may only be used for short-term excursions to higher ambient operating temperatures, not to exceed 96 hours per instance, 360 hours per year, and a maximum of 15 instances per year, as compliant with NEBS Level 3. Operation at the Short-Term Thermal Profile for durations exceeding 360 hours per year violate the processor thermal specifications and may result in permanent damage to the processor.

Table 5-30. 8-Core LV70W Thermal Profile Table, Embedded Server SKU (Sheet 1 of 2)
Maximum TCASE (C) Power (W) Long Term Short Term Maximum DTS (C) Long Term Short Term

0 5 10 15 20

52.0 53.8 55.6 57.4 59.2

67.0 68.8 70.6 72.4 74.2

52 54 57 59 62

67 69 72 74 77

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Table 5-30. 8-Core LV70W Thermal Profile Table, Embedded Server SKU (Sheet 2 of 2)
Maximum TCASE (C) Power (W) Long Term Short Term Maximum DTS (C) Long Term Short Term

25 30 35 40 45 50 55 60 65 70

61.0 62.7 64.5 66.3 68.1 69.9 71.7 73.5 75.3 77.1

76.0 77.7 79.5 81.3 83.1 84.9 86.7 88.5 90.3 92.1

64 66 69 71 74 76 78 81 83 86

79 81 84 86 89 91 93 96 98 101

5.1.5

Thermal Metrology
The minimum and maximum case temperatures (TCASE) specified in Table 5-2 through Table 5-30 are measured at the geometric top center of the processor integrated heat spreader (IHS). Figure 5-32 illustrates the location where TCASE temperature measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide.

Figure 5-32. Case Temperature (TCASE) Measurement Location

Notes: 1. Figure is not to scale and is for reference only. 2. B1: Max = 52.57 mm, Min = 52.43 mm. 3. B2: Max = 45.07 mm, Min = 44.93 mm. 4. C1: Max = 43.1 mm, Min = 42.9 mm. 5. C2: Max = 42.6 mm, Min = 42.4 mm. 6. C3: Max = 2.35 mm, Min = 2.15 mm.

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5.2
5.2.1

Processor Core Thermal Features

Processor Temperature
A new feature in the processor is a software readable field in the TEMPERATURE_TARGET MSR register that contains the minimum temperature at which the TCC will be activated and PROCHOT_N will be asserted. The TCC activation temperature is calibrated on a part-by-part basis and normal factory variation may result in the actual TCC activation temperature being higher than the value listed in the register. TCC activation temperatures may change based on processor stepping, frequency or manufacturing efficiencies.

5.2.2

Adaptive Thermal Monitor

The Adaptive Thermal Monitor feature provides an enhanced method for controlling the processor temperature when the processor silicon reaches its maximum operating temperature. Adaptive Thermal Monitor uses Thermal Control Circuit (TCC) activation to reduce processor power via a combination of methods. The first method (Frequency/ SVID control) involves the processor adjusting its operating frequency (via the core ratio multiplier) and input voltage (via the SVID signals). This combination of reduced frequency and voltage results in a reduction to the processor power consumption. The second method (clock modulation) reduces power consumption by modulating (starting and stopping) the internal processor core clocks. The processor intelligently selects the appropriate TCC method to use on a dynamic basis. BIOS is not required to select a specific method. The Adaptive Thermal Monitor feature must be enabled for the processor to be operating within specifications. Snooping and interrupt processing are performed in the normal manner while the TCC is active. With a properly designed and characterized thermal solution, it is anticipated that the TCC would be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable. An underdesigned thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature which may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the Intel Xeon Processor E5-1600/E5-2600/ E5-4600 Product Families Thermal/Mechanical Design Guide for information on designing a compliant thermal solution. The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified. The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines.

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5.2.2.1

Frequency/SVID Control
The processor uses Frequency/SVID control whereby TCC activation causes the processor to adjust its operating frequency (via the core ratio multiplier) and VCC input voltage (via the SVID signals). This combination of reduced frequency and voltage results in a reduction to the processor power consumption. This method includes multiple operating points, each consisting of a specific operating frequency and voltage. The first operating point represents the normal operating condition for the processor. The remaining points consist of both lower operating frequencies and voltages. When the TCC is activated, the processor automatically transitions to the new lower operating frequency. This transition occurs very rapidly (on the order of microseconds).Once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new SVID code to the VCC voltage regulator. The voltage regulator must support dynamic SVID steps to support this method. During the voltage change, it will be necessary to transition through multiple SVID codes to reach the target operating voltage. Each step will be one SVID table entry (see Table 7-3). The processor continues to execute instructions during the voltage transition. Operation at the lower voltages reduces the power consumption of the processor. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point via the intermediate SVID/frequency points. Transition of the SVID code will occur first, to insure proper operation once the processor reaches its normal operating frequency. Refer to Figure 5-33 for an illustration of this ordering.

Figure 5-33. Frequency and Voltage Ordering

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5.2.2.2

Clock Modulation
Clock modulation is performed by alternately turning the clocks off and on at a duty cycle specific to the processor (factory configured to 37.5% on and 62.5% off for TM1). The period of the duty cycle is configured to 32 microseconds when the TCC is active. Cycle times are independent of processor frequency. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases. Clock modulation is automatically engaged as part of the TCC activation when the Frequency/ SVID targets are at their minimum settings. It may also be initiated by software at a configurable duty cycle.

5.2.3

On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as OnDemand mode and is distinct from the Adaptive Thermal Monitor feature. On-Demand mode is intended as a means to reduce system level power consumption. Systems must not rely on software usage of this mechanism to limit the processor temperature. If bit 4 of the IA32_CLOCK_MODULATION MSR is set to a 1, the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using OnDemand mode, the duty cycle of the clock modulation is programmable via bits 3:0 of the same IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can be programmed from 6.25% on / 93.75% off to 93.75% on / 6.25% off in 6.25% increments. On-Demand mode may be used in conjunction with the Adaptive Thermal Monitor; however, if the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode.

5.2.4

PROCHOT_N Signal
An external signal, PROCHOT_N (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If Adaptive Thermal Monitor is enabled (note it must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT_N is asserted. The processor can be configured to generate an interrupt upon the assertion or de-assertion of PROCHOT_N. The PROCHOT_N signal is bi-directional in that it can either signal when the processor (any core) has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT_N can provide a means for thermal protection of system components. As an output, PROCHOT_N will go active when the processor temperature monitoring sensor detects that one or more cores has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT_N by the system will activate the TCC, if enabled, for all cores. TCC activation due to PROCHOT_N assertion by the system will result in the processor immediately transitioning to the minimum frequency and corresponding voltage (using Freq/SVID control). Clock modulation is not activated in this case. The TCC will remain active until the system de-asserts PROCHOT_N.

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PROCHOT_N can allow voltage regulator (VR) thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on PROCHOT_N as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power. With a properly designed and characterized thermal solution, it is anticipated that PROCHOT_N will be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT_N in the anticipated ambient environment may cause a noticeable performance loss. Refer to the appropriate platform design guide and for details on implementing the bi-directional PROCHOT_N feature.

5.2.5

THERMTRIP_N Signal
Regardless of whether Adaptive Thermal Monitor is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP_N definition in Section 6, Signal Descriptions). At this point, the THERMTRIP_N signal will go active and stay active. THERMTRIP_N activation is independent of processor activity and does not generate any Intel QuickPath Interconnect transactions. If THERMTRIP_N is asserted, all processor supplies (VCC, VTTA, VTTD, VSA, VCCPLL, VCCD) must be removed within the timeframe provided. The temperature at which THERMTRIP_N asserts is not user configurable and is not software visible.

5.2.6
5.2.6.1

Integrated Memory Controller (IMC) Thermal Features

DRAM Throttling Options
The Integrated Memory Controller (IMC) has two, independent mechanisms that cause system memory throttling: Open Loop Thermal Throttling (OLTT) and Hybrid OLTT (OLTT_Hybrid) Closed Loop Thermal Throttling (CLTT) and Hybrid CLTT (CLTT_Hybrid)

5.2.6.1.1

Open Loop Thermal Throttling (OLTT) Pure energy based estimation for systems with no BMC or Intel ME. No memory temperature information is provided by the platform or DIMMs. The CPU is informed of the ambient temperature estimate by the BIOS or by a device via the PECI interface. DIMM temperature estimates and bandwidth control are monitored and managed by the PCU on a per rank basis.

5.2.6.1.2

Hybrid Open Loop Thermal Throttling (OLTT_Hybrid) Temperature information is provided by the platform (for example, BMC or Intel Management Engine (Intel ME)) through PECI and the PCU interpolates gaps with energy based estimations.

5.2.6.1.3

Closed Loop Thermal Throttling (CLTT) The processor periodically samples temperatures from the DIMM TSoD devices over a programmable interval. The PCU determines the hottest DIMM rank from TSoD data and informs the integrated memory controller for use in bandwidth throttling decisions.

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5.2.6.2

Hybrid Closed Loop Thermal Throttling (CLTT_Hybrid)

The processor periodically samples temperature from the DIMM TSoD devices over a programmable interval and interpolates gaps or the BMC/Intel ME samples a motherboard thermal sensor in the memory subsection and provides this data to the PCU via the PECI interface. This data is combined with an energy based estimations calculated by the PCU. When needed, system memory is then throttled using CAS bandwidth control. The processor supports dynamic reprogramming of the memory thermal limits based on system thermal state by the BMC or Intel ME.

5.2.6.3

MEM_HOT_C01_N and MEM_HOT_C23_N Signal

The processor includes a pair of new bi-directional memory thermal status signals useful for manageability schemes. Each signal presents and receives thermal status for a pair of memory channels (channels 0 and 1 and channels 2 and 3). Input Function: The processor can periodically sense the MEM_HOT_{C01/C23}_N signals to detect if the platform is requesting a memory throttling event. Manageability hardware could drive this signal due to a memory voltage regulator thermal or electrical issue or because of a detected system thermal event (for example, fan is going to fail) other system devices are exceeding their thermal target. The input sense period of these signals are programmable, 100 us is the default value. The input sense assertion time recognized by the processor is programmable, 1 us is the default value. If the sense assertion time is programmed to zero, then the processor ignores all external assertions of MEM_HOT_{C01/ C23}_N signals (in effect they become outputs). Output Function: The output behavior of the MEM_HOT_{C01/C23}_N signals supports Level mode. In this mode, MEM_HOT_{C01/C23}_N event temperatures are programmable via TEMP_OEM_HI, TEMP_LOW, TEMP_MID, and TEMP_HI threshold settings in the iMC. In Level mode, when asserted, the signal indicates to the platform that a BIOS-configured thermal threshold has been reached by one or more DIMMs in the covered channel pair.

5.2.6.4

Integrated Dual SMBus Master Controllers for SMI

The processor includes two integrated SMBus master controllers running at 100 KHz for dedicated PCU access to the serial presence detect (SPD) devices and thermal sensors (TSoD) on the DIMMs. Each controller is responsible for a pair of memory channels and supports up to eight SMBus slave devices. Note that clock-low stretching is not supported by the processor. To avoid design complexity and minimize package C-state transitions, the SMBus interface between the processor and DIMMs must be connected. The SMBus controllers for the system memory interface support the following SMBus protocols/commands: Random byte Read Byte Write I2C* Write to Pointer Register I2C Present Pointer Register Word Read I2C Pointer Write Register Read. Refer to the System Management Bus (SMBus) Specification, Revision 2.0 for standing timing protocols and specific command structure details.

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Signal Descriptions
This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category.

6.1
Table 6-1.

System Memory Interface Signals

Memory Channel DDR0, DDR1, DDR2, DDR3
Signal Name Description

DDR{0/1/2/3}_BA[2:0] DDR{0/1/2/3}_CAS_N DDR{0/1/2/3}_CKE[5:0] DDR{0/1/2/3}_CLK_DN[3:0] DDR{0/1/2/3}_CLK_DP[3:0] DDR{0/1/2/3}_CS_N[9:0] DDR{0/1/2/3}_DQ[63:00] DDR{0/1/2/3}_DQS_DP[17:00] DDR{0/1/2/3}_DQS_DN[17:00]

Bank Address. Defines the bank which is the destination for the current Activate, Read, Write, or Precharge command. Column Address Strobe. Clock Enable. Differential clocks to the DIMM. All command and control signals are valid on the rising edge of clock. Chip Select. Each signal selects one rank as the target of the command and address. Data Bus. DDR3 Data bits. Data strobes. Differential pair, Data/ECC Strobe. Differential strobes latch data/ECC for each DRAM. Different numbers of strobes are used depending on whether the connected DRAMs are x4,x8. Driven with edges in center of data, receive edges are aligned with data edges. Check bits. An error correction code is driven along with data on these lines for DIMMs that support that capability Memory Address. Selects the Row address for Reads and writes, and the column address for activates. Also used to set values for DRAM configuration registers. Odd parity across Address and Command. On Die Termination. Enables DRAM on die termination during Data Write or Data Read transactions. Parity Error detected by Registered DIMM (one for each channel). Row Address Strobe. Write Enable.

DDR{0/1/2/3}_ECC[7:0] DDR{0/1/2/3}_MA[15:00]

DDR{0/1/2/3}_MA_PAR DDR{0/1/2/3}_ODT[5:0] DDR{0/1/2/3}_PAR_ERR_N DDR{0/1/2/3}_RAS_N DDR{0/1/2/3}_WE_N

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Signal Descriptions

Table 6-2.

Memory Channel Miscellaneous

Signal Name Description

DDR_RESET_C01_N DDR_RESET_C23_N

System memory reset: Reset signal from processor to DRAM devices on the DIMMs. DDR_RESET_C01_N is used for memory channels 0 and 1 while DDR_RESET_C23_N is used for memory channels 2 and 3. SMBus clock for the dedicated interface to the serial presence detect (SPD) and thermal sensors (TSoD) on the DIMMs. DDR_SCL_C01 is used for memory channels 0 and 1 while DDR_SCL_C23 is used for memory channels 2 and 3. SMBus data for the dedicated interface to the serial presence detect (SPD) and thermal sensors (TSoD) on the DIMMs. DDR_SDA_C1 is used for memory channels 0 and 1 while DDR_SDA_C23 is used for memory channels 2 and 3. Voltage reference for system memory reads. DDR_VREFDQRX_C01 is used for memory channels 0 and 1 while DDR_VREFDQRX_C23 is used for memory channels 2 and 3. Voltage reference for system memory writes. DDR_VREFDQTX_C01 is used for memory channels 0 and 1 while DDR_VREFDQTX_C23 is used for memory channels 2 and 3. These signals are not connected. System memory impedance compensation. Impedance compensation must be terminated on the system board using a precision resistor. See the appropriate Platform Design Guide (PDG) for implementation details. Power good input signal used to indicate that the VCCD power supply is stable for memory channels 0 & 1 and channels 2 & 3.

DDR_SCL_C01 DDR_SCL_C23

DDR_SDA_C01 DDR_SDA_C23

DDR_VREFDQRX_C01 DDR_VREFDQRX_C23 DDR_VREFDQTX_C01 DDR_VREFDQTX_C23

DDR{01/23}_RCOMP[2:0]

DRAM_PWR_OK_C01 DRAM_PWR_OK_C23

6.2
Note:

PCI Express* Based Interface Signals

PCI Express* Ports 1, 2 and 3 Signals are receive and transmit differential pairs. PCI Express* Port 1 Signals
Signal Name Description

Table 6-3.

PE1A_RX_DN[3:0] PE1A_RX_DP[3:0] PE1B_RX_DN[7:4] PE1B_RX_DP[7:4] PE1A_TX_DN[3:0] PE1A_TX_DP[3:0] PE1B_TX_DN[7:4] PE1B_TX_DP[7:4]

PCIe* Receive Data Input PCIe* Receive Data Input PCIe* Transmit Data Output PCIe* Transmit Data Output

Table 6-4.

PCI Express* Port 2 Signals (Sheet 1 of 2)

Signal Name Description

PE2A_RX_DN[3:0] PE2A_RX_DP[3:0] PE2B_RX_DN[7:4] PE2B_RX_DP[7:4] PE2C_RX_DN[11:8] PE2C_RX_DP[11:8]

PCIe* Receive Data Input PCIe* Receive Data Input PCIe* Receive Data Input

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Table 6-4.

PCI Express* Port 2 Signals (Sheet 2 of 2)

Signal Name Description

PE2D_RX_DN[15:12] PE2D_RX_DP[15:12] PE2A_TX_DN[3:0] PE2A_TX_DP[3:0] PE2B_TX_DN[7:4] PE2B_TX_DP[7:4] PE2C_TX_DN[11:8] PE2C_TX_DP[11:8] PE2D_TX_DN[15:12] PE2D_TX_DP[15:12]

PCIe* Receive Data Input PCIe* Transmit Data Output PCIe* Transmit Data Output PCIe* Transmit Data Output PCIe* Transmit Data Output

Table 6-5.

PCI Express* Port 3 Signals

Signal Name Description

PE3A_RX_DN[3:0] PE3A_RX_DP[3:0] PE3B_RX_DN[7:4] PE3B_RX_DP[7:4] PE3C_RX_DN[11:8] PE3C_RX_DP[11:8] PE3D_RX_DN[15:12] PE3D_RX_DP[15:12] PE3A_TX_DN[3:0] PE3A_TX_DP[3:0] PE3B_TX_DN[7:4] PE3B_TX_DP[7:4] PE3C_TX_DN[11:8] PE3C_TX_DP[11:8] PE3D_TX_DN[15:12] PE3D_TX_DP[15:12]

PCIe* Receive Data Input PCIe* Receive Data Input PCIe* Receive Data Input PCIe* Receive Data Input PCIe* Transmit Data Output PCIe* Transmit Data Output PCIe* Transmit Data Output PCIe* Transmit Data Output

Table 6-6.

PCI Express* Miscellaneous Signals (Sheet 1 of 2)

Signal Name Description

PE_RBIAS

This input is used to control PCI Express* bias currents. A 50 ohm 1% tolerance resistor must be connected from this land to VSS by the platform. PE_RBIAS is required to be connected as if the link is being used even when PCIe* is not used. Refer to the appropriate Platform Design Guide (PDG) for further details. Provides dedicated bias resistor sensing to minimize the voltage drop caused by packaging and platform effects. PE_RBIAS_SENSE is required to be connected as if the link is being used even when PCIe* is not used. Refer to the appropriate Platform Design Guide (PDG) for further details. PCI Express* voltage reference used to measure the actual output voltage and comparing it to the assumed voltage. A 0.01uF capacitor must be connected from this land to VSS. PCI Express* Hot-Plug SMBus Clock: Provides PCI Express* hotplug support via a dedicated SMBus interface. Requires an external general purpose input/output (GPIO) expansion device on the platform.

PE_RBIAS_SENSE

PE_VREF_CAP

PEHPSCL

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Table 6-6.

PCI Express* Miscellaneous Signals (Sheet 2 of 2)

Signal Name Description

PEHPSDA

PCI Express* Hot-Plug SMBus Data: Provides PCI Express* hotplug support via a dedicated SMBus interface. Requires an external general purpose input/output (GPIO) expansion device on the platform.

Note:

Refer to the appropriate Platform Design Guide (PDG) for additional implementation details.

6.3
Table 6-7.

DMI2/PCI Express* Port 0 Signals

DMI2 and PCI Express* Port 0 Signals
Signal Name Description

DMI_RX_DN[3:0] DMI_RX_DP[3:0] DMI_TX_DP[3:0] DMI_TX_DN[3:0]

DMI2 Receive Data Input DMI2 Transmit Data Output

6.4
Table 6-8.

Intel QuickPath Interconnect Signals

Intel QPI Port 0 and 1 Signals
Signal Name Description

QPI{0/1}_CLKRX_DN/DP

Reference Clock Differential Input. These pins provide the PLL reference clock differential input. The Intel QPI forward clock frequency is half the Intel QPI data rate. Reference Clock Differential Output. These pins provide the PLL reference clock differential input. The Intel QPI forward clock frequency is half the Intel QPI data rate. Intel QPI Receive data input. Intel QPI Transmit data output.

QPI{0/1}_CLKTX_DN/DP

QPI{0/1}_DRX_DN/DP[19:00] QPI{0/1}_DTX_DN/DP[19:00]

Table 6-9.

Intel QPI Miscellaneous Signals

Signal Name Description

QPI_RBIAS

This input is used to control Intel QPI bias currents. QPI_RBIAS is required to be connected as if the link is being used even when Intel QPI is not used. Refer to the appropriate Platform Design Guide (PDG) for further details. Provides dedicated bias resistor sensing to minimize the voltage drop caused by packaging and platform effects. QPI_RBIAS_SENSE is required to be connected as if the link is being used even when Intel QPI is not used. Refer to the appropriate Platform Design Guide (PDG) for further details. Intel QPI voltage reference used to measure the actual output voltage and comparing it to the assumed voltage. Refer to the appropriate Platform Design Guide (PDG) for further details.

QPI_RBIAS_SENSE

QPI_VREF_CAP

Note:

Refer to the appropriate Platform Design Guide (PDG) for additional implementation details.

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6.5

PECI Signal

Table 6-10. PECI Signals

Signal Name Description

PECI

PECI (Platform Environment Control Interface) is the serial sideband interface to the processor and is used primarily for thermal, power and error management. Details regarding the PECI electrical specifications, protocols and functions can be found in the Platform Environment Control Interface Specification.

6.6

System Reference Clock Signals

Table 6-11. System Reference Clock (BCLK{0/1}) Signals

Signal Name Description

BCLK{0/1}_D[N/P]

Reference Clock Differential input. These pins provide the PLL reference clock differential input into the processor. Both 100MHz BCLK0 and BCLK1 from the same clock source provide the required reference clock inputs to the various PLLs inside the CPU.

6.7

JTAG and TAP Signals

Table 6-12. JTAG and TAP Signals

Signal Name Description

BPM_N[7:0]

Breakpoint and Performance Monitor Signals: I/O signals from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. These are 100 MHz signals. External Alignment of Reset, used to bring the processor up into a deterministic state. This signal is pulled up on the die, refer to Table 7-6 for details. Probe Mode Ready is a processor output used by debug tools to determine processor debug readiness. Probe Mode Request is used by debug tools to request debug operation of the processor. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRST_N (Test Reset) resets the Test Access Port (TAP) logic. TRST_N must be driven low during power on Reset.

EAR_N PRDY_N PREQ_N TCK TDI TDO TMS TRST_N

Note:

Refer to the appropriate Platform Design Guide (PDG) for Debug Port implementation details.

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6.8

Serial VID Interface (SVID) Signals

Table 6-13. SVID Signals

SVIDALERT_N SVIDCLK SVIDDATA Serial VID alert. Serial VID clock. Serial VID data out.

6.9

Processor Asynchronous Sideband and Miscellaneous Signals

Table 6-14. Processor Asynchronous Sideband Signals (Sheet 1 of 3)

Signal Name Description

BIST_ENABLE BMCINIT

BIST Enable Strap. Input which allows the platform to enable or disable built-in self test (BIST) on the processor. This signal is pulled up on the die, refer to Table 7-6 for details. BMC Initialization Strap. Indicates whether Service Processor Boot Mode should be used. Used in combination with FRMAGENT and SOCKET_ID inputs. 0: Service Processor Boot Mode Disabled. Example boot modes: Local PCH (this processor hosts a legacy PCH with firmware behind it), Intel QPI Link Boot (for processors one hop away from the FW agent), or Intel QPI Link Init (for processors more than one hop away from the firmware agent). 1: Service Processor Boot Mode Enabled. In this mode of operation, the processor performs the absolute minimum internal configuration and then waits for the Service Processor to complete its initialization. The socket boots after receiving a GO handshake signal via a firmware scratchpad register. This signal is pulled down on the die, refer to Table 7-6 for details. Indicates that the system has experienced a fatal or catastrophic error and cannot continue to operate. The processor will assert CAT_ERR_N for nonrecoverable machine check errors and other internal unrecoverable errors. It is expected that every processor in the system will wire-OR CAT_ERR_N for all processors. Since this is an I/O land, external agents are allowed to assert this land which will cause the processor to take a machine check exception. This signal is sampled after PWRGOOD assertion. On the processor, CAT_ERR_N is used for signaling the following types of errors: Legacy MCERRs, CAT_ERR_N is asserted for 16 BCLKs. Legacy IERRs, CAT_ERR_N remains asserted until warm or cold reset. Resets all the processors on the platform without resetting the DMI2 links. Error status signals for integrated I/O (IIO) unit: 0 = Hardware correctable error (no operating system or firmware action necessary) 1 = Non-fatal error (operating system or firmware action required to contain and recover) 2 = Fatal error (system reset likely required to recover) Bootable Firmware Agent Strap. This input configuration strap used in combination with SOCKET_ID to determine whether the socket is a legacy socket, bootable firmware agent is present, and DMI links are used in PCIe* mode (instead of DMI2 mode). The firmware flash ROM is located behind the local PCH attached to the processor via the DMI2 interface.This signal is pulled down on the die, refer to Table 7-6 for details. Memory throttle control. MEM_HOT_C01_N and MEM_HOT_C23_N signals have two modes of operation input and output mode. Input mode is externally asserted and is used to detect external events such as VR_HOT# from the memory voltage regulator and causes the processor to throttle the appropriate memory channels. Output mode is asserted by the processor known as level mode. In level mode, the output indicates that a particular branch of memory subsystem is hot. MEM_HOT_C01_N is used for memory channels 0 & 1 while MEM_HOT_C23_N is used for memory channels 2 & 3. Power Management Sync. A sideband signal to communicate power management status from the Platform Controller Hub (PCH) to the processor.

CAT_ERR_N

CPU_ONLY_RESET ERROR_N[2:0]

FRMAGENT

MEM_HOT_C01_N MEM_HOT_C23_N

PMSYNC

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Table 6-14. Processor Asynchronous Sideband Signals (Sheet 2 of 3)

Signal Name Description

PROCHOT_N

PROCHOT_N will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. This signal can also be driven to the processor to activate the Thermal Control Circuit. This signal is sampled after PWRGOOD assertion. If PROCHOT_N is asserted at the deassertion of RESET_N, the processor will tristate its outputs. Power Good is a processor input. The processor requires this signal to be a clean indication that BCLK, VTTA/VTTD, VSA, VCCPLL, and VCCD_01 and VCCD_23 supplies are stable and within their specifications. Clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. PWRGOOD transitions from inactive to active when all supplies except VCC are stable. VCC has a VBOOT of zero volts and is not included in PWRGOOD indication in this phase. However, for the active to inactive transition, if any CPU power supply (VCC, VTTA/VTTD, VSA, VCCD, or VCCPLL) is about to fail or is out of regulation, the PWRGOOD is to be negated. The signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. Note: VCC has a Vboot setting of 0.0V and is not included in the PWRGOOD indication and VSA has a Vboot setting of 0.9V. Refer to the VR12/IMVP7 Pulse Width Modulation Specification. Asserting the RESET_N signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. Note some PLL, Intel QuickPath Interconnect and error states are not effected by reset and only PWRGOOD forces them to a known state. RESERVED. All signals that are RSVD must be left unconnected on the board. Refer to Section 7.1.10, Reserved or Unused Signals for details. Safe mode boot Strap. SAFE_MODE_BOOT allows the processor to wake up safely by disabling all clock gating, this allows BIOS to load registers or patches if required. This signal is sampled after PWRGOOD assertion. The signal is pulled down on the die, refer to Table 7-6 for details. Socket ID Strap. Socket identification configuration straps for establishing the PECI address, Intel QPI Node ID, and other settings. This signal is used in combination with FRMAGENT to determine whether the socket is a legacy socket, bootable firmware agent is present, and DMI links are used in PCIe* mode (instead of DMI2 mode). Each processor socket consumes one Node ID, and there are 128 Home Agent tracker entries. This signal is pulled down on the die, refer to Table 7-6 for details. Test[4:0] must be individually connected to an appropriate power source or ground through a resistor for proper processor operation. Refer to the appropriate Platform Design Guide (PDG) for additional implementation details. Assertion of THERMTRIP_N (Thermal Trip) indicates one of two possible critical overtemperature conditions: One, the processor junction temperature has reached a level beyond which permanent silicon damage may occur and Two, the system memory interface has exceeded a critical temperature limit set by BIOS. Measurement of the processor junction temperature is accomplished through multiple internal thermal sensors that are monitored by the Digital Thermal Sensor (DTS). Simultaneously, the Power Control Unit (PCU) monitors external memory temperatures via the dedicated SMBus interface to the DIMMs. If any of the DIMMs exceed the BIOS defined limits, the PCU will signal THERMTRIP_N to prevent damage to the DIMMs. Once activated, the processor will stop all execution and shut down all PLLs. To further protect the processor, its core voltage (VCC), VTTA, VTTD, VSA, VCCPLL, VCCD supplies must be removed following the assertion of THERMTRIP_N. Once activated, THERMTRIP_N remains latched until RESET_N is asserted. While the assertion of the RESET_N signal may de-assert THERMTRIP_N, if the processor's junction temperature remains at or above the trip level, THERMTRIP_N will again be asserted after RESET_N is de-asserted. This signal can also be asserted if the system memory interface has exceeded a critical temperature limit set by BIOS. This signal is sampled after PWRGOOD assertion.

PWRGOOD

RESET_N

RSVD SAFE_MODE_BOOT

SOCKET_ID[1:0]

TEST[4:0]

THERMTRIP_N

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Table 6-14. Processor Asynchronous Sideband Signals (Sheet 3 of 3)

Signal Name Description

TXT_AGENT

Intel TXT Platform Enable Strap. 0 = Default. The socket is not the Intel TXT Agent. 1 = The socket is the Intel TXT Agent. In non-Scalable DP platforms, the legacy socket (identified by SOCKET_ID[1:0] = 00b) with Intel TXT Agent should always set the TXT_AGENT to 1b. On Scalable DP platforms the Intel TXT AGENT is at the Node Controller. Refer to the Platform Design Guide for more details. This signal is pulled down on the die, refer to Table 7-6 for details. Intel TXT Platform Enable Strap. 0 = The platform is not Intel TXT enabled. All sockets should be set to zero. Scalable DP (sDP) platforms should choose this setting if the Node Controller does not support Intel TXT. 1 = Default. The platform is Intel TXT enabled. All sockets should be set to one. In a nonScalable DP platform this is the default. When this is set, Intel TXT functionality requires user to explicitly enable Intel TXT via BIOS setup. This signal is pulled up on the die, refer to Table 7-6 for details.

TXT_PLTEN

Table 6-15. Miscellaneous Signals

Signal Name Description

IVT_ID_N

This output can be used by the platform to determine if the installed processor is a future processor planned for the Intel Xeon processor E5-1600/E5-2600/E5-4600 product families-based Platform. There is no connection to the processor silicon for this signal. This signal is also used by the VCCPLL and VTT rails to switch their output voltage to support future processors. SKTOCC_N (Socket occupied) is used to indicate that a processor is present. This is pulled to ground on the processor package; there is no connection to the processor silicon for this signal.

SKTOCC_N

6.10

Processor Power and Ground Supplies

Table 6-16. Power and Ground Signals (Sheet 1 of 2)

Signal Name Description

VCC

Variable power supply for the processor cores, lowest level caches (LLC), ring interface, and home agent. It is provided by a VRM/ EVRD 12.0 compliant regulator for each CPU socket. The output voltage of this supply is selected by the processor, using the serial voltage ID (SVID) bus. Note: VCC has a Vboot setting of 0.0V and is not included in the PWRGOOD indication. Refer to the VR12/IMVP7 Pulse Width Modulation Specification. VCC_SENSE and VSS_VCC_SENSE provide an isolated, low impedance connection to the processor core power and ground. These signals must be connected to the voltage regulator feedback circuit, which insures the output voltage (that is, processor voltage) remains within specification. Please see the applicable platform design guide for implementation details. VSA_SENSE and VSS_VSA_SENSE provide an isolated, low impedance connection to the processor system agent (VSA) power plane. These signals must be connected to the voltage regulator feedback circuit, which insures the output voltage (that is, processor voltage) remains within specification. Please see the applicable platform design guide for implementation details.

VCC_SENSE VSS_VCC_SENSE

VSA_SENSE VSS_VSA_SENSE

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Table 6-16. Power and Ground Signals (Sheet 2 of 2)

Signal Name Description

VTTD_SENSE VSS_VTTD_SENSE

VTTD_SENSE and VSS_VTTD_SENSE provide an isolated, low impedance connection to the processor I/O power plane. These signals must be connected to the voltage regulator feedback circuit, which insures the output voltage (that is, processor voltage) remains within specification. Please see the applicable platform design guide for implementation details. Variable power supply for the processor system memory interface. Provided by two VRM/EVRD 12.0 compliant regulators per CPU socket. VCCD_01 and VCCD_23 are used for memory channels 0, 1, 2, and 3 respectively. The valid voltage of this supply (1.50 V or 1.35 V) is configured by BIOS after determining the operating voltages of the installed memory. VCCD_01 and VCCD_23 will also be referred to as VCCD. Note: The processor must be provided VCCD_01 and VCCD_23 for proper operation, even in configurations where no memory is populated. A VRM/EVRD 12.0 controller is recommended, but not required. Fixed power supply (1.8V) for the processor phased lock loop (PLL). Variable power supply for the processor system agent units. These include logic (non-I/O) for the integrated I/O controller, the integrated memory controller (iMC), the Intel QPI agent, and the Power Control Unit (PCU). The output voltage of this supply is selected by the processor, using the serial voltage ID (SVID) bus. Note: VSA has a Vboot setting of 0.9V. Refer to the VR12/IMVP7 Pulse Width Modulation Specification. Processor ground node. Combined fixed analog and digital power supply for I/O sections of the processor Intel QPI interface, Direct Media Interface Gen 2 (DMI2) interface, and PCI Express* interface. These signals will also be referred to as VTT. Please see the appropriate Platform Design Guide (PDG)for implementation details.

VCCD_01 and VCCD_23

VCCPLL

VSA

VSS VTTA VTTD

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7
7.1

Electrical Specifications
Processor Signaling
The processor includes 2011 lands, which utilize various signaling technologies. Signals are grouped by electrical characteristics and buffer type into various signal groups. These include DDR3 (Reference Clock, Command, Control, and Data), PCI Express*, DMI2, Intel QuickPath Interconnect, Platform Environmental Control Interface (PECI), System Reference Clock, SMBus, JTAG and Test Access Port (TAP), SVID Interface, Processor Asynchronous Sideband, Miscellaneous, and Power/Other signals. Refer to Table 7-5 for details. Detailed layout, routing, and termination guidelines corresponding to these signal groups can be found in the applicable platform design guide (Refer to Section 1.7, Related Documents). Intel strongly recommends performing analog simulations of all interfaces. Please refer to Section 1.7, Related Documents for signal integrity model availability.

7.1.1

System Memory Interface Signal Groups

The system memory interface utilizes DDR3 technology, which consists of numerous signal groups. These include: Reference Clocks, Command Signals, Control Signals, and Data Signals. Each group consists of numerous signals, which may utilize various signaling technologies. Please refer to Table 7-5 for further details. Throughout this chapter the system memory interface maybe referred to as DDR3.

7.1.2

PCI Express* Signals

The PCI Express* Signal Group consists of PCI Express* ports 1, 2, and 3, and PCI Express* miscellaneous signals. Please refer to Table 7-5 for further details.

7.1.3

DMI2/PCI Express* Signals

The Direct Media Interface Gen 2 (DMI2) sends and receives packets and/or commands to the PCH. The DMI2 is an extension of the standard PCI Express* Specification. The DMI2/PCI Express* Signals consist of DMI2 receive and transmit input/output signals and a control signal to select DMI2 or PCIe* 2.0 operation for port 0. Please refer to Table 7-5 for further details.

7.1.4

Intel QuickPath Interconnect (Intel QPI)

The processor provides two Intel QPI port for high speed serial transfer between other processors. Each port consists of two uni-directional links (for transmit and receive). A differential signaling scheme is utilized, which consists of opposite-polarity (DP, DN) signal pairs.

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7.1.5

Platform Environmental Control Interface (PECI)

PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external system management logic and thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature. Temperature sensors located throughout the die are implemented as analog-to-digital converters calibrated at the factory. PECI provides an interface for external devices to read processor temperature, perform processor manageability functions, and manage processor interface tuning and diagnostics. Please refer to Section 2.5, Platform Environment Control Interface (PECI) for processor specific implementation details for PECI. The PECI interface operates at a nominal voltage set by VTTD. The set of DC electrical specifications shown in Table 7-17 is used with devices normally operating from a VTTD interface supply.

7.1.5.1

Input Device Hysteresis

The PECI client and host input buffers must use a Schmitt-triggered input design for improved noise immunity. Please refer to Figure 7-1 and Table 7-17.

Figure 7-1.

Input Device Hysteresis

VTTD Maximum VP Minimum VP Minimum Hysteresis Maximum VN Minimum VN PECI Ground PECI Low Range Valid Input Signal Range PECI High Range

7.1.6

System Reference Clocks (BCLK{0/1}_DP, BCLK{0/ 1}_DN)

The processor core, processor uncore, Intel QuickPath Interconnect link, PCI Express* and DDR3 memory interface frequencies) are generated from BCLK{0/1}_DP and BCLK{0/1}_DN signals. There is no direct link between core frequency and Intel QuickPath Interconnect link frequency (for example, no core frequency to Intel QuickPath Interconnect multiplier). The processor maximum core frequency, Intel QuickPath Interconnect link frequency and DDR memory frequency are set during manufacturing. It is possible to override the processor core frequency setting using software. This permits operation at lower core frequencies than the factory set maximum core frequency.

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The processor core frequency is configured during reset by using values stored within the device during manufacturing. The stored value sets the lowest core multiplier at which the particular processor can operate. If higher speeds are desired, the appropriate ratio can be configured via the IA32_PERF_CTL MSR (MSR 199h); Bits [15:0]. Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP, BCLK{0/1}_DN inputs are provided in Table 7-18. These specifications must be met while also meeting the associated signal quality specifications outlined in Section 7.9.

7.1.6.1

PLL Power Supply

An on-die PLL filter solution is implemented on the processor. Refer to Table 7-11 for DC specifications and to the applicable platform design guide for decoupling and routing guidelines.

7.1.7

JTAG and Test Access Port (TAP) Signals

Due to the voltage levels supported by other components in the JTAG and Test Access Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any other components within the system. Please refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families BSDL (Boundary Scan Description Language) for more details. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage. Two copies of each signal may be required with each driving a different voltage level.

7.1.8

Processor Sideband Signals

The processor include asynchronous sideband signals that provide asynchronous input, output or I/O signals between the processor and the platform or Platform Controller Hub. Details can be found in Table 7-5 and the applicable platform design guide. All Processor Asynchronous Sideband input signals are required to be asserted/ deasserted for a defined number of BCLKs in order for the processor to recognize the proper signal state. Refer to Section 7.9 for applicable signal integrity specifications.

7.1.9

Power, Ground and Sense Signals

Processors also include various other signals including power/ground and sense points. Details can be found in Table 7-5 and the applicable platform design guide.

7.1.9.1

Power and Ground Lands

All VCC, VCCPLL, VSA, VCCD, VTTA, and VTTD lands must be connected to their respective processor power planes, while all VSS lands must be connected to the system ground plane. Refer to the applicable platform design guide for decoupling, voltage plane and routing guidelines for each power supply voltage. For clean on-chip power distribution, processors include lands for all required voltage supplies. These are listed in Table 7-1.

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Table 7-1.

Power and Ground Lands

Power and Ground Lands Number of Lands Comments

VCC

208

Each VCC land must be supplied with the voltage determined by the SVID Bus signals. Table 7-3 Defines the voltage level associated with each core SVID pattern.Table 7-11, Figure 7-2, and Figure 7-5 represent VCC static and transient limits. VCC has a VBOOT setting of 0.0V. Each VCCPLL land is connected to a 1.80 V supply, power the Phase Lock Loop (PLL) clock generation circuitry. An on-die PLL filter solution is implemented within the processor. Each VCCD land is connected to a switchable 1.50 V and 1.35 V supply, provide power to the processor DDR3 interface. These supplies also power the DDR3 memory subsystem. VCCD is also controlled by the SVID Bus. VCCD is the generic term for VCCD_01, VCCD_23. VTTA lands must be supplied by a fixed 1.05 V supply. VTTD lands must be supplied by a fixed 1.05 V supply. Each VSA land must be supplied with the voltage determined by the SVID Bus signals, typically set at 0.965V. VSA has a VBOOT setting of 0.9 V. Ground

VCCPLL

VCCD_01 VCCD_23

51

VTTA VTTD VSA

14 19 25

VSS

548

7.1.9.2

Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Large electrolytic bulk capacitors (CBULK), help maintain the output voltage during current transients, for example coming out of an idle condition. Care must be taken in the baseboard design to ensure that the voltages provided to the processor remain within the specifications listed in Table 7-11. Failure to do so can result in timing violations or reduced lifetime of the processor. For further information, refer to the appropriate Platform Design Guide (PDG).

7.1.9.3

Voltage Identification (VID)

The Voltage Identification (VID) specification for the VCC, VSA, VCCD voltage are defined by the VR12/IMVP7 Pulse Width Modulation Specification. The reference voltage or the VID setting is set via the SVID communication bus between the processor and the voltage regulator controller chip. The VID settings are the nominal voltages to be delivered to the processor's VCC, VSA, VCCD lands. Table 7-3 specifies the reference voltage level corresponding to the VID value transmitted over serial VID. The VID codes will change due to temperature and/or current load changes in order to minimize the power and to maximize the performance of the part. The specifications are set so that a voltage regulator can operate with all supported frequencies. Individual processor VID values may be calibrated during manufacturing such that two processor units with the same core frequency may have different default VID settings. The processor uses voltage identification signals to support automatic selection of VCC, VSA, and VCCD power supply voltages. If the processor socket is empty (SKTOCC_N high), or a not supported response is received from the SVID bus, then the voltage regulation circuit cannot supply the voltage that is requested, the voltage regulator must disable itself or not power on. Vout MAX register (30h) is programmed by the processor to set the maximum supported VID code and if the programmed VID code is

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higher than the VID supported by the VR, then VR will respond with a not supported acknowledgement. See the VR12/IMVP7 Pulse Width Modulation Specification for further details. 7.1.9.3.1 SVID Commands The processor provides the ability to operate while transitioning to a new VID setting and its associated processor voltage rails (VCC, VSA, and VCCD). This is represented by a DC shift. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target voltage. Transitions above the maximum specified VID are not supported. The processor supports the following VR commands: SetVID_fast (20 mV/s for VCC,10 mV/s for VSA/VCCD), SetVID_slow (5 mV/s for VCC, 2.5 mV/s for VSA/VCCD), and Slew Rate Decay (downward voltage only and its a function of the output capacitances time constant) commands. Table 7-3 and Table 7-21 includes SVID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in Table 7-11. The VRM or EVRD utilized must be capable of regulating its output to the value defined by the new VID. The VR12/IMVP7 Pulse Width Modulation Specification contains further details. Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable. 7.1.9.3.2 SetVID Fast Command The SetVID-fast command contains the target VID in the payload byte. The range of voltage is defined in the VID table. The VR should ramp to the new VID setting with a fast slew rate as defined in the slew rate data register. Typically 10 to 20 mV/s depending on platform, voltage rail, and the amount of decoupling capacitance. The SetVID-fast command is preemptive, the VR interrupts its current processes and moves to the new VID. The SetVID-fast command operates on 1 VR address at a time. This command is used in the processor for package C6 fast exit and entry. 7.1.9.3.3 SetVID Slow Command The SetVID-slow command contains the target VID in the payload byte. The range of voltage is defined in the VID table. The VR should ramp to the new VID setting with a slow slew rate as defined in the slow slew rate data register. The SetVID_Slow is 1/4 slower than the SetVID_fast slew rate. The SetVID-slow command is preemptive, the VR interrupts its current processes and moves to the new VID. This is the instruction used for normal P-state voltage change. This command is used in the processor for the Intel Enhanced SpeedStep Technology transitions. 7.1.9.3.4 SetVID-Decay Command The SetVID-Decay command is the slowest of the DVID transitions. It is only used for VID down transitions. The VR does not control the slew rate, the output voltage declines with the output load current only. The SetVID- Decay command is preemptive, that is, the VR interrupts its current processes and moves to the new VID.

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7.1.9.3.5

SVID Power State Functions: SetPS The processor has three power state functions and these will be set seamlessly via the SVID bus using the SetPS command. Based on the power state command, the SetPS commands sends information to VR controller to configure the VR to improve efficiency, especially at light loads. For example, typical power states are: PS0(00h): Represents full power or active mode PS1(01h): Represents a light load 5 A to 20 A PS2(02h): Represents a very light load <5 A The VR may change its configuration to meet the processors power needs with greater efficiency. For example, it may reduce the number of active phases, transition from CCM (Continuous Conduction Mode) to DCM (Discontinuous Conduction Mode) mode, reduce the switching frequency or pulse skip, or change to asynchronous regulation. For example, typical power states are 00h = run in normal mode; a command of 01h= shed phases mode, and an 02h=pulse skip. The VR may reduce the number of active phases from PS0 to PS1 or PS0 to PS2 for example. There are multiple VR design schemes that can be used to maintain a greater efficiency in these different power states, please work with your VR controller suppliers for optimizations. The SetPS command sends a byte that is encoded as to what power state the VR should transition to. If a power state is not supported by the controller, the slave should acknowledge with command rejected (11b) Note the mapping of power states 0-n will be detailed in the VR12/IMVP7 Pulse Width Modulation Specification. If the VR is in a low power state and receives a SetVID command moving the VID up then the VR exits the low power state to normal mode (PS0) to move the voltage up as fast as possible. The processor must re-issue low power state (PS1 or PS2) command if it is in a low current condition at the new higher voltage. See Figure 7-2 for VR power state transitions.

Figure 7-2.

VR Power-State Transitions

PS0

PS1

PS2

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7.1.9.3.6

SVID Voltage Rail Addressing The processor addresses 4 different voltage rail control segments within VR12 (VCC, VCCD_01, VCCD_23, and VSA). The SVID data packet contains a 4-bit addressing code:

Table 7-2.

SVID Address Usage

PWM Address (HEX) Processor

00 01 02 03 04 05

Vcc Vsa VCCD_01 +1 not used VCCD_23 +1 not used

Notes: 1. Check with VR vendors for determining the physical address assignment method for their controllers. 2. VR addressing is assigned on a per voltage rail basis. 3. Dual VR controllers will have two addresses with the lowest order address, always being the higher phase count. 4. For future platform flexibility, the VR controller should include an address offset, as shown with +1 not used.

Table 7-3.
HEX

VR12.0 Reference Code Voltage Identification (VID) Table (Sheet 1 of 2)

HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD

VCC, VSA, VCCD

00 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48

0.00000 0.50000 0.50500 0.51000 0.51500 0.52000 0.52500 0.53000 0.53500 0.54000 0.54500 0.55000 0.55500 0.56000 0.56500 0.57000 0.57500 0.58000 0.58500 0.59000 0.59500 0.60000 0.60500

55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B

0.67000 0.67500 0.68000 0.68500 0.69000 0.69500 0.70000 0.70500 0.71000 0.71500 0.72000 0.72500 0.73000 0.73500 0.74000 0.74500 0.75000 0.75500 0.76000 0.76500 0.77000 0.77500 0.78000

78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E

0.84500 0.85000 0.85500 0.86000 0.86500 0.87000 0.87500 0.88000 0.88500 0.89000 0.89500 0.90000 0.90500 0.91000 0.91500 0.92000 0.92500 0.93000 0.93500 0.94000 0.94500 0.95000 0.95500

9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1

1.02000 1.02500 1.03000 1.03500 1.04000 1.04500 1.05000 1.05500 1.06000 1.06500 1.07000 1.07500 1.08000 1.08500 1.09000 1.09500 1.10000 1.10500 1.11000 1.11500 1.12000 1.12500 1.13000

BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4

1.19500 1.20000 1.20500 1.21000 1.21500 1.22000 1.22500 1.23000 1.23500 1.24000 1.24500 1.25000 1.25500 1.26000 1.26500 1.27000 1.27500 1.28000 1.28500 1.29000 1.29500 1.30000 1.30500

E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7

1.37000 1.37500 1.38000 1.38500 1.39000 1.39500 1.40000 1.40500 1.41000 1.41500 1.42000 1.42500 1.43000 1.43500 1.44000 1.44500 1.45000 1.45500 1.46000 1.46500 1.47000 1.47500 1.48000

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Table 7-3.
HEX

VR12.0 Reference Code Voltage Identification (VID) Table (Sheet 2 of 2)

HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD

VCC, VSA, VCCD

49 4A 4B 4C 4D 4E 4F 50 51 52 53 54

0.61000 0.61500 0.62000 0.62500 0.63000 0.63500 0.64000 0.64500 0.65000 0.65500 0.66000 0.66500

6C 6D 6E 6F 70 71 72 73 74 75 76 77

0.78500 0.79000 0.79500 0.80000 0.80500 0.81000 0.81500 0.82000 0.82500 0.83000 0.83500 0.84000

8F 90 91 92 93 94 95 96 97 98 99 9A

0.96000 0.96500 0.97000 0.97500 0.98000 0.98500 0.99000 0.99500 1.00000 1.00500 1.01000 1.01500

B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD

1.13500 1.14000 1.14500 1.15000 1.15500 1.16000 1.16500 1.17000 1.17500 1.18000 1.18500 1.19000

D5 D6 D7 D8 D9 DA DB DC DD DE DF E0

1.31000 1.31500 1.32000 1.32500 1.33000 1.33500 1.34000 1.34500 1.35000 1.35500 1.36000 1.36500

F8 F9 FA FB FC FD FE FF

1.48500 1.49000 1.49500 1.50000 1.50500 1.51000 1.51500 1.52000

Notes: 1. 00h = Off State 2. VID Range HEX 01-32 are not used by the processor. 3. For VID Ranges supported see Table 7-11. 4. VCCD is a fixed voltage of 1.35 V or 1.5 V.

7.1.10

Reserved or Unused Signals

All Reserved (RSVD) signals must not be connected. Connection of these signals to VCC, VTTA, VTTD, VCCD, VCCPLL, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 8, Processor Land Listing for a land listing of the processor and the location of all Reserved signals. For reliable operation, always connect unused inputs or bi-directional signals to an appropriate signal level. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs maybe left unconnected; however, this may interfere with some Test Access Port (TAP) functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bi-directional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within 20% of the impedance of the baseboard trace, unless otherwise noted in the appropriate platform design guidelines.

7.2

Signal Group Summary

Signals are grouped by buffer type and similar characteristics as listed in Table 7-5. The buffer type indicates which signaling technology and specifications apply to the signals.

Table 7-4.

Signal Description Buffer Types (Sheet 1 of 2)

Signal Description

Analog Asynchronous1 CMOS

Analog reference or output. May be used as a threshold voltage or for buffer compensation Signal has no timing relationship with any system reference clock. CMOS buffers: 1.05 V or 1.5 V tolerant

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Table 7-4.

Signal Description Buffer Types (Sheet 2 of 2)

Signal Description

DDR3 DMI2 Intel QPI Open Drain CMOS PCI Express*

DDR3 buffers: 1.5 V and 1.35 V tolerant Direct Media Interface Gen 2 signals. These signals are compatible with PCI Express* 2.0 and 1.0 Signaling Environment AC Specifications. Current-mode 6.4 GT/s and 8.0 GT/s forwarded-clock Intel QuickPath Interconnect signaling Open Drain CMOS (ODCMOS) buffers: 1.05 V tolerant PCI Express* interface signals. These signals are compatible with PCI Express* 3.0 Signalling Environment AC Specifications and are AC coupled. The buffers are not 3.3-V tolerant. Refer to the PCIe* specification. Voltage reference signal. Source Series Terminated Logic (JEDEC SSTL_15)

Reference SSTL
Notes:

1.

Qualifier for a buffer type.

Table 7-5.

Signal Groups (Sheet 1 of 3)

Differential/Single Ended DDR3 Reference Clocks2 Buffer Type Signals1

Differential

SSTL Output
2

DDR{0/1/2/3}_CLK_D[N/P][3:0]

DDR3 Command Signals

Single ended

SSTL Output

DDR{0/1/2/3}_BA[2:0] DDR{0/1/2/3}_CAS_N DDR{0/1/2/3}_MA[15:00] DDR{0/1/2/3}_MA_PAR DDR{0/1/2/3}_RAS_N DDR{0/1/2/3}_WE_N DDR_RESET_C{01/23}_N

CMOS1.5v Output
DDR3 Control Signals
2

Single ended

CMOS1.5v Output

DDR{0/1/2/3}_CS_N[9:0] DDR{0/1/2/3}_ODT[5:0] DDR{0/1/2/3}_CKE[5:0] DDR_VREFDQTX_C{01/23} DDR_VREFDQRX_C{01/23} DDR{01/23}_RCOMP[2:0]

Reference Output Reference Input

DDR3 Data Signals2

Differential Single ended

SSTL Input/Output SSTL Input/Output SSTL Input

DDR{0/1/2/3}_DQS_D[N/P][17:00] DDR{0/1/2/3}_DQ[63:00] DDR{0/1/2/3}_ECC[7:0] DDR{0/1/2/3}_PAR_ERR_N

DDR3 Miscellaneous Signals

Single ended

CMOS1.5v Input

DRAM_PWR_OK_C{01/23}

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Table 7-5.

Signal Groups (Sheet 2 of 3)

Differential/Single Ended Buffer Type Signals1

PCI Express* Port 1, 2, & 3 Signals

Differential

PCI Express* Input

PE1A_RX_D[N/P][3:0] PE1B_RX_D[N/P][7:4] PE2A_RX_D[N/P][3:0] PE2B_RX_D[N/P][7:4] PE2C_RX_D[N/P][11:8] PE2D_RX_D[N/P][15:12] PE3A_RX_D[N/P][3:0] PE3B_RX_D[N/P][7:4] PE3C_RX_D[N/P][11:8] PE3D_RX_D[N/P][15:12] PE1A_TX_D[N/P][3:0] PE1B_TX_D[N/P][7:4] PE2A_TX_D[N/P][3:0] PE2B_TX_D[N/P][7:4] PE2C_TX_D[N/P][11:8] PE2D_TX_D[N/P][15:12] PE3A_TX_D[N/P][3:0] PE3B_TX_D[N/P][7:4] PE3C_TX_D[N/P][11:8] PE3D_TX_D[N/P][15:12]

Differential

PCI Express* Output

PCI Express* Miscellaneous Signals

Single ended

Analog Input Reference Input/Output

PE_RBIAS_SENSE PE_RBIAS PE_VREF_CAP

DMI2/PCI Express* Signals

Differential

DMI2 Input DMI2 Output

DMI_RX_D[N/P][3:0] DMI_TX_D[N/P][3:0]

Intel QuickPath Interconnect (QPI) Signals

Differential

Intel QPI Input Intel QPI Output

QPI{0/1}_DRX_D[N/P][19:00] QPI{0/1}_CLKRX_D[N/P] QPI{0/1}_DTX_D[N/P][19:00] QPI{0/1}_CLKTX_D[N/P] QPI_RBIAS_SENSE QPI_RBIAS

Single ended

Analog Input Analog Input/Output

Platform Environmental Control Interface (PECI)

Single ended

PECI

PECI

System Reference Clock (BCLK{0/1})

Differential
SMBus

CMOS1.05v Input

BCLK{0/1}_D[N/P]

Single ended

Open Drain CMOS Input/ Output

DDR_SCL_C{01/23} DDR_SDA_C{01/23} PEHPSCL PEHPSDA

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Table 7-5.

Signal Groups (Sheet 3 of 3)

Differential/Single Ended JTAG & TAP Signals Buffer Type Signals1

Single ended

CMOS1.05V Input CMOS1.05V Input/Output CMOS1.05V Output Open Drain CMOS Input/ Output Open Drain CMOS Output

TCK, TDI, TMS, TRST_N PREQ_N PRDY_N BPM_N[7:0] EAR_N TDO

Serial VID Interface (SVID) Signals

Single ended

CMOS1.05v Input Open Drain CMOS Input/ Output Open Drain CMOS Output

SVIDALERT_N SVIDDATA SVIDCLK

Processor Asynchronous Sideband Signals

Single ended

CMOS1.05v Input

BIST_ENABLE BMCINIT FRMAGENT PWRGOOD PMSYNC RESET_N SAFE_MODE_BOOT SOCKET_ID[1:0] TXT_AGENT TXT_PLTEN CAT_ERR_N CPU_ONLY_RESET MEM_HOT_C{01/23}_N PROCHOT_N ERROR_N[2:0] THERMTRIP_N

Open Drain CMOS Input/ Output

Open Drain CMOS Output

Miscellaneous Signals

N/A

Output

IVT_ID_N SKTOCC_N

Power/Other Signals

Power / Ground Sense Points

VCC, VTTA, VTTD, VCCD_01, VCCD_23,VCCPLL, VSA and VSS VCC_SENSE VSS_VCC_SENSE VSS_VTTD_SENSE VTTD_SENSE VSA_SENSE VSS_VSA_SENSE

Notes:

1. 2.

Refer to Section 6, Signal Descriptions for signal description details. DDR{0/1/2/3} refers to DDR3 Channel 0, DDR3 Channel 1, DDR3 Channel 2 and DDR3 Channel 3.

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Table 7-6.

Signals with On-Die Termination

Signal Name Pull Up /Pull Down Rail Value Units Notes

DDR{0/1}_PAR_ERR_N DDR{2/3}_PAR_ERR_N BMCINIT FRMAGENT TXT_AGENT SAFE_MODE_BOOT SOCKET_ID[1:0] BIST_ENABLE TXT_PLTEN EAR_N

Pull Up Pull Up Pull Down Pull Down Pull Down Pull Down Pull Down Pull Up Pull Up Pull Up

VCCD_01 VCCD_23 VSS VSS VSS VSS VSS VTT VTT VTT

65 65 2K 2K 2K 2K 2K 2K 2K 2K

1 1 1 1 1 1 1 2

Notes: 1. Please refer to the applicable platform design guide to change the default states of these signals. 2. Refer to Table 7-20 for details on the RON (Buffer on Resistance) value for this signal.

7.3

Power-On Configuration (POC) Options

Several configuration options can be configured by hardware. The processor samples its hardware configuration at reset, on the active-to-inactive transition of RESET_N, or upon assertion of PWRGOOD (inactive-to-active transition). For specifics on these options, please refer to Table 7-7. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset transition of the latching signal (RESET_N or PWRGOOD).

Table 7-7.

Power-On Configuration Option Lands

Configuration Option Land Name Notes

Output tri state Execute BIST (Built-In Self Test) Enable Service Processor Boot Mode Enable Intel TXT Platform Power-up Sequence Halt for ITP configuration Enable Bootable Firmware Agent Enable Intel TXT Agent Enable Safe Mode Boot Configure Socket ID

PROCHOT_N BIST_ENABLE BMCINIT TXT_PLTEN EAR_N FRMAGENT TXT_AGENT SAFE_MODE_BOOT SOCKET_ID[1:0]

1 2 3 3 3 3 3 3 3

Notes: 1. Output tri-state option enables Fault Resilient Booting (FRB), for FRB details see Section 7.4. The signal used to latch PROCHOT_N for enabling FRB mode is RESET_N. 2. BIST_ENABLE is sampled at RESET_N de-assertion and CPU_ONLY_RESET de-assertion (on the falling edge). 3. This signal is sampled after PWRGOOD assertion.

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7.4

Fault Resilient Booting (FRB)

The processor supports both socket and core level Fault Resilient Booting (FRB), which provides the ability to boot the system as long as there is one processor functional in the system. One limitation to socket level FRB is that the system cannot boot if the legacy socket that connects to an active PCH becomes unavailable since this is the path to the system BIOS. See Table 7-8 for a list of output tri-state FRB signals. Socket level FRB will tri-state processor outputs via the PROCHOT_N signal. Assertion of the PROCHOT_N signal through RESET_N de-assertion will tri-state processor outputs. Note, that individual core disabling is also supported for those cases where disabling the entire package is not desired. The processor extends the FRB capability to the core granularity by maintaining a register in the uncore so that BIOS or another entity can disable one or more specific processor cores.

Table 7-8.

Fault Resilient Booting (Output Tri-State) Signals

Output Tri-State Signal Groups Signals

Intel QPI

QPI0_CLKTX_DN[1:0] QPI0_CLKTX_DP[1:0] QPI0_DTX_DN[19:00] QPI0_DTX_DP[19:00] QPI1_CLKTX_DN[1:0] QPI1_CLKTX_DP[1:0] QPI1_DTX_DN[19:00] QPI1_DTX_DP[19:00] DDR_SCL_C01 DDR_SDA_C01 DDR_SCL_C23 DDR_SDA_C23 PEHPSCL PEHPSDA TDO CAT_ERR_N ERROR_N[2:0] BPM_N[7:0] PRDY_N THERMTRIP_N PROCHOT_N PECI SVIDCLK

SMBus

JTAG & TAP

Processor Sideband

SVID

7.5

Mixing Processors
Intel supports and validates and four two processor configurations only in which all processors operate with the same Intel QuickPath Interconnect frequency, core frequency, power segment, and have the same internal cache sizes. Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel. Combining processors from different power segments is also not supported.

Note:

Processors within a system must operate at the same frequency per bits [15:8] of the FLEX_RATIO MSR (Address: 194h); however this does not apply to frequency transitions initiated due to thermal events, Extended HALT, Enhanced Intel SpeedStep

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Technology transitions signal. Please refer to the Intel 64 and IA-32 Architectures Software Developers Manual (SDM) Volumes 1, 2, and 3 for details on the FLEX_RATIO MSR and setting the processor core frequency. Not all operating systems can support dual processors with mixed frequencies. Mixing processors of different steppings but the same model (as per CPUID instruction) is supported provided there is no more than one stepping delta between the processors, for example, S and S+1. S and S+1 is defined as mixing of two CPU steppings in the same platform where one CPU is S (stepping) = CPUID.(EAX=01h):EAX[3:0], and the other is S+1 = CPUID.(EAX=01h):EAX[3:0]+1. The stepping ID is found in EAX[3:0] after executing the CPUID instruction with Function 01h. Details regarding the CPUID instruction are provided in the AP-485, Intel Processor Identification and the CPUID Instruction application note. Also refer to the Intel Xeon Processor E5 Prodcut Family Specification Update.

7.6

Flexible Motherboard Guidelines (FMB)

The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the processor will have over certain time periods. The values are only estimates and actual specifications for future processors may differ. Processors may or may not have specifications equal to the FMB value in the foreseeable future. System designers should meet the FMB values to ensure their systems will be compatible with future processors.

7.7

Absolute Maximum and Minimum Ratings

Table 7-9 specifies absolute maximum and minimum ratings. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. Although the processor contains protective circuitry to resist damage from ElectroStatic Discharge (ESD), precautions should always be taken to avoid high static voltages or electric fields.

Table 7-9.

Processor Absolute Minimum and Maximum Ratings

Symbol Parameter Min Max Unit

VCC VCCPLL VCCD VCCD VSA VTTA VTTD

Processor core voltage with respect to Vss Processor PLL voltage with respect to Vss Processor IO supply voltage for DDR3 (standard voltage) with respect to VSS Processor IO supply voltage for DDR3L (low Voltage) with respect to VSS Processor SA voltage with respect to VSS Processor analog IO voltage with respect to VSS

-0.3 -0.3 -0.3 -0.3 -0.3 -0.3

1.4 2.0 1.85 1.7 1.4 1.4

V V V V V V

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Notes: 1. For functional operation, all processor electrical, signal quality, mechanical, and thermal specifications must be satisfied. 2. Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Section 7.9.5. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

7.7.1

Storage Conditions Specifications

Environmental storage condition limits define the temperature and relative humidity limits to which the device is exposed to while being stored in a Moisture Barrier Bag. The specified storage conditions are for component level prior to board attach (see notes in Table 7-10 for post board attach limits). Table 7-10 specifies absolute maximum and minimum storage temperature limits which represent the maximum or minimum device condition beyond which damage, latent or otherwise, may occur. The table also specifies sustained storage temperature, relative humidity, and time-duration limits. These limits specify the maximum or minimum device storage conditions for a sustained period of time. At conditions outside sustained limits, but within absolute maximum and minimum ratings, quality & reliability may be affected.

Table 7-10. Storage Condition Ratings

Symbol Parameter Min Max Unit

Tabsolute storage

The minimum/maximum device storage temperature beyond which damage (latent or otherwise) may occur when subjected to for any length of time. The minimum/maximum device storage temperature for a sustained period of time. The ambient storage temperature (in shipping media) for a short period of time. The maximum device storage relative humidity for a sustained period of time. A prolonged or extended period of time; typically associated with sustained storage conditions Unopened bag, includes 6 months storage time by customer. A short period of time (in shipping media).

-25

125

Tsustained storage Tshort term storage RHsustained storage Timesustained storage

-5 -20

40 85

C C C months

60% @ 24 0 30

Timeshort term storage

72

hours

Notes: 1. Storage conditions are applicable to storage environments only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device. For functional operation, please refer to the processor case temperature specifications. 2. These ratings apply to the Intel component and do not include the tray or packaging. 3. Failure to adhere to this specification can affect the long-term reliability of the processor. 4. Non-operating storage limits post board attach: Storage condition limits for the component once attached to the application board are not specified. Intel does not conduct component level certification assessments post board attach given the multitude of attach methods, socket types and board types used by customers. Provided as general guidance only, Intel board products are specified and certified to meet the following temperature and humidity limits (Non-Operating Temperature Limit: -40C to 70C & Humidity: 50% to 90%, non condensing with a maximum wet bulb of 28C). 5. Device storage temperature qualification methods follow JEDEC High and Low Temperature Storage Life Standards: JESD22-A119 (low temperature) and JESD22-A103 (high temperature).

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7.8

DC Specifications
DC specifications are defined at the processor pads, unless otherwise noted. DC specifications are only valid while meeting specifications for case temperature (TCASE specified in Section 5), clock frequency, and input voltages. Care should be taken to read all notes associated with each specification.

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7.8.1

Voltage and Current Specifications

Table 7-11. Voltage Specification

Symbol Parameter Voltage Plane Min Typ Max Unit Notes1

VCC VID VCC VVID_STEP (Vcc, Vsa, Vccd) VCCPLL VCCD (VCCD_01, VCCD_23) VCCD (VCCD_01. VCCD_23) VTT (VTTA, VTTD) VSA_VID VSA

VCC VID Range Core Voltage (Launch - FMB) VID step size during a transition PLL Voltage I/O Voltage for DDR3 (Standard Voltage) I/O Voltage for DDR3L (Low Voltage) Uncore Voltage (Launch - FMB) Vsa VID Range System Agent Voltage (Launch - FMB) VCCPLL VCCD VCC

0.6

1.35

V V mV

2, 3 3, 4, 7, 8, 12, 14, 18 10

See Table 7-13, Table 7-14 and Figure 7-3, Figure 7-4 5.0

0.955*VCCPLL_TYP 0.95*VCCD_TYP

1.8 1.5

1.045*VCCPLL_TYP 1.05*VCCD_TYP

V V

11, 12, 13, 17 11, 13, 14, 16, 17 11, 13, 14, 16, 17 3, 5, 9, 12, 13 2, 3, 14, 15 3, 6, 12, 14, 19

VCCD

0.95*VCCD_TYP

1.35

1.075*VCCD_TYP

VTT VSA VSA

0.957*VTT_TYP 0.6 VSA_VID - 0.064

1.05 0.965 VSA_VID

1.043*VTT_TYP 1.20 VSA_VID + 0.064

V V V

Notes: 1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on final silicon characterization. 2. Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different settings. 3. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. 4. The VCC voltage specification requirements are measured across the remote sense pin pairs (VCC_SENSE and VSS_VCC_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1M minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe. 5. The VTTA, and VTTD voltage specification requirements are measured across the remote sense pin pairs (VTTD_SENSE and VSS_VTTD_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1M minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe. 6. The VSA voltage specification requirements are measured across the remote sense pin pairs (VSA_SENSE and VSS_VSA_SENSE) on the processor package. Voltage measurement should be taken with a DC to 100 MHz bandwidth oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a 1.5 pF maximum probe capacitance, and 1M minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe. 7. For the 8/6-core processor refer to Table 7-13 and corresponding Figure 7-3. For the 4/2-core processor refer to Table 7-14 and corresponding Figure 7-4.The processor should not be subjected to any static VCC level that exceeds the VCC_MAX associated with any particular current. Failure to adhere to this specification can shorten processor lifetime. 8. Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE) shown in Section 5, Thermal Management Specifications. ICC_MAX is specified at the relative VCC_MAX point on the VCC load line. The processor is capable of drawing ICC_MAX for up to 5 seconds. Refer to Figure 7-5 for further details on the average processor current draw over various time durations. 9. The processor should not be subjected to any static VTTA, VTTD level that exceeds the VTT_MAX associated with any particular current. Failure to adhere to this specification can shorten processor lifetime. 10. This specification represents the VCC reduction or VCC increase due to each VID transition, see Section 7.1.9.3, Voltage Identification (VID). 11. Baseboard bandwidth is limited to 20 MHz. 12. FMB is the flexible motherboard guidelines. See Section 7.6 for FMB details. 13. DC + AC + Ripple = Total Tolerance 14. For Power State Functions see Section 7.1.9.3.5. 15. VSA_VID does not have a loadline, the output voltage is expected to be the VID value.

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16. VCCD tolerance at processor pins. Tolerance for VR at remote sense is 3.3%*VCCD. 17. The VCCPLL, VCCD01, VCCD23 voltage specification requirements are measured across vias on the platform. Choose VCCPLL, VCCD01, or VCCD23 vias close to the socket and measure with a DC to 100 MHz bandwidth oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using 1.5 pF maximum probe capacitance, and 1M minimum impedance. The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe. 18. VCC has a Vboot setting of 0.0 V and is not included in the PWRGOOD indication. Refer to the VR12/IMVP7 Pulse Width Modulation Specification. 19. VSA has a Vboot setting of 0.9 V. Refer to the VR12/IMVP7 Pulse Width Modulation Specification.

Table 7-12. Processor Current Specifications

Parameter Symbol and Definition Processor TDP / Core Count TDC (A) Max (A) Notes1

ITT I/O Termination Supply, Processor Current on VTTA/VTTD ISA System Agent Supply, Processor Current on VSA ICCD_01 DDR3 Supply, Processor Current VCCD_01 ICCD_23 DDR3 Supply, Processor Current VCCD_23 ICCPLL PLL Supply, Processor Current on VCCPLL ICCD_01_S3 ICCD_23_S3 DDR3 Supply, Processor Current on VCCD_01/VCCD_23 in System S3 Standby State
8-core/6-core

20

24

2, 3, 5, 6

20

24

All Intel Xeon processor E5-1600/E52600/E5-4600 product families

--

150 W 8-core 135 W 8-core 130 W 6-core, 6-core 1S WS and 8-core 115 W 8-core

155

185

2, 5, 6

135

165

ICC Core Supply, Processor Current on VCC

95 W 6-core, 8-core and LV95W-8C 70 W 8-core and LV70W-8C 60 W 6-core

4-core/2-core

115 80 70

135 100 85

130 W 4-core and 4-core 1S WS 95 W 4-core 80 W 2-core and 4-core

115 115 80

150 135 100

2, 5, 6

Notes: 1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on final silicon characterization. 2. Launch to FMB, this is the flexible motherboard guidelines. See Section 7.6 for FMB details. 3. ICC_TDC (Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and should be used for the voltage regulator thermal assessment. The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion. Please refer to the VR12/IMVP7 Pulse Width Modulation Specification for further details. 4. Specification is at TCASE = 50C. Characterized by design (not tested). 5. ICCD_01_MAX and ICCD_23_MAX refers only to the processors current draw and does not account for the current consumption by the memory devices. 6. Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE) shown in Section 5, Thermal Management Specifications. ICC_MAX is specified at the relative VCC_MAX point on the VCC load line. The processor is

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capable of drawing ICC_MAX for up to 5 seconds. Refer to Figure 7-5 for further details on the average processor current draw over various time durations.

Table 7-13. 8/6 Core: Processor VCC Static and Transient Tolerance
ICC (A) VCC_MAX (V) VCC_TYP (V) VCC_MIN (V) Notes

0 5 10 15 19 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175 180 185

VID + 0.015 VID + 0.011 VID + 0.007 VID + 0.003 VID + 0.000 VID - 0.005 VID - 0.009 VID - 0.013 VID - 0.017 VID - 0.021 VID - 0.025 VID - 0.029 VID - 0.033 VID - 0.037 VID - 0.041 VID - 0.045 VID - 0.049 VID - 0.053 VID - 0.057 VID - 0.061 VID - 0.065 VID - 0.069 VID - 0.073 VID - 0.077 VID - 0.081 VID - 0.085 VID - 0.089 VID - 0.093 VID - 0.097 VID - 0.101 VID - 0.105 VID - 0.109 VID - 0.113 VID - 0.117 VID - 0.121 VID - 0.125 VID - 0.129 VID - 0.133

VID - 0.000 VID - 0.004 VID - 0.008 VID - 0.012 VID - 0.015 VID - 0.020 VID - 0.024 VID - 0.028 VID - 0.032 VID - 0.036 VID - 0.040 VID - 0.044 VID - 0.048 VID - 0.052 VID - 0.056 VID - 0.060 VID - 0.064 VID - 0.068 VID - 0.072 VID - 0.076 VID - 0.080 VID - 0.084 VID - 0.088 VID - 0.092 VID - 0.096 VID - 0.100 VID - 0.104 VID - 0.108 VID - 0.112 VID - 0.116 VID - 0.120 VID - 0.124 VID - 0.128 VID - 0.132 VID - 0.136 VID - 0.140 VID - 0.144 VID - 0.148

VID - 0.015 VID - 0.019 VID - 0.023 VID - 0.027 VID - 0.030 VID - 0.035 VID - 0.039 VID - 0.043 VID - 0.047 VID - 0.051 VID - 0.055 VID - 0.059 VID - 0.063 VID - 0.067 VID - 0.071 VID - 0.075 VID - 0.079 VID - 0.083 VID - 0.087 VID - 0.091 VID - 0.095 VID - 0.099 VID - 0.103 VID - 0.107 VID - 0.111 VID - 0.115 VID - 0.119 VID - 0.123 VID - 0.127 VID - 0.131 VID - 0.135 VID - 0.139 VID - 0.143 VID - 0.147 VID - 0.151 VID - 0.155 VID - 0.159 VID - 0.163

1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6

Notes: 1. The loadline specification includes both static and transient limits.

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Electrical Specifications

2. 3.

4. 5. 6.

This table is intended to aid in reading discrete points on graph in Figure 7-3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_VCC_SENSE lands. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and VSS_VCC_SENSE lands. Refer to the VR12/IMVP7 Pulse Width Modulation Specification for loadline guidelines and VR implementation details. The Vcc_min and Vcc_max loadlines represent static and transient limits. Please see Section 6 for Vcc Overshoot specifications. The Adaptive Loadline Positioning slope is 0.8 m. The 8/6-core Icc ranges are as follows: 0-185 A for 150 W processor 0-165 A for 135 W, 130 W, 115 W processors 0-135 A for 95 W, LV95W-8C processors 0-100 A for 70 W, LV70W-8C processors 0-85 A for 60 W processors

Figure 7-3.

8/6-Core: VCC Static and Transient Tolerance Loadlines

Table 7-14. 4/2-Core: Processor VCC Static and Transient Tolerance (Sheet 1 of 2)
ICC (A) VCC_MAX (V) VCC_TYP (V) VCC_MIN (V) Notes

0 5 10 15 19 25 30 35 40 45 50 55

VID + 0.015 VID + 0.011 VID + 0.007 VID + 0.003 VID + 0.000 VID - 0.005 VID - 0.009 VID - 0.013 VID - 0.017 VID - 0.021 VID - 0.025 VID - 0.029

VID - 0.000 VID - 0.004 VID - 0.008 VID - 0.012 VID - 0.015 VID - 0.020 VID - 0.024 VID - 0.028 VID - 0.032 VID - 0.036 VID - 0.040 VID - 0.044

VID - 0.015 VID - 0.019 VID - 0.023 VID - 0.027 VID - 0.030 VID - 0.035 VID - 0.039 VID - 0.043 VID - 0.047 VID - 0.051 VID - 0.055 VID - 0.059

1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6

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Table 7-14. 4/2-Core: Processor VCC Static and Transient Tolerance (Sheet 2 of 2)
ICC (A) VCC_MAX (V) VCC_TYP (V) VCC_MIN (V) Notes

60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150

VID - 0.033 VID - 0.037 VID - 0.041 VID - 0.045 VID - 0.049 VID - 0.053 VID - 0.057 VID - 0.061 VID - 0.065 VID - 0.069 VID - 0.073 VID - 0.077 VID - 0.081 VID - 0.085 VID - 0.089 VID - 0.093 VID - 0.097 VID - 0.101 VID - 0.105

VID - 0.048 VID - 0.052 VID - 0.056 VID - 0.060 VID - 0.064 VID - 0.068 VID - 0.072 VID - 0.076 VID - 0.080 VID - 0.084 VID - 0.088 VID - 0.092 VID - 0.096 VID - 0.100 VID - 0.104 VID - 0.108 VID - 0.112 VID - 0.116 VID - 0.120

VID - 0.063 VID - 0.067 VID - 0.071 VID - 0.075 VID - 0.079 VID - 0.083 VID - 0.087 VID - 0.091 VID - 0.095 VID - 0.099 VID - 0.103 VID - 0.107 VID - 0.111 VID - 0.115 VID - 0.119 VID - 0.123 VID - 0.127 VID - 0.131 VID - 0.135

1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6 1,2,3,4,5,6

Notes: 1. The loadline specification includes both static and transient limits. 2. This table is intended to aid in reading discrete points on graph in Figure 7-4. 3. The loadlines specify voltage limits at the die measured at the Vcc_sense and Vss_Vcc_sense lands. Voltage regulation feedback for voltage regulator circuits must also be taken from processor Vcc_sense and Vss_Vcc_sense lands. Refer to the VR12/IMVP7 Pulse Width Modulation Specification for loadline guidelines and VR implementation details. 4. The Vcc_min and Vcc_max loadlines represent static and transient limits. Please see Section 7.8.2.1, VCC Overshoot Specifications. 5. The Adaptive Loadline Positioning slope is 0.8 m. 6. The 4/2-core Icc ranges are as follows: 0-150 A for 130 W processor 0-135 A for 95 W processor 0-100 A for 80 W processor

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Electrical Specifications

Figure 7-4.

4/2-Core: Processor VCC Static and Transient Tolerance Loadlines

Icc [A] 0 -VID - 0.020 VID + 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

VID VID+- 0.000 0.000

VID - 0.020

VCC Maximum

VID - 0.040

VID - 0.060

Vcc [V]

VID - 0.080 VCC Typical

VID - 0.100

VID - 0.120 VCC Minimum VID - 0.140

VID - 0.160

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7.8.2

Die Voltage Validation

Core voltage (VCC) overshoot events at the processor must meet the specifications in Table 7-15 when measured across the VCC_SENSE and VSS_VCC_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope.

Figure 7-5.

Load Current Versus Time

Notes: 1. The peak current for any 5 second sample does not exceed Icc_max. 2. The average current for any 10 second sample does not exceed the Y value at 10 seconds. 3. The average current for any 20 second period or greater does not exceed Icc_tdc. 4. Turbo performance may be impacted by failing to meet durations specified in this graph. Ensure that the platform design can handle peak and average current based on the specification. 5. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 6. Not 100% tested. Specified by design characterization.

7.8.2.1

VCC Overshoot Specifications

The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high-to-low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_VCC_SENSE lands.

Table 7-15. VCC Overshoot Specifications (Sheet 1 of 2)

Symbol Parameter Min Max Units Figure Notes

VOS_MAX

Magnitude of VCC overshoot above VID

65

mV

7-6

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Table 7-15. VCC Overshoot Specifications (Sheet 2 of 2)

Symbol Parameter Min Max Units s Figure Notes

TOS_MAX

Time duration of VCC overshoot above VccMAX value at the new lighter load

25

7-6

Figure 7-6.

VCC Overshoot Example Waveform

VID + VOS_MAX

VOS_MAX

Voltage [V]

VccMAX (I1) TOS_MAX

10

15

20

25

30

Time [us]
Notes: 1. VOS_MAX is the measured overshoot voltage. 2. TOS_MAX is the measured time duration above VccMAX(I1). 3. Istep: Load Release Current Step, for example, I2 to I1, where I2 > I1. 4. VccMAX(I1) = VID - I1*RLL + 15 mV

7.8.3

Signal DC Specifications
DC specifications are defined at the processor pads, unless otherwise noted. DC specifications are only valid while meeting specifications for case temperature (TCASE specified in Section 5, Thermal Management Specifications), clock frequency, and input voltages. Care should be taken to read all notes associated with each specification.

Table 7-16. DDR3 and DDR3L Signal DC Specifications (Sheet 1 of 2)

Symbol Parameter Min Typ Max Units Notes1

IIL
Data Signals

Input Leakage Current

-500

+500

uA

10

VIL VIH RON Data ODT PAR_ERR_N ODT

Input Low Voltage Input High Voltage DDR3 Data Buffer On Resistance On-Die Termination for Data Signals On-Die Termination for Parity Error Signals 0.57*VCCD 21 45 90 59

0.43*VCC
D

V V

2, 3 2, 4, 5 6 8

31 55 110 72

Reference Clock Signals, Command, and Data Signals

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Table 7-16. DDR3 and DDR3L Signal DC Specifications (Sheet 2 of 2)

Symbol Parameter Min Typ Max Units Notes1

VOL VOH

Output Low Voltage Output High Voltage

(VCCD/ 2)* (RON /(RON+RVTT_TERM)) VCCD- ((VCCD / 2)* (RON/ (RON+RVTT_TERM))

V V

2, 7 2, 5, 7

Reference Clock Signal

RON

DDR3 Clock Buffer On Resistance

21

31

Command Signals

RON RON VOL_CMOS1.5v VOH_CMOS1.5v IIL_CMOS1.5v

Control Signals

DDR3 Command Buffer On Resistance DDR3 Reset Buffer On Resistance Output Low Voltage, Signals DDR_RESET_ C{01/23}_N Output High Voltage, Signals DDR_RESET_ C{01/23}_N Input Leakage Current

16 25

24 75 0.2*VCCD

6 6 1,2 1,2 1,2

V V

0.9*VCCD -100 +100

RON

DDR3 Control Buffer On Resistance

21 128.7 25.839 198 128.7 25.839 198 130 26.1 200 130 26.1 200

31 131.3 26.361 202 131.3 26.361 202

6 9,12 9,12 9,12 9,12 9,12 9,12

DDR01_RCOMP[0 COMP Resistance ] DDR01_RCOMP[1 COMP Resistance ] DDR01_RCOMP[2 COMP Resistance ] DDR23_RCOMP[0 COMP Resistance ] DDR23_RCOMP[1 COMP Resistance ] DDR23_RCOMP[2 COMP Resistance ]
DDR3 Miscellaneous Signals

VIL VIH

Input Low Voltage DRAM_PWR_OK_C{01/23} Input High Voltage DRAM_PWR_OK_C{01/23} 0.55*VCC D + 0.3

0.55*VCC D - 0.2

V V

2, 3, 11, 13 2, 4, 5, 11, 13

Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The voltage rail VCCD which will be set to 1.50 V or 1.35 V nominal depending on the voltage of all DIMMs connected to the processor. 3. VIL is the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 4. VIH is the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 5. VIH and VOH may experience excursions above VCCD. However, input signal drivers must comply with the signal quality specifications. Refer to Section 7.9. 6. This is the pull down driver resistance. Refer to processor signal integrity models for I/V characteristics. Reset drive does not have a termination. 7. RVTT_TERM is the termination on the DIMM and not controlled by the processor. Please refer to the applicable DIMM datasheet. 8. The minimum and maximum values for these signals are programmable by BIOS to one of the pairs. 9. COMP resistance must be provided on the system board with 1% resistors. See the applicable platform design guide for implementation details. DDR01_RCOMP[2:0] and DDR23_RCOMP[2:0] resistors are terminated to VSS. 10. Input leakage current is specified for all DDR3 signals. 11. DRAM_PWR_OK_C{01/23} must have a maximum of 30 ns rise or fall time over VCCD * 0.55 +300 mV and -200 mV and the edge must be monotonic. 12. The DDR01/23_RCOMP error tolerance is 15% from the compensated value.

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13. DRAM_PWR_OK_C{01/23}: Data Scrambling must be enabled for production environments. Disabling Data scrambling may be used for debug and testing purposes only. Operating systems with Data Scrambling off will make the configuration out of specification.

Table 7-17. PECI DC Specifications

Symbol Definition and Conditions Min Max Units Figure Notes1

VIn VHysteresis VN VP ISOURCE ILeak+ CBus VNoise

Input Voltage Range Hysteresis Negative-edge threshold voltage Positive-edge threshold voltage High level output source VOH = 0.75 * VTT High impedance state leakage to VTTD (Vleak = VOL) Bus capacitance per node Signal noise immunity above 300 MHz

-0.150 0.100 * VTT 0.275 * VTT 0.550 * VTT -6.0

VTT

V V

0.500 * VTT 0.725 * VTT

V V mA

7-1 7-1

2 2

50 N/A 0.100 * VTT

200 10 N/A

A pF Vp-p

3 4,5

Notes: 1. VTTD supplies the PECI interface. PECI behavior does not affect VTTD min/max specification 2. It is expected that the PECI driver will take into account, the variance in the receiver input thresholds and consequently, be able to drive its output within safe limits (-0.150 V to 0.275*VTTD for the low level and 0.725*VTTD to VTTD+0.150 V for the high level). 3. The leakage specification applies to powered devices on the PECI bus. 4. One node is counted for each client and one node for the system host. Extended trace lengths might appear as additional nodes. 5. Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently limit the maximum bit rate at which the interface can operate.

Table 7-18. System Reference Clock (BCLK{0/1}) DC Specifications

Symbol Parameter Signal Min Max

Unit
V V V

Figure
7-8 7-8 7-7 7-9 7-7 7-10

Notes1

VBCLK_diff_ih VBCLK_diff_il Vcross (abs) Vcross(rel)

Differential Input High Voltage Differential Input Low Voltage Absolute Crossing Point Relative Crossing Point

Differential Differential Single Ended Single Ended

0.150

N/A -0.150

0.250 0.250 + 0.5*(VHavg 0.700) N/A Vcross - 0.1

0.550 0.550 + 0.5*(VHavg 0.700) 0.140 Vcross + 0.1 1.50

2, 4, 7

V V V
A

3, 4, 5 6

Vcross
VTH IIL Cpad

Range of Crossing Points Threshold Voltage Input Leakage Current Pad Capacitance

Single Ended Single Ended N/A N/A

0.9

1.1

pF

Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. These specifications are specified at the processor pad. 2. Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK{0/1}_DN is equal to the falling edge of BCLK{0/1}_DP. 3. VHavg is the statistical average of the VH measured by the oscilloscope. 4. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 5. VHavg can be measured directly using Vtop on Agilent* and High on Tektronix oscilloscopes. 6. VCROSS is defined as the total variation of all crossing voltages as defined in Note 3. 7. The rising edge of BCLK{0/1}_DN is equal to the falling edge of BCLK{0/1}_DP. 8. For Vin between 0 and Vih.

Table 7-19. SMBus DC Specifications (Sheet 1 of 2)

Symbol Parameter Min Max Units Notes

VIL

Input Low Voltage

0.3*VTT

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Table 7-19. SMBus DC Specifications (Sheet 2 of 2)

Symbol Parameter Min Max Units Notes

VIH VOL VOH RON IL

Input High Voltage Output Low Voltage Output High Voltage Buffer On Resistance Leakage Current Signals DDR_SCL_C{01/23}, DDR_SDA_C{01/ 23} Leakage Current Signals PEHPSCL, PEHPSDA

0.7*VTT 0.2*VTT VTT(max) 14 -100 +100

V V V
A

IL

+900

Table 7-20. JTAG and TAP Signals DC Specifications

Symbol Parameter Min Max Units Notes

VIL VIH VOL VOH RON IIL IIL

Input Low Voltage Input High Voltage Output Low Voltage (RTEST = 500 ohm) Output High Voltage (RTEST = 500 ohm) Buffer On Resistance Signals BPM_N[7:0], TDO, EAR_N Input Leakage Current Signals PREQ_N, TCK, TDI, TMS, TRST_N Input Leakage Current Signals BPM_N[7:0], TDO, EAR_N (RTEST = 50 ohm) Output Current Signal PRDY_N (RTEST = 500 ohm) Input Edge Rate Signals: BPM_N[7:0], EAR_N, PREQ_N, TCK, TDI, TMS, TRST_N -1.50 -50 0.88*VTT 0.7*VTT

0.3*VTT

V V

0.12*VTT

V V

14 +50

+900

IO

+1.50

mA

0.05

V/ns

1, 2

Note: 1. These signals are measured between VIL and VIH. 2. The signal edge rate must be met or the signal must transition monotonically to the asserted state.

Table 7-21. Serial VID Interface (SVID) DC Specifications (Sheet 1 of 2)

Symbol Parameter Min Typ Max Units Notes

VTT VIL VIH VOH

CPU I/O Voltage Input Low Voltage Signals SVIDDATA, SVIDALERT_N Input High Voltage Signals SVIDDATA, SVIDALERT_N Output High Voltage Signals SVIDCLK, SVIDDATA

VTT - 3%

1.05

VTT + 3% 0.3*VTT

V V V 1 1 1

0.7*VTT VTT(max)

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Table 7-21. Serial VID Interface (SVID) DC Specifications (Sheet 2 of 2)

Symbol Parameter Min Typ Max Units A A Notes

RON IIL IIL

Buffer On Resistance Signals SVIDCLK, SVIDDATA Input Leakage Current Signals SVIDCLK, SVIDDATA Input Leakage Current Signal SVIDALERT_N

14 900 500

2 3,4 3,4

Notes: 1. VTT refers to instantaneous VTT. 2. Measured at 0.31*VTT 3. Vin between 0V and VTT 4. Refer to the appropriate Platform Design Guide (PDG) for routing design guidelines.

Table 7-22. Processor Asynchronous Sideband DC Specifications

Symbol Parameter Min Max Units Notes

Input Edge Rate Signals: CAT_ERR_N, MEM_HOT_C{01/23}_N, PMSYNC, PROCHOT_N, PWRGOOD, RESET_N
CMOS1.05v Signals

0.05

V/ns

4,5

VIL_CMOS1.05v VIH_CMOS1.05v VIL_MAX VIH_MIN VOL_CMOS1.05v VOH_CMOS1.05v IIL_CMOS1.05v IO_CMOS1.05v ANM_Rise ANM_Fall

Input Low Voltage Input High Voltage Input Low Voltage Signal PWRGOOD Input High Voltage Signal PWRGOOD Output Low Voltage Output High Voltage Input Leakage Current Output Current (RTEST = 500 ohm) Non-Monotonicity Amplitude, Rising Edge Signal PWRGOOD Non-Monotonicity Amplitude, Falling Edge Signal PWRGOOD 0.88*VTT 0.640 0.7*VTT

0.3*VTT

V V

1,2 1,2 1,2,5, 1,2,5 1,2 1,2 1,2 1,2 5 5

0.320

V V

0.12*VTT

V V

50 1.50 0.135 0.165

mA mA V V

Open Drain CMOS (ODCMOS) Signals

VIL_ODCMOS VIH_ODCMOS VOH_ODCMOS

Input Low Voltage Input High Voltage Output High Voltage Signals: CAT_ERR_N, ERROR_N[2:0], THERMTRIP_N, PROCHOT_N, CPU_ONLY_RESET Output Leakage Current, Signal MEM_HOT_C{01/23}_N Output Leakage Current (RTEST = 50 ohm) Buffer On Resistance Signals: CAT_ERR_N, CPU_ONLY_RESET, ERROR_N[2:0], MEM_HOT_C{01/23}_N, PROCHOT_N, THERMTRIP_N 0.7*VTT

0.3*VTT

V V

1,2 1,2 1,2

VTT(max)

IOL IOL RON

100 900

mA mA

3 3

14

1,2

Notes:

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1. 2. 3. 4. 5. 6.

These specifications This table applies to the processor sideband and miscellaneous signals specified in Table 7-5. Unless otherwise noted, all specifications in this table apply to all processor frequencies. For Vin between 0 and Voh.For Vin between 0 and Voh. PWRGOOD Non Monotonicity duration (TNM) time is maximum 1.3 ns. These are measured between VIL and VIH. If the edge rate specification is not met, make sure there is a monotonic edge and the edge rate is not lower than the edge rate specification for the monotonic edges. The monotonic input edge rate is 0.02 V/ns. The waveform could be non-monotonic when measured at the land (near the socket at the bottom side of via) but not when observed at the pad during simulation. The waveform measured at the land could violate specifications defined at the pad. Customers could measure the land timings on their boards and then use the package length information found in the Model Usage Guidelines (MUG) which comes with the I/O model to correlate the results to the specification at the pad.

Table 7-23. Miscellaneous Signals DC Specifications

Symbol IVT_ID_N Signal Parameter Min Typical Max Units Notes

VO_ABS_MAX IO
SKTOCC_N Signal

Output Absolute Max Voltage Output Current

1.10

1.80 0

V
A

1 1, 3

VO_ABS_MAX IOMAX

Output Absolute Max Voltage Output Max Current

3.30

3.50 1

V mA

1 2

Notes: 1. For specific routing guidelines, see the appropriate Platform Design Guide (PDG) for details. 2. See the appropriate Platform Design Guide (PDG) for details. 3. IVT_ID_N land is a no connect on die.

7.8.3.1

PCI Express* DC Specifications

The processor DC specifications for the PCI Express* are available in the PCI Express Base Specification - Revision 3.0. This document will provide only the processor exceptions to the PCI Express Base Specification - Revision 3.0.

7.8.3.2

DMI2/PCI Express* DC Specifications

The processor DC specifications for the DMI2/PCI Express* are available in the PCI Express Base Specification 2.0 and 1.0. This document will provide only the processor exceptions to the PCI Express Base Specification 2.0 and 1.0.

7.8.3.3

Intel QuickPath Interconnect DC Specifications

Intel QuickPath Interconnect specifications are defined at the processor lands. Please refer to the appropriate platform design guidelines for specific implementation details. In most cases, termination resistors are not required as these are integrated into the processor silicon.

7.8.3.4

Reset and Miscellaneous Signal DC Specifications

For a power-on Reset, RESET_N must stay active for at least 3.5 millisecond after VCC and BCLK{0/1} have reached their proper specifications. RESET_N must not be kept asserted for more than 100 ms while PWRGOOD is asserted. RESET_N must be held asserted for at least 3.5 millisecond before it is deasserted again. RESET_N must be held asserted before PWRGOOD is asserted. This signal does not have on-die termination and must be terminated on the system board.

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Figure 7-7.

BCLK{0/1} Differential Clock Crosspoint Specification

650 600

Crossing Point (mV)

550 500 450 400 350 300 250

550 mV 550 + 0.5 (VHavg - 700)

250 + 0.5 (VHavg - 700)

250 mV

200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850

VHavg (mV)

Figure 7-8.

BCLK{0/1} Differential Clock Measurement Point for Ringback

T STABLE

VRB-Differential

VIH = +150 mV VRB = +100 mV 0.0V VRB = -100 mV VIL = -150 mV REFCLK +

T STABLE

VRB-Differential

Figure 7-9.

BCLK{0/1} Single Ended Clock Measurement Points for Absolute Cross Point and Swing

VMAX = 1.40V BCLK_DN VCROSS MAX = 550mV VCROSS MIN = 250mV BCLK_DP VMIN = -0.30V

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Figure 7-10. BCLK{0/1} Single Ended Clock Measurement Points for Delta Cross Point

BCLK_DN

VCROSS DELTA = 140 m V

BCLK_DP

7.9

Signal Quality
Data transfer requires the clean reception of data signals and clock signals. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swings will adversely affect system timings. Ringback and signal non-monotonicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines. Excessive signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can cause device failure if absolute voltage limits are exceeded. Overshoot and undershoot can also cause timing degradation due to the build up of inter-symbol interference (ISI) effects. For these reasons, it is crucial that the designer work towards a solution that provides acceptable signal quality across all systematic variations encountered in volume manufacturing. This section documents signal quality metrics used to derive topology and routing guidelines through simulation. All specifications are specified at the processor die (pad measurements). Specifications for signal quality are for measurements at the processor core only and are only observable through simulation. Therefore, proper simulation is the only way to verify proper timing and signal quality.

7.9.1

DDR3 Signal Quality Specifications

Various scenarios for the DDR3 Signals have been simulated to generate a set of layout guidelines which are available in the appropriate Platform Design Guide (PDG). Overshoot (or undershoot) is the absolute value of the maximum voltage above or below VSS. The overshoot/undershoot specifications limit transitions beyond specified maximum voltages or VSS due to the fast signal edge rates. The processor can be damaged by single and/or repeated overshoot or undershoot events on any input, output, or I/O buffer if the charge is large enough (i.e., if the over/undershoot is great enough). Baseboard designs which meet signal integrity and timing requirements and which do not exceed the maximum overshoot or undershoot limits listed in Table 7-24 will insure reliable IO performance for the lifetime of the processor.

7.9.2

I/O Signal Quality Specifications

Signal Quality specifications for PCIe* Signals are included as part of the PCIe* DC specifications. Various scenarios have been simulated to generate a set of layout guidelines which are available in the appropriate Platform Design Guide (PDG).

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7.9.3

Intel QuickPath Interconnect Signal Quality Specifications

Signal Quality specifications for Differential Intel QuickPath Interconnect Signals are included as part of the Intel QuickPath Interconnect signal quality specifications. Various scenarios have been simulated to generate a set of layout guidelines which are available in the appropriate Platform Design Guide (PDG).

7.9.4

Input Reference Clock Signal Quality Specifications

Overshoot/Undershoot and Ringback specifications for BCLK{0/1}_D[N/P] are found in Table 7-24. Overshoot/Undershoot and Ringback specifications for the DDR3 Reference Clocks are specified by the DIMM.

7.9.5

Overshoot/Undershoot Tolerance
Overshoot (or undershoot) is the absolute value of the maximum voltage above or below VSS, see Figure 7-11. The overshoot/undershoot specifications limit transitions beyond VCCD or VSS due to the fast signal edge rates. The processor can be damaged by single and/or repeated overshoot or undershoot events on any input, output, or I/O buffer if the charge is large enough (that is, if the over/undershoot is great enough). Determining the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse direction, and the activity factor (AF). Permanent damage to the processor is the likely result of excessive overshoot/undershoot. Baseboard designs which meet signal integrity and timing requirements and which do not exceed the maximum overshoot or undershoot limits listed in Table 7-24 will insure reliable IO performance for the lifetime of the processor.

Table 7-24. Processor I/O Overshoot/Undershoot Specifications

Signal Group Minimum Undershoot Maximum Overshoot Overshoot Duration Undershoot Duration Notes

Intel QuickPath Interconnect DDR3 System Reference Clock (BCLK{0/1}) PWRGOOD Signal

-0.2 * VTT -0.2 * VCCD -0.3V -0.420V

1.2 * VTT 1.2 * VCCD 1.15V VTT + 0.28

39 ps 0.25*TCH N/A N/A

15 ps 0.1*TCH N/A N/A

1,2 1,2,3 1,2 4

Notes: 1. These specifications are measured at the processor pad. 2. Refer to Figure 7-11 for description of allowable Overshoot/Undershoot magnitude and duration. 3. TCH is the minimum high pulse width duration. 4. For PWRGOOD DC specifications see Table 7-22.

7.9.5.1

Overshoot/Undershoot Magnitude
Overshoot/Undershoot magnitude describes the maximum potential difference between a signal and its voltage reference level. For the processor, both overshoot and undershoot magnitude are referenced to VSS. It is important to note that the overshoot and undershoot conditions are separate and their impact must be determined independently. The pulse magnitude and duration, and activity factor must be used to determine if the overshoot/undershoot pulse is within specifications.

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7.9.5.2

Overshoot/Undershoot Pulse Duration

Overshoot/undershoot pulse duration describes the total amount of time that an overshoot/undershoot event exceeds the overshoot/undershoot reference voltage. The total time could encompass several oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration.

Note:

Oscillations below the reference voltage cannot be subtracted from the total overshoot/ undershoot pulse duration.

7.9.5.3

Activity Factor
Activity factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. Since the highest frequency of assertion of any common clock signal is every other clock, an AF = 0.1 indicates that the specific overshoot (or undershoot) waveform occurs every other clock cycle. The specification provided in the table shows the maximum pulse duration allowed for a given overshoot/undershoot magnitude at a specific activity factor. Each table entry is independent of all others, meaning that the pulse duration reflects the existence of overshoot/undershoot events of that magnitude ONLY. A platform with an overshoot/ undershoot that just meets the pulse duration for a specific magnitude where the AF < 0.1, means that there can be no other overshoot/undershoot events, even of lesser magnitude (note that if AF = 0.1, then the event occurs at all times and no other events can occur).

7.9.5.4

Reading Overshoot/Undershoot Specification Tables

The overshoot/undershoot specification for the processor is not a simple single value. Instead, many factors are needed to determine the over/undershoot specification. In addition to the magnitude of the overshoot, the following parameters must also be known: the width of the overshoot and the activity factor (AF). To determine the allowed overshoot for a particular overshoot event, the following must be done: 1. Determine the signal group a particular signal falls into. 2. Determine the magnitude of the overshoot or the undershoot (relative to VSS). 3. Determine the activity factor (How often does this overshoot occur?). 4. Next, from the appropriate specification table, determine the maximum pulse duration (in nanoseconds) allowed. 5. Compare the specified maximum pulse duration to the signal being measured. If the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications. Undershoot events must be analyzed separately from overshoot events as they are mutually exclusive.

7.9.5.5

Determining if a System Meets the Overshoot/Undershoot Specifications

The overshoot/undershoot specifications listed in the table specify the allowable overshoot/undershoot for a single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that each have their own set of parameters (duration, AF and magnitude). While each overshoot on its own may meet

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the overshoot specification, when you add the total impact of all overshoot events, the system may fail. A guideline to ensure a system passes the overshoot and undershoot specifications is shown below. 1. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot specifications in the following tables, OR 2. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse duration for each magnitude and compare the results against the AF = 0.1 specifications. If all of these worst case overshoot or undershoot events meet the specifications (measured time < specifications) in the table (where AF= 0.1), then the system passes. Table 7-25. Processor Sideband Signal Group Overshoot/Undershoot Tolerance
Absolute Maximum Overshoot Absolute Maximum Undershoot (V) (V) Pulse Duration (ns) AF=0.1 Pulse Duration (ns) AF=0.01

1.3335 V 1.2600 V

0.2835 V 0.210 V

3 ns 5 ns

5 ns 5 ns

Figure 7-11. Maximum Acceptable Overshoot/Undershoot Waveform

Over Shoot

Over Shoot Duration Under Shoot Duration

VSS Under Shoot

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Processor Land Listing

Processor Land Listing

This chapter provides sorted land list in Section 8.1 and Section 8.2. Table 8-1 is a listing of all processor lands ordered alphabetically by land name. Table 8-2 is a listing of all processor lands ordered by land number.

8.1
Table 8-1.
Land Name

Listing by Land Name

Land Name (Sheet 1 of 49)
Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 2 of 49)

Land No. Buffer Type Direction

BCLK0_DN BCLK0_DP BCLK1_DN BCLK1_DP BIST_ENABLE BMCINIT BPM_N[0] BPM_N[1] BPM_N[2] BPM_N[3] BPM_N[4] BPM_N[5] BPM_N[6] BPM_N[7] CAT_ERR_N CPU_ONLY_RESET DDR_RESET_C01_N DDR_RESET_C23_N DDR_SCL_C01 DDR_SCL_C23 DDR_SDA_C01 DDR_SDA_C23 DDR_VREFDQRX_C01 DDR_VREFDQRX_C23 DDR_VREFDQTX_C01 DDR_VREFDQTX_C23 DDR0_BA[0] DDR0_BA[1] DDR0_BA[2] DDR0_CAS_N DDR0_CKE[0] DDR0_CKE[1]

CM44 CN43 BA45 AW45 AT48 AL47 AR43 AT44 AU43 AV44 BB44 AW43 BA43 AY44 CC51 AN43 CB18 AE27 CY42 U43 CW41 R43 BY16 J1 CN41 P42 CM28 CN27 CM20 CL29 CL19 CM18

CMOS CMOS CMOS CMOS CMOS CMOS ODCMOS ODCMOS ODCMOS ODCMOS ODCMOS ODCMOS ODCMOS ODCMOS ODCMOS ODCMOS CMOS1.5v CMOS1.5v ODCMOS ODCMOS ODCMOS ODCMOS DC DC DC DC SSTL SSTL SSTL SSTL SSTL SSTL

I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I/O I/O I/O I/O I I O O O O O O O O

DDR0_CKE[2] DDR0_CKE[3] DDR0_CKE[4] DDR0_CKE[5] DDR0_CLK_DN[0] DDR0_CLK_DN[1] DDR0_CLK_DN[2] DDR0_CLK_DN[3] DDR0_CLK_DP[0] DDR0_CLK_DP[1] DDR0_CLK_DP[2] DDR0_CLK_DP[3] DDR0_CS_N[0] DDR0_CS_N[1] DDR0_CS_N[2] DDR0_CS_N[3] DDR0_CS_N[4] DDR0_CS_N[5] DDR0_CS_N[6] DDR0_CS_N[7] DDR0_CS_N[8] DDR0_CS_N[9] DDR0_DQ[00] DDR0_DQ[01] DDR0_DQ[02] DDR0_DQ[03] DDR0_DQ[04] DDR0_DQ[05] DDR0_DQ[06] DDR0_DQ[07] DDR0_DQ[08] DDR0_DQ[09] DDR0_DQ[10]

CH20 CP18 CF20 CE19 CF24 CE23 CE21 CF22 CH24 CG23 CG21 CH22 CN25 CH26 CC23 CB28 CG27 CF26 CB26 CC25 CL27 CK28 CC7 CD8 CK8 CL9 BY6 CA7 CJ7 CL7 CB2 CB4 CH4

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL

O O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 3 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 4 of 49)

Land No. Buffer Type Direction

DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] DDR0_DQ[16] DDR0_DQ[17] DDR0_DQ[18] DDR0_DQ[19] DDR0_DQ[20] DDR0_DQ[21] DDR0_DQ[22] DDR0_DQ[23] DDR0_DQ[24] DDR0_DQ[25] DDR0_DQ[26] DDR0_DQ[27] DDR0_DQ[28] DDR0_DQ[29] DDR0_DQ[30] DDR0_DQ[31] DDR0_DQ[32] DDR0_DQ[33] DDR0_DQ[34] DDR0_DQ[35] DDR0_DQ[36] DDR0_DQ[37] DDR0_DQ[38] DDR0_DQ[39] DDR0_DQ[40] DDR0_DQ[41] DDR0_DQ[42] DDR0_DQ[43] DDR0_DQ[44] DDR0_DQ[45] DDR0_DQ[46] DDR0_DQ[47] DDR0_DQ[48] DDR0_DQ[49] DDR0_DQ[50] DDR0_DQ[51] DDR0_DQ[52]

CJ5 CA1 CA3 CG3 CG5 CK12 CM12 CK16 CM16 CG13 CL11 CJ15 CL15 BY10 BY12 CB12 CD12 BW9 CA9 CH10 CF10 CE31 CC31 CE35 CC35 CD30 CB30 CD34 CB34 CL31 CJ31 CL35 CJ35 CK30 CH30 CK34 CH34 CB38 CD38 CE41 CD42 CC37

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

DDR0_DQ[53] DDR0_DQ[54] DDR0_DQ[55] DDR0_DQ[56] DDR0_DQ[57] DDR0_DQ[58] DDR0_DQ[59] DDR0_DQ[60] DDR0_DQ[61] DDR0_DQ[62] DDR0_DQ[63] DDR0_DQS_DN[00] DDR0_DQS_DN[01] DDR0_DQS_DN[02] DDR0_DQS_DN[03] DDR0_DQS_DN[04] DDR0_DQS_DN[05] DDR0_DQS_DN[06] DDR0_DQS_DN[07] DDR0_DQS_DN[08] DDR0_DQS_DN[09] DDR0_DQS_DN[10] DDR0_DQS_DN[11] DDR0_DQS_DN[12] DDR0_DQS_DN[13] DDR0_DQS_DN[14] DDR0_DQS_DN[15] DDR0_DQS_DN[16] DDR0_DQS_DN[17] DDR0_DQS_DP[00] DDR0_DQS_DP[01] DDR0_DQS_DP[02] DDR0_DQS_DP[03] DDR0_DQS_DP[04] DDR0_DQS_DP[05] DDR0_DQS_DP[06] DDR0_DQS_DP[07] DDR0_DQS_DP[08] DDR0_DQS_DP[09] DDR0_DQS_DP[10] DDR0_DQS_DP[11] DDR0_DQS_DP[12]

CE37 CC41 CB42 CH38 CK38 CH42 CK42 CJ37 CL37 CJ41 CL41 CG7 CE3 CH14 CD10 CE33 CL33 CB40 CH40 CE17 CF8 CD4 CL13 CC11 CB32 CH32 CE39 CL39 CF16 CH8 CF4 CK14 CE11 CC33 CJ33 CD40 CK40 CC17 CE7 CC5 CJ13 CB10

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 5 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 6 of 49)

Land No. Buffer Type Direction

DDR0_DQS_DP[13] DDR0_DQS_DP[14] DDR0_DQS_DP[15] DDR0_DQS_DP[16] DDR0_DQS_DP[17] DDR0_ECC[0] DDR0_ECC[1] DDR0_ECC[2] DDR0_ECC[3] DDR0_ECC[4] DDR0_ECC[5] DDR0_ECC[6] DDR0_ECC[7] DDR0_MA_PAR DDR0_MA[00] DDR0_MA[01] DDR0_MA[02] DDR0_MA[03] DDR0_MA[04] DDR0_MA[05] DDR0_MA[06] DDR0_MA[07] DDR0_MA[08] DDR0_MA[09] DDR0_MA[10] DDR0_MA[11] DDR0_MA[12] DDR0_MA[13] DDR0_MA[14] DDR0_MA[15] DDR0_ODT[0] DDR0_ODT[1] DDR0_ODT[2] DDR0_ODT[3] DDR0_ODT[4] DDR0_ODT[5] DDR0_PAR_ERR_N DDR0_RAS_N DDR0_WE_N DDR01_RCOMP[0] DDR01_RCOMP[1] DDR01_RCOMP[2]

CD32 CK32 CC39 CJ39 CD16 CE15 CC15 CH18 CF18 CB14 CD14 CG17 CK18 CM26 CL25 CR25 CG25 CK24 CM24 CL23 CN23 CM22 CK22 CN21 CK26 CL21 CK20 CG29 CG19 CN19 CE25 CE27 CH28 CF28 CB24 CC27 CC21 CE29 CN29 CA17 CC19 CB20

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Analog Analog Analog

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O O O O I O O I I I

DDR1_BA[0] DDR1_BA[1] DDR1_BA[2] DDR1_CAS_N DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3] DDR1_CKE[4] DDR1_CKE[5] DDR1_CLK_DN[0] DDR1_CLK_DN[1] DDR1_CLK_DN[2] DDR1_CLK_DN[3] DDR1_CLK_DP[0] DDR1_CLK_DP[1] DDR1_CLK_DP[2] DDR1_CLK_DP[3] DDR1_CS_N[0] DDR1_CS_N[1] DDR1_CS_N[2] DDR1_CS_N[3] DDR1_CS_N[4] DDR1_CS_N[5] DDR1_CS_N[6] DDR1_CS_N[7] DDR1_CS_N[8] DDR1_CS_N[9] DDR1_DQ[00] DDR1_DQ[01] DDR1_DQ[02] DDR1_DQ[03] DDR1_DQ[04] DDR1_DQ[05] DDR1_DQ[06] DDR1_DQ[07] DDR1_DQ[08] DDR1_DQ[09] DDR1_DQ[10] DDR1_DQ[11] DDR1_DQ[12] DDR1_DQ[13]

DB26 DC25 DF18 CY30 CT20 CU19 CY18 DA17 CR19 CT18 CV20 CV22 CY24 DA21 CY20 CY22 CV24 DC21 DB24 CU23 CR23 CR27 CU25 CT24 DA29 CT26 CR21 DA27 CP4 CP2 CV4 CY4 CM4 CL3 CV2 CW3 DA7 DC7 DC11 DE11 CY6 DB6

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL

O O O O O O O O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 7 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 8 of 49)

Land No. Buffer Type Direction

DDR1_DQ[14] DDR1_DQ[15] DDR1_DQ[16] DDR1_DQ[17] DDR1_DQ[18] DDR1_DQ[19] DDR1_DQ[20] DDR1_DQ[21] DDR1_DQ[22] DDR1_DQ[23] DDR1_DQ[24] DDR1_DQ[25] DDR1_DQ[26] DDR1_DQ[27] DDR1_DQ[28] DDR1_DQ[29] DDR1_DQ[30] DDR1_DQ[31] DDR1_DQ[32] DDR1_DQ[33] DDR1_DQ[34] DDR1_DQ[35] DDR1_DQ[36] DDR1_DQ[37] DDR1_DQ[38] DDR1_DQ[39] DDR1_DQ[40] DDR1_DQ[41] DDR1_DQ[42] DDR1_DQ[43] DDR1_DQ[44] DDR1_DQ[45] DDR1_DQ[46] DDR1_DQ[47] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55]

DB10 DF10 CR7 CU7 CT10 CP10 CP6 CT6 CW9 CV10 CR13 CU13 CR17 CU17 CT12 CV12 CT16 CV16 CT30 CP30 CT34 CP34 CU29 CR29 CU33 CR33 DA33 DD32 DC35 DA35 DA31 CY32 DF34 DE35 CR37 CU37 CR41 CU41 CT36 CV36 CT40 CV40

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63] DDR1_DQS_DN[00] DDR1_DQS_DN[01] DDR1_DQS_DN[02] DDR1_DQS_DN[03] DDR1_DQS_DN[04] DDR1_DQS_DN[05] DDR1_DQS_DN[06] DDR1_DQS_DN[07] DDR1_DQS_DN[08] DDR1_DQS_DN[09] DDR1_DQS_DN[10] DDR1_DQS_DN[11] DDR1_DQS_DN[12] DDR1_DQS_DN[13] DDR1_DQS_DN[14] DDR1_DQS_DN[15] DDR1_DQS_DN[16] DDR1_DQS_DN[17] DDR1_DQS_DP[00] DDR1_DQS_DP[01] DDR1_DQS_DP[02] DDR1_DQS_DP[03] DDR1_DQS_DP[04] DDR1_DQS_DP[05] DDR1_DQS_DP[06] DDR1_DQS_DP[07] DDR1_DQS_DP[08] DDR1_DQS_DP[09] DDR1_DQS_DP[10] DDR1_DQS_DP[11] DDR1_DQS_DP[12] DDR1_DQS_DP[13] DDR1_DQS_DP[14] DDR1_DQS_DP[15]

DE37 DF38 DD40 DB40 DA37 DC37 DA39 DF40 CT4 DC9 CV8 CR15 CT32 CY34 CR39 DE39 DE15 CR1 DB8 CT8 CP14 CR31 DE33 CT38 CY38 DB14 CR3 DE9 CU9 CU15 CP32 DB34 CU39 DC39 DC15 CT2 DD8 CP8 CT14 CU31 DC33 CP38

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 9 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 10 of 49)

Land No. Buffer Type Direction

DDR1_DQS_DP[16] DDR1_DQS_DP[17] DDR1_ECC[0] DDR1_ECC[1] DDR1_ECC[2] DDR1_ECC[3] DDR1_ECC[4] DDR1_ECC[5] DDR1_ECC[6] DDR1_ECC[7] DDR1_MA_PAR DDR1_MA[00] DDR1_MA[01] DDR1_MA[02] DDR1_MA[03] DDR1_MA[04] DDR1_MA[05] DDR1_MA[06] DDR1_MA[07] DDR1_MA[08] DDR1_MA[09] DDR1_MA[10] DDR1_MA[11] DDR1_MA[12] DDR1_MA[13] DDR1_MA[14] DDR1_MA[15] DDR1_ODT[0] DDR1_ODT[1] DDR1_ODT[2] DDR1_ODT[3] DDR1_ODT[4] DDR1_ODT[5] DDR1_PAR_ERR_N DDR1_RAS_N DDR1_WE_N DDR2_BA[0] DDR2_BA[1] DDR2_BA[2] DDR2_CAS_N DDR2_CKE[0] DDR2_CKE[1]

DB38 CY14 DE13 DF14 DD16 DB16 DA13 DC13 DA15 DF16 DE25 DC23 DE23 DF24 DA23 DB22 DF22 DE21 DF20 DB20 DA19 DF26 DE19 DC19 DB30 DB18 DC17 CT22 DA25 CY26 CV26 CU27 CY28 CU21 DB28 CV28 R17 L17 P24 T16 AA25 T26

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O O O O I O O O O O O O O

DDR2_CKE[2] DDR2_CKE[3] DDR2_CKE[4] DDR2_CKE[5] DDR2_CLK_DN[0] DDR2_CLK_DN[1] DDR2_CLK_DN[2] DDR2_CLK_DN[3] DDR2_CLK_DP[0] DDR2_CLK_DP[1] DDR2_CLK_DP[2] DDR2_CLK_DP[3] DDR2_CS_N[0] DDR2_CS_N[1] DDR2_CS_N[2] DDR2_CS_N[3] DDR2_CS_N[4] DDR2_CS_N[5] DDR2_CS_N[6] DDR2_CS_N[7] DDR2_CS_N[8] DDR2_CS_N[9] DDR2_DQ[00] DDR2_DQ[01] DDR2_DQ[02] DDR2_DQ[03] DDR2_DQ[04] DDR2_DQ[05] DDR2_DQ[06] DDR2_DQ[07] DDR2_DQ[08] DDR2_DQ[09] DDR2_DQ[10] DDR2_DQ[11] DDR2_DQ[12] DDR2_DQ[13] DDR2_DQ[14] DDR2_DQ[15] DDR2_DQ[16] DDR2_DQ[17] DDR2_DQ[18] DDR2_DQ[19]

U27 AD24 AE25 AE23 Y24 Y22 W21 W23 AB24 AB22 AA21 AA23 AB20 AE19 AD16 AA15 AA19 P18 AB16 Y16 W17 AA17 T40 V40 P36 T36 R41 U41 R37 U37 AE41 AD40 AA37 AC37 AC41 AA41 AF38 AE37 U33 R33 W29 U29

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL

O O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 11 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 12 of 49)

Land No. Buffer Type Direction

DDR2_DQ[20] DDR2_DQ[21] DDR2_DQ[22] DDR2_DQ[23] DDR2_DQ[24] DDR2_DQ[25] DDR2_DQ[26] DDR2_DQ[27] DDR2_DQ[28] DDR2_DQ[29] DDR2_DQ[30] DDR2_DQ[31] DDR2_DQ[32] DDR2_DQ[33] DDR2_DQ[34] DDR2_DQ[35] DDR2_DQ[36] DDR2_DQ[37] DDR2_DQ[38] DDR2_DQ[39] DDR2_DQ[40] DDR2_DQ[41] DDR2_DQ[42] DDR2_DQ[43] DDR2_DQ[44] DDR2_DQ[45] DDR2_DQ[46] DDR2_DQ[47] DDR2_DQ[48] DDR2_DQ[49] DDR2_DQ[50] DDR2_DQ[51] DDR2_DQ[52] DDR2_DQ[53] DDR2_DQ[54] DDR2_DQ[55] DDR2_DQ[56] DDR2_DQ[57] DDR2_DQ[58] DDR2_DQ[59] DDR2_DQ[60] DDR2_DQ[61]

T34 P34 V30 T30 AC35 AE35 AE33 AF32 AA35 W35 AB32 AD32 AC13 AE13 AG11 AF10 AD14 AA13 AB10 AD10 V6 Y6 AF8 AG7 U7 W7 AD8 AE7 R13 U13 T10 V10 T14 V14 R9 U9 W3 Y4 AF4 AE5 U3 V4

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

DDR2_DQ[62] DDR2_DQ[63] DDR2_DQS_DN[00] DDR2_DQS_DN[01] DDR2_DQS_DN[02] DDR2_DQS_DN[03] DDR2_DQS_DN[04] DDR2_DQS_DN[05] DDR2_DQS_DN[06] DDR2_DQS_DN[07] DDR2_DQS_DN[08] DDR2_DQS_DN[09] DDR2_DQS_DN[10] DDR2_DQS_DN[11] DDR2_DQS_DN[12] DDR2_DQS_DN[13] DDR2_DQS_DN[14] DDR2_DQS_DN[15] DDR2_DQS_DN[16] DDR2_DQS_DN[17] DDR2_DQS_DP[00] DDR2_DQS_DP[01] DDR2_DQS_DP[02] DDR2_DQS_DP[03] DDR2_DQS_DP[04] DDR2_DQS_DP[05] DDR2_DQS_DP[06] DDR2_DQS_DP[07] DDR2_DQS_DP[08] DDR2_DQS_DP[09] DDR2_DQS_DP[10] DDR2_DQS_DP[11] DDR2_DQS_DP[12] DDR2_DQS_DP[13] DDR2_DQS_DP[14] DDR2_DQS_DP[15] DDR2_DQS_DP[16] DDR2_DQS_DP[17] DDR2_ECC[0] DDR2_ECC[1] DDR2_ECC[2] DDR2_ECC[3]

AF2 AE3 T38 AD38 W31 AA33 AC11 AB8 U11 AC3 AB28 W39 AC39 T32 AB34 AD12 AA7 V12 AD4 AD28 V38 AB38 U31 AC33 AE11 AC7 W11 AB4 AC27 U39 AB40 V32 Y34 AB12 Y8 T12 AC5 AC29 AF30 AF28 Y26 AB26

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 13 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 14 of 49)

Land No. Buffer Type Direction

DDR2_ECC[4] DDR2_ECC[5] DDR2_ECC[6] DDR2_ECC[7] DDR2_MA_PAR DDR2_MA[00] DDR2_MA[01] DDR2_MA[02] DDR2_MA[03] DDR2_MA[04] DDR2_MA[05] DDR2_MA[06] DDR2_MA[07] DDR2_MA[08] DDR2_MA[09] DDR2_MA[10] DDR2_MA[11] DDR2_MA[12] DDR2_MA[13] DDR2_MA[14] DDR2_MA[15] DDR2_ODT[0] DDR2_ODT[1] DDR2_ODT[2] DDR2_ODT[3] DDR2_ODT[4] DDR2_ODT[5] DDR2_PAR_ERR_N DDR2_RAS_N DDR2_WE_N DDR23_RCOMP[0] DDR23_RCOMP[1] DDR23_RCOMP[2] DDR3_BA[0] DDR3_BA[1] DDR3_BA[2] DDR3_CAS_N DDR3_CKE[0] DDR3_CKE[1] DDR3_CKE[2] DDR3_CKE[3] DDR3_CKE[4]

AB30 AD30 W27 AA27 M18 AB18 R19 U19 T20 P20 U21 R21 P22 T22 R23 T18 U23 T24 R15 W25 U25 Y20 W19 AD18 Y18 AD22 AE21 AD20 U17 P16 U15 AC15 Y14 A17 E19 B24 B14 K24 M24 J25 N25 R25

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Analog Analog Analog SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL

I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O O O O I O O I I I O O O O O O O O O

DDR3_CKE[5] DDR3_CLK_DN[0] DDR3_CLK_DN[1] DDR3_CLK_DN[2] DDR3_CLK_DN[3] DDR3_CLK_DP[0] DDR3_CLK_DP[1] DDR3_CLK_DP[2] DDR3_CLK_DP[3] DDR3_CS_N[0] DDR3_CS_N[1] DDR3_CS_N[2] DDR3_CS_N[3] DDR3_CS_N[4] DDR3_CS_N[5] DDR3_CS_N[6] DDR3_CS_N[7] DDR3_CS_N[8] DDR3_CS_N[9] DDR3_DQ[00] DDR3_DQ[01] DDR3_DQ[02] DDR3_DQ[03] DDR3_DQ[04] DDR3_DQ[05] DDR3_DQ[06] DDR3_DQ[07] DDR3_DQ[08] DDR3_DQ[09] DDR3_DQ[10] DDR3_DQ[11] DDR3_DQ[12] DDR3_DQ[13] DDR3_DQ[14] DDR3_DQ[15] DDR3_DQ[16] DDR3_DQ[17] DDR3_DQ[18] DDR3_DQ[19] DDR3_DQ[20] DDR3_DQ[21] DDR3_DQ[22]

R27 J23 J21 M20 K22 L23 L21 K20 M22 G19 J19 F14 G15 K18 G17 F16 E15 D16 K16 B40 A39 C37 E37 F40 D40 F38 A37 N39 L39 L35 J35 M40 K40 K36 H36 A35 F34 D32 F32 E35 C35 A33

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL

O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 15 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 16 of 49)

Land No. Buffer Type Direction

DDR3_DQ[23] DDR3_DQ[24] DDR3_DQ[25] DDR3_DQ[26] DDR3_DQ[27] DDR3_DQ[28] DDR3_DQ[29] DDR3_DQ[30] DDR3_DQ[31] DDR3_DQ[32] DDR3_DQ[33] DDR3_DQ[34] DDR3_DQ[35] DDR3_DQ[36] DDR3_DQ[37] DDR3_DQ[38] DDR3_DQ[39] DDR3_DQ[40] DDR3_DQ[41] DDR3_DQ[42] DDR3_DQ[43] DDR3_DQ[44] DDR3_DQ[45] DDR3_DQ[46] DDR3_DQ[47] DDR3_DQ[48] DDR3_DQ[49] DDR3_DQ[50] DDR3_DQ[51] DDR3_DQ[52] DDR3_DQ[53] DDR3_DQ[54] DDR3_DQ[55] DDR3_DQ[56] DDR3_DQ[57] DDR3_DQ[58] DDR3_DQ[59] DDR3_DQ[60] DDR3_DQ[61] DDR3_DQ[62] DDR3_DQ[63] DDR3_DQS_DN[00]

B32 M32 L31 M28 L27 L33 K32 N27 M26 D12 A11 C9 E9 F12 B12 F10 A9 J13 L13 J9 L9 K14 M14 K10 M10 E7 F6 N7 P6 C7 D6 L7 M6 G3 H2 N3 P4 F4 H4 L1 M2 B38

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

DDR3_DQS_DN[01] DDR3_DQS_DN[02] DDR3_DQS_DN[03] DDR3_DQS_DN[04] DDR3_DQS_DN[05] DDR3_DQS_DN[06] DDR3_DQS_DN[07] DDR3_DQS_DN[08] DDR3_DQS_DN[09] DDR3_DQS_DN[10] DDR3_DQS_DN[11] DDR3_DQS_DN[12] DDR3_DQS_DN[13] DDR3_DQS_DN[14] DDR3_DQS_DN[15] DDR3_DQS_DN[16] DDR3_DQS_DN[17] DDR3_DQS_DP[00] DDR3_DQS_DP[01] DDR3_DQS_DP[02] DDR3_DQS_DP[03] DDR3_DQS_DP[04] DDR3_DQS_DP[05] DDR3_DQS_DP[06] DDR3_DQS_DP[07] DDR3_DQS_DP[08] DDR3_DQS_DP[09] DDR3_DQS_DP[10] DDR3_DQS_DP[11] DDR3_DQS_DP[12] DDR3_DQS_DP[13] DDR3_DQS_DP[14] DDR3_DQS_DP[15] DDR3_DQS_DP[16] DDR3_DQS_DP[17] DDR3_ECC[0] DDR3_ECC[1] DDR3_ECC[2] DDR3_ECC[3] DDR3_ECC[4] DDR3_ECC[5] DDR3_ECC[6]

L37 G33 P28 B10 L11 J7 L3 G27 G39 K38 B34 M30 G11 M12 H6 K4 H28 D38 J37 E33 N29 D10 N11 K6 M4 E27 E39 M38 D34 N31 E11 K12 G7 J3 F28 G29 J29 E25 C25 F30 H30 F26

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 17 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 18 of 49)

Land No. Buffer Type Direction

DDR3_ECC[7] DDR3_MA_PAR DDR3_MA[00] DDR3_MA[01] DDR3_MA[02] DDR3_MA[03] DDR3_MA[04] DDR3_MA[05] DDR3_MA[06] DDR3_MA[07] DDR3_MA[08] DDR3_MA[09] DDR3_MA[10] DDR3_MA[11] DDR3_MA[12] DDR3_MA[13] DDR3_MA[14] DDR3_MA[15] DDR3_ODT[0] DDR3_ODT[1] DDR3_ODT[2] DDR3_ODT[3] DDR3_ODT[4] DDR3_ODT[5] DDR3_PAR_ERR_N DDR3_RAS_N DDR3_WE_N DMI_RX_DN[0] DMI_RX_DN[1] DMI_RX_DN[2] DMI_RX_DN[3] DMI_RX_DP[0] DMI_RX_DP[1] DMI_RX_DP[2] DMI_RX_DP[3] DMI_TX_DN[0] DMI_TX_DN[1] DMI_TX_DN[2] DMI_TX_DN[3] DMI_TX_DP[0] DMI_TX_DP[1] DMI_TX_DP[2]

H26 B18 A19 E21 F20 B20 D20 A21 F22 B22 D22 G23 D18 A23 E23 A13 D24 F24 L19 F18 E17 J17 D14 M16 G21 B16 A15 E47 D48 E49 D50 C47 B48 C49 B50 D42 E43 D44 E45 B42 C43 B44

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX PCIEX

I/O O O O O O O O O O O O O O O O O O O O O O O O I O O I I I I I I I I O O O O O O O

DMI_TX_DP[3] TXT_PLTEN DRAM_PWR_OK_C01 DRAM_PWR_OK_C23 EAR_N ERROR_N[0] ERROR_N[1] ERROR_N[2] FRMAGENT IVT_ID_N TXT_AGENT MEM_HOT_C01_N MEM_HOT_C23_N PE_RBIAS PE_RBIAS_SENSE PE_VREF_CAP PE1A_RX_DN[0] PE1A_RX_DN[1] PE1A_RX_DN[2] PE1A_RX_DN[3] PE1A_RX_DP[0] PE1A_RX_DP[1] PE1A_RX_DP[2] PE1A_RX_DP[3] PE1A_TX_DN[0] PE1A_TX_DN[1] PE1A_TX_DN[2] PE1A_TX_DN[3] PE1A_TX_DP[0] PE1A_TX_DP[1] PE1A_TX_DP[2] PE1A_TX_DP[3] PE1B_RX_DN[4] PE1B_RX_DN[5] PE1B_RX_DN[6] PE1B_RX_DN[7] PE1B_RX_DP[4] PE1B_RX_DP[5] PE1B_RX_DP[6] PE1B_RX_DP[7] PE1B_TX_DN[4] PE1B_TX_DN[5]

C45 V52 CW17 L15 CH56 BD50 CB54 BC51 AT50 AH42 AK52 CB22 E13 AH52 AF52 AJ43 E51 F52 F54 G55 C51 D52 D54 E55 K42 L43 K44 L45 H42 J43 H44 J45 L53 M54 L57 M56 J53 K54 J57 K56 K46 L47

PCIEX CMOS CMOS1.5v CMOS1.5v ODCMOS ODCMOS ODCMOS ODCMOS CMOS

O I I I I/O O O O I O

CMOS ODCMOS ODCMOS PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3

I I/O I/O I/O I I/O I I I I I I I I O O O O O O O O I I I I I I I I O O

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 19 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 20 of 49)

Land No. Buffer Type Direction

PE1B_TX_DN[6] PE1B_TX_DN[7] PE1B_TX_DP[4] PE1B_TX_DP[5] PE1B_TX_DP[6] PE1B_TX_DP[7] PE2A_RX_DN[0] PE2A_RX_DN[1] PE2A_RX_DN[2] PE2A_RX_DN[3] PE2A_RX_DP[0] PE2A_RX_DP[1] PE2A_RX_DP[2] PE2A_RX_DP[3] PE2A_TX_DN[0] PE2A_TX_DN[1] PE2A_TX_DN[2] PE2A_TX_DN[3] PE2A_TX_DP[0] PE2A_TX_DP[1] PE2A_TX_DP[2] PE2A_TX_DP[3] PE2B_RX_DN[4] PE2B_RX_DN[5] PE2B_RX_DN[6] PE2B_RX_DN[7] PE2B_RX_DP[4] PE2B_RX_DP[5] PE2B_RX_DP[6] PE2B_RX_DP[7] PE2B_TX_DN[4] PE2B_TX_DN[5] PE2B_TX_DN[6] PE2B_TX_DN[7] PE2B_TX_DP[4] PE2B_TX_DP[5] PE2B_TX_DP[6] PE2B_TX_DP[7] PE2C_RX_DN[10] PE2C_RX_DN[11] PE2C_RX_DN[8] PE2C_RX_DN[9]

K48 L49 H46 J47 H48 J49 N55 V54 V56 W55 L55 T54 T56 U55 AR49 AP50 AR51 AP52 AN49 AM50 AN51 AM52 AD54 AD56 AE55 AF58 AB54 AB56 AC55 AE57 AJ53 AK54 AR53 AT54 AG53 AH54 AN53 AP54 AL57 AU57 AK56 AM58

PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3

O O O O O O I I I I I I I I O O O O O O O O I I I I I I I I O O O O O O O O I I I I

PE2C_RX_DP[10] PE2C_RX_DP[11] PE2C_RX_DP[8] PE2C_RX_DP[9] PE2C_TX_DN[10] PE2C_TX_DN[11] PE2C_TX_DN[8] PE2C_TX_DN[9] PE2C_TX_DP[10] PE2C_TX_DP[11] PE2C_TX_DP[8] PE2C_TX_DP[9] PE2D_RX_DN[12] PE2D_RX_DN[13] PE2D_RX_DN[14] PE2D_RX_DN[15] PE2D_RX_DP[12] PE2D_RX_DP[13] PE2D_RX_DP[14] PE2D_RX_DP[15] PE2D_TX_DN[12] PE2D_TX_DN[13] PE2D_TX_DN[14] PE2D_TX_DN[15] PE2D_TX_DP[12] PE2D_TX_DP[13] PE2D_TX_DP[14] PE2D_TX_DP[15] PE3A_RX_DN[0] PE3A_RX_DN[1] PE3A_RX_DN[2] PE3A_RX_DN[3] PE3A_RX_DP[0] PE3A_RX_DP[1] PE3A_RX_DP[2] PE3A_RX_DP[3] PE3A_TX_DN[0] PE3A_TX_DN[1] PE3A_TX_DN[2] PE3A_TX_DN[3] PE3A_TX_DP[0] PE3A_TX_DP[1]

AJ57 AR57 AH56 AK58 BB54 BA51 AY52 BA53 AY54 AW51 AV52 AW53 AV58 AT56 BA57 BB56 AT58 AP56 AY58 AY56 AY50 BA49 AY48 BA47 AV50 AW49 AV48 AW47 AH44 AJ45 AH46 AC49 AF44 AG45 AF46 AA49 K50 L51 U47 T48 H50 J51

PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3

I I I I O O O O O O O O I I I I I I I I O O O O O O O O I I I I I I I I O O O O O O

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 21 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 22 of 49)

Land No. Buffer Type Direction

PE3A_TX_DP[2] PE3A_TX_DP[3] PE3B_RX_DN[4] PE3B_RX_DN[5] PE3B_RX_DN[6] PE3B_RX_DN[7] PE3B_RX_DP[4] PE3B_RX_DP[5] PE3B_RX_DP[6] PE3B_RX_DP[7] PE3B_TX_DN[4] PE3B_TX_DN[5] PE3B_TX_DN[6] PE3B_TX_DN[7] PE3B_TX_DP[4] PE3B_TX_DP[5] PE3B_TX_DP[6] PE3B_TX_DP[7] PE3C_RX_DN[10] PE3C_RX_DN[11] PE3C_RX_DN[8] PE3C_RX_DN[9] PE3C_RX_DP[10] PE3C_RX_DP[11] PE3C_RX_DP[8] PE3C_RX_DP[9] PE3C_TX_DN[10] PE3C_TX_DN[11] PE3C_TX_DN[8] PE3C_TX_DN[9] PE3C_TX_DP[10] PE3C_TX_DP[11] PE3C_TX_DP[8] PE3C_TX_DP[9] PE3D_RX_DN[12] PE3D_RX_DN[13] PE3D_RX_DN[14] PE3D_RX_DN[15] PE3D_RX_DP[12] PE3D_RX_DP[13] PE3D_RX_DP[14] PE3D_RX_DP[15]

R47 P48 AB50 AB52 AC53 AC51 Y50 Y52 AA53 AA51 T52 U51 T50 U49 P52 R51 P50 R49 AH50 AJ49 AH48 AJ51 AF50 AG49 AF48 AG51 U45 AB46 T46 AC47 R45 Y46 P46 AA47 AJ47 AR47 AP46 AR45 AG47 AN47 AM46 AN45

PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3

O O I I I I I I I I O O O O O O O O I I I I I I I I O O O O O O O O I I I I I I I I

PE3D_TX_DN[12] PE3D_TX_DN[13] PE3D_TX_DN[14] PE3D_TX_DN[15] PE3D_TX_DP[12] PE3D_TX_DP[13] PE3D_TX_DP[14] PE3D_TX_DP[15] PECI PEHPSCL PEHPSDA PMSYNC PRDY_N PREQ_N PROCHOT_N PWRGOOD QPI_RBIAS QPI_RBIAS_SENSE QPI_VREF_CAP QPI0_CLKRX_DN QPI0_CLKRX_DP QPI0_CLKTX_DN QPI0_CLKTX_DP QPI0_DRX_DN[00] QPI0_DRX_DN[01] QPI0_DRX_DN[02] QPI0_DRX_DN[03] QPI0_DRX_DN[04] QPI0_DRX_DN[05] QPI0_DRX_DN[06] QPI0_DRX_DN[07] QPI0_DRX_DN[08] QPI0_DRX_DN[09] QPI0_DRX_DN[10] QPI0_DRX_DN[11] QPI0_DRX_DN[12] QPI0_DRX_DN[13] QPI0_DRX_DN[14] QPI0_DRX_DN[15] QPI0_DRX_DN[16] QPI0_DRX_DN[17] QPI0_DRX_DN[18]

AC45 AB44 AA43 P44 AA45 Y44 AC43 T44 BJ47 BH48 BF48 K52 R53 U53 BD52 BJ53 CE53 CC53 CU51 BM58 BK58 CG45 CE45 BJ51 BH52 BG53 BG55 BH56 BH54 BH50 BF58 BG57 BN57 BP56 BN55 BP54 BN53 BP52 BR51 BP50 BJ49 BN49

PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PECI ODCMOS ODCMOS CMOS CMOS CMOS ODCMOS CMOS Analog Analog QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI

O O O O O O O O I/O I/O I/O I O I/O I/O I I/O I I/O I I O O I I I I I I I I I I I I I I I I I I I

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 23 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 24 of 49)

Land No. Buffer Type Direction

QPI0_DRX_DN[19] QPI0_DRX_DP[00] QPI0_DRX_DP[01] QPI0_DRX_DP[02] QPI0_DRX_DP[03] QPI0_DRX_DP[04] QPI0_DRX_DP[05] QPI0_DRX_DP[06] QPI0_DRX_DP[07] QPI0_DRX_DP[08] QPI0_DRX_DP[09] QPI0_DRX_DP[10] QPI0_DRX_DP[11] QPI0_DRX_DP[12] QPI0_DRX_DP[13] QPI0_DRX_DP[14] QPI0_DRX_DP[15] QPI0_DRX_DP[16] QPI0_DRX_DP[17] QPI0_DRX_DP[18] QPI0_DRX_DP[19] QPI0_DTX_DN[00] QPI0_DTX_DN[01] QPI0_DTX_DN[02] QPI0_DTX_DN[03] QPI0_DTX_DN[04] QPI0_DTX_DN[05] QPI0_DTX_DN[06] QPI0_DTX_DN[07] QPI0_DTX_DN[08] QPI0_DTX_DN[09] QPI0_DTX_DN[10] QPI0_DTX_DN[11] QPI0_DTX_DN[12] QPI0_DTX_DN[13] QPI0_DTX_DN[14] QPI0_DTX_DN[15] QPI0_DTX_DN[16] QPI0_DTX_DN[17] QPI0_DTX_DN[18] QPI0_DTX_DN[19] QPI0_DTX_DP[00]

BM48 BG51 BF52 BE53 BE55 BF56 BF54 BF50 BD58 BE57 BL57 BM56 BL55 BM54 BL53 BM52 BN51 BM50 BG49 BR49 BP48 BW49 BW51 BW53 BY54 BW55 BV58 BW47 BW57 BY56 BW45 CF46 BY52 CA47 CA49 CG47 CF48 CF50 CF52 CG51 CG49 BV50

QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI

I I I I I I I I I I I I I I I I I I I I I O O O O O O O O O O O O O O O O O O O O O

QPI0_DTX_DP[01] QPI0_DTX_DP[02] QPI0_DTX_DP[03] QPI0_DTX_DP[04] QPI0_DTX_DP[05] QPI0_DTX_DP[06] QPI0_DTX_DP[07] QPI0_DTX_DP[08] QPI0_DTX_DP[09] QPI0_DTX_DP[10] QPI0_DTX_DP[11] QPI0_DTX_DP[12] QPI0_DTX_DP[13] QPI0_DTX_DP[14] QPI0_DTX_DP[15] QPI0_DTX_DP[16] QPI0_DTX_DP[17] QPI0_DTX_DP[18] QPI0_DTX_DP[19] QPI1_CLKRX_DN QPI1_CLKRX_DP QPI1_CLKTX_DN QPI1_CLKTX_DP QPI1_DRX_DN[00] QPI1_DRX_DN[01] QPI1_DRX_DN[02] QPI1_DRX_DN[03] QPI1_DRX_DN[04] QPI1_DRX_DN[05] QPI1_DRX_DN[06] QPI1_DRX_DN[07] QPI1_DRX_DN[08] QPI1_DRX_DN[09] QPI1_DRX_DN[10] QPI1_DRX_DN[11] QPI1_DRX_DN[12] QPI1_DRX_DN[13] QPI1_DRX_DN[14] QPI1_DRX_DN[15] QPI1_DRX_DN[16] QPI1_DRX_DN[17] QPI1_DRX_DN[18]

BV52 BU53 BV54 BU55 BT58 BV48 BU57 BV56 BV46 CD46 CA51 BY48 BY50 CE47 CD48 CD50 CD52 CE51 CE49 CU55 CR55 CY54 DB54 CE55 CF56 CF54 CL55 CM56 CM54 CT58 CU57 CV56 CL53 CM52 CR53 CT52 CL51 CK50 CL49 CM48 CN47 CM46

QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI

O O O O O O O O O O O O O O O O O O O I I O O I I I I I I I I I I I I I I I I I I I

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 25 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 26 of 49)

Land No. Buffer Type Direction

QPI1_DRX_DN[19] QPI1_DRX_DP[00] QPI1_DRX_DP[01] QPI1_DRX_DP[02] QPI1_DRX_DP[03] QPI1_DRX_DP[04] QPI1_DRX_DP[05] QPI1_DRX_DP[06] QPI1_DRX_DP[07] QPI1_DRX_DP[08] QPI1_DRX_DP[09] QPI1_DRX_DP[10] QPI1_DRX_DP[11] QPI1_DRX_DP[12] QPI1_DRX_DP[13] QPI1_DRX_DP[14] QPI1_DRX_DP[15] QPI1_DRX_DP[16] QPI1_DRX_DP[17] QPI1_DRX_DP[18] QPI1_DRX_DP[19] QPI1_DTX_DN[00] QPI1_DTX_DN[01] QPI1_DTX_DN[02] QPI1_DTX_DN[03] QPI1_DTX_DN[04] QPI1_DTX_DN[05] QPI1_DTX_DN[06] QPI1_DTX_DN[07] QPI1_DTX_DN[08] QPI1_DTX_DN[09] QPI1_DTX_DN[10] QPI1_DTX_DN[11] QPI1_DTX_DN[12] QPI1_DTX_DN[13] QPI1_DTX_DN[14] QPI1_DTX_DN[15] QPI1_DTX_DN[16] QPI1_DTX_DN[17] QPI1_DTX_DN[18] QPI1_DTX_DN[19] QPI1_DTX_DP[00]

CN45 CC55 CD56 CD54 CJ55 CK56 CK54 CP58 CR57 CT56 CJ53 CK52 CU53 CV52 CN51 CM50 CN49 CK48 CL47 CK46 CL45 CV48 CV50 CW49 DC53 DB52 CW47 DE51 DB50 CV46 DE49 DD48 CW45 DC47 DD46 CV44 DC45 DD44 CW43 DC43 DD42 CT48

QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI

I I I I I I I I I I I I I I I I I I I I I O O O O O O O O O O O O O O O O O O O O O

QPI1_DTX_DP[01] QPI1_DTX_DP[02] QPI1_DTX_DP[03] QPI1_DTX_DP[04] QPI1_DTX_DP[05] QPI1_DTX_DP[06] QPI1_DTX_DP[07] QPI1_DTX_DP[08] QPI1_DTX_DP[09] QPI1_DTX_DP[10] QPI1_DTX_DP[11] QPI1_DTX_DP[12] QPI1_DTX_DP[13] QPI1_DTX_DP[14] QPI1_DTX_DP[15] QPI1_DTX_DP[16] QPI1_DTX_DP[17] QPI1_DTX_DP[18] QPI1_DTX_DP[19] RESET_N RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

CT50 CU49 DA53 DD52 CU47 DC51 DD50 CT46 DC49 DB48 CU45 DE47 DB46 CT44 DE45 DB44 CU43 DE43 DB42 CK44 A53 AB48 AJ55 AL55 AM44 AP48 AR55 AU55 AV46 AY46 B46 BC47 BD44 BD46 BD48 BE43 BE45 BE47 BF46 BG43 BG45 BH44

QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI CMOS

O O O O O O O O O O O O O O O O O O O I

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 27 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 28 of 49)

Land No. Buffer Type Direction

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

BH46 BJ43 BJ45 BK44 BL43 BL45 BM44 BM46 BN47 BP44 BP46 BR43 BR47 BT44 BU43 BY46 C53 CA45 CD44 CE43 CF44 CG11 CP54 CY46 CY48 CY56 CY58 D46 D56 DA57 DB56 DC55 DD54 DE55 E53 E57 F46 F56 F58 H56 H58 J15

RSVD RSVD RSVD RSVD SAFE_MODE_BOOT SKTOCC_N SOCKET_ID[0] SOCKET_ID[1] SVIDALERT_N SVIDCLK SVIDDATA TCK TDI TDO TEST0 TEST1 TEST2 TEST3 TEST4 THERMTRIP_N TMS TRST_N VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

K58 M48 W15 Y48 DA55 BU49 CY52 BC49 CR43 CB44 BR45 BY44 BW43 CA43 DB4 CW1 F2 D4 BA55 BL47 BV44 CT54 AG19 AG25 AG27 AG29 AG31 AG33 AG35 AG37 AG39 AG41 AL1 AL11 AL13 AL15 AL17 AL3 AL5 AL7 AL9 AM10 ODCMOS CMOS CMOS PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR CMOS CMOS CMOS ODCMOS ODCMOS CMOS CMOS ODCMOS CMOS I O I I I O I/O I I O O O O O I O I I

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 29 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 30 of 49)

Land No. Buffer Type Direction

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

AM12 AM14 AM16 AM2 AM4 AM6 AM8 AN1 AN11 AN13 AN15 AN17 AN3 AN5 AN7 AN9 AP10 AP12 AP14 AP16 AP2 AP4 AP6 AP8 AU1 AU11 AU13 AU15 AU17 AU3 AU5 AU7 AU9 AV10 AV12 AV14 AV16 AV2 AV4 AV6 AV8 AW1

PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

AW11 AW13 AW15 AW17 AW3 AW5 AW7 AW9 AY10 AY12 AY14 AY16 AY2 AY4 AY6 AY8 BA1 BA11 BA13 BA15 BA17 BA3 BA5 BA7 BA9 BB10 BB12 BB14 BB16 BB2 BB4 BB6 BB8 BE1 BE11 BE13 BE15 BE17 BE3 BE5 BE7 BE9

PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 31 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 32 of 49)

Land No. Buffer Type Direction

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

BF10 BF12 BF14 BF16 BF2 BF4 BF6 BF8 BG1 BG11 BG13 BG15 BG17 BG3 BG5 BG7 BG9 BH10 BH12 BH14 BH16 BH2 BH4 BH6 BH8 BJ1 BJ11 BJ13 BJ15 BJ17 BJ3 BJ5 BJ7 BJ9 BK10 BK12 BK14 BK16 BK2 BK4 BK6 BK8

PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

BN1 BN11 BN13 BN15 BN17 BN3 BN5 BN7 BN9 BP10 BP12 BP14 BP16 BP2 BP4 BP6 BP8 BR1 BR11 BR13 BR15 BR17 BR3 BR5 BR7 BR9 BT10 BT12 BT14 BT16 BT2 BT4 BT6 BT8 BU1 BU11 BU13 BU15 BU17 BU3 BU5 BU7

PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 33 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 34 of 49)

Land No. Buffer Type Direction

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_SENSE VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01

BU9 BV10 BV12 BV14 BV16 BV2 BV4 BV6 BV8 BY18 BY26 BY28 BY30 BY32 BY34 BY36 BY38 BY40 CA25 CA29 BW3 CD20 CD22 CD24 CD26 CD28 CJ19 CJ21 CJ23 CJ25 CJ27 CP20 CP22 CP24 CP26 CP28 CW19 CW21 CW23 CW25 CW27 DD18

PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR O PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR

VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCPLL VCCPLL VCCPLL VSA VSA VSA VSA VSA VSA VSA VSA VSA

DD20 DD22 DD24 DD26 AC17 AC19 AC21 AC23 AC25 C15 C17 C19 C21 C23 G13 H16 H18 H20 H22 H24 N15 N17 N19 N21 N23 V16 V18 V20 V22 V24 BY14 CA13 CA15 AE15 AE17 AF18 AG15 AG17 AH10 AH12 AH14 AH16

PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 35 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 36 of 49)

Land No. Buffer Type Direction

VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA VSA_SENSE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AH2 AH4 AH6 AH8 AJ1 AJ11 AJ13 AJ3 AJ5 AJ7 AJ9 B54 G43 G49 N45 N51 AG13 A41 A43 A45 A47 A49 A5 A51 A7 AA11 AA29 AA3 AA31 AA39 AA5 AA55 AA9 AB14 AB36 AB42 AB6 AC31 AC9 AD26 AD34 AD36

PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR O GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AD42 AD44 AD46 AD48 AD50 AD52 AD6 AE29 AE31 AE39 AE43 AE47 AE49 AE51 AE9 AF12 AF16 AF20 AF26 AF34 AF36 AF40 AF42 AF54 AF56 AF6 AG1 AG3 AG43 AG5 AG55 AG57 AG9 AH58 AJ15 AJ17 AK10 AK12 AK14 AK16 AK2 AK4

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Table 8-1.
Land Name

Land Name (Sheet 37 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 38 of 49)

Land No. Buffer Type Direction

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK42 AK44 AK46 AK48 AK50 AK6 AK8 AL43 AL45 AL49 AL51 AL53 AM56 AN55 AN57 AP42 AP44 AP58 AR1 AR11 AR13 AR15 AR17 AR3 AR5 AR7 AR9 AT10 AT12 AT14 AT16 AT2 AT4 AT46 AT52 AT6 AT8 AU45 AU47 AU49 AU51 AV42

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AV54 AV56 AW55 AW57 B36 B52 B6 B8 BB42 BB46 BB48 BB50 BB52 BB58 BC1 BC11 BC13 BC15 BC17 BC3 BC43 BC45 BC5 BC53 BC55 BC57 BC7 BC9 BD10 BD12 BD14 BD16 BD2 BD4 BD54 BD56 BD6 BD8 BE49 BE51 BF42 BF44

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 39 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 40 of 49)

Land No. Buffer Type Direction

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

BG47 BH58 BJ55 BJ57 BK42 BK46 BK48 BK50 BK52 BK54 BL1 BL11 BL13 BL15 BL17 BL3 BL49 BL5 BL7 BL9 BM10 BM12 BM14 BM16 BM2 BM4 BM6 BM8 BN43 BN45 BP58 BR53 BR57 BT46 BT48 BT50 BT52 BT54 BT56 BU45 BU51 BW1

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

BW11 BW13 BW15 BW17 BW5 BW7 BY24 BY4 BY42 BY58 BY8 C11 C13 C3 C33 C39 C41 C5 C55 CA11 CA19 CA27 CA31 CA33 CA35 CA37 CA39 CA41 CA5 CA55 CA57 CB16 CB36 CB46 CB48 CB50 CB52 CB56 CB6 CB8 CC13 CC29

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Table 8-1.
Land Name

Land Name (Sheet 41 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 42 of 49)

Land No. Buffer Type Direction

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

CC3 CC43 CC47 CC49 CC9 CD18 CD36 CD6 CE13 CE5 CE9 CF12 CF14 CF30 CF32 CF34 CF36 CF38 CF40 CF42 CF6 CG15 CG31 CG33 CG35 CG37 CG39 CG41 CG43 CG53 CG9 CH12 CH16 CH36 CH44 CH46 CH48 CH50 CH52 CH54 CH6 CJ11

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

CJ17 CJ29 CJ3 CJ43 CJ45 CJ47 CJ51 CJ9 CK10 CK36 CK4 CK6 CL17 CL43 CL5 CM10 CM14 CM30 CM32 CM34 CM36 CM38 CM40 CM42 CM6 CM8 CN11 CN13 CN15 CN17 CN3 CN31 CN33 CN35 CN37 CN39 CN5 CN53 CN55 CN57 CN7 CN9

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 43 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 44 of 49)

Land No. Buffer Type Direction

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

CP12 CP16 CP36 CP40 CP42 CP44 CP46 CP48 CP50 CP52 CP56 CR11 CR35 CR47 CR49 CR5 CR9 CT28 CT42 CU1 CU11 CU3 CU35 CU5 CV14 CV18 CV30 CV32 CV34 CV38 CV42 CV54 CV58 CV6 CW11 CW13 CW15 CW29 CW31 CW33 CW35 CW37

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

CW39 CW5 CW51 CW53 CW55 CW57 CW7 CY10 CY12 CY16 CY2 CY36 CY40 CY44 CY50 CY8 D2 D26 D36 D8 DA11 DA3 DA41 DA43 DA45 DA47 DA5 DA51 DA9 DB12 DB2 DB32 DB36 DB58 DC3 DC41 DC5 DD10 DD12 DD14 DD34 DD36

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Table 8-1.
Land Name

Land Name (Sheet 45 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 46 of 49)

Land No. Buffer Type Direction

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

DD38 DD6 DE17 DE41 DE53 DE7 DF12 DF36 DF42 DF44 DF46 DF48 DF50 DF52 DF8 E1 E29 E3 E31 E41 E5 F36 F42 F44 F48 F50 F8 G1 G25 G31 G35 G37 G41 G45 G47 G5 G51 G53 G57 G9 H10 H12

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H14 H32 H34 H38 H40 H52 H54 H8 J11 J27 J31 J33 J39 J41 J5 J55 K2 K26 K28 K30 K34 K8 L25 L29 L41 L5 M34 M36 M42 M44 M46 M50 M52 M8 N13 N33 N35 N37 N41 N43 N47 N49

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Processor Land Listing

Table 8-1.
Land Name

Land Name (Sheet 47 of 49)

Land No. Buffer Type Direction

Table 8-1.
Land Name

Land Name (Sheet 48 of 49)

Land No. Buffer Type Direction

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

N5 N53 N9 P10 P12 P14 P26 P30 P32 P38 P40 P54 P56 P8 R11 R29 R3 R31 R35 R39 R5 R55 R7 T28 T4 T42 T6 T8 U35 U5 V26 V28 V34 V36 V42 V44 V46 V48 V50 V8 W13 W33

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_VCC_SENSE VSS_VSA_SENSE VSS_VTTD_SENSE VTTA VTTA VTTA VTTA VTTA VTTA VTTA VTTA VTTA VTTA VTTA VTTA VTTA VTTA VTTD VTTD VTTD VTTD VTTD VTTD

W37 W41 W43 W45 W47 W5 W51 W53 W9 Y10 Y12 Y28 Y30 Y32 Y36 Y38 Y40 Y42 Y56 BY2 AF14 BT42 AE45 AE53 AM48 AM54 AU53 CA53 CC45 CG55 CJ49 CR45 CR51 DA49 W49 Y54 AF22 AF24 AG21 AG23 AM42 AT42

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND O O O PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR

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Table 8-1.
Land Name

Land Name (Sheet 49 of 49)

Land No. Buffer Type Direction

VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD_SENSE

AY42 BD42 BH42 BK56 BL51 BM42 BR55 BU47 BV42 BY20 BY22 CA21 CA23 BP42

PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR O

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8.2
Table 8-2.
Land No.

Listing by Land Number

Land Number (Sheet 1 of 48)
Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 2 of 48)

Land Name Buffer Type Direction

A11 A13 A15 A17 A19 A21 A23 A33 A35 A37 A39 A41 A43 A45 A47 A49 A5 A51 A53 A7 A9 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AA25 AA27 AA29 AA3 AA31 AA33 AA35 AA37 AA39 AA41 AA43 AA45

DDR3_DQ[33] DDR3_MA[13] DDR3_WE_N DDR3_BA[0] DDR3_MA[00] DDR3_MA[05] DDR3_MA[11] DDR3_DQ[22] DDR3_DQ[16] DDR3_DQ[07] DDR3_DQ[01] VSS VSS VSS VSS VSS VSS VSS RSVD VSS DDR3_DQ[39] VSS DDR2_DQ[37] DDR2_CS_N[3] DDR2_CS_N[9] DDR2_CS_N[4] DDR2_CLK_DP[2] DDR2_CLK_DP[3] DDR2_CKE[0] DDR2_ECC[7] VSS VSS VSS DDR2_DQS_DN[03] DDR2_DQ[28] DDR2_DQ[10] VSS DDR2_DQ[13] PE3D_TX_DN[14] PE3D_TX_DP[12]

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND GND GND GND GND GND GND

I/O O O O O O O I/O I/O I/O I/O

AA47 AA49 AA5 AA51 AA53 AA55 AA7 AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AB26 AB28 AB30

PE3C_TX_DP[9] PE3A_RX_DP[3] VSS PE3B_RX_DP[7] PE3B_RX_DP[6] VSS DDR2_DQS_DN[14] VSS DDR2_DQ[38] DDR2_DQS_DP[13] VSS DDR2_CS_N[6] DDR2_MA[00] DDR2_CS_N[0] DDR2_CLK_DP[1] DDR2_CLK_DP[0] DDR2_ECC[3] DDR2_DQS_DN[08] DDR2_ECC[4] DDR2_DQ[30] DDR2_DQS_DN[12] VSS DDR2_DQS_DP[01] DDR2_DQS_DP[07] DDR2_DQS_DP[10] VSS PE3D_TX_DN[13] PE3C_TX_DN[11] RSVD PE3B_RX_DN[4] PE3B_RX_DN[5] PE2B_RX_DP[4] PE2B_RX_DP[5] VSS DDR2_DQS_DN[05] DDR2_DQS_DN[04] DDR2_DQ[32] DDR23_RCOMP[1] VCCD_23 VCCD_23

PCIEX3 PCIEX3 GND PCIEX3 PCIEX3 GND SSTL GND SSTL SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL SSTL SSTL GND PCIEX3 PCIEX3

O I

I I

I/O

I/O I/O

O O O O O I/O I/O I/O I/O I/O

GND SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND GND GND SSTL SSTL SSTL GND SSTL PCIEX3 PCIEX3 I/O O O I/O I/O I/O I/O O O O O O O I/O I/O

AB32 AB34 AB36 AB38 AB4 AB40 AB42 AB44 AB46 AB48 AB50 AB52 AB54 AB56 AB6 AB8 AC11 AC13 AC15 AC17 AC19

I/O I/O I/O

O O

PCIEX3 PCIEX3 PCIEX3 PCIEX3 GND SSTL SSTL SSTL Analog PWR PWR

I I I I

I/O I/O I/O I

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Table 8-2.
Land No.

Land Number (Sheet 3 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 4 of 48)

Land Name Buffer Type Direction

AC21 AC23 AC25 AC27 AC29 AC3 AC31 AC33 AC35 AC37 AC39 AC41 AC43 AC45 AC47 AC49 AC5 AC51 AC53 AC55 AC7 AC9 AD10 AD12 AD14 AD16 AD18 AD20 AD22 AD24 AD26 AD28 AD30 AD32 AD34 AD36 AD38 AD4 AD40 AD42 AD44 AD46

VCCD_23 VCCD_23 VCCD_23 DDR2_DQS_DP[08] DDR2_DQS_DP[17] DDR2_DQS_DN[07] VSS DDR2_DQS_DP[03] DDR2_DQ[24] DDR2_DQ[11] DDR2_DQS_DN[10] DDR2_DQ[12] PE3D_TX_DP[14] PE3D_TX_DN[12] PE3C_TX_DN[9] PE3A_RX_DN[3] DDR2_DQS_DP[16] PE3B_RX_DN[7] PE3B_RX_DN[6] PE2B_RX_DP[6] DDR2_DQS_DP[05] VSS DDR2_DQ[39] DDR2_DQS_DN[13] DDR2_DQ[36] DDR2_CS_N[2] DDR2_ODT[2] DDR2_PAR_ERR_N DDR2_ODT[4] DDR2_CKE[3] VSS DDR2_DQS_DN[17] DDR2_ECC[5] DDR2_DQ[31] VSS VSS DDR2_DQS_DN[01] DDR2_DQS_DN[16] DDR2_DQ[09] VSS VSS VSS

PWR PWR PWR SSTL SSTL SSTL GND SSTL SSTL SSTL SSTL SSTL PCIEX3 PCIEX3 PCIEX3 PCIEX3 SSTL PCIEX3 PCIEX3 PCIEX3 SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL SSTL SSTL GND GND SSTL SSTL SSTL GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I O O I/O I/O I/O I/O I/O O O O I I/O I I I I/O I/O I/O I/O

AD48 AD50 AD52 AD54 AD56 AD6 AD8 AE11 AE13 AE15 AE17 AE19 AE21 AE23 AE25 AE27 AE29 AE3 AE31 AE33 AE35 AE37 AE39 AE41 AE43 AE45 AE47 AE49 AE5 AE51 AE53 AE55 AE57 AE7 AE9 AF10 AF12 AF14 AF16 AF18 AF2 AF20

VSS VSS VSS PE2B_RX_DN[4] PE2B_RX_DN[5] VSS DDR2_DQ[46] DDR2_DQS_DP[04] DDR2_DQ[33] VSA VSA DDR2_CS_N[1] DDR2_ODT[5] DDR2_CKE[5] DDR2_CKE[4] DDR_RESET_C23_N VSS DDR2_DQ[63] VSS DDR2_DQ[26] DDR2_DQ[25] DDR2_DQ[15] VSS DDR2_DQ[08] VSS VTTA VSS VSS DDR2_DQ[59] VSS VTTA PE2B_RX_DN[6] PE2B_RX_DP[7] DDR2_DQ[47] VSS DDR2_DQ[35] VSS VSS_VSA_SENSE VSS VSA DDR2_DQ[62] VSS

GND GND GND PCIEX3 PCIEX3 GND SSTL SSTL SSTL PWR PWR SSTL SSTL SSTL SSTL CMOS1.5v GND SSTL GND SSTL SSTL SSTL GND SSTL GND PWR GND GND SSTL GND PWR PCIEX3 PCIEX3 SSTL GND SSTL GND O GND PWR SSTL GND I/O I/O I I I/O I/O I/O I/O I/O I/O I/O O O O O O I/O I/O I/O I I

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 5 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 6 of 48)

Land Name Buffer Type Direction

AF22 AF24 AF26 AF28 AF30 AF32 AF34 AF36 AF38 AF4 AF40 AF42 AF44 AF46 AF48 AF50 AF52 AF54 AF56 AF58 AF6 AF8 AG1 AG11 AG13 AG15 AG17 AG19 AG21 AG23 AG25 AG27 AG29 AG3 AG31 AG33 AG35 AG37 AG39 AG41 AG43 AG45

VTTD VTTD VSS DDR2_ECC[1] DDR2_ECC[0] DDR2_DQ[27] VSS VSS DDR2_DQ[14] DDR2_DQ[58] VSS VSS PE3A_RX_DP[0] PE3A_RX_DP[2] PE3C_RX_DP[8] PE3C_RX_DP[10] PE_RBIAS_SENSE VSS VSS PE2B_RX_DN[7] VSS DDR2_DQ[42] VSS DDR2_DQ[34] VSA_SENSE VSA VSA VCC VTTD VTTD VCC VCC VCC VSS VCC VCC VCC VCC VCC VCC VSS PE3A_RX_DP[1]

PWR PWR GND SSTL SSTL SSTL GND GND SSTL SSTL GND GND PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 GND GND PCIEX3 GND SSTL GND SSTL I/O O PWR PWR PWR PWR PWR PWR PWR PWR GND PWR PWR PWR PWR PWR PWR GND PCIEX3 I I/O I I I I I I I/O I/O I/O I/O I/O

AG47 AG49 AG5 AG51 AG53 AG55 AG57 AG7 AG9 AH10 AH12 AH14 AH16 AH2 AH4 AH42 AH44 AH46 AH48 AH50 AH52 AH54 AH56 AH58 AH6 AH8 AJ1 AJ11 AJ13 AJ15 AJ17 AJ3 AJ43 AJ45 AJ47 AJ49 AJ5 AJ51 AJ53 AJ55 AJ57 AJ7

PE3D_RX_DP[12] PE3C_RX_DP[11] VSS PE3C_RX_DP[9] PE2B_TX_DP[4] VSS VSS DDR2_DQ[43] VSS VSA VSA VSA VSA VSA VSA IVT_ID_N PE3A_RX_DN[0] PE3A_RX_DN[2] PE3C_RX_DN[8] PE3C_RX_DN[10] PE_RBIAS PE2B_TX_DP[5] PE2C_RX_DP[8] VSS VSA VSA VSA VSA VSA VSS VSS VSA PE_VREF_CAP PE3A_RX_DN[1] PE3D_RX_DN[12] PE3C_RX_DN[11] VSA PE3C_RX_DN[9] PE2B_TX_DN[4] RSVD PE2C_RX_DP[10] VSA

PCIEX3 PCIEX3 GND PCIEX3 PCIEX3 GND GND SSTL GND PWR PWR PWR PWR PWR PWR

I I

I O

I/O

O PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 GND PWR PWR PWR PWR PWR GND GND PWR PCIEX3 PCIEX3 PCIEX3 PCIEX3 PWR PCIEX3 PCIEX3 I O I/O I I I I I I I I/O O I

PCIEX3 PWR

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Table 8-2.
Land No.

Land Number (Sheet 7 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 8 of 48)

Land Name Buffer Type Direction

AJ9 AK10 AK12 AK14 AK16 AK2 AK4 AK42 AK44 AK46 AK48 AK50 AK52 AK54 AK56 AK58 AK6 AK8 AL1 AL11 AL13 AL15 AL17 AL3 AL43 AL45 AL47 AL49 AL5 AL51 AL53 AL55 AL57 AL7 AL9 AM10 AM12 AM14 AM16 AM2 AM4 AM42

VSA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS TXT_AGENT PE2B_TX_DN[5] PE2C_RX_DN[8] PE2C_RX_DP[9] VSS VSS VCC VCC VCC VCC VCC VCC VSS VSS BMCINIT VSS VCC VSS VSS RSVD PE2C_RX_DN[10] VCC VCC VCC VCC VCC VCC VCC VCC VTTD

PWR GND GND GND GND GND GND GND GND GND GND GND CMOS PCIEX3 PCIEX3 PCIEX3 GND GND PWR PWR PWR PWR PWR PWR GND GND CMOS GND PWR GND GND I I O I I

AM44 AM46 AM48 AM50 AM52 AM54 AM56 AM58 AM6 AM8 AN1 AN11 AN13 AN15 AN17 AN3 AN43 AN45 AN47 AN49 AN5 AN51 AN53 AN55 AN57 AN7 AN9 AP10 AP12 AP14 AP16 AP2

RSVD PE3D_RX_DP[14] VTTA PE2A_TX_DP[1] PE2A_TX_DP[3] VTTA VSS PE2C_RX_DN[9] VCC VCC VCC VCC VCC VCC VCC VCC CPU_ONLY_RESET PE3D_RX_DP[15] PE3D_RX_DP[13] PE2A_TX_DP[0] VCC PE2A_TX_DP[2] PE2B_TX_DP[6] VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS PE3D_RX_DN[14] RSVD PE2A_TX_DN[1] PE2A_TX_DN[3] PE2B_TX_DP[7] PE2D_RX_DP[13] VSS PCIEX3 PCIEX3 PCIEX3 PCIEX3 GND O O O I PCIEX3 PWR PCIEX3 PCIEX3 PWR GND PCIEX3 PWR PWR PWR PWR PWR PWR PWR PWR ODCMOS PCIEX3 PCIEX3 PCIEX3 PWR PCIEX3 PCIEX3 GND GND PWR PWR PWR PWR PWR PWR PWR PWR GND GND PCIEX3 I O O I/O I I O I O O I

PCIEX3 PWR PWR PWR PWR PWR PWR PWR PWR PWR

AP4 AP42 AP44 AP46 AP48 AP50 AP52 AP54 AP56 AP58

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 9 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 10 of 48)

Land Name Buffer Type Direction

AP6 AP8 AR1 AR11 AR13 AR15 AR17 AR3 AR43 AR45 AR47 AR49 AR5 AR51 AR53 AR55 AR57 AR7 AR9 AT10 AT12 AT14 AT16 AT2 AT4 AT42 AT44 AT46 AT48 AT50 AT52 AT54 AT56 AT58 AT6 AT8 AU1 AU11 AU13 AU15 AU17 AU3

VCC VCC VSS VSS VSS VSS VSS VSS BPM_N[0] PE3D_RX_DN[15] PE3D_RX_DN[13] PE2A_TX_DN[0] VSS PE2A_TX_DN[2] PE2B_TX_DN[6] RSVD PE2C_RX_DP[11] VSS VSS VSS VSS VSS VSS VSS VSS VTTD BPM_N[1] VSS BIST_ENABLE FRMAGENT VSS PE2B_TX_DN[7] PE2D_RX_DN[13] PE2D_RX_DP[12] VSS VSS VCC VCC VCC VCC VCC VCC

PWR PWR GND GND GND GND GND GND ODCMOS PCIEX3 PCIEX3 PCIEX3 GND PCIEX3 PCIEX3 O O I/O I I O

AU43 AU45 AU47 AU49 AU5 AU51 AU53 AU55 AU57 AU7 AU9 AV10 AV12 AV14 AV16 AV2

BPM_N[2] VSS VSS VSS VCC VSS VTTA RSVD PE2C_RX_DN[11] VCC VCC VCC VCC VCC VCC VCC VCC VSS BPM_N[3] RSVD PE2D_TX_DP[14] PE2D_TX_DP[12] PE2C_TX_DP[8] VSS VSS PE2D_RX_DN[12] VCC VCC VCC VCC VCC VCC VCC VCC BPM_N[5] BCLK1_DP PE2D_TX_DP[15] PE2D_TX_DP[13] VCC PE2C_TX_DP[11] PE2C_TX_DP[9] VSS

ODCMOS GND GND GND PWR GND PWR

I/O

PCIEX3 PWR PWR PWR PWR PWR PWR PWR PWR GND ODCMOS

PCIEX3 GND GND GND GND GND GND GND GND PWR ODCMOS GND CMOS CMOS GND PCIEX3 PCIEX3 PCIEX3 GND GND PWR PWR PWR PWR PWR PWR

AV4 AV42 AV44 AV46 AV48 AV50 AV52 AV54 AV56 AV58

I/O

PCIEX3 PCIEX3 PCIEX3 GND GND PCIEX3 PWR PWR PWR PWR PWR PWR PWR PWR ODCMOS CMOS PCIEX3 PCIEX3 PWR PCIEX3 PCIEX3 GND

O O O

I/O

AV6 AV8

I I

AW1 AW11 AW13

O I I

AW15 AW17 AW3 AW43 AW45 AW47 AW49 AW5 AW51 AW53 AW55

I/O I O O

O O

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 11 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 12 of 48)

Land Name Buffer Type Direction

AW57 AW7 AW9 AY10 AY12 AY14 AY16 AY2 AY4 AY42 AY44 AY46 AY48 AY50 AY52 AY54 AY56 AY58 AY6 AY8 B10 B12 B14 B16 B18 B20 B22 B24 B32 B34 B36 B38 B40 B42 B44 B46 B48 B50 B52 B54 B6 B8

VSS VCC VCC VCC VCC VCC VCC VCC VCC VTTD BPM_N[7] RSVD PE2D_TX_DN[14] PE2D_TX_DN[12] PE2C_TX_DN[8] PE2C_TX_DP[10] PE2D_RX_DP[15] PE2D_RX_DP[14] VCC VCC DDR3_DQS_DN[04] DDR3_DQ[37] DDR3_CAS_N DDR3_RAS_N DDR3_MA_PAR DDR3_MA[03] DDR3_MA[07] DDR3_BA[2] DDR3_DQ[23] DDR3_DQS_DN[11] VSS DDR3_DQS_DN[00] DDR3_DQ[00] DMI_TX_DP[0] DMI_TX_DP[2] RSVD DMI_RX_DP[1] DMI_RX_DP[3] VSS VSA VSS VSS

GND PWR PWR PWR PWR PWR PWR PWR PWR PWR ODCMOS I/O

BA1 BA11 BA13 BA15 BA17 BA3 BA43 BA45 BA47 BA49 BA5 BA51

VCC VCC VCC VCC VCC VCC BPM_N[6] BCLK1_DN PE2D_TX_DN[15] PE2D_TX_DN[13] VCC PE2C_TX_DN[11] PE2C_TX_DN[9] TEST4 PE2D_RX_DN[14] VCC VCC VCC VCC VCC VCC VCC VCC VSS BPM_N[4] VSS VSS VSS VSS PE2C_TX_DN[10] PE2D_RX_DN[15] VSS VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS

PWR PWR PWR PWR PWR PWR ODCMOS CMOS PCIEX3 PCIEX3 PWR PCIEX3 PCIEX3 O O I PCIEX3 PWR PWR PWR PWR PWR PWR PWR PWR GND ODCMOS GND GND GND GND PCIEX3 PCIEX3 GND PWR PWR GND GND GND GND GND GND GND GND O I I/O I I/O I O O

PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PWR PWR SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL SSTL PCIEX PCIEX

O O O O I I

BA53 BA55 BA57 BA7 BA9 BB10 BB12 BB14

I/O I/O O O O O O O I/O I/O

BB16 BB2 BB4 BB42 BB44 BB46 BB48 BB50 BB52 BB54 BB56

I/O I/O O O

BB58 BB6 BB8 BC1 BC11

PCIEX PCIEX GND PWR GND GND

I I

BC13 BC15 BC17 BC3 BC43 BC45

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 13 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 14 of 48)

Land Name Buffer Type Direction

BC47 BC49 BC5 BC51 BC53 BC55 BC57 BC7 BC9 BD10 BD12 BD14 BD16 BD2 BD4 BD42 BD44 BD46 BD48 BD50 BD52 BD54 BD56 BD58 BD6 BD8 BE1 BE11 BE13 BE15 BE17 BE3 BE43 BE45 BE47 BE49 BE5 BE51 BE53 BE55 BE57 BE7

RSVD SOCKET_ID[1] VSS ERROR_N[2] VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTTD RSVD RSVD RSVD ERROR_N[0] PROCHOT_N VSS VSS QPI0_DRX_DP[07] VSS VSS VCC VCC VCC VCC VCC VCC RSVD RSVD RSVD VSS VCC VSS QPI0_DRX_DP[02] QPI0_DRX_DP[03] QPI0_DRX_DP[08] VCC GND PWR GND QPI QPI QPI PWR I I I ODCMOS ODCMOS GND GND QPI GND GND PWR PWR PWR PWR PWR PWR I O I/O CMOS GND ODCMOS GND GND GND GND GND GND GND GND GND GND GND PWR O I

BE9 BF10 BF12 BF14 BF16 BF2 BF4 BF42 BF44 BF46 BF48 BF50 BF52 BF54 BF56 BF58 BF6 BF8 BG1 BG11 BG13 BG15 BG17 BG3 BG43 BG45 BG47 BG49 BG5 BG51 BG53 BG55 BG57 BG7 BG9 BH10 BH12 BH14 BH16 BH2 BH4 BH42

VCC VCC VCC VCC VCC VCC VCC VSS VSS RSVD PEHPSDA QPI0_DRX_DP[06] QPI0_DRX_DP[01] QPI0_DRX_DP[05] QPI0_DRX_DP[04] QPI0_DRX_DN[07] VCC VCC VCC VCC VCC VCC VCC VCC RSVD RSVD VSS QPI0_DRX_DP[17] VCC QPI0_DRX_DP[00] QPI0_DRX_DN[02] QPI0_DRX_DN[03] QPI0_DRX_DN[08] VCC VCC VCC VCC VCC VCC VCC VCC VTTD

PWR PWR PWR PWR PWR PWR PWR GND GND

ODCMOS QPI QPI QPI QPI QPI PWR PWR PWR PWR PWR PWR PWR PWR

I/O I I I I I

GND QPI PWR QPI QPI QPI QPI PWR PWR PWR PWR PWR PWR PWR PWR PWR I I I I I

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Table 8-2.
Land No.

Land Number (Sheet 15 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 16 of 48)

Land Name Buffer Type Direction

BH44 BH46 BH48 BH50 BH52 BH54 BH56 BH58 BH6 BH8 BJ1 BJ11 BJ13 BJ15 BJ17 BJ3 BJ43 BJ45 BJ47 BJ49 BJ5 BJ51 BJ53 BJ55 BJ57 BJ7 BJ9 BK10 BK12 BK14 BK16 BK2 BK4 BK42 BK44 BK46 BK48 BK50 BK52 BK54 BK56 BK58

RSVD RSVD PEHPSCL QPI0_DRX_DN[06] QPI0_DRX_DN[01] QPI0_DRX_DN[05] QPI0_DRX_DN[04] VSS VCC VCC VCC VCC VCC VCC VCC VCC RSVD RSVD PECI QPI0_DRX_DN[17] VCC QPI0_DRX_DN[00] PWRGOOD VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VSS RSVD VSS VSS VSS VSS VSS VTTD QPI0_CLKRX_DP GND GND GND GND GND PWR QPI I PECI QPI PWR QPI CMOS GND GND PWR PWR PWR PWR PWR PWR PWR PWR GND I I I/O I ODCMOS QPI QPI QPI QPI GND PWR PWR PWR PWR PWR PWR PWR PWR I/O I I I I

BK6 BK8 BL1 BL11 BL13 BL15 BL17 BL3 BL43 BL45 BL47 BL49 BL5 BL51 BL53 BL55 BL57 BL7 BL9 BM10 BM12 BM14 BM16 BM2 BM4 BM42 BM44 BM46 BM48 BM50 BM52 BM54 BM56 BM58 BM6 BM8 BN1 BN11 BN13 BN15 BN17 BN3

VCC VCC VSS VSS VSS VSS VSS VSS RSVD RSVD THERMTRIP_N VSS VSS VTTD QPI0_DRX_DP[13] QPI0_DRX_DP[11] QPI0_DRX_DP[09] VSS VSS VSS VSS VSS VSS VSS VSS VTTD RSVD RSVD QPI0_DRX_DN[19] QPI0_DRX_DP[16] QPI0_DRX_DP[14] QPI0_DRX_DP[12] QPI0_DRX_DP[10] QPI0_CLKRX_DN VSS VSS VCC VCC VCC VCC VCC VCC

PWR PWR GND GND GND GND GND GND

ODCMOS GND GND PWR QPI QPI QPI GND GND GND GND GND GND GND GND PWR

I I I

QPI QPI QPI QPI QPI QPI GND GND PWR PWR PWR PWR PWR PWR

I I I I I I

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 17 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 18 of 48)

Land Name Buffer Type Direction

BN43 BN45 BN47 BN49 BN5 BN51 BN53 BN55 BN57 BN7 BN9 BP10 BP12 BP14 BP16 BP2 BP4 BP42 BP44 BP46 BP48 BP50 BP52 BP54 BP56 BP58 BP6 BP8 BR1 BR11 BR13 BR15 BR17 BR3 BR43 BR45 BR47 BR49 BR5 BR51 BR53 BR55

VSS VSS RSVD QPI0_DRX_DN[18] VCC QPI0_DRX_DP[15] QPI0_DRX_DN[13] QPI0_DRX_DN[11] QPI0_DRX_DN[09] VCC VCC VCC VCC VCC VCC VCC VCC VTTD_SENSE RSVD RSVD QPI0_DRX_DP[19] QPI0_DRX_DN[16] QPI0_DRX_DN[14] QPI0_DRX_DN[12] QPI0_DRX_DN[10] VSS VCC VCC VCC VCC VCC VCC VCC VCC RSVD SVIDDATA RSVD QPI0_DRX_DP[18] VCC QPI0_DRX_DN[15] VSS VTTD

GND GND

BR57 BR7 BR9

VSS VCC VCC VCC VCC VCC VCC VCC VCC VSS_VTTD_SENSE RSVD VSS VSS VSS VSS VSS VSS QPI0_DTX_DP[05] VCC VCC VCC VCC VCC VCC VCC VCC RSVD VSS VTTD SKTOCC_N VCC VSS QPI0_DTX_DP[02] QPI0_DTX_DP[04] QPI0_DTX_DP[07] VCC VCC VCC VCC VCC VCC VCC

GND PWR PWR PWR PWR PWR PWR PWR PWR O

QPI PWR QPI QPI QPI QPI PWR PWR PWR PWR PWR PWR PWR PWR

BT10 BT12

I I I I

BT14 BT16 BT2 BT4 BT42 BT44 BT46 BT48 BT50 BT52 BT54 BT56

GND GND GND GND GND GND QPI PWR PWR PWR PWR PWR PWR PWR PWR O

BT58 BT6 BT8

QPI QPI QPI QPI QPI GND PWR PWR PWR PWR PWR PWR PWR PWR

I I I I I

BU1 BU11 BU13 BU15 BU17 BU3 BU43 BU45 BU47 BU49 BU5 BU51 BU53 BU55 BU57

GND PWR O PWR GND QPI QPI QPI PWR PWR PWR PWR PWR PWR PWR O O O

ODCMOS

I/O

BU7 BU9

QPI PWR QPI GND PWR

BV10 BV12

BV14 BV16 BV2

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 19 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 20 of 48)

Land Name Buffer Type Direction

BV4 BV42 BV44 BV46 BV48 BV50 BV52 BV54 BV56 BV58 BV6 BV8 BW1 BW11 BW13 BW15 BW17 BW3 BW43 BW45 BW47 BW49 BW5 BW51 BW53 BW55 BW57 BW7 BW9 BY10 BY12 BY14 BY16 BY18 BY2 BY20 BY22 BY24 BY26 BY28 BY30 BY32

VCC VTTD TMS QPI0_DTX_DP[09] QPI0_DTX_DP[06] QPI0_DTX_DP[00] QPI0_DTX_DP[01] QPI0_DTX_DP[03] QPI0_DTX_DP[08] QPI0_DTX_DN[05] VCC VCC VSS VSS VSS VSS VSS VCC_SENSE TDI QPI0_DTX_DN[09] QPI0_DTX_DN[06] QPI0_DTX_DN[00] VSS QPI0_DTX_DN[01] QPI0_DTX_DN[02] QPI0_DTX_DN[04] QPI0_DTX_DN[07] VSS DDR0_DQ[28] DDR0_DQ[24] DDR0_DQ[25] VCCPLL DDR_VREFDQRX_C01 VCC VSS_VCC_SENSE VTTD VTTD VSS VCC VCC VCC VCC

PWR PWR CMOS QPI QPI QPI QPI QPI QPI QPI PWR PWR GND GND GND GND GND O CMOS QPI QPI QPI GND QPI QPI QPI QPI GND SSTL SSTL SSTL PWR DC PWR O PWR PWR GND PWR PWR PWR PWR I I/O I/O I/O O O O O I O O O I O O O O O O O

BY34 BY36 BY38 BY4 BY40 BY42 BY44 BY46 BY48 BY50 BY52 BY54 BY56 BY58 BY6 BY8 C11 C13 C15 C17 C19 C21 C23 C25 C3 C33 C35 C37 C39 C41 C43 C45 C47 C49 C5 C51 C53 C55 C7 C9 CA1 CA11

VCC VCC VCC VSS VCC VSS TCK RSVD QPI0_DTX_DP[12] QPI0_DTX_DP[13] QPI0_DTX_DN[11] QPI0_DTX_DN[03] QPI0_DTX_DN[08] VSS DDR0_DQ[04] VSS VSS VSS VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 DDR3_ECC[3] VSS VSS DDR3_DQ[21] DDR3_DQ[02] VSS VSS DMI_TX_DP[1] DMI_TX_DP[3] DMI_RX_DP[0] DMI_RX_DP[2] VSS PE1A_RX_DP[0] RSVD VSS DDR3_DQ[52] DDR3_DQ[34] DDR0_DQ[12] VSS

PWR PWR PWR GND PWR GND CMOS I

QPI QPI QPI QPI QPI GND SSTL GND GND GND PWR PWR PWR PWR PWR SSTL GND GND SSTL SSTL GND GND PCIEX PCIEX PCIEX PCIEX GND PCIEX3

O O O O O

I/O

I/O

I/O I/O

O O I I

GND SSTL SSTL SSTL GND I/O I/O I/O

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 21 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 22 of 48)

Land Name Buffer Type Direction

CA13 CA15 CA17 CA19 CA21 CA23 CA25 CA27 CA29 CA3 CA31 CA33 CA35 CA37 CA39 CA41 CA43 CA45 CA47 CA49 CA5 CA51 CA53 CA55 CA57 CA7 CA9 CB10 CB12 CB14 CB16 CB18 CB2 CB20 CB22 CB24 CB26 CB28 CB30 CB32 CB34 CB36

VCCPLL VCCPLL DDR01_RCOMP[0] VSS VTTD VTTD VCC VSS VCC DDR0_DQ[13] VSS VSS VSS VSS VSS VSS TDO RSVD QPI0_DTX_DN[12] QPI0_DTX_DN[13] VSS QPI0_DTX_DP[11] VTTA VSS VSS DDR0_DQ[05] DDR0_DQ[29] DDR0_DQS_DP[12] DDR0_DQ[26] DDR0_ECC[4] VSS DDR_RESET_C01_N DDR0_DQ[08] DDR01_RCOMP[2] MEM_HOT_C01_N DDR0_ODT[4] DDR0_CS_N[6] DDR0_CS_N[3] DDR0_DQ[37] DDR0_DQS_DN[13] DDR0_DQ[39] VSS

PWR PWR Analog GND PWR PWR PWR GND PWR SSTL GND GND GND GND GND GND ODCMOS O I/O I

CB38 CB4 CB40 CB42 CB44 CB46 CB48 CB50 CB52 CB54 CB56 CB6 CB8 CC11 CC13 CC15 CC17 CC19

DDR0_DQ[48] DDR0_DQ[09] DDR0_DQS_DN[06] DDR0_DQ[55] SVIDCLK VSS VSS VSS VSS ERROR_N[1] VSS VSS VSS DDR0_DQS_DN[12] VSS DDR0_ECC[1] DDR0_DQS_DP[08] DDR01_RCOMP[1] DDR0_PAR_ERR_N DDR0_CS_N[2] DDR0_CS_N[7] DDR0_ODT[5] VSS VSS DDR0_DQ[33] DDR0_DQS_DP[04] DDR0_DQ[35] DDR0_DQ[52] DDR0_DQS_DP[15] DDR0_DQ[54] VSS VTTA VSS VSS DDR0_DQS_DP[10] CAT_ERR_N QPI_RBIAS_SENSE QPI1_DRX_DP[00] DDR0_DQ[00] VSS DDR0_DQS_DN[03] DDR0_DQ[27]

SSTL SSTL SSTL SSTL ODCMOS GND GND GND GND ODCMOS GND GND GND SSTL GND SSTL SSTL Analog SSTL SSTL SSTL SSTL GND GND SSTL SSTL SSTL SSTL SSTL SSTL GND PWR GND GND SSTL ODCMOS Analog QPI SSTL GND SSTL SSTL

I/O I/O I/O I/O O

I/O

I/O I/O I I O O O

QPI QPI GND QPI PWR GND GND SSTL SSTL SSTL SSTL SSTL GND CMOS1.5v SSTL Analog ODCMOS SSTL SSTL SSTL SSTL SSTL SSTL GND

O O

CC21 CC23 CC25

CC27 CC29 CC3 CC31

I/O I/O I/O I/O I/O I/O

I/O I/O I/O I/O I/O

CC33 CC35 CC37 CC39 CC41 CC43

O I/O I I/O O O O I/O I/O I/O

CC45 CC47 CC49 CC5 CC51 CC53 CC55 CC7 CC9 CD10 CD12

I/O I/O I I I/O

I/O I/O

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 23 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 24 of 48)

Land Name Buffer Type Direction

CD14 CD16 CD18 CD20 CD22 CD24 CD26 CD28 CD30 CD32 CD34 CD36 CD38 CD4 CD40 CD42 CD44 CD46 CD48 CD50 CD52 CD54 CD56 CD6 CD8 CE11 CE13 CE15 CE17 CE19 CE21 CE23 CE25 CE27 CE29 CE3 CE31 CE33 CE35 CE37 CE39 CE41

DDR0_ECC[5] DDR0_DQS_DP[17] VSS VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 DDR0_DQ[36] DDR0_DQS_DP[13] DDR0_DQ[38] VSS DDR0_DQ[49] DDR0_DQS_DN[10] DDR0_DQS_DP[06] DDR0_DQ[51] RSVD QPI0_DTX_DP[10] QPI0_DTX_DP[15] QPI0_DTX_DP[16] QPI0_DTX_DP[17] QPI1_DRX_DP[02] QPI1_DRX_DP[01] VSS DDR0_DQ[01] DDR0_DQS_DP[03] VSS DDR0_ECC[0] DDR0_DQS_DN[08] DDR0_CKE[5] DDR0_CLK_DN[2] DDR0_CLK_DN[1] DDR0_ODT[0] DDR0_ODT[1] DDR0_RAS_N DDR0_DQS_DN[01] DDR0_DQ[32] DDR0_DQS_DN[04] DDR0_DQ[34] DDR0_DQ[53] DDR0_DQS_DN[15] DDR0_DQ[50]

SSTL SSTL GND PWR PWR PWR PWR PWR SSTL SSTL SSTL GND SSTL SSTL SSTL SSTL

I/O I/O

CE43 CE45 CE47 CE49 CE5 CE51 CE53 CE55

RSVD QPI0_CLKTX_DP QPI0_DTX_DP[14] QPI0_DTX_DP[19] VSS QPI0_DTX_DP[18] QPI_RBIAS QPI1_DRX_DN[00] DDR0_DQS_DP[09] VSS DDR0_DQ[31] VSS VSS DDR0_DQS_DN[17] DDR0_ECC[3] DDR0_CKE[4] DDR0_CLK_DN[3] DDR0_CLK_DN[0] DDR0_CS_N[5] DDR0_ODT[3] VSS VSS VSS VSS VSS DDR0_DQS_DP[01] VSS VSS RSVD QPI0_DTX_DN[10] QPI0_DTX_DN[15] QPI0_DTX_DN[16] QPI0_DTX_DN[17] QPI1_DRX_DN[02] QPI1_DRX_DN[01] VSS DDR0_DQS_DN[09] RSVD DDR0_DQ[20] VSS DDR0_ECC[6] DDR0_MA[14] SSTL GND SSTL SSTL I/O O I/O QPI QPI QPI QPI QPI QPI GND SSTL I/O O O O O I I QPI QPI QPI GND QPI Analog QPI SSTL GND SSTL GND GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND GND GND GND GND SSTL GND GND I/O I/O I/O O O O O O I/O O I/O I I/O O O O

I/O I/O I/O

CE7 CE9 CF10 CF12

I/O I/O I/O I/O

CF14 CF16 CF18 CF20 CF22

QPI QPI QPI QPI QPI QPI GND SSTL SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL

O O O O I I

CF24 CF26 CF28 CF30 CF32 CF34 CF36

I/O I/O

CF38 CF4 CF40

I/O I/O O O O O O O I/O I/O I/O I/O I/O I/O I/O

CF42 CF44 CF46 CF48 CF50 CF52 CF54 CF56 CF6 CF8 CG11 CG13 CG15 CG17 CG19

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 25 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 26 of 48)

Land Name Buffer Type Direction

CG21 CG23 CG25 CG27 CG29 CG3 CG31 CG33 CG35 CG37 CG39 CG41 CG43 CG45 CG47 CG49 CG5 CG51 CG53 CG55 CG7 CG9 CH10 CH12 CH14 CH16 CH18 CH20 CH22 CH24 CH26 CH28 CH30 CH32 CH34 CH36 CH38 CH4 CH40 CH42 CH44 CH46

DDR0_CLK_DP[2] DDR0_CLK_DP[1] DDR0_MA[02] DDR0_CS_N[4] DDR0_MA[13] DDR0_DQ[14] VSS VSS VSS VSS VSS VSS VSS QPI0_CLKTX_DN QPI0_DTX_DN[14] QPI0_DTX_DN[19] DDR0_DQ[15] QPI0_DTX_DN[18] VSS VTTA DDR0_DQS_DN[00] VSS DDR0_DQ[30] VSS DDR0_DQS_DN[02] VSS DDR0_ECC[2] DDR0_CKE[2] DDR0_CLK_DP[3] DDR0_CLK_DP[0] DDR0_CS_N[1] DDR0_ODT[2] DDR0_DQ[45] DDR0_DQS_DN[14] DDR0_DQ[47] VSS DDR0_DQ[56] DDR0_DQ[10] DDR0_DQS_DN[07] DDR0_DQ[58] VSS VSS

SSTL SSTL SSTL SSTL SSTL SSTL GND GND GND GND GND GND GND QPI QPI QPI SSTL QPI GND PWR SSTL GND SSTL GND SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL SSTL SSTL SSTL GND GND

O O O O O I/O

CH48 CH50 CH52 CH54 CH56 CH6 CH8 CJ11 CJ13 CJ15 CJ17 CJ19 CJ21

VSS VSS VSS VSS EAR_N VSS DDR0_DQS_DP[00] VSS DDR0_DQS_DP[11] DDR0_DQ[22] VSS VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 VSS VSS DDR0_DQ[41] DDR0_DQS_DP[05] DDR0_DQ[43] DDR0_DQ[60] DDR0_DQS_DP[16] DDR0_DQ[62] VSS VSS VSS VTTA DDR0_DQ[11] VSS QPI1_DRX_DP[09] QPI1_DRX_DP[03] DDR0_DQ[06] VSS VSS DDR0_DQ[16] DDR0_DQS_DP[02] DDR0_DQ[18] DDR0_ECC[7] DDR0_MA[12] DDR0_MA[08] DDR0_MA[03]

GND GND GND GND ODCMOS GND SSTL GND SSTL SSTL GND PWR PWR PWR PWR PWR GND GND SSTL SSTL SSTL SSTL SSTL SSTL GND GND GND PWR SSTL GND QPI QPI SSTL GND GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL I/O I/O I/O I/O O O O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

O O O I/O O

CJ23 CJ25 CJ27 CJ29 CJ3 CJ31 CJ33

I/O

CJ35 CJ37

I/O

CJ39 CJ41

I/O

CJ43 CJ45

I/O O O O O O I/O I/O I/O

CJ47 CJ49 CJ5 CJ51 CJ53 CJ55 CJ7 CJ9 CK10 CK12

I/O I/O I/O I/O

CK14 CK16 CK18 CK20 CK22 CK24

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 27 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 28 of 48)

Land Name Buffer Type Direction

CK26 CK28 CK30 CK32 CK34 CK36 CK38 CK4 CK40 CK42 CK44 CK46 CK48 CK50 CK52 CK54 CK56 CK6 CK8 CL11 CL13 CL15 CL17 CL19 CL21 CL23 CL25 CL27 CL29 CL3 CL31 CL33 CL35 CL37 CL39 CL41 CL43 CL45 CL47 CL49 CL5 CL51

DDR0_MA[10] DDR0_CS_N[9] DDR0_DQ[44] DDR0_DQS_DP[14] DDR0_DQ[46] VSS DDR0_DQ[57] VSS DDR0_DQS_DP[07] DDR0_DQ[59] RESET_N QPI1_DRX_DP[18] QPI1_DRX_DP[16] QPI1_DRX_DN[14] QPI1_DRX_DP[10] QPI1_DRX_DP[05] QPI1_DRX_DP[04] VSS DDR0_DQ[02] DDR0_DQ[21] DDR0_DQS_DN[11] DDR0_DQ[23] VSS DDR0_CKE[0] DDR0_MA[11] DDR0_MA[05] DDR0_MA[00] DDR0_CS_N[8] DDR0_CAS_N DDR1_DQ[05] DDR0_DQ[40] DDR0_DQS_DN[05] DDR0_DQ[42] DDR0_DQ[61] DDR0_DQS_DN[16] DDR0_DQ[63] VSS QPI1_DRX_DP[19] QPI1_DRX_DP[17] QPI1_DRX_DN[15] VSS QPI1_DRX_DN[13]

SSTL SSTL SSTL SSTL SSTL GND SSTL GND SSTL SSTL CMOS QPI QPI QPI QPI QPI QPI GND SSTL SSTL SSTL SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND QPI QPI QPI GND QPI

O O I/O I/O I/O

CL53 CL55 CL7 CL9 CM10 CM12

QPI1_DRX_DN[09] QPI1_DRX_DN[03] DDR0_DQ[07] DDR0_DQ[03] VSS DDR0_DQ[17] VSS DDR0_DQ[19] DDR0_CKE[1] DDR0_BA[2] DDR0_MA[07] DDR0_MA[04] DDR0_MA_PAR DDR0_BA[0] VSS VSS VSS VSS VSS DDR1_DQ[04] VSS VSS BCLK0_DN QPI1_DRX_DN[18] QPI1_DRX_DN[16] QPI1_DRX_DP[14] QPI1_DRX_DN[10] QPI1_DRX_DN[05] QPI1_DRX_DN[04] VSS VSS VSS VSS VSS VSS DDR0_MA[15] DDR0_MA[09] DDR0_MA[06] DDR0_CS_N[0] DDR0_BA[1] DDR0_WE_N VSS

QPI QPI SSTL SSTL GND SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND GND GND GND GND SSTL GND GND CMOS QPI QPI QPI QPI QPI QPI GND GND GND GND GND GND SSTL SSTL SSTL SSTL SSTL SSTL GND

I I I/O I/O

I/O

I/O

CM14 CM16

I/O O O O O O O

I/O I/O I I I I I I I

CM18 CM20 CM22 CM24 CM26 CM28 CM30 CM32 CM34 CM36

I/O I/O I/O I/O

CM38 CM4 CM40 CM42 CM44

I/O

I I I I I I I

O O O O O O I/O I/O I/O I/O I/O I/O I/O

CM46 CM48 CM50 CM52 CM54 CM56 CM6 CM8 CN11 CN13 CN15 CN17 CN19 CN21

O O O O O O

I I I

CN23 CN25 CN27 CN29

CN3

Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 29 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 30 of 48)

Land Name Buffer Type Direction

CN31 CN33 CN35 CN37 CN39 CN41 CN43 CN45 CN47 CN49 CN5 CN51 CN53 CN55 CN57 CN7 CN9 CP10 CP12 CP14 CP16 CP18 CP2 CP20 CP22 CP24 CP26 CP28 CP30 CP32 CP34 CP36 CP38 CP4 CP40 CP42 CP44 CP46 CP48 CP50 CP52 CP54

VSS VSS VSS VSS VSS DDR_VREFDQTX_C01 BCLK0_DP QPI1_DRX_DN[19] QPI1_DRX_DN[17] QPI1_DRX_DP[15] VSS QPI1_DRX_DP[13] VSS VSS VSS VSS VSS DDR1_DQ[19] VSS DDR1_DQS_DN[12] VSS DDR0_CKE[3] DDR1_DQ[01] VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01 DDR1_DQ[33] DDR1_DQS_DP[04] DDR1_DQ[35] VSS DDR1_DQS_DP[15] DDR1_DQ[00] VSS VSS VSS VSS VSS VSS VSS RSVD

GND GND GND GND GND DC CMOS QPI QPI QPI GND QPI GND GND GND GND GND SSTL GND SSTL GND SSTL SSTL PWR PWR PWR PWR PWR SSTL SSTL SSTL GND SSTL SSTL GND GND GND GND GND GND GND I/O I/O I/O I/O I/O O I/O I/O I/O I O I I I I

CP56 CP58 CP6 CP8 CR1 CR11 CR13 CR15 CR17 CR19 CR21 CR23 CR25 CR27 CR29 CR3 CR31 CR33 CR35 CR37 CR39 CR41 CR43 CR45 CR47 CR49 CR5 CR51 CR53 CR55 CR57 CR7 CR9 CT10 CT12 CT14 CT16 CT18 CT2 CT20 CT22 CT24

VSS QPI1_DRX_DP[06] DDR1_DQ[20] DDR1_DQS_DP[11] DDR1_DQS_DN[09] VSS DDR1_DQ[24] DDR1_DQS_DN[03] DDR1_DQ[26] DDR1_CKE[4] DDR1_CS_N[8] DDR1_CS_N[2] DDR0_MA[01] DDR1_CS_N[3] DDR1_DQ[37] DDR1_DQS_DP[00] DDR1_DQS_DN[13] DDR1_DQ[39] VSS DDR1_DQ[48] DDR1_DQS_DN[06] DDR1_DQ[50] SVIDALERT_N VTTA VSS VSS VSS VTTA QPI1_DRX_DN[11] QPI1_CLKRX_DP QPI1_DRX_DP[07] DDR1_DQ[16] VSS DDR1_DQ[18] DDR1_DQ[28] DDR1_DQS_DP[12] DDR1_DQ[30] DDR1_CKE[5] DDR1_DQS_DP[09] DDR1_CKE[0] DDR1_ODT[0] DDR1_CS_N[5]

GND QPI SSTL SSTL SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL SSTL SSTL CMOS PWR GND GND GND PWR QPI QPI QPI SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL I/O I/O I/O I/O O I/O O O O I I I I/O I/O I/O I/O I I/O I/O I/O O O O O O I/O I/O I/O I/O I I/O I/O I/O

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 31 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 32 of 48)

Land Name Buffer Type Direction

CT26 CT28 CT30 CT32 CT34 CT36 CT38 CT4 CT40 CT42 CT44 CT46 CT48 CT50 CT52 CT54 CT56 CT58 CT6 CT8 CU1 CU11 CU13 CU15 CU17 CU19 CU21 CU23 CU25 CU27 CU29 CU3 CU31 CU33 CU35 CU37 CU39 CU41 CU43 CU45 CU47 CU49

DDR1_CS_N[7] VSS DDR1_DQ[32] DDR1_DQS_DN[04] DDR1_DQ[34] DDR1_DQ[52] DDR1_DQS_DN[15] DDR1_DQS_DN[00] DDR1_DQ[54] VSS QPI1_DTX_DP[14] QPI1_DTX_DP[08] QPI1_DTX_DP[00] QPI1_DTX_DP[01] QPI1_DRX_DN[12] TRST_N QPI1_DRX_DP[08] QPI1_DRX_DN[06] DDR1_DQ[21] DDR1_DQS_DN[11] VSS VSS DDR1_DQ[25] DDR1_DQS_DP[03] DDR1_DQ[27] DDR1_CKE[1] DDR1_PAR_ERR_N DDR1_CS_N[1] DDR1_CS_N[4] DDR1_ODT[4] DDR1_DQ[36] VSS DDR1_DQS_DP[13] DDR1_DQ[38] VSS DDR1_DQ[49] DDR1_DQS_DP[06] DDR1_DQ[51] QPI1_DTX_DP[17] QPI1_DTX_DP[11] QPI1_DTX_DP[05] QPI1_DTX_DP[02]

SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND QPI QPI QPI QPI QPI CMOS QPI QPI SSTL SSTL GND GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL SSTL GND SSTL SSTL SSTL QPI QPI QPI QPI

CU5 CU51

VSS QPI_VREF_CAP QPI1_DRX_DP[11] QPI1_CLKRX_DN QPI1_DRX_DN[07] DDR1_DQ[17] DDR1_DQS_DP[02] DDR1_DQ[23] DDR1_DQ[29] VSS DDR1_DQ[31] VSS DDR1_DQ[06] DDR1_CLK_DN[0] DDR1_CLK_DN[1] DDR1_CLK_DP[2] DDR1_ODT[3] DDR1_WE_N VSS VSS VSS DDR1_DQ[53] VSS DDR1_DQ[02] DDR1_DQ[55] VSS QPI1_DTX_DN[14] QPI1_DTX_DN[08] QPI1_DTX_DN[00] QPI1_DTX_DN[01] QPI1_DRX_DP[12] VSS QPI1_DRX_DN[08] VSS VSS DDR1_DQS_DN[02] TEST1 VSS VSS VSS DRAM_PWR_OK_C01 VCCD_01

GND QPI QPI QPI QPI SSTL SSTL SSTL SSTL GND SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL GND GND GND SSTL GND SSTL SSTL GND QPI QPI QPI QPI QPI GND QPI GND GND SSTL I/O O GND GND GND CMOS1.5v PWR I I O O O O I I/O I/O I/O I/O O O O O O I/O I/O I I I I/O I/O I/O I/O

I/O I/O I/O I/O I/O I/O I/O

CU53 CU55 CU57 CU7 CU9 CV10 CV12 CV14

O O O O I I I I I/O I/O

CV16 CV18 CV2 CV20 CV22 CV24 CV26 CV28 CV30 CV32 CV34 CV36

I/O I/O I/O O I O O O I/O

CV38 CV4 CV40 CV42 CV44 CV46 CV48 CV50 CV52 CV54

I/O I/O

CV56 CV58 CV6

I/O I/O I/O O O O O

CV8 CW1 CW11 CW13 CW15 CW17 CW19

Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 33 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 34 of 48)

Land Name Buffer Type Direction

CW21 CW23 CW25 CW27 CW29 CW3 CW31 CW33 CW35 CW37 CW39 CW41 CW43 CW45 CW47 CW49 CW5 CW51 CW53 CW55 CW57 CW7 CW9 CY10 CY12 CY14 CY16 CY18 CY2 CY20 CY22 CY24 CY26 CY28 CY30 CY32 CY34 CY36 CY38 CY4 CY40 CY42

VCCD_01 VCCD_01 VCCD_01 VCCD_01 VSS DDR1_DQ[07] VSS VSS VSS VSS VSS DDR_SDA_C01 QPI1_DTX_DN[17] QPI1_DTX_DN[11] QPI1_DTX_DN[05] QPI1_DTX_DN[02] VSS VSS VSS VSS VSS VSS DDR1_DQ[22] VSS VSS DDR1_DQS_DP[17] VSS DDR1_CKE[2] VSS DDR1_CLK_DP[0] DDR1_CLK_DP[1] DDR1_CLK_DN[2] DDR1_ODT[2] DDR1_ODT[5] DDR1_CAS_N DDR1_DQ[45] DDR1_DQS_DN[05] VSS DDR1_DQS_DN[16] DDR1_DQ[03] VSS DDR_SCL_C01

PWR PWR PWR PWR GND SSTL GND GND GND GND GND ODCMOS QPI QPI QPI QPI GND GND GND GND GND GND SSTL GND GND SSTL GND SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL SSTL GND ODCMOS I/O I/O I/O O O O O O O I/O I/O O I/O I/O I/O O O O O I/O

CY44 CY46 CY48 CY50 CY52 CY54 CY56 CY58 CY6 CY8 D10 D12 D14 D16 D18 D2 D20 D22 D24 D26 D32 D34 D36 D38 D4 D40 D42 D44 D46 D48 D50 D52 D54 D56 D6 D8 DA11 DA13 DA15 DA17 DA19 DA21

VSS RSVD RSVD VSS SOCKET_ID[0] QPI1_CLKTX_DN RSVD RSVD DDR1_DQ[12] VSS DDR3_DQS_DP[04] DDR3_DQ[32] DDR3_ODT[4] DDR3_CS_N[8] DDR3_MA[10] VSS DDR3_MA[04] DDR3_MA[08] DDR3_MA[14] VSS DDR3_DQ[18] DDR3_DQS_DP[11] VSS DDR3_DQS_DP[00] TEST3 DDR3_DQ[05] DMI_TX_DN[0] DMI_TX_DN[2] RSVD DMI_RX_DN[1] DMI_RX_DN[3] PE1A_RX_DP[1] PE1A_RX_DP[2] RSVD DDR3_DQ[53] VSS VSS DDR1_ECC[4] DDR1_ECC[6] DDR1_CKE[3] DDR1_MA[09] DDR1_CLK_DN[3]

GND

GND CMOS QPI I O

SSTL GND SSTL SSTL SSTL SSTL SSTL GND SSTL SSTL SSTL GND SSTL SSTL GND SSTL

I/O

I/O I/O O O O

O O O

I/O I/O

I/O O

SSTL PCIEX PCIEX

I/O O O

PCIEX PCIEX PCIEX3 PCIEX3

I I I I

SSTL GND GND SSTL SSTL SSTL SSTL SSTL

I/O

I/O I/O O O O

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 35 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 36 of 48)

Land Name Buffer Type Direction

DA23 DA25 DA27 DA29 DA3 DA31 DA33 DA35 DA37 DA39 DA41 DA43 DA45 DA47 DA49 DA5 DA51 DA53 DA55 DA57 DA7 DA9 DB10 DB12 DB14 DB16 DB18 DB2 DB20 DB22 DB24 DB26 DB28 DB30 DB32 DB34 DB36 DB38 DB4 DB40 DB42 DB44

DDR1_MA[03] DDR1_ODT[1] DDR1_CS_N[9] DDR1_CS_N[6] VSS DDR1_DQ[44] DDR1_DQ[40] DDR1_DQ[43] DDR1_DQ[60] DDR1_DQ[62] VSS VSS VSS VSS VTTA VSS VSS QPI1_DTX_DP[03] SAFE_MODE_BOOT RSVD DDR1_DQ[08] VSS DDR1_DQ[14] VSS DDR1_DQS_DN[17] DDR1_ECC[3] DDR1_MA[14] VSS DDR1_MA[08] DDR1_MA[04] DDR1_CS_N[0] DDR1_BA[0] DDR1_RAS_N DDR1_MA[13] VSS DDR1_DQS_DP[05] VSS DDR1_DQS_DP[16] TEST0 DDR1_DQ[59] QPI1_DTX_DP[19] QPI1_DTX_DP[16]

SSTL SSTL SSTL SSTL GND SSTL SSTL SSTL SSTL SSTL GND GND GND GND PWR GND GND QPI CMOS

O O O O

DB46 DB48 DB50 DB52 DB54

QPI1_DTX_DP[13] QPI1_DTX_DP[10] QPI1_DTX_DN[07] QPI1_DTX_DN[04] QPI1_CLKTX_DP RSVD VSS DDR1_DQ[13] DDR1_DQS_DN[10] DDR1_DQ[10] DDR1_ECC[5] DDR1_DQS_DP[08] DDR1_MA[15] DDR1_MA[12] DDR1_CLK_DP[3] DDR1_MA[00] DDR1_BA[1] VSS DDR1_DQS_DP[14] DDR1_DQ[42] DDR1_DQ[61] DDR1_DQS_DP[07] VSS QPI1_DTX_DN[18] QPI1_DTX_DN[15] QPI1_DTX_DN[12] QPI1_DTX_DP[09] VSS QPI1_DTX_DP[06] QPI1_DTX_DN[03] RSVD DDR1_DQ[09] DDR1_DQS_DN[01] VSS VSS VSS DDR1_ECC[2] VCCD_01 VCCD_01 VCCD_01 VCCD_01 VCCD_01

QPI QPI QPI QPI QPI

O O O O O

I/O I/O I/O I/O I/O

DB56 DB58 DB6 DB8 DC11 DC13 DC15 DC17 DC19 DC21 DC23 DC25

GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL SSTL SSTL SSTL GND QPI QPI QPI QPI GND QPI QPI O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O

O I

DC3 DC33 DC35

SSTL GND SSTL GND SSTL SSTL SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL GND SSTL

I/O

DC37 DC39

I/O

DC41 DC43

I/O I/O O

DC45 DC47 DC49 DC5

O O O O O O

DC51 DC53 DC55 DC7 DC9 DD10 DD12

SSTL SSTL GND GND GND SSTL PWR PWR PWR PWR PWR

I/O I/O

I/O

DD14 DD16

I/O

I/O O

DD18 DD20 DD22 DD24 DD26

SSTL QPI QPI

I/O O O

Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 37 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 38 of 48)

Land Name Buffer Type Direction

DD32 DD34 DD36 DD38 DD40 DD42 DD44 DD46 DD48 DD50 DD52 DD54 DD6 DD8 DE11 DE13 DE15 DE17 DE19 DE21 DE23 DE25 DE33 DE35 DE37 DE39 DE41 DE43 DE45 DE47 DE49 DE51 DE53 DE55 DE7 DE9 DF10 DF12 DF14 DF16 DF18 DF20

DDR1_DQ[41] VSS VSS VSS DDR1_DQ[58] QPI1_DTX_DN[19] QPI1_DTX_DN[16] QPI1_DTX_DN[13] QPI1_DTX_DN[10] QPI1_DTX_DP[07] QPI1_DTX_DP[04] RSVD VSS DDR1_DQS_DP[10] DDR1_DQ[11] DDR1_ECC[0] DDR1_DQS_DN[08] VSS DDR1_MA[11] DDR1_MA[06] DDR1_MA[01] DDR1_MA_PAR DDR1_DQS_DN[14] DDR1_DQ[47] DDR1_DQ[56] DDR1_DQS_DN[07] VSS QPI1_DTX_DP[18] QPI1_DTX_DP[15] QPI1_DTX_DP[12] QPI1_DTX_DN[09] QPI1_DTX_DN[06] VSS RSVD VSS DDR1_DQS_DP[01] DDR1_DQ[15] VSS DDR1_ECC[1] DDR1_ECC[7] DDR1_BA[2] DDR1_MA[07]

SSTL GND GND GND SSTL QPI QPI QPI QPI QPI QPI

I/O

DF22 DF24 DF26 DF34

DDR1_MA[05] DDR1_MA[02] DDR1_MA[10] DDR1_DQ[46] VSS DDR1_DQ[57] DDR1_DQ[63] VSS VSS VSS VSS VSS VSS VSS VSS DDR3_DQS_DP[13] MEM_HOT_C23_N DDR3_CS_N[7] DDR3_ODT[2] DDR3_BA[1] DDR3_MA[01] DDR3_MA[12] DDR3_ECC[2] DDR3_DQS_DP[08] VSS VSS VSS DDR3_DQS_DP[02] DDR3_DQ[20] DDR3_DQ[03] DDR3_DQS_DP[09] VSS DMI_TX_DN[1] DMI_TX_DN[3] DMI_RX_DN[0] DMI_RX_DN[2] VSS PE1A_RX_DN[0] RSVD PE1A_RX_DP[3] RSVD DDR3_DQ[48]

SSTL SSTL SSTL SSTL GND SSTL SSTL GND GND GND GND GND GND GND GND SSTL ODCMOS SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND GND GND SSTL SSTL SSTL SSTL GND PCIEX PCIEX PCIEX PCIEX GND PCIEX3

O O O I/O

I/O O O O O O O

DF36 DF38 DF40 DF42 DF44 DF46 DF48 DF50

I/O I/O

GND SSTL SSTL SSTL SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND QPI QPI QPI QPI QPI GND O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O

DF52 DF8 E1 E11 E13 E15 E17 E19 E21 E23 E25 E27 E29 E3 E31 E33 E35 E37 E39 E41 E43 E45

I/O I/O O O O O O I/O I/O

I/O I/O I/O I/O

O O I I

GND SSTL SSTL GND SSTL SSTL SSTL SSTL I/O I/O O O I/O I/O

E47 E49 E5 E51 E53 E55 E57 E7

PCIEX3

SSTL

I/O

230

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 39 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 40 of 48)

Land Name Buffer Type Direction

E9 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F28 F30 F32 F34 F36 F38 F4 F40 F42 F44 F46 F48 F50 F52 F54 F56 F58 F6 F8 G1 G11 G13 G15 G17 G19 G21 G23 G25 G27 G29 G3

DDR3_DQ[35] DDR3_DQ[38] DDR3_DQ[36] DDR3_CS_N[2] DDR3_CS_N[6] DDR3_ODT[1] TEST2 DDR3_MA[02] DDR3_MA[06] DDR3_MA[15] DDR3_ECC[6] DDR3_DQS_DP[17] DDR3_ECC[4] DDR3_DQ[19] DDR3_DQ[17] VSS DDR3_DQ[06] DDR3_DQ[60] DDR3_DQ[04] VSS VSS RSVD VSS VSS PE1A_RX_DN[1] PE1A_RX_DN[2] RSVD RSVD DDR3_DQ[49] VSS VSS DDR3_DQS_DN[13] VCCD_23 DDR3_CS_N[3] DDR3_CS_N[5] DDR3_CS_N[0] DDR3_PAR_ERR_N DDR3_MA[09] VSS DDR3_DQS_DN[08] DDR3_ECC[0] DDR3_DQ[56]

SSTL SSTL SSTL SSTL SSTL SSTL

I/O I/O I/O O O O O

G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G5 G51 G53 G55 G57 G7

VSS DDR3_DQS_DN[02] VSS VSS DDR3_DQS_DN[09] VSS VSA VSS VSS VSA VSS VSS VSS PE1A_RX_DN[3] VSS DDR3_DQS_DP[15] VSS VSS VSS VSS VCCD_23 VCCD_23 DDR3_DQ[57] VCCD_23 VCCD_23 VCCD_23 DDR3_ECC[7] DDR3_DQS_DN[17] DDR3_ECC[5] VSS VSS DDR3_DQ[15] VSS DDR3_DQ[61] VSS PE1A_TX_DP[0] PE1A_TX_DP[2] PE1B_TX_DP[4] PE1B_TX_DP[6] PE3A_TX_DP[0] VSS VSS

GND SSTL GND GND SSTL GND PWR GND GND PWR GND GND GND PCIEX3 GND SSTL GND GND GND GND PWR PWR SSTL PWR PWR PWR SSTL SSTL SSTL GND GND SSTL GND SSTL GND PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 GND GND O O O O O I/O I/O I/O I/O I/O I/O I/O I I/O I/O

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL SSTL SSTL GND GND

O O O I/O I/O I/O I/O I/O

I/O I/O I/O

G9 H10 H12 H14 H16 H18

GND GND PCIEX3 PCIEX3 I I

H2 H20 H22 H24 H26 H28

SSTL GND GND SSTL PWR SSTL SSTL SSTL SSTL SSTL GND SSTL SSTL SSTL

I/O

H30 H32 H34

I/O

H36 H38

O O O I O

H4 H40 H42 H44 H46 H48

I/O I/O I/O

H50 H52 H54

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 41 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 42 of 48)

Land Name Buffer Type Direction

H56 H58 H6 H8 J1 J11 J13 J15 J17 J19 J21 J23 J25 J27 J29 J3 J31 J33 J35 J37 J39 J41 J43 J45 J47 J49 J5 J51 J53 J55 J57 J7 J9 K10 K12 K14 K16 K18 K2 K20 K22 K24

RSVD RSVD DDR3_DQS_DN[15] VSS DDR_VREFDQRX_C23 VSS DDR3_DQ[40] RSVD DDR3_ODT[3] DDR3_CS_N[1] DDR3_CLK_DN[1] DDR3_CLK_DN[0] DDR3_CKE[2] VSS DDR3_ECC[1] DDR3_DQS_DP[16] VSS VSS DDR3_DQ[11] DDR3_DQS_DP[01] VSS VSS PE1A_TX_DP[1] PE1A_TX_DP[3] PE1B_TX_DP[5] PE1B_TX_DP[7] VSS PE3A_TX_DP[1] PE1B_RX_DP[4] VSS PE1B_RX_DP[6] DDR3_DQS_DN[06] DDR3_DQ[42] DDR3_DQ[46] DDR3_DQS_DP[14] DDR3_DQ[44] DDR3_CS_N[9] DDR3_CS_N[4] VSS DDR3_CLK_DP[2] DDR3_CLK_DN[3] DDR3_CKE[0] SSTL SSTL SSTL SSTL SSTL GND SSTL SSTL GND GND SSTL SSTL GND GND PCIEX3 PCIEX3 PCIEX3 PCIEX3 GND PCIEX3 PCIEX3 GND PCIEX3 SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL SSTL SSTL O O O I I/O I/O I/O I/O I/O O O O I O O O O I/O I/O I/O I/O O O O O O SSTL GND DC GND SSTL I/O I I/O

K26 K28 K30 K32 K34 K36 K38 K4 K40 K42 K44 K46 K48 K50 K52 K54 K56 K58 K6 K8 L1 L11 L13 L15 L17 L19 L21 L23 L25 L27 L29 L3 L31 L33 L35 L37 L39 L41 L43 L45 L47 L49

VSS VSS VSS DDR3_DQ[29] VSS DDR3_DQ[14] DDR3_DQS_DN[10] DDR3_DQS_DN[16] DDR3_DQ[13] PE1A_TX_DN[0] PE1A_TX_DN[2] PE1B_TX_DN[4] PE1B_TX_DN[6] PE3A_TX_DN[0] PMSYNC PE1B_RX_DP[5] PE1B_RX_DP[7] RSVD DDR3_DQS_DP[06] VSS DDR3_DQ[62] DDR3_DQS_DN[05] DDR3_DQ[41] DRAM_PWR_OK_C23 DDR2_BA[1] DDR3_ODT[0] DDR3_CLK_DP[1] DDR3_CLK_DP[0] VSS DDR3_DQ[27] VSS DDR3_DQS_DN[07] DDR3_DQ[25] DDR3_DQ[28] DDR3_DQ[10] DDR3_DQS_DN[01] DDR3_DQ[09] VSS PE1A_TX_DN[1] PE1A_TX_DN[3] PE1B_TX_DN[5] PE1B_TX_DN[7]

GND GND GND SSTL GND SSTL SSTL SSTL SSTL PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 CMOS PCIEX3 PCIEX3 I/O I/O I/O I/O O O O O O I I I I/O

SSTL GND SSTL SSTL SSTL CMOS1.5v SSTL SSTL SSTL SSTL GND SSTL GND SSTL SSTL SSTL SSTL SSTL SSTL GND PCIEX3 PCIEX3 PCIEX3 PCIEX3

I/O

I/O I/O I/O I O O O O

I/O

I/O I/O I/O I/O I/O I/O

O O O O

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Table 8-2.
Land No.

Land Number (Sheet 43 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 44 of 48)

Land Name Buffer Type Direction

L5 L51 L53 L55 L57 L7 L9 M10 M12 M14 M16 M18 M2 M20 M22 M24 M26 M28 M30 M32 M34 M36 M38 M4 M40 M42 M44 M46 M48 M50 M52 M54 M56 M6 M8 N11 N13 N15 N17 N19 N21 N23

VSS PE3A_TX_DN[1] PE1B_RX_DN[4] PE2A_RX_DP[0] PE1B_RX_DN[6] DDR3_DQ[54] DDR3_DQ[43] DDR3_DQ[47] DDR3_DQS_DN[14] DDR3_DQ[45] DDR3_ODT[5] DDR2_MA_PAR DDR3_DQ[63] DDR3_CLK_DN[2] DDR3_CLK_DP[3] DDR3_CKE[1] DDR3_DQ[31] DDR3_DQ[26] DDR3_DQS_DN[12] DDR3_DQ[24] VSS VSS DDR3_DQS_DP[10] DDR3_DQS_DP[07] DDR3_DQ[12] VSS VSS VSS RSVD VSS VSS PE1B_RX_DN[5] PE1B_RX_DN[7] DDR3_DQ[55] VSS DDR3_DQS_DP[05] VSS VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23

GND PCIEX3 PCIEX3 PCIEX3 PCIEX3 SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND GND SSTL SSTL SSTL GND GND GND I/O I/O I/O O I I I I/O I/O I/O I/O I/O O O I/O O O O I/O I/O I/O I/O

N25 N27 N29 N3 N31 N33 N35 N37 N39 N41 N43 N45 N47 N49 N5 N51 N53 N55 N7 N9 P10 P12 P14 P16 P18 P20 P22 P24 P26

DDR3_CKE[3] DDR3_DQ[30] DDR3_DQS_DP[03] DDR3_DQ[58] DDR3_DQS_DP[12] VSS VSS VSS DDR3_DQ[08] VSS VSS VSA VSS VSS VSS VSA VSS PE2A_RX_DN[0] DDR3_DQ[50] VSS VSS VSS VSS DDR2_WE_N DDR2_CS_N[5] DDR2_MA[04] DDR2_MA[07] DDR2_BA[2] VSS DDR3_DQS_DN[03] VSS VSS DDR2_DQ[21] DDR2_DQ[02] VSS DDR3_DQ[59] VSS DDR_VREFDQTX_C23 PE3D_TX_DN[15] PE3C_TX_DP[8] PE3A_TX_DP[3] PE3B_TX_DP[6]

SSTL SSTL SSTL SSTL SSTL GND GND GND SSTL GND GND PWR GND GND GND PWR GND PCIEX3 SSTL GND GND GND GND SSTL SSTL SSTL SSTL SSTL GND SSTL GND GND SSTL SSTL GND SSTL GND DC PCIEX3 PCIEX3 PCIEX3 PCIEX3

O I/O I/O I/O I/O

I/O

I I/O

O O O O O

GND GND PCIEX3 PCIEX3 SSTL GND SSTL GND PWR PWR PWR PWR PWR I/O I I I/O

P28 P30 P32 P34 P36 P38 P4 P40 P42 P44 P46 P48 P50

I/O

I/O I/O

I/O

O O O O O

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Table 8-2.
Land No.

Land Number (Sheet 45 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 46 of 48)

Land Name Buffer Type Direction

P52 P54 P56 P6 P8 R11 R13 R15 R17 R19 R21 R23 R25 R27 R29 R3 R31 R33 R35 R37 R39 R41 R43 R45 R47 R49 R5 R51 R53 R55 R7 R9 T10 T12 T14 T16 T18 T20 T22 T24 T26 T28

PE3B_TX_DP[4] VSS VSS DDR3_DQ[51] VSS VSS DDR2_DQ[48] DDR2_MA[13] DDR2_BA[0] DDR2_MA[01] DDR2_MA[06] DDR2_MA[09] DDR3_CKE[4] DDR3_CKE[5] VSS VSS VSS DDR2_DQ[17] VSS DDR2_DQ[06] VSS DDR2_DQ[04] DDR_SDA_C23 PE3C_TX_DP[10] PE3A_TX_DP[2] PE3B_TX_DP[7] VSS PE3B_TX_DP[5] PRDY_N VSS VSS DDR2_DQ[54] DDR2_DQ[50] DDR2_DQS_DP[15] DDR2_DQ[52] DDR2_CAS_N DDR2_MA[10] DDR2_MA[03] DDR2_MA[08] DDR2_MA[12] DDR2_CKE[1] VSS

PCIEX3 GND GND SSTL GND GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND GND GND SSTL GND SSTL GND SSTL ODCMOS PCIEX3 PCIEX3 PCIEX3 GND PCIEX3 CMOS GND GND SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND

T30 T32 T34

DDR2_DQ[23] DDR2_DQS_DN[11] DDR2_DQ[20] DDR2_DQ[03] DDR2_DQS_DN[00] VSS DDR2_DQ[00] VSS PE3D_TX_DP[15] PE3C_TX_DN[8] PE3A_TX_DN[3] PE3B_TX_DN[6] PE3B_TX_DN[4] PE2A_RX_DP[1] PE2A_RX_DP[2] VSS VSS DDR2_DQS_DN[06] DDR2_DQ[49] DDR23_RCOMP[0] DDR2_RAS_N DDR2_MA[02] DDR2_MA[05] DDR2_MA[11] DDR2_MA[15] DDR2_CKE[2] DDR2_DQ[19] DDR2_DQ[60] DDR2_DQS_DP[02] DDR2_DQ[16] VSS DDR2_DQ[07] DDR2_DQS_DP[09] DDR2_DQ[05] DDR_SCL_C23 PE3C_TX_DN[10] PE3A_TX_DN[2] PE3B_TX_DN[7] VSS PE3B_TX_DN[5] PREQ_N PE2A_RX_DP[3]

SSTL SSTL SSTL SSTL SSTL GND SSTL GND PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 PCIEX3 GND GND SSTL SSTL Analog SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND SSTL SSTL SSTL ODCMOS PCIEX3 PCIEX3 PCIEX3 GND PCIEX3 CMOS PCIEX3

I/O I/O I/O I/O I/O

I/O

T36 T38 T4

I/O O O O O O O O

T40 T42 T44 T46 T48 T50 T52 T54 T56 T6 T8

I/O

O O O O O I I

I/O

U11 U13

I/O I/O I O O O O O O I/O I/O I/O I/O

I/O

U15 U17

I/O I/O O O O

U19 U21 U23 U25 U27 U29

O O

U3 U31 U33 U35

I/O I/O I/O I/O O O O O O O

U37 U39 U41 U43 U45 U47 U49 U5 U51 U53 U55

I/O I/O I/O I/O O O O

O I/O I

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Processor Land Listing

Table 8-2.
Land No.

Land Number (Sheet 47 of 48)

Land Name Buffer Type Direction

Table 8-2.
Land No.

Land Number (Sheet 48 of 48)

Land Name Buffer Type Direction

U7 U9 V10 V12 V14 V16 V18 V20 V22 V24 V26 V28 V30 V32 V34 V36 V38 V4 V40 V42 V44 V46 V48 V50 V52 V54 V56 V6 V8 W11 W13 W15 W17 W19 W21 W23 W25 W27 W29 W3 W31 W33

DDR2_DQ[44] DDR2_DQ[55] DDR2_DQ[51] DDR2_DQS_DN[15] DDR2_DQ[53] VCCD_23 VCCD_23 VCCD_23 VCCD_23 VCCD_23 VSS VSS DDR2_DQ[22] DDR2_DQS_DP[11] VSS VSS DDR2_DQS_DP[00] DDR2_DQ[61] DDR2_DQ[01] VSS VSS VSS VSS VSS TXT_PLTEN PE2A_RX_DN[1] PE2A_RX_DN[2] DDR2_DQ[40] VSS DDR2_DQS_DP[06] VSS RSVD DDR2_CS_N[8] DDR2_ODT[1] DDR2_CLK_DN[2] DDR2_CLK_DN[3] DDR2_MA[14] DDR2_ECC[6] DDR2_DQ[18] DDR2_DQ[56] DDR2_DQS_DN[02] VSS

SSTL SSTL SSTL SSTL SSTL PWR PWR PWR PWR PWR GND GND SSTL SSTL GND GND SSTL SSTL SSTL GND GND GND GND GND CMOS PCIEX3 PCIEX3 SSTL GND SSTL GND

I/O I/O I/O I/O I/O

W35 W37 W39 W41 W43 W45 W47 W49 W5 W51 W53 W55

DDR2_DQ[29] VSS DDR2_DQS_DN[09] VSS VSS VSS VSS VTTA VSS VSS VSS PE2A_RX_DN[3] DDR2_DQ[45] VSS VSS VSS DDR23_RCOMP[2] DDR2_CS_N[7] DDR2_ODT[3] DDR2_ODT[0] DDR2_CLK_DN[1] DDR2_CLK_DN[0] DDR2_ECC[2] VSS VSS VSS DDR2_DQS_DP[12] VSS VSS DDR2_DQ[57] VSS VSS PE3D_TX_DP[13] PE3C_TX_DP[11] RSVD PE3B_RX_DP[4] PE3B_RX_DP[5] VTTA VSS DDR2_DQ[41] DDR2_DQS_DP[14]

SSTL GND SSTL GND GND GND GND PWR GND GND GND PCIEX3 SSTL GND GND GND Analog SSTL SSTL SSTL SSTL SSTL SSTL GND GND GND SSTL GND GND SSTL GND GND PCIEX3 PCIEX3

I/O

I/O

I I/O

I/O I/O

W7 W9 Y10 Y12

I/O I/O I/O

Y14 Y16 Y18 Y20 Y22 Y24 Y26 Y28

I O O O O O I/O

I I I I/O

Y30 Y32 Y34 Y36 Y38

I/O

I/O

Y4 Y40 Y42

I/O

SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL GND

O O O O O I/O I/O I/O I/O

Y44 Y46 Y48 Y50 Y52 Y54 Y56 Y6 Y8

O O

PCIEX3 PCIEX3 PWR GND SSTL SSTL

I I

I/O I/O

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Package Mechanical Specifications

The processor is packaged in a Flip-Chip Land Grid Array (FCLGA10) package that interfaces with the baseboard via an LGA2011-0 land FCLGA10 socket. The package consists of a processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink. Figure 9-1 shows a sketch of the processor package components and how they are assembled together. Refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for complete details on the LGA2011-0 land FCLGA10 socket. The package components shown in Figure 9-1 include the following: 1. Integrated Heat Spreader (IHS) 2. Thermal Interface Material (TIM) 3. Processor core (die) 4. Package substrate 5. Capacitors

Figure 9-1.

Processor Package Assembly Sketch

IHS Substrate

Die

TIM

Capacitors LGA2011-0 Socket System Board

Note: 1. Socket and baseboard are included for reference and are not part of processor package.

9.1

Package Mechanical Drawing

The package mechanical drawings are shown in Figure 9-2 and Figure 9-3. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include: 1. Package reference with tolerances (total height, length, width, and so forth) 2. IHS parallelism and tilt 3. Land dimensions 4. Top-side and back-side component keep-out dimensions

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Package Mechanical Specifications

5. Reference datums 6. All drawing dimensions are in millimeters (mm). 7. Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the Intel Xeon Processor E51600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide.

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Figure 9-2.

Processor Package Drawing Sheet 1 of 2

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Package Mechanical Specifications

Figure 9-3.

Processor Package Drawing Sheet 2 of 2

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9.2

Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Do not contact the Test Pad Area with conductive material. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 9-2 and Figure 9-3 for keep-out zones. The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep-in.

9.3

Package Loading Specifications

Table 9-1 provides load specifications for the processor package. These maximum limits should not be exceeded during heatsink assembly, shipping conditions, or standard use condition. Exceeding these limits during test may result in component failure. The processor substrate should not be used as a mechanical reference or loadbearing surface for thermal solutions.

Table 9-1.

Processor Loading Specifications

Parameter Maximum Notes

Static Compressive Load Dynamic Load

890 N [200 lbf] 540 N [121 lbf]

1, 2, 3, 5 1, 3, 4, 5

Notes: 1. These specifications apply to uniform compressive loading in a direction normal to the processor IHS. 2. This is the maximum static force that can be applied by the heatsink and Independent Loading Mechanism (ILM). 3. These specifications are based on limited testing for design characterization. Loading limits are for the package constrained by the limits of the processor socket. 4. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement. 5. See Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for minimum socket load to engage processor within socket.

9.4

Package Handling Guidelines

Table 9-2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal.

Table 9-2.

Package Handling Guidelines

Parameter Maximum Recommended Notes

Shear Tensile Torque

80 lbs (36.287 kg) 35 lbs (15.875 kg) 35 in.lbs (15.875 kg-cm)

9.5

Package Insertion Specifications

The processor can be inserted into and removed from an LGA2011-0 land FCLGA10 socket 15 times. The socket should meet the LGA2011-0 land FCLGA10 requirements detailed in the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide.

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Package Mechanical Specifications

9.6

Processor Mass Specification

The typical mass of the processor is currently 45 grams. This mass [weight] includes all the components that are included in the package.

9.7
Table 9-3.

Processor Materials
Table 9-3 lists some of the package components and associated materials. Processor Materials
Component Material

Integrated Heat Spreader (IHS) Substrate Substrate Lands

Nickel Plated Copper Halogen Free, Fiber Reinforced Resin Gold Plated Copper

9.8

Processor Markings
Figure 9-4 shows the topside markings on the processor. This diagram is to aid in the identification of the processor.

Figure 9-4.

Processor Top-Side Markings

GRP1 LINE1 GRP1 LINE2 GRP1 LINE3 GRP1 LINE4 GRP1 LINE5

LOT NO S/N

Legend: Mark Text ( Production Mark): GRP 1LINE1: i{M}{ C}YY GRP 1LINE2: SUB - BRAND PROC # GRP1LINE3: SSPEC SPEED GRP1LINE4: XXXXX GRP1LINE5: {FPO }{ e4}

Notes: 1. XXXXX = Country of Origin 2. SPEED Format = X.XX GHz and no rounding

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Boxed Processor Specifications

10
10.1

Boxed Processor Specifications

Introduction
Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The Intel Xeon processor E52600 product family (LGA2011-0 land FCLGA10) processors will be offered as Intel boxed processors, however the thermal solutions will be sold separately. Boxed processors will not include a thermal solution in the box. Intel will offer boxed thermal solutions separately through the same distribution channels. Please reference Section 10.1.1 - Section 10.1.3 for a description of Boxed Processor thermal solutions.

10.1.1

Available Boxed Thermal Solution Configurations

Intel will offer three different Boxed Heat Sink solutions to support LGA2011-0 land FCLGA10 Boxed Processors Boxed Intel Thermal Solution STS200C (Order Code BXSTS200C): A Passive / Active Combination Heat Sink Solution that is intended for processors with a TDP up to 150W in a pedestal or 130W in 2U+ chassis with appropriate ducting. Boxed Intel Thermal Solution STS200P (Order Code BXSTS200P): A 25.5 mm Tall Passive Heat Sink Solution that is intended for processors with a TDP of 130W or lower in 1U, or 2U chassis with appropriate ducting. Check with Blade manufacturer for compatibility. Boxed Intel Thermal Solution STS200PNRW (Order Code BXSTS200PNRW): A 25.5 mm Tall Passive Heat Sink Solution that is intended for processors with a TDP of 130W or lower in 1U, or 2U chassis with appropriate ducting. Compatible with the narrow processor integrated load mechanism. Check with Blade manufacturer for compatibility.

10.1.2

Intel Thermal Solution STS200C (Passive/Active Combination Heat Sink Solution)

The STS200C, based on a 2U passive heat sink with a removable fan, is intended for use with processors with TDPs up to 150W in active configuration and 130W in passive configuration. This heat pipe-based solution is intended to be used as either a passive heat sink in a 2U or larger chassis, or as an active heat sink for pedestal chassis. Figure 10-1 and Figure 10-2 are representations of the heat sink solution. Although the active combination solution with the removable fan installed mechanically fits into a 2U keepout, its use has not been validated in that configuration. The STS200C in the active fan configuration is primarily designed to be used in a pedestal chassis where sufficient air inlet space is present. The STS200C with the fan removed, as with any passive thermal solution, will require the use of chassis ducting and are targeted for use in rack mount or ducted pedestal servers. The retention solution used for these products is called ILM Retention System (ILM-RS).

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Figure 10-1. STS200C Passive/Active Combination Heat Sink (with Removable Fan)

Figure 10-2. STS200C Passive/Active Combination Heat Sink (with Fan Removed)

The STS200C utilizes a fan capable of 4-pin pulse width modulated (PWM) control. Use of a 4-pin PWM controlled active thermal solution helps customers meet acoustic targets in pedestal platforms through the baseboards ability to directly control the RPM of the processor heat sink fan. See Section 10.3 for more details on fan speed control. Also see Section 2.5, Platform Environment Control Interface (PECI) for more on the PWM and PECI interface along with Digital Thermal Sensors (DTS).

10.1.3

Intel Thermal Solution STS200P and STS200PNRW (Boxed 25.5 mm Tall Passive Heat Sink Solutions)
The STS200P and STS200PNRW are available for use with boxed processors that have TDPs of 130W and lower. These 25.5 mm Tall passive solutions are designed to be used in SSI Blades, 1U, and 2U chassis where ducting is present. The use of a 25.5 mm Tall heatsink in a 2U chassis is recommended to achieve a lower heatsink TLA and more flexibility in system design optimization. Figure 10-3 is a representation of the heat

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Boxed Processor Specifications

sink solutions. The retention solution used for the STS200P Heat Sink Solution is called the ILM Retention System (ILM-RS).The retention solution used for the STS200PNRW Narrow Heat Sink Solution is called the Narrow ILM Retention System (Narrow ILM-RS). Figure 10-3. STS200P and STS200PNRW 25.5 mm Tall Passive Heat Sinks

10.2
10.2.1

Mechanical Specifications
This section documents the mechanical specifications of the boxed processor solution.

Boxed Processor Heat Sink Dimensions and Baseboard Keepout Zones

The boxed processor and boxed thermal solutions will be sold separately. Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling. Baseboard keepout zones are Figure 10-4 - Figure 10-7. Physical space requirements and dimensions for the boxed processor and assembled heat sink are shown in Figure 10-8 and Figure 10-9. Mechanical drawings for the 4-pin fan header and 4-pin connector used for the active fan heat sink solution are represented in Figure 10-10 and Figure 10-11. None of the heat sink solutions exceed a mass of 550 grams. Note that this is per processor, a dual processor system will have up to 1100 grams total mass in the heat sinks. See Section 9.6 for details on the processor mass test.

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The drawing contains corporation information. Its may not be reproduced, THIS DRAWING CONTAINS INTEL intel CORPORATION CONFIDENTIAL INFORMATION. IT IScontents DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION. displayed, or modified without the prior written consent of Intel Corporation.
06/30/10

A -

INITIAL RELEASE FOR FUTURE BOARD BUILDS DEVIATING FROM E59036. CHANGED ZONE 4, UPDATED NOTES FOR CLARIFICATION. ADDED A NEW ZONE 7 ON PRIMARY SIDE. CHANGED ZONE 8 FOR UPDATED BACKPLATE. REMOVED HEATSINK HOLE MOUNTING LOCATIONS REMOVED LEVER FINGER ACCESS TABS OUTSIDE 93.5x93.5 SQUARE. REDUCED MAX THERMAL RETENTION OUTLINE TO 93X93MM.

NOTES:

B
ADDED NOTE 8 FOR FURTHER CLARIFICATION
08/26/10

DL

D
1. THIS DRAWING TO BE USED IN CORELATION WITH SUPPLIED 3D DATA BASE FILE. ALL DIMENSIONS AND TOLERANCES ON THIS DRAWING TAKE PRECEDENCE OVER SUPPLIED FILE. 2. DIMENSIONS STATED IN MILLIMETERS AND DEFINE ZONES, THEY HAVE NO TOLERANCES ASSOCIATED WITH THEM. 3. SOCKET KEEP OUT DIMENSIONS SHOWN FOR REFERNCE ONLY. 4. MAXIMUM OUTLINE OF SOCKET MUST BE PLACED SYMMETRIC TO THE ILM HOLE PATTERN FOR PROPER ILM AND SOCKET FUNCTION. 5 A HEIGHT RESTRICTION ZONE IS DEFINED AS ONE WHERE ALL COMPONENTS PLACED ON THE SURFACE OF THE MOTHERBOARD MUST HAVE A MAXIMUM HEIGHT NO GREATER THAN THE HEIGHT DEFINED BY THAT ZONE. ALL ZONES DEFINED WITHIN THE 93.5 X 93.5 MM OUTLINE REPRESENT SPACE THAT RESIDES BENEATH THE HEATSINK FOOTPRINT. UNLESS OTHERWISE NOTED ALL VIEW DIMENSION ARE NOMINAL. ALL HEIGHT RESTRICTIONS ARE MAXIMUMS. NEITHER ARE DRIVEN BY IMPLIED TOLERANCES. A HEIGHT RESTRICTION OF 0.0 MM REPRESENTS THE TOP (OR BOTTOM) SURFACE OF THE MOTHERBOARD AS THE MAXIMUM HEIGHT. THIS IS A NO COMPONENT PLACEMENT ZONE INCLUDING SOLDER BUMPS. SEE NOTE 6 FOR ADDITIONAL DETAILS.

93.0 MAX THERMAL SOLUTION ENVELOPE AND MECHANICAL PART CLEARANCE (FINGER ACCESS NOT INCLUDED)

2X FINGER ACCESS 8

6 ASSUMING A GENERIC A MAXIMUM COMPONENT HEIGHT ZONE. CHOICE OF AND COMPONENT PLACEMENT IN THIS ZONE MUST INCLUDE: - COMPONENT NOMINAL HEIGHT - COMPONENT TOLERANCES - COMPONENT PLACEMENT TILT - SOLDER REFLOW THICKNESS DO NOT PLACE COMPONENTS IN THIS ZONE THAT WILL EXCEED THIS MAXIMUM COMPONENT HEIGHT. 7 ASSUMES PLACEMENT OF A 0805 CAPACITOR WITH DIMENSIONS: - CAP NOMINAL HEIGHT = 1.25MM (0.049") - COMPONENT MAX MATERIAL CONDITION HEIGHT NOT TO EXCEED 1.50MM. 8 SIZE & HEIGHT OF FINGER ACCESS TO BE DETERMINED BY SYSTEM/BOARD ARCHITECT. THIS IS ILM MECHANICAL CLEARANCE ONLY AND FINGER AND/OR TOOL ACCESS SHOULD DETERMINED SEPERATELY.

(58.5 ) SOCKET BODY OUTLINE (FOR REFERENCE ONLY)

LEGEND, SHEETS 1 & 2 ONLY

ZONE 1: 0.0 MM MAX COMPONENT HEIGHT, NO COMPONENT PLACEMENT, SOCKET, ILM, AND FINGER ACCESS KEEPIN ZONE ZONE 2: 7.2 MM MAX COMPONENT HEIGHT.

93.0 MAX THERMAL SOLUTION ENVELOPE AND MECHANICAL PART CLEARANCE

2X 69.2 SOCKET ILM HOLE PATTERN

B
6 ZONE 3: 0.0 MM MAX COMPONENT HEIGHT, NO COMPONENT PLACEMENT, NO ROUTE ZONE ZONE 4: 1.67 MM MAX COMPONENT HEIGHT AFTER REFLOW 5 6 1.50 MM MAX (MMC) COMPONENT HEIGHT BEFORE REFLOW ZONE 5: 1.6 MM MAX COMPONENT HEIGHT. ZONE 6: 1.5 MM MAX COMPONENT HEIGHT. ZONE 7: 1.9 MM MAX COMPONENT HEGHT. 5 7

Figure 10-4. Boxed Processor Motherboard Keepout Zones (1 of 4)

2X 46.0 SOCKET ILM HOLE PATTERN 3.8 4X SOCKET ILM MOUNTING HOLES

BALL 1 CORNER POSITIONAL MARKING (FOR REFERENCE ONLY) (51.0 ) SOCKET BODY OUTLINE (FOR REFERENCE ONLY)

DESIGNED BY DATE

DEPARTMENT
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D. LLAPITAN
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DATE

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CHECKED BY

2200 MISSION COLLEGE BLVD. P.O. BOX 58119 SANTA CLARA, CA 95052-8119

A
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DATE TITLE

UNLESS OTHERWISE SPECIFIED INTERPRET DIMENSIONS AND TOLERANCES IN ACCORDANCE WITH ASME Y14.5M-1994 DIMENSIONS ARE IN MM TOLERANCES: .X 0.0 Angles 0.0 .XX 0.00 .XXX 0.000

THIRD ANGLE PROJECTION

NEAL ULEN

07/05/10
APPROVED BY DATE

LGA 2011 ENABLING KEEPOUT ZONES

SIZE DRAWING NUMBER MATERIAL FINISH

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2X 92.0 2X 53.808 2X 41.46 2X 8.80 2X 3.30 2X 4.50 4X 6.5 COPPER WEAR PAD ON PRIMARY SURFACE, BRING AS CLOSE TO HOLE EDGE AS POSSIBLE 4.80

Boxed Processor Specifications

4.55

C
3.80 2X 73.55 18.20 2X 67.57

SEE DETAIL

+.06 -.03 NPTH SOCKET ILM MOUNTING HOLES

DETAIL B SCALE 4.0

(93.0 ) 2X 34.05 2X 31.55 2X 25.25

Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One

2X 3.45 2X 7.05 (93.0 ) 12.80 SEE DETAIL B 2X 22.75

Figure 10-5. Boxed Processor Motherboard Keepout Zones (2 of 4)

AS VIEWED FROM PRIMARY SIDE OF MAINBOARD

DETAIL A SCALE 4.0

2X 30.0

DEPARTMENT
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D
71.5 14.0 R1.00 TYP

4X 4.8 NO ROUTE ZONE THRU ALL LAYERS

22.37

81.5

2X 26.50

Figure 10-6. Boxed Processor Motherboard Keepout Zones (3 of 4)

B

B
2X 5.0

4X R7.0

2X 23.40

LEGEND, SHEET 3 ONLY

ZONE 8: NO COMPONENT PLACEMENT, STIFFENING PLATE CONTACT AREA ZONE 9: 1.8 MM MAX COMPONENT HEIGHT FOR SSI BLADES CONFIGURATION * ALL OTHER FORM FACTORS DEPENDANT ON SYSTEM CONSTRAINTS. ZONE 10: NO COMPONENT PLACEMENT & NO ROUTE ZONE

AS VIEWED FROM SECONDARY SIDE OF MAINBOARD

DEPARTMENT
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The drawing contains intel corporation information. Its contents may not be reproduced, THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS displayed, or modified without the prior written consent of Intel Corporation. MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION.

Boxed Processor Specifications

Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One

PRIMARY SIDE 3D HEIGHT RESTRICTION ZONES AND VOLUMETRIC SWEEPS OF LOADPLATE AND LEVER OPENING/CLOSING

SECONDARY SIDE 3D HEIGHT RESTRICTION ZONES

B
97.0 MIN 97.0 MIN

Figure 10-7. Boxed Processor Motherboard Keepout Zones (4 of 4)

81.50 76.50

TOP SURFACE OF MOTHERBOARD .03 4.38 93.00 93.0

DEPARTMENT
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ZONE 2B2 A VOLUME FOR DIE CAST GEOMETRY INTEGRATED SPRING/SCREW CUP FEATURE IN TO CAST GEOMETRY ROLLED PART TO -002 CHANGED SPRING CUP GEOMETRY TO FIT DELRIN SPACER 7/21/10 REV DESCRIPTION

The drawing contains intel corporation information. Its contents may not be reproduced, THIS DRAWING CONTAINS INTEL CORPORAT ION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONT displayed, or modified without prior of PRI Intel MAY NOT BE DISCLOSED, REPRODUCED, DI the SPLAYED OR written MODIFIED, consent WITHOUT THE OR Corporation. WRITTEN CONSENT OF INTEL CORPORAT
ENTS ION.
B

4X 12.00

[0.472+0.039 -0.000 ]
NOTES: 1. 2. 3. 4. 6. 7. 8. 9

+1.00 0

4X 12.00

+1.00 0

[0.472+0.039 -0.000 ]

91.50

0 -0.25 +0.000 3.602 -0.009

THIS DRAWING TO BE USED IN CONJUNCTION WITH SUPPLIED 3D DATABASE FILE. ALL DIMENSIONS AND TOLERANCES ON THIS DRAWING TAKE PRECEDENCE OVER SUPPLIED FILE. PRIMARY DIMENSIONS STATED IN MILLIMETERS, [BRACKETED] DIMENSIONS STATED IN INCHES. CRITICAL TO FUNCTION DIMENSION. ALL DIMENSION AND TOLERANCES PER ANSI Y14.5-1994. HEAT SINK VOLUMETRIC. ALL HEAT SINK GEOMETRY MUST FIT WITHIN THE SPACE DEFINED BY THIS DRAWING.. REMOVE ALL BURRS, SHARP EDGES, GREASES, AND/OR SOLVENTS AFTER MACHINING AND FIN ASSEMBLY. LOCAL FLATNESS ZONE .076 MM [0.003"] CENTERED ON HEAT SINK BASE. NO EXPOSED CORNER FINS ALLOWED. CHAMFER ALL EXPOSED FIN CORNERS TO THE VALUE SPECIFIED. CRITICAL TO FUNCTION DIMENSION.

C
AIRFLOW DIRECTION
SEE NOTE 8

91.50

[3.602+0.000 -0.009 ]
TOP VIEW

0 -0.25 A

B
SEE NOTE 4

Figure 10-8. Boxed Processor Heat Sink Volumetric (1 of 2)

B

64.00 [2.520]

MAX.

TOP
QTY ITEM NO

E95132-002
PART NUMBER

ROMLEY 2U HS VOLUMETRIC
DESCRIPTION

PARTS LIST
DESIGNED BY DATE DEPARTMENT
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N. ULEN
DRAWN BY

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DATE

EASD / PTMI N. ULEN 3/29/10

TITLE

UNLESS OTHERWISE SPECIFIED INTERPRET DIMENSIONS AND TOLERANCES IN ACCORDANCE WITH ASME Y14.5-1994 DIMENSIONS ARE IN MILLIMETERS TOLERANCES: .X # .5 Angles # 1.0 $ .XX # 0.25 .XXX # 0.127

2200 MISSION COLLEGE BLVD. P.O. BOX 58119 SANTA CLARA, CA 95052-8119
CHECKED BY DATE

A
THIRD ANGLE PROJECTION
D. LLAPITAN APPROVED BY MATERIAL

3/29/10 DATE FINISH

ROMLEY 2U HS VOLUMETRIC, DIE CAST BASES ONLY

SIZE DRAWING NUMBER

D
SEE NOTES SEE NOTES

E95132
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The drawing contains intel corporation information. Its contents may not be reproduced, THIS DRAWING CONTAINS INTEL CORPORAT ION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONT ENTS displayed, or modified without the prior written consent of Intel Corporation. MAY NOT BE DISCLOSED, REPRODUCED, DI SPLAYED OR MODIFIED, WITHOUT THE PRI OR WRITTEN CONSENT OF INTEL CORPORAT ION.

D
TOP VIEW
3.0 [0.118] X 45 $TYP SEE NOTE 8

Boxed Processor Specifications

AIRFLOW DIRECTION

DETAIL C SCALE 6.000

C
10.450 [0.4114]

SEE DETAIL

C 7.95

[
SEE DETAIL B

0.313

+0.13 0 +0.005 -0.000 9

]
0.5 x 45 $ ALL AROUND 5.50 [0.217 ]

Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One

SECTION A-A 4.50 # 0.13 [0.177 # 0.005 ] BASE THICKNESS 1.00 [0.039 ] A A 9

Figure 10-9. Boxed Processor Heat Sink Volumetric (2 of 2)

0.00 ORDINATE BASELINE [ 0.000 ]

DETAIL B SCALE 10.000 9 38.00 # 0.50 [1.496 # 0.019 ]

80.00 [3.150]

+0.13 5.40 0 +0.005 0.213 -0.000

]
9

0.1 [0.00] A B C

0.077 [0.0030] FLATNESS ZONE, SEE NOTE 7

A
38.00 # 0.50 [1.496 # 0.019 ]

BOTTOM VIEW

80.00 [3.150] 9

DEPARTMENT

SIZE DRAWING NUMBER

REV

AIRFLOW DIRECTION

PTMI

2200 MISSION COLLEGE BLVD. P.O. BOX 58119 SANTA CLARA, CA 95052-8119

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Boxed Processor Specifications

Figure 10-10.4-Pin Fan Cable Connector (For Active Heat Sink)

252

The drawing contains intel corporation information. Its contents may not be reproduced, displayed, or modified without the prior written consent of Intel Corporation.

Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One

Boxed Processor Specifications

Figure 10-11. 4-Pin Base Baseboard Fan Header (For Active Heat Sink)

Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One

The drawing contains intel corporation information. Its contents may not be reproduced, displayed, or modified without the prior written consent of Intel Corporation.

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Boxed Processor Specifications

10.2.2

Boxed Processor Retention Mechanism and Heat Sink Support (ILM-RS)

Baseboards designed for use by a system integrator should include holes that are in proper alignment with each other to support the boxed processor. The standard and narrow ILM-RSs are designed to extend air-cooling capability through the use of larger heat sinks with minimal airflow blockage and bypass. ILM-RS retention transfers load to the baseboard via the ILM Assembly. The ILM-RS spring, captive in the heatsink, provides the necessary compressive load for the thermal interface material. For specific design details on the standard and narrow ILM-RS and the Backplate please refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide. All components of the ILM-RS heat sink solution will be captive to the heat sink and will only require a Phillips screwdriver to attach to the ILM Backplate Assembly. When installing the ILM-RS the screws should be tightened until they will no longer turn easily. This should represent approximately 8 inch-pounds of torque. More than that may damage the retention mechanism components.

10.3

Fan Power Supply [STS200C]

The 4-pin PWM controlled thermal solution is being offered to help provide better control over pedestal chassis acoustics. This is achieved through more accurate measurement of processor die temperature through the processors Digital Thermal Sensors. Fan RPM is modulated through the use of an ASIC located on the baseboard that sends out a PWM control signal to the 4th pin of the connector labeled as Control. This thermal solution requires a constant +12 V supplied to pin 2 of the active thermal solution and does not support variable voltage control or 3-pin PWM control. See Figure 10-12 and Table 10-1 for details on the 4-pin active heat sink solution connectors. The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it. The fan power header identification and location must be documented in the suppliers platform documentation, or on the baseboard itself. The baseboard fan power header should be positioned within 177.8 mm [7 in.] from the center of the processor socket.

Table 10-1. PWM Fan Frequency Specifications For 4-Pin Active Thermal Solution
Description Min Frequency Nominal Frequency Max Frequency Unit

PWM Control Frequency Range

21,000

25,000

28,000

Hz

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Figure 10-12. Fan Cable Connector Pin Out For 4-Pin Active Thermal Solution

10.3.1

Boxed Processor Cooling Requirements

As previously stated the boxed processor will have three thermal solutions available. Each configuration will require unique design considerations. Meeting the processors temperature specifications is also the function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor temperature specifications are found in Section 5, Thermal Management Specifications of this document.

10.3.1.1

STS200C (Passive / Active Combination Heat Sink Solution)

The active configuration of the combination solution is designed to help pedestal chassis users to meet the thermal processor requirements without the use of processor chassis ducting. However, it is strongly recommended to implement some form of air duct to meet memory cooling and processor TLA temperature requirements. Use of the active configuration in a 2U rackmount chassis is not recommended. In the passive configuration it is assumed that a chassis duct will be implemented. For a list processor and thermal solution boundary conditions, such as Psica, TLA, airflow, flow impedance, etc, see Table 10-2 and Table 10-3. It is recommended that the ambient air temperature outside of the chassis be kept at or below 35 C. Meeting the processors temperature specification is the responsibility of the system integrator.This thermal solution is for use with processor SKUs no higher than 150W (8 Core) or 130W (4 and 6 core).

10.3.1.2

STS200P and STS200PNRW (25.5mm Tall Passive Heat Sink Solution) (Blade + 1U + 2U Rack)
These passive solutions are intended for use in SSI Blade, 1U or 2U rack configurations. It is assumed that a chassis duct will be implemented in all configurations. For a list processor and thermal solution boundary conditions, such as Psica, TLA, airflow, flow impedance, etc, see Table 10-2 and Table 10-3. It is recommended that the ambient air temperature outside of the chassis be kept at or below 35 C. Meeting the processors temperature specification is the responsibility of the system integrator. These thermal solutions are for use with processor SKUs no higher than 130W (6 and 8 Core), or 80W (4 Core).

Note:

Please refer to the Intel Xeon Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for detailed mechanical drawings of the STS200P and STS200PNRW.
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Table 10-2. 8 Core / 6 Core Server Thermal Solution Boundary Conditions

TDP Thermal Solution CA2 (C/W) TLA 1 (C) Airflow 3 (CFM) Delta P (inch of H2O) Heatsink Volumetric4 (mm)

150W (WS Only) 8 Core 130W (1U) 6 and 8 Core 130W (1U) 6 and 8 Core 130W (2U) 6 and 8 Core 130W (Pedestal) 6 and 8 Core 115W (Pedestal) 8 Core 115W (Pedestal) 8 Core 115W (Pedestal) 8 Core 95W (1U) 6 and 8 Core 95W (1U) 6 and 8 Core 95W (Pedestal) 6 and 8 Core 70W(1U) 8 Core 70W(1U) 8 Core 70W (Pedestal) 8 Core 60W(1U) 8 Core 60W(1U) 8 Core 60W(Pedestal) 8 Core

STS200C (with fan) STS200P STS200PNRW STS200C (without fan) STS200C (with fan) STS200P STS200PNRW STS200C (with fan) STS200P STS200PNRW STS200C (with fan) STS200P STS200PNRW STS200C (with fan) STS200P STS200PNRW STS200C (with fan)

0.180 0.242 0.253 0.180 0.180 0.241 0.252 0.179 0.243 0.254 0.181 0.239 0.250 0.177 0.239 0.250 0.177

40.0 53.6 52.2 61.6 61.6 52.2 51.0 59.4 49.9 48.9 55.8 47.2 46.5 51.6 45.7 45.0 49.4

Max RPM 16 14 26 Max RPM 16 14 Max RPM 16 14 Max RPM 16 14 Max RPM 16 14 Max RPM

N/A 0.406 0.347 0.14 N/A 0.406 0.347 N/A 0.406 0.347 N/A 0.406 0.347 N/A 0.406 0.347 N/A

91.5x91.5x64 91.5x91.5x25.5 70x106x25.5 91.5x91.5x64 91.5x91.5x64 91.5x91.5x25.5 70x106x25.5 91.5x91.5x64 91.5x91.5x25.5 70x106x25.5 91.5x91.5x64 91.5x91.5x25.5 70x106x25.5 91.5x91.5x64 91.5x91.5x25.5 70x106x25.5 91.5x91.5x64

Table 10-3. 4 Core Server Thermal Solution Boundary Conditions

TDP Thermal Solution CA2 (C/W) TLA 1 (C) Airflow 3 (CFM) (inch of H2O) Delta P Heatsink Volumetric4 (mm)

130W (Pedestal) 80W- 1U) 80W- 1U)

STS200C (with fan) STS200P STS200PNRW

0.199 0.261 0.272

47.1 49.1 48.2

Max RPM 16 14

N/A 0.406 0.347

91.5x91.5x64 91.5x91.5x25.5 70x106x25.5

Notes: 1. Local ambient temperature of the air entering the heatsink or fan. System ambient and altitude are assumed 35C and sea level. 2. Max target (mean + 3 sigma) for thermal characterization parameter. 3. Airflow through the heatsink fins with zero bypass. Max target for pressure drop (dP) measured in inches H2O. 4. See Table 10-2 and Table 10-3 for detailed dimensions. Dimensions of heatsinks do not include socket or processor.

10.4

Boxed Processor Contents

The Boxed Processor and Boxed Thermal Solution contents are outlined below.

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Boxed Processor Intel Xeon processor E5-2600 product family Installation and warranty manual Intel Inside Logo Boxed Thermal Solution Thermal solution assembly Thermal interface material (pre-applied) Installation and warranty manual

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