VSRD International Journal of Electrical, Electronics & Communication C Engineering, Vol. 3 No.

3 March 2013 e-ISSN : 2231-3346, p-ISSN : 2319-2232 VSRD International Journals : www.vsrdjournals.com

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REVIEW ARTICLE

A REVIEW OF ANTENNA EFFECTS EFFECT IN VLSI DESIGN

Singh Kushwaha Kushwaha* and 2Bhumika humika Bisht

Professor, Department of Electronics & Communication Engineering, Professor BBDIT, Ghaziabad, Uttar Pradesh, INDIA. *Corresponding Corresponding Author : [email protected]

ABSTRACT
In the modern age of VLSI designing, as the size of device is decreasing day by day, we are using more advance techniques for the fabrication process but those techniques have some disadvantages and one of the most important adverse effects is Antenna effect. In this review paper antenna effect has been discussed and with few of its definitions. Keywords : Plasma Etch, Charging Damage, Stress Voltage, Antenna Ratio, Ra Charge Buildup.

1. INTRODUCTION Plasma etch or dry etch are used very widely these days for wafer processing. Plasma is defined as a reactive gas that is supposed to etch. It was very difficult controlling the pattern and the chemical reactions[1][2] that took place during the etching process especially wet etching. As it is a long process, many times a few undesirable outcomes are also obtained. Charging damage is one of those undesired outcomes. 2. THE CHARGING DAMAGE The charging damage based on plasma is mainly because of the unintentional high-field field stressing of the gate-oxide gate in a MOSFET during the processing of plasma. Following are the three important sources that are obtained due to the stress potential that is developed across the gate and substrate.

The third source i.e. the stress voltage due to AC effects is not very important in plasma processing as they are not responsible in destroying the plasma anyways. But fully negligence of this source is not appreciated as it is added to the amplitude of the stress voltages obtained by either nonuniform plasma potential or topographic filtering of charge. In few cases both of the potentials are added. The responsible net charges are obtained by the exposed conductor with connection to the gate or substrate from the plasma. During the process of wafer preparation both types of charges whether they are negative or positive encroach on the open conductor. An imbalance between charges is always found as there is always a flux difference that exists between the charges. Fig. 1 shows sh the overall available charge that is channeled to the gate.

Fig. 1 : Plasma Charging Damage This helps in defining the concept of Antenna Effect. The dimension of the conductor that is offered to the plasma p rays has a big importance in calculating the amplitude of the available charge collection rate and hence obtaining the tunneling current[3]. The dimensions so obtained results in giving birth to a new term known as Antenna ratio.

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Antenna Ratio is defined as the area ratio of the conductor to the oxide under the gate. The antenna ratio of proportional to the tunneling current density across the gate oxide. Also for a constant antenna ratio, tunneling current is proportional to plasma density. Hence we can generalize by saying so that all of the three antenna ratio, tunneling current density and the plasma density are proportional to each other. It is true that the more the value of tunneling current the higher damage it causes. When metallization process cess is done between two layers few of the wires are kept open till the upper metal layers are deposited. It means that one connection is stable and the other one is kept open so that it can be customized. One end

connected and other one open behaves like a capacitor with a good amount of storage of charge. The charge stored is obtained at the time of fabrication as plasma etching. We can say that an antenna is a metallic or polysilicon interface that conducts and is connected to silicon electrically. It is never grounded during preparation of wafer. An electrical path is developed to reject any accumulated charge due to the connection of silicon. If unavailable, charges and may build up on the interinter connect to the point at which rapid discharge does take place and permanent physical damage results, e.g., to MOSFET gate oxides. This destructive phenomenon is known as the 'antenna effect'.

Fig. 2

3. THE ANTENNA RATIO The antenna ratio is very useful in determining the presence or absence of antenna effect. Antenna Ratio= (Physical area of the conductor making up the antenna/ Total gate oxide area to which the antenna is electrically connected)[4,5,6]

The objective does not fulfill if the ratio is very high. Hence our objective is to keep the ratio under limit. For a smaller antenna ratio we keep relatively larger area to collect charge (the denominator is kept high) or we reduce the value of gate oxide on which the charge is concentrated (the numerator if kept small).

Fig. 3

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4. THE FOLLOWING ARE THE REASONS THAT AFFECT CHARGE BUILDUP Diffusion Path There is an PN diode to substrate at the drain/source of any output pin During plasma-etch this diode is reverse biased and at high temp This causes the diode to behave like a resistor Wire Length Longer wires act as antennas to pick up more charge Gate Area Larger gate area == larger gate capacitor At fixed charge, voltage potential reduces as cap size increases Reducing the voltage prevents punch through Diffusion Area Bigger diffusion == Smaller resistor Smaller R allows more current to pass Antenna effect will also depend upon the fabrication technology. A single stage is also very important for the avoidance of antenna effect. As there are some set of rules depending on which antenna performed well so we have to break that rules at the time of fabrication of a chip. 5. CONCLUSION Antenna effect is a very important consideration which plays a very significant role in VLSI circuits. So if we want that our circuit will perform as we required we have to pay attention during fabrication and try to avoid antenna effect as much as possible. We have to take care at each stage of fabrication. 6. REFERENCES
[1] H. T. Heineken, J. Khare, W. Maly, P.K. Nag, C. Ouyang, et.al., CAD at the design-manufacturing interface, Proc. ACM/IEEE Design Automation Conf., pp. 321-326, 1997. [2] W. Maly, et.al., Detection of an antenna effect in VLSI designs, Research report No. CMUCAD-96-17, May. 1996. [3] H. Shirota, T. Sadakane, M. Terai, and K. Okazaki, A new router for reducing antenna effect in ASIC design, in Proc. IEEE Custom Integrated Circuits Conf., Santa Clara, CA, 1998, pp. 601604. [4] F. Shone, K. Wu, J. Shaw, E. Hokelet, S. Mittal, and A. Haranahalli, Gate Oxide Charging and Its Elimination for Metal Antenna Capacitor and Transistor in VLSI CMOS Double Layer Metal Technology, Sym. VLSI Tech. Dig. Papers, pp. 73-74, 1989. [5] H. Shin, C.-C. King, T. Horiuchi, and C. Hu, Thin Oxide Charging Current During Plasma Etching of Aluminum, IEEE Electron Device Letters, Vol. 12, No. 8, pp. 404-406, August 1991. [6] H. Shin, C.-C. King and C. Hu, Thin Oxide Damage by Plasma Etching and Ashing Process, PTOC. IEEE/IRPS, pp. 37-41, 1992.

Devendra Singh Kushwaha and Bhumika Bisht

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