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Model Paper

The document provides two model papers for the subject "Fundamentals of HDL" with questions covering various topics related to HDL such as VHDL, Verilog, data types, operators, logic synthesis, data flow modeling, behavioral modeling, modules, files, arrays, and mixed language descriptions. The first model paper has 8 questions with 4 questions in Part A and 4 in Part B. The second model paper also has 8 questions split similarly between two parts. The questions test concepts, require code writing, truth tables, derivations and explanations on HDL fundamentals.

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Abhi Shek
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71 views2 pages

Model Paper

The document provides two model papers for the subject "Fundamentals of HDL" with questions covering various topics related to HDL such as VHDL, Verilog, data types, operators, logic synthesis, data flow modeling, behavioral modeling, modules, files, arrays, and mixed language descriptions. The first model paper has 8 questions with 4 questions in Part A and 4 in Part B. The second model paper also has 8 questions split similarly between two parts. The questions test concepts, require code writing, truth tables, derivations and explanations on HDL fundamentals.

Uploaded by

Abhi Shek
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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MODEL PAPER-1

Subject: Fundamentals of HDL SUBJECT CODE: 06ES45 Max marks : 100 Duration: 3Hrs
Note: Answer any five full questions selecting at least two from each part Q Part A marks 1 a Differentiate between VHDL and Verilog HDL 6 b Discuss different logical operators used in HDL. Illustrate each of them with an example. 10 c What is logic synthesis? 4 2 a Write a data flow description of a full adder with enable. Draw the Truth table of this adder and derive the Boolean function after minimization. 4 b With relevant example, explain the signal declaration and signal assignment statements. 4 c What are the data types available in VHDL? 4 3 a Explain different loop statements in HDL 8 b Write a Behavioral Description of D Latch using Variable and Signal assignments. 12 4 a What is module Instantiation, explain with an example 8 b Write the HDL description of 2x1 Multiplexer with Active Low Enable in VHDL / Verilog. 12

Part B
5 a Write a HDL code for converting a binary(fraction) to a real number. 10 b Describe all file processing tasks in Verilog with examples. 10 6 a Explain implementation of two dimensional arrays in VHDL 10 b Explain Fetch and Execute cycles of a basic computer for an addition operation. 1 0 7 a How to invoke VHDL module from a Verilog module. 10 b Explain Mixed Language Description of an AND gate 10 8 a Explain synthesis steps 10 b Explain function mapping with example. 10

MODEL PAPER-2
Subject: Fundamentals of HDL SUBJECT CODE: 06ES45 Max marks : 100 Duration: 3Hrs
Note: Answer any five full questions selecting at least two from each part Q Part A marks 1 a Describe different types of HDL Description with suitable example. 10 b Discuss different types of HDL objects. 6 c What is HDL? Why do you need it? 4 2 a The following VHDL code describes an SR latch. Translate the code to Verilog.
Entity SR is Port (S, R : in bit; Q : buffer bit; Qb : out bit); End SR; Architecture SR_DtFL of SR is Begin

Q <= s or ( not R and Q); Qb <= not Q; End SR_DtFL;

10 b Write a data flow description of a system that has three 1-bit inputs a(1), a(2) and a(3) and one 1-bit output b. The least significant bit is a(1) and b is 1 only when (a(1)a(2)a(3) = 1, 3, 6 or 7 ( all in decimal), otherwise b is 0. Derive a minimized Boolean function of the system and write the data-flow description. 10 3 a What are the facts of Behavioral Description. 4 b Explain the Booth algorithm with a flow chart. Write VHDL/Verilog description for 4X4 Booth algorithm. 10 c Use the case statement to describe a 3 bit logical shift of register. The register should have a right/left control signal to control the direction of shift 6 4 a What is Binding? Discuss binding between library & components 6 b Design a counter that counts 0, 2, 3, 5, 7, 0, 2, using the state machine approach. Show all details of your answer. Write VHDL/Verilog code. 14

Part B
5 a Explain the following with syntax (i) Procedure in VHDL (ii) Tasks in Verilog with suitable examples in both the cases. 10 b Describe all file processing tasks in VHDL with examples 10 6 a What is necessity of Mixed-Type Description 4 b Write about User-defined types and Packages in VHDL 8 c Write a program to arrange n numbers in ascending order using one dimensional array 8 7 a How to invoke Verilog module from a VHDL module. 10 b Explain Mixed Language Description of a JK flip-flop with a clear pin 10 8 a What is synthesis information from entity and module 10 b Explain signal assignment statements and variable assignment statements with example 10

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