7.

Creating a System With Qsys

May 2013 QII51020-13.0.0 QII51020-13.0.0

Qsys is a system integration tool included as part of the Quartus II software. Qsys captures system-level hardware designs at a high level of abstraction and automates the task of defining and integrating customized HDL components, which may include IP cores, verification IP, and other design modules. Qsys facilitates design reuse by packaging and making available your custom components and systems, and integrates your custom components with Altera and third-party developer components. Qsys automatically creates interconnect logic from the connectivity options you specify, eliminating the error-prone and time-consuming task of writing HDL to specify the system-level connections. Qsys supports standard Avalon, AMBA AXI3 (version 1.0), AMBA AXI4 (version 2.0), and AMBA APB 3 (version 1.0) interfaces. For more information about Avalon and AMBA interfaces, refer to the Avalon Interface Specifications and the AMBA Protocol Specifications on the ARM website. AXI4-Lite is not supported. Qsys provides the following advantages for system design:

Automates the process of customizing and integrating components Supports 64-bit addressing Supports modular system design Supports visualization of systems Supports optimization of interconnect and pipelining within the system Provides full integration with the Quartus II software

f For descriptions of unique or exceptional AXI and APB support in the Qsys software, refer to the Qsys Interconnect chapter in volume 1 of the Quartus II Handbook. For more information about Avalon, AXI, and APB interfaces, refer to the Avalon Interface Specifications and the AMBA Protocol Specifications on the ARM website.

Qsys 64-Bit Addressing Support

Qsys interconnect supports up to 64-bit addressing for all Qsys interfaces and components, with a range of 0x0000 0000 0000 0000 to 0xFFFF FFFF FFFF FFFF, inclusive. In Qsys, address parameters appear in the Base and End columns on the System Contents tab, on the Address Map tab, in the parameter editor, and in validation messages. The Qsys GUI displays as many digits as needed in order to display the top-most set bit, for example, 12 hex digits for a 48-bit address.
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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A Qsys system can have multiple 64-bit masters, with each master establishing its own address space. Slaves may be shared among masters and masters can map slaves in different ways; for example, one master may interact with slave 0 at base address 0000_0000_0000, and another master may see the same slave at base address c000_000_000. 64-bit are also supported for narrow-to-wide and wide-to-narrow transactions across Avalon and AXI interfaces, though bursts that exceed 32-bits are legal only within the Avalon interface. AXI3 allows bursts of 1 - 16 transfers. AXI4 allows burst lengths of 256. Quartus II debug tools that provide access to the state of an addressable system via the Avalon-MM interconnect are also 64-bit compatible and process within a 64-bit address space, including a JTAG to Avalon master bridge.

Ports and Bridges

You can configure address ports within memory-mapped interfaces to be 64-bits wide. When a component's master port is not 64-bit capable, you can use the window bridge component (address span extender) to enable it to access a specific 32-bit segment of a 64-bit address map. The address span extender enables a 32-bit master to access a windowed portion of a larger memory map. The slave interface has an address port size corresponding to the address window. f For more information about the Address Span Extender feature, refer to the Qsys System Design Components chapter in volume 1 of the Quartus II Handbook.

DMA Controllers
DMA controllers are limited to 32-bit addressing. As a workaround, you can use the window bridge component, as described in Ports and Bridges above.

Qsys Interface Support

Qsys interconnect connects the following interface types:

Memory-MappedImplements a partial crossbar interconnect structure (AvalonMM, AXI, and APB) that provides concurrent paths between master and slaves. Interconnect consists of synchronous logic and routing resources inside the FPGA, and implementation is based on a network-on-chip architecture. StreamingConnects Avalon Streaming (Avalon-ST) sources and sinks that stream unidirectional data, as well as high-bandwidth, low-latency components. Streaming creates datapaths for unidirectional traffic including multichannel streams, packets, and DSP data. The Avalon-ST interconnect is flexible and can be used to implement on-chip interfaces for industry standard telecommunications and data communications cores, such as Ethernet, Interlaken, and video. In all cases, you can define bus widths, packets, and error conditions.

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InterruptsConnects interrupt senders and the interrupt receivers of the component that serves them. In systems with interrupt request sender (IRQ) interfaces, Qsys interconnect includes several components to implement interrupt processing. Qsys processes individual, single-bit interrupt requests (IRQs). In the event that multiple senders assert their IRQs simultaneously, the receiver logic (typically under software control) determines which IRQ has highest priority, then responds appropriately. ClocksConnects clock sources with clock input interfaces. ResetsConnects reset sources with reset input interfaces. If your system requires a particular positive-edge or negative-edge synchronized reset, Qsys inserts a reset controller to create the appropriate reset signal. If you design a system with multiple reset inputs, the Reset Controller ORs all reset inputs and generate a single reset output. A Reset Bridge allows you to use a reset signal in two or more subsystems of your Qsys system. ConduitsConnects point-to-point conduit interfaces. Conduit interfaces are brought to the top level of the system as additional ports, and are always point-topoint connections. Exported signals are usually either application-specific signals or the interface signals. Application-specific signals are exported to the top level of the system by the conduit interface(s) defined in a component. These are I/O signals in a components HDL logic that are not part of any Avalon interfaces and connect to an external device, for example DDR SDRAM memory, or logic defined outside of the Qsys system.

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Chapter 7: Creating a System With Qsys Understanding the Qsys Design Flow

Understanding the Qsys Design Flow

Figure 71 illustrates a bottom-up design flow example in Qsys.
Figure 71. Complete Qsys Design Flow
Create Component Using Component Editor, or Manually Creating the _hw.tcl File

Simulation at Unit-Level, Possibly Using BFMs

Does Simulation Give Expected Results? No 3

Yes

Debug Design

Complete System, Adding Components, IRQs, Addrs

Generate Qsys System

Yes

Constraint, Compile in Quartus II Generating .sof

Perform System-Level Simulation

Download .sof to PCB with Altera FPGA

Does Simulation Give Expected Results? No 7 10

Does HW Testing Give Expected Results? No Modify Design or Constraints

Yes Qsys System Complete

Debug Design

In the alternative top-down design flow, you begin by designing the Qsys system, and then define and instantiate custom Qsys components. The top-down design flow clarifies the system requirements earlier in the design process. Designs targeting HardCopy series devices require specific design constraints. Consequently, if you are targeting a HardCopy series device, you must verify your design for the HardCopy companion device.

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Follow these guidelines to verify your design for HardCopy devices: 1. In the Device dialog box in the Quartus II software, select both the FPGA and the appropriate HardCopy companion device. 2. In Step 8 of the design flow shown in Figure 71 compile for both the FPGA and HardCopy device. 3. After Step 10 of the design flow shown in Figure 71, if the FPGA passes all functional simulation and hardware verification tests, generate the HardCopy handoff archive file and send this archive file to the HardCopy Design Center for the backend flow implementation. h For more information about designing for HardCopy devices, refer to About Designing HardCopy Devices in Quartus II Help.

Searching for Component Files to Add to the Component Library

The component library includes the design elements that you use in your Qsys systems. Components can include Altera-provided IP cores, third-party IP cores, and custom IP cores that you provide. Previously created Qsys systems can also appear in the component library, and you can use these systems in other designs if they have exported interfaces. Altera and third-party developers provide ready-to-use components, which are installed automatically with the Quartus II software and are available in the Qsys component library. The Qsys component library includes the following components:

Microprocessors, such as the Nios II processor DSP IP cores, such as the Reed Solomon II core Interface protocols, such as the IP Compiler for PCI Express Memory controllers, such as the RLDRAM II Controller with UniPHY Avalon Streaming (Avalon-ST) components, such as the Avalon-ST Multiplexer IP core Qsys Interconnect components Verification IP (VIP) Bus Functional Models (BFMs)

You can set the IP Search Path option to specify custom and third-party components that you want to appear in the component library. Qsys searches for component files each time you open the tool, and locates and displays the list of available components in the component library. Qsys searches the directories listed in the IP Search Path for the following component file types:

Hardware Component Description Files (_hw.tcl) files. Each _hw.tcl file defines a single component. IP Index (.ipx) files. Each file indexes a collection of available components, or a reference to other directories to search. In general, .ipx files facilitate faster startup for Qsys and other tools because fewer directories need to be searched and analyzed.

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Qsys searches some directories recursively and other directories only to a specific depth. When a directory is recursively searched, the search stops at any directory containing a _hw.tcl or .ipx file; subdirectories are not searched. In the following list of search locations, a recursive descent is annotated by **. The * signifies any file.

PROJECT_DIR/* PROJECT_DIR/ip/**/* QUARTUS_INSTALLDIR/../ip/**/*

Complete the following steps to extend the default search path by specifying additional directories: 1. On the Tools menu, click Options. 2. In the Category list, click IP Search Path. 3. Click Add. 4. Browse to locate additional directories and click Open to add them to your search path. 1 You do not need to include the components specified in the IP Search Path as part of your Quartus II project.

Adding Components to the Component Library

Use one of the following methods to add components to the component library:

Copy Components to the Install Directory

The simplest method to add a new component to the Qsys Component Library is to copy your components into the default <install_dir>/ip/ directory provided by Altera. This approach is useful in the following situations:

You want to associate your components with a specific release of the Quartus II software. You want to have the same components available across multiple projects.

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Figure 72 illustrates this approach.

Figure 72. User Library Included In Subdirectory of <install_dir>/ip/

<install_dir> quartus ip altera altera_components.ipx <components> . .

user_components 2 component1 component1_hw.tcl component1.v component2 component2_hw.tcl component2.v

In Figure 72, the circled numbers identify a typical directory structure for the Quartus II software. For the directory structure above, Qsys performs the component discovery algorithm described below to locate .ipx and_hw.tcl files and initiate the component library: 1. Qsys recursively searches the <install_dir>/ip/ directory by default. The recursive search stops when Qsys finds an .ipx file. 2. As part of the recursive search, Qsys also looks in the user_components directory because this directory path appears as an IP Search Path in the Options dialog box. Qsys finds the component1 directory, which contains component1_hw.tcl. When Qsys finds that component, the recursive search ends, and no components in subdirectories of component1 are found. 3. Qsys then searches the component2 directory, because this directory path also appears as an IP Search Path, and discovers component2_hw.tcl. When Qsys finds component2_hw.tcl, the recursive search ends. 1 If you save your _hw.tcl file in the <install_dir>/ip/ directory, Qsys finds your _hw.tcl file and stops. Qsys does not conduct the component discovery algorithm just described.

Reference Components in an .ipx File

You can specify the search path in a user_components.ipx file under the <install_dir>/ip directory. This method allows you to store components in a location that is not linked to a specific Quartus II installation, and to add a location that is independent of the default search path. You can also save the .ipx file in any of the default search locations, for example, the Quartus II project directory, or the /ip directory in the project directory.

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The user_components.ipx file includes a single line of code redirecting Qsys to the location of each user library. Example 71 shows the redirection code.
Example 71. Redirect to User Library
<library> <path path="<user_lib_dir>/user_ip/**/*"/> </library>

You can verify that components are available with the ip-catalog command. You can use the ip-make-ipx command to create an .ipx file for a directory tree, which can reduce the startup time for Qsys. The following sections describe these commands. ipcatalog This command displays the catalog of available components relative to the current project directory in either plain text or XML format. Usage
ip-catalog [--project-dir=<directory>] [--name=<value>] [--verbose] [--xml] [--help]

Options

--project-dir=<directory>Optional. Components are found in locations relative to the project, if any. By default, the current directory, . is used. To exclude any project directory, leave the value empty. --name=<value>Optional. This argument provides a pattern to filter the names of the components found. To show all components, use a * or . By default, all components are shown. The argument is not case sensitive. --verboseOptional. If set, reports the progress of the command. --xmlOptional. If set, generates the output in XML format instead of a lineand colon-delimited format. --helpShows Help for the ip-catalog command.

ip-make-ipx This command creates an ip-make-ipx (.ipx) file and is a convenient way to include a collection of components from an arbitrary directory in the Qsys search path. You can also edit the .ipx file to disable visibility of one or more components in the Qsys component library. Usage
ip-make-ipx [--source-directory=<directory>] [--output=<file>] [--relative-vars=<value>] [--thorough-descent] [--message-before=<value>] [--message-after=<value>] [--help]

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Options

--source-directory=<directory>Optional. Specifies the root director(ies) that Qsys uses to find the component files. The default directory is .. You can also provide a comma separated list of directories. --output=<file>Optional. Specifies the name of the file to generate. The default name is /components.ipx. --relative-vars=<value>Optional. Causes the output file to include references relative to the specified variable or variables where possible. You can specify multiple variables as a comma-separated list. --thorough-descentOptional. If set, a component or .ipx file in a directory does not prevent subdirectories from being searched. --message-before=<value>Optional. A message to print to stdout when indexing begins. --message-after=<value>Optional. A message to send to stdout when indexing completes. --helpShow Help for this command.

Understanding IPX File Syntax An .ipx file is an XML file that describes the search path used to discover components that are available for a Qsys system. A <path> entry specifies a directory in which components may be found. A <component> entry specifies the path to a single component. Example 72 illustrates this format.
Example 72. .ipx File Structure
<library> <path path="<user directory>" /> <path path="<user directory>" /> <component file="<user directory>" /> </library>

A <path> element contains a path attribute, which specifies the path to a directory, or the path to another .ipx file, and can use wildcards in its definition. An asterisk matches any file name. If you use an asterisk as a directory name, it matches any number of subdirectories. When searching the specified path, the following three types of files are identified:

.ipxadditional index files _hw.tclQsys component definitions _sw.tclNios II board support package (BSP) software component definitions

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A <component> element contains several attributes to define a component. If you provide the required details for each component in an .ipx file, the startup time for Qsys is less than if Qsys must discover the files in a directory. Example 73 shows two <component> elements. Note that the paths for file names are specified relative to the .ipx file.
Example 73. Component Elements
<library> <component name="A Qsys Component" displayName="Qsys FIR Filter Component" version="2.1" file="./components/qsys_filters/fir_hw.tcl" /> <component name="rgb2cmyk_component" displayName="RGB2CMYK Converter(Color Conversion Category!)" version="0.9" file="./components/qsys_converters/color/rgb2cmyk_hw.tcl" /> </library>

Integrating Third-Party Components

You can use Qsys components created by third-party IP developers. Altera awards the Qsys Compliant label to IP cores that are fully supported in Qsys. These cores support Avalon AXI interfaces and may include timing and placement constraints, software drivers, simulation models, and reference designs. f To find supported third-party Qsys components, on the Intellectual Property & Reference Designs web page, type Qsys Certified in the Search box, select IP Core & Reference Designs, and then press Enter.

Creating a Qsys System

You can create a Qsys system in the Quartus II software by clicking Qsys System File in the New dialog box, or opening Qsys from the Tools menu. To open a previously created Qsys design, click Open on the File menu in the Quartus II software window, or the Qsys window. h For more information about the Qsys GUI, refer to About Qsys in Quartus II Help. Qsys is more powerful if you design your custom components using standard interfaces. By using standard interfaces, your components inter-operate with the components in the Qsys component library. In addition, you can take advantage of bus functional models (BFMs), monitors, and other verification IP to verify your design.

Adding System Contents

The Component Library tab displays the components that you add to your system.

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Adding Components
To add a component to your system, select the component in the Component Library, and then click Add. A parameter editor appears allowing you to configure the component instance. 1 You can type some or all of the components name in the Component Library search box to help locate a particular component type. For example, you can type memory to locate memory-mapped components, or axi to locate AXI interconnect components.

Working With Presets for Supported IP Components

When you add a component to your system, the Qsys Presets Editor opens for IP components whose parameters you are allowed to modify and lists presets that you can apply to your component, depending on the design protocol. When you apply a preset to a component, the parameters with specific required values for the protocol are automatically set for you. You can search for text to filter the Presets list. For example, if you select the DDR3 SDRAM Controller with UniPHY component, and then type 1g micron 256, the Presets list shows only those presets that apply to the 1g micron 256 protocol. Presets whose parameter values match the current parameter settings are shown in bold. Selecting a preset does not prevent you from changing any parameter to meet the requirements of your design. Clicking Update allows you to update parameter values for a custom preset. The Update Preset dialog box displays the default value, which you can edit, and the current value, which is static. You can also create your own preset by clicking New. When you create a preset, you specify a name, description and the list of parameters whose values are set by the preset. You can remove a preset from the Quartus II project directory by clicking Delete. h For more information about presets, refer to Presets Editor in Quartus II Help.

Connecting Components
When you add connections to a Qsys system, you connect the interfaces of the modules in the system. The individual signals in each interface are connected by the Qsys interconnect when the HDL for the system is generated. You connect interfaces of compatible types and opposite directions. For example, you can connect a memory-mapped master interface to a slave interface, and an Interrupt sender interface to an Interrupt receiver interface.

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To view possible connections for an interface on the System Contents by hovering your pointer in the Connections column. In this view, open circles represent possible connections, and filled circles indicate connections that you have made. To make a connection, click the open circle at the intersection of the two interface names. Clicking a filled-in circle removes the connection. Figure 73 illustrates the connections display.
Figure 73. Connections Column

h For more information about connecting components, refer to Connecting Qsys Components in Quartus II Help.

Filtering Components
You can use the Filters dialog box to filter the display of your system in the System Contents tab. You can filter the display of your system by interface type, instance name, or by using custom tags. For example, you can use filtering to view only instances that include memory-mapped interfaces, instances that are connected to a particular Nios II processor, or to temporarily hide clock and reset interfaces to simplify the display. h For more information about filtering components, refer to the Filters Dialog Box in Quartus II Help.

Using the System Inspector

The System Inspector tab displays the underlying model of your complete system, and provides comprehensive details about your system such as the following information:

The connections between signals The names of signals included in exported interfaces

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The internal connections of Qsys subsystems that are included as components 1 In contrast, the System Contents tab displays only the exported interfaces of Qsys subsystems included as components.

The global parameter settings that you specified on the Project Settings tab

You can use the System Inspector tab to review and change component parameters and to review interface timing. For example, Figure 74 shows the timing for the Avalon-MM DMA write master for the PCI Express-to-Ethernet system illustrated in Figure 712 on page 730.
.

Figure 74. Avalon-MM Write Master Timing Waveforms Available on the Project Settings Tab

To display the timing for an interface, expand the component, and then click the interface name.

Defining the Address Map

The Address Map tab provides a table including all the memory-mapped slaves in your design and the address range that each connected memory-mapped master uses to address that slave. The table shows the slaves on the left and masters across the top, with the address span of the connection shown in each cell. A blank cell implies that there is no connection between that master and slave. Follow these steps to change or create a connection between master and slave components: 1. In Qsys, click the Address Map tab. 2. Locate the table cell that represents the connection between the master and slave component pair. 3. Either type in a base address or update the current base address in the cell.

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You can design a system where two masters access a slave at different addresses. If you use this feature, the Base and End address columns of the System Contents tab are labeled mixed rather than providing the address range.

Specifying Clock Settings

The Clock Settings tab defines the Name, Source, and frequency (MHz) of each clock in your system. Clicking the Add button adds a new clock. h For more information, refer to the Adding Components to a Qsys System in Quartus II Help.

Specifying Project Settings

The Project Settings tab allows you to view and change the properties of your Qsys system. Table 71 describes system-level parameters available on the Project Settings tab.
Table 71. Project Settings Parameters Parameter Name Device Family Device Specifies the Altera device family. Specifies the target device for the selected device family. Specifies the default implementation for automatically inserted clock crossing adapters. The following choices are available:

Description

HandshakeThis adapter uses a simple hand-shaking protocol to propagate transfer control signals and responses across the clock boundary. This methodology uses fewer hardware resources because each transfer is safely propagated to the target domain before the next transfer can begin. The Handshake adapter is appropriate for systems with low throughput requirements. FIFOThis adapter uses dual-clock FIFOs for synchronization. The latency of the FIFO-based adapter is a couple of clock cycles more than the handshaking clock crossing component, but the FIFO-based adapter can sustain higher throughput because it supports multiple transactions at any given time. The FIFO-based clock crossers require more resources. The FIFO adapter is appropriate for memory-mapped transfers requiring high throughput across clock domains. AutoIf you select Auto, Qsys specifies the FIFO adapter for bursting links, and the Handshake adapter for all other links.

Clock Crossing Adapter Type

Limit interconnect pipeline stages to

Specifies the maximum number of pipeline stages that Qsys may insert in each command and response path to increase the fMAX at the expense of additional latency. You can specify between 04 pipeline stages, where 0 means that the interconnect has a combinational data path. Choosing 3 or 4 pipeline stages may significantly increase the logic utilization of the system. This setting is per Qsys system or subsystem, meaning that each subsystem can have a different setting. Note that the additional latency is for both the command and response directions for the two Qsys systems, even if you combine them into a single Quartus II project. A unique integer value that is set to a timestamp just before Qsys system generation that Qsys uses to check for software compatibility.

Generation Id

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Qsys generates a warning message if the selected device family and target device do not match the Quartus II software project settings. Also, when you open Qsys from within the Quartus II software, the device type in your Qsys project is replaced with the selected device in your open Quartus II software project.

Defining Qsys Instance Parameters

The Instance Parameters tab allows you to define parameters for a Qsys system. You can use instance parameters to modify a Qsys system when you use the system as a subcomponent in another Qsys system. The higher-level Qsys system can assign values to these instance parameters. The Instance Script on the Instance Parameters tab defines how the specified values for the instance parameters should affect your Qsys design subcomponents. The instance script allows you to make queries about the instance parameters you define and set the values of the parameters for the subcomponents in your design. When you click Preview Instance, Qsys creates a preview of the current Qsys system with the specified parameters and instance script, and shows the parameter editor for the instance. This allows you to see how an instance of this system appears when you use it in another system. The preview instance does not affect your saved system. h For more information, refer to Working with Instance Parameters in Qsys in Quartus II Help. To use Instance Parameters, the components or subsystems in your Qsys system must have parameters that can be set when they are instantiated in a higher-level system. Many components in the Component Library have parameters that you can set when adding the component to your system. If you create your own IP components, you use the _hw.tcl file to specify which parameters can be set when the component is added to a system. If you create hierarchical Qsys systems, each Qsys system in the hierarchy can include instance parameters to pass parameter values through multiple levels of hierarchy. f For more information on creating your own components and specifying parameters, refer to the Component Interface Tcl Reference chapter in the Quartus II Handbook.

Creating an Instance Script

The first command in an instance script must specify the version of the Tcl commands to be used in the script. This command ensures the Tcl commands behave identically in future versions of the tool. Use the following Tcl command to specify the version of the Tcl commands, where <version> is a Quartus II software version number, such as 13.0:
package require -exact qsys <version>

To use Tcl commands that work with instance parameters in the instance script, you must specify the commands within a Tcl procedure called a composition callback. In the instance script, you specify the name for the composition callback with the following command:
set_module_property COMPOSITION_CALLBACK <name of callback procedure>

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Specify the appropriate Tcl commands inside the Tcl procedure with the following syntax:
proc <name of procedure defined in previous command> {} { #Tcl commands to query and set parameters go here }

Use Tcl commands in the procedure to query the parameters of a Qsys system, or to set the values of the parameters of the subcomponents instantiated in the system. Table 72 describes the supported Tcl commands.
Table 72. Hardware Tcl Commands Used in Instance Scripts Command Name get_parameters get_parameter_value get_instance_parameters get_instance_parameter_value Value <parameter name > <instance name> <instance name> Description Get the names of all defined parameters (as a space-separated list). Get the value of a parameter. Get the names of parameters on a child instance that can be manipulated by the parent (as a space-separated list). Get the value of a parameter for a child instance. Send a message to the user of the component, using one of the message levels Error, Warning, Info, or Debug. Enclose text with multiple words in quotation marks. Set a parameter value for a child instance.

send_message

<message level> <message text>

set_instance_parameter_value

<instance name> <parameter name> <parameter value>

f For more information about _hw.tcl syntax and manipulating parameters, refer to the Component Interface Tcl Reference chapter in the Quartus II Handbook. You can use standard Tcl commands to manipulate parameters in the script, such as the set command to create variables, or the expr command for mathematical manipulation of the parameter values. Example 74 shows an instance script of a simple system that uses a parameter called pio_width to set the width parameter of a parallel I/O (PIO) component. Note that the script combines the get_parameter_value and set_instance_parameter_value commands into one command using square brackets []. Example 74. Simple Instance Script
# Request a specific version of the scripting API package require -exact qsys 13.0 # Set the name of the procedure to manipulate parameters: set_module_property COMPOSITION_CALLBACK compose proc compose {} { #Get the pio_width parameter value from this Qsys system and pass the #value to the width parameter of the pio_0 instance set_instance_parameter_value pio_0 width [get_parameter_value \ pio_width] }

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For another example, refer to Hierarchical System Using Instance Parameters Example on page 733.

Viewing the HDL Example

The HDL Example tab provides the top-level HDL definition of your system in either Verilog HDL or VHDL, and also displays VHDL component declarations. You can copy and paste the example into a top-level HDL file that instantiates the Qsys system, if the system is not the top-level module in your Quartus II project.

Creating Hierarchical Systems

Qsys supports team-based and hierarchical system design. You can include any Qsys system that exports an interface as a component in another Qsys system. In a teambased design flow, you can have one or more systems in your design developed simultaneously by other team members, decreasing time-to-market for the complete design. Figure 75 shows the top-level of a Qsys hierarchical design that implements a PCI Express to Ethernet bridge. This example combines separate PCI Express and Ethernet subsystems with Alteras DDR3 SDRAM Controller with UniPHY IP core.
Figure 75. Top-Level for a PCI Express to Ethernet Bridge
Qsys System PCIe to Ethernet Bridge

DDR3 SDRAM

DDR3 SDRAM Controller

PHY Cntl Mem Slave

PCI Express Subsystem

Mem Mstr CSR

PCIe

Embedded Cntl

Mem Mstr

CSR

Ethernet Subsystem

Ethernet

Hierarchical system design in Qsys offers the following advantages:

Enables team-based, modular design by dividing large designs into subsystems. Enables design reuse by allowing you to use any Qsys system as a component. Enables scalability by allowing you to instantiate multiple instances of a Qsys system.

For more information about hierarchical design, refer to PCI Express Subsystem Example on page 729.

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Adding Systems to the Component Library

Any Qsys system that exports an interface is available for use in other Qsys systems. Figure 76 shows the component library, including the PCI Express and Ethernet subsystems as components in the component library for the PCI Express to Ethernet Bridge example system in Figure 715 on page 731. To include systems as components in other designs, you can add the system to the component library, or include the directory for the system in component search path for Qsys.

Creating a Component Based on a System

The Export System as hw.tcl Component command on the File menu allows you to save the system currently open in Qsys as an _hw.tcl file in the current working directory. The saved system appears in the System list under Project in the Qsys Component Library. 1 Because Qsys systems become components in the component library, be careful not to give your system a name that is already is use.

Figure 76. Qsys Component Library

Creating Secure Systems (TrustZones)

TrustZone refers to the security extension of the ARM architecture, which includes the concept of secure and non-secure transactions, and a protocol for processing between the designations. TrustZone security support is a part of the Qsys interconnect. In Qsys, AXI masters are treated as TrustZone-aware; all other memory-mapped interfaces are set to secure, non-secure or TrustZone-aware (only for AXI slaves with TrustZone support). The default value for non-AXI master interfaces is non-secure. Unless specified, all non-TrustZone-aware components are treated as non-secure, for example, Avalon master and slave components. Qsys provides compilation-time TrustZone support for non-TrustZone-aware components, for cases such as when an Avalon master needs to communicate with a secure AXI slave. For example, the designer can specify whether the connection point is secure or non-secure at compilation time. You can specify secure address ranges on memory slaves, if a per-interface security setting is not sufficient.

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For TrustZone-aware masters, the interconnect uses the master's AxPROT signal to determine the security status of each transaction. The table below summarizes secure and non-secure access between master, slave, and memory components in Qsys. Per-access refers to allowing a TrustZone-aware master to allow or disallow a particular access (or transactions).
Table 73. Transaction Type TrustZone-aware slave/memory Non-TrustZone-aware slave (secure) Non-TrustZone-aware slave (non-secure) Non-TrustZone-aware memory (secure region) TrustZone-aware Master OK Per-access OK Per-access Non-TrustZone-aware Master Secure OK OK OK OK OK Non-TrustZone-aware Master Non-Secure OK Not allowed OK Not allowed OK

Non-TrustZone-aware memory (non-secure region) OK

If a master issues transactions that fall into the per-access or not allowed cells, as described in the table above, your design must contain a default slave. A transaction that violates security is rerouted to the default slave and subsequently terminated with an error. You can connect any slave as the default that is able to respond to the master that requires a default slave with errors. You can share the default slave between multiple masters. Altera recommends that you have one default slave for each domain. Altera also recommends that you use the altera_axi_default_slave component as the default slave because this component has the required TrustZone features. In Qsys, you can achieve an optimized secure system by planning how you partition your design. For example, for masters and slaves under the same hierarchy, it is possible for a non-secure master to initiate continuous transactions resulting in unsuccessful transfer to a secure slave. In the case of a memory aliasing, you must carefully designate secure or non-secure address maps to maintain reliable data.

Managing Secure Settings in Qsys

To create a secure design, you must first add masters and slaves and the connections between them. Once you establish connections between the masters and slaves, you can then set the security options, as required, with options in the Security column. On the System Contents tab, in the Security column, the following selections are available for master, slave, and memory components:

Non-secureMaster issues only non-secure transactions. There is no security available for the slave. SecureMaster issues only secure transactions. For the slave, Qsys prevents nonsecure transactions from reaching the slave, and routes them to the default slave for the master that issued the transaction. Secure RangesSlave only, the specified address ranges within the slave's address span are secure; all others are not. The format is a comma-separated list of inclusiveLow:inclusiveHigh addresses, for example, 0x0:0xfff,0x2000:0x20ff. TrustZone-awareMaster issues either secure or non-secure transactions at runtime. The slave accepts either secure or non-secure transactions at run-time.

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After setting security options for the masters and slaves, you must identify those masters that require a default slave before generation. To designate a slave as the default slave, turn on Default Slave in the Systems Contents tab. A master can have only one default slave.

Understanding Compilation-Time Security Configuration Options

The following compile-time configurations are available when creating secure designs that have mixed secure and non-secure components:

Masters that support TrustZone and are connected to slaves that are compile-time secure. This configuration requires a default slave. Slaves that support TrustZone and are connected to masters that have compiletime secure settings. This configuration does not require a default slave. Master connected to slaves with secure address ranges. This configuration requires a default slave.

Generating Output Files From a Qsys System

Qsys system generation creates the interconnect between components and generates files that you use to synthesize or simulate the design. You specify the files that you want to generate on the Generation tab. You can generate simulation models, simulation testbench files, as well as HDL files for Quartus II synthesis, or a Block Symbol File (.bsf) for schematic design. For your simulation model and testbench system, you can select Verilog or VHDL for the top-level module language, which applies to the system's top-level definition and child instance that support generation for the selected target language. For synthesis, you can select the top-level module language as Verilog or VHDL, which applies to the systems top-level definition. If the design contains a composed _hw.tcl component or .qsys sub-modules, the language selection also applies to the sub-modules. For non-composed _hw.tcl sub-modules, a Verilog synthesis file is generated. The default target language for simulation, testbench system, and synthesis is Verilog. Qsys places the generated output files in a subdirectory of your project directory, along with an HTML report file. To change the default behavior, on the Generation tab, specify a new directory under Output Directory.

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Figure 77 illustrates the directory structure for the output files.

Figure 77. Qsys Generated Files Directory Structure
<qsys_design> synthesis submodules simulation submodules testbench simulation submodules

Table 74 describes the files that Qsys generates. Each time you generate your system, Qsys overwrites these files, therefore, you should not edit Qsys-generated output files. If you have constraints, such as board-level timing constraints, Altera recommends that you create a separate Synopsys Design Constraints File (.sdc) and include that file in your Quartus II project. If you need to change top-level I/O pin names or instance name, Altera recommends you create a top-level HDL file that instantiates the Qsys system, so that the Qsys-generated output is instantiated in your design without any changes to the Qsys output files.
Table 74. Qsys Generated Files (Part 1 of 2) File Name or Directory Name <qsys_design> <qsys_design>.bsf <qsys_design>.html The top-level project directory. A Block Symbol File (.bsf) representation of the top-level Qsys system for use in Quartus II Block Diagram Files (.bdf). A report for the system, which provides a system overview including the following information:

Description

External connections for the system A memory map showing the address of each slave with respect to each master to which it is connected Parameter assignments for each component

<qsys_design>.sopcinfo

Describes the components and connections in your system. This file is a complete system description and is used by downstream tools such as the Nios II tool chain. It also describes the parameterization of each component in the system; consequently, you can parse its contents to get requirements when developing software drivers for Qsys components. This file and the system.h file generated for the Nios II tool chain include address map information for each slave relative to each master that accesses the slave. Different masters may have a different address map to access a particular slave component.

/synthesis <qsys_design>.v

This directory includes the Qsys-generated output files that the Quartus II software uses to synthesize your design. An HDL file for the top-level Qsys system that instantiates each component in the system.

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Table 74. Qsys Generated Files (Part 2 of 2) File Name or Directory Name <qsys_design>.qip <qsys_design>.sip <qsys_design>.spd /submodules /simulation <qsys_design>.v or <qsys_design>.vhd /mentor/ /aldec /synopsys/vcs/ /synopsys/vcsmx /cadence /testbench <qsys_design>_tb.qsys <qsys_design>_tb.v <qsys_design>_tb.vhd <system_name>_<module_name>_ <master_interface_name>.svd Description This file lists the Quartus II software needed to compile your design. You must add the.qip file to your Quartus II project. This file lists the files necessary for simulation with Nativelink. You must add the .sip file to your Quartus II project. Required input file for ip-make-simscript to generate simulation script for supported simulators. Contains Verilog HDL or VHDL submodule files for synthesis. This directory includes the Qsys-generated output files to simulate your Qsys design or testbench system. An HDL file for the top-level Qsys system that instantiates each submodule in the system. Contains a ModelSim script msim_setup.tcl to set up and run a simulation. Contains Riviera-PRO script rivierapro_setup.tcl to setup and run a simulation. Contains a shell script vcs_setup.sh to set up and run a VCS simulation. Contains a shell script vcsmx_setup.sh and synopsys_sim.setup to set up and run a VCS MX simulation. Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation. Contains a Qsys testbench system as described in the Simulating a Qsys System section below. A Qsys testbench system. The top-level testbench file, which connects BFMs to the top-level interfaces of <qsys_design>.qsys. Allows HPS System Debug tools to view the register maps of peripherals connected to the HPS within a Qsys design.

CMSIS Support for Qsys Systems With An HPS Component

Qsys systems that contain a Hard Processor System (HPS) component generate a System View Description (.svd) file that lists peripherals connected to the ARM processor. The .svd (or CMSIS-SVD) file format is an XML schema specified as part of the Cortex Microcontroller Software Interface Standard (CMSIS) provided by ARM. The CMSIS-SVD file allows HPS System Debug tools (such as the DS-5 Debugger) to gain visibility into the register maps of peripherals connected to the HPS within a Qsys system. Qsys supports the ability for IP component designers to specify register map information on their slave interfaces. This allows components with slave interfaces that are connected to an HPS component to include their internal register description in the generated .svd file. To specify their internal register map, the IP component designer must write and generate their own .svd file and attach it to the slave interface using the following command: set_interface_property <slave interface> CMSIS_SVD_FILE <file path>

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For information about the set_interface_property command and its properties, refer to the Component Interface Tcl Reference chapter in the Quartus II Handbook. For complete CMSIS specifications, refer to CMSIS - Cortex Microcontroller Software Interface Standard on the ARM website.

Using Qsys With the Quartus II Software

This section describes the Quartus II software features that integrate with Qsys, including the following:

Quartus II IP File Synopsys Design Constraint Quartus II Simulation IP File PLLs and Clocks

Quartus II Project Files

The Quartus II IP File (.qip) provides the Quartus II software with all required information about your Qsys system. Qsys creates the .qip during system generation and adds a reference to it in the Quartus II Settings File (.qsf). The information required to process most Qsys components is included in the system's single .qip file, though some more complex components provide their own .qip file, in which case the system's .qip file references the components .qip file. You must add the Qsys-generated Quartus II IP File (.qip) to your Quartus II project before you compile a design that includes a Qsys system. The .qip file is stored in the synthesis directory after generation, and lists the files necessary for compilation, and includes references to the following information:

HDL files used in the Qsys system TimeQuest Timing Analyzer Synopsys Design Constraint (.sdc) files Component definition files for archiving purposes

Qsys automatically generates an .sdc file for Qsys systems and components. In most cases, you use TimeQuest constraints to declare false paths for signals that cross clock domains within a component, so that the TimeQuest Timing Analyzer does not perform setup and hold analysis for them. You can add .sdc files for custom components, with the Add Files command on Files tab in the Component Editor. To use Nativelink simulation integration with a Qsys system, you must add the Quartus II Simulation IP File (.sip) file to your Quartus II project. The .sip file lists the files necessary for simulation with Nativelink. The .sip file is stored in the synthesis directory after generation. 1 Add the generated .qip file, not the .qsys file, to your Quartus II project.

f Refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook for further description of the TimeQuest Timing Analyzer. h For more information about adding files to your Quartus II project, refer to Managing Files in a Project in Quartus II Help.

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Working With PLLs and Clocks

You must provide clock and timing constraints in Synopsys Design Constraint File (.sdc) format to direct Quartus II synthesis and fitting to optimize the design appropriately, and to set up the TimeQuest timing analyzer to check that the design meets timing performance requirements. You must specify a base clock assignment for each clock input with the create_clock command, and then you can use the derive_pll_clocks command to define the PLL clock output frequencies and phase shifts for all PLLs in the Quartus II project. The Qsys system shown in Figure 78 illustrates the .sdc commands required for the case of a single clock input signal called clk, and one PLL with a single output.
Figure 78. Single Clock Input Signal

For this system, use the following commands in your .sdc file for the TimeQuest Timing Analyzer:
create_clock -name master_clk -period 20 [get_ports {clk}] derive_pll_clocks

These commands create the input clock and the derived clock output of the PLL. The TimeQuest Timing Analyzer analyzes and reports performance of the constrained clocks in the Clocks Summary report, as shown in Figure 79.
Figure 79. Clocks Summary Report

master_clk is defined by the create_clock command, and the_my_pll clock is derived from the derive_pll_clocks command.

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Simulating a Qsys System

The Qsys Generation tab provides the following options for simulating a Qsys system:

Generate the Verilog or VHDL simulation model for your system to use in your own simulation environment. Generate a standard or simple testbench system with BFM or Mentor Verification IP (for AXI3/AXI4) components that drive the external interfaces of your system, and generate a Verilog or VHDL simulation model for the testbench system to use in your simulation tool. First generate a testbench system, and then modify the testbench system in Qsys before generating its simulation model.

In most cases, you should select only one of the simulation model options, that is generate a simulation model for the original system, or for the testbench system. Table 75 summarizes the options on the Generation tab that correspond to the simulation flows described above.
le

Table 75. Summary of Settings Simulation and Synthesis on Qsys Generation Tab Simulation Setting Create simulation model Value None Verilog VHDL Description Creates simulation model files and simulation scripts. Use this option to include the simulation model in your own custom testbench or simulation environment. You can also use this option to generate models for a testbench system that you have modified. Creates a testbench Qsys system with BFM components attached to exported Avalon and AXI3 interfaces. Includes any simulation partner modules specified by IP cores in the system. In Qsys 13.0, the testbench generator supports AXI interfaces and can connect AXI3/AXI4 interfaces to Mentor Graphics AXI3/AXI4 master/slave BFM. For more information, refer to the Mentor Verification IP (VIP) Altera Edition (AE) document. However, BFM supports only an address width of up to 32-bits. Creates a testbench Qsys system with BFM components driving only clocks and reset interfaces. Includes any simulation partner modules specified by IP cores in the system. Creates simulation model files and simulation scripts for the testbench Qsys system specified in the setting above. Use this option if you do not need to modify the Qsys-generated testbench before running the simulation. Creates Verilog or VHDL design files. Creates the top-level module in the system in the selected language. You can optionally create a (.bsf) file to use in schematic Block Diagram File (.bdf) designs. Allows you to browse and locate an alternate directory than the project directory for each generation target.

Create testbench Qsys system

Standard, BFMs for standard Qsys Interconnect

Simple, BFMs for clocks and resets None Verilog VHDL On/Off Verilog VHDL On/Off <directory name>

Create testbench simulation model Create HDL design files for synthesis Top-level module language for synthesis Create block symbol files (.bsf) Output Directory

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f For more information about using bus functional models (BFMs) and monitors to simulate Avalon standard interfaces, including tutorials demonstrating sample systems, refer to the Avalon Verification IP Suite User Guide. For AXI verification protocol information, refer to the Mentor Verification IP (VIP) Altera Edition (AE) document. h For more information about generating system synthesis or simulation models, and a standard Qsys testbench, refer to Generating a System for Synthesis or Simulation and Generation Tab (Qsys) in Quartus II Help.

Testbench Design Flow

You can use the following design flows to create a testbench system of your Verilog or VHDL design.

Generate the Testbench System and a Simulation model at the Same Time (Verilog only)
1. Create a Qsys system. 2. Generate a Verilog testbench system and the simulation model for the testbench system on the Qsys Generation tab. 3. Create a custom test program for the BFMs. 4. Compile and load the Qsys design and testbench in your simulator, and then run the simulation.

Generate the Testbench System (Verilog and VHDL)

1. Create a Qsys system. 2. Generate a Verilog or VHDL testbench system on the Qsys Generation tab. 3. Open the testbench system in Qsys. Make changes, as needed, to the BFMs, such as changing the BFM instance names and BFM's VHDL ID value. You can modify the VHDL ID value in the Altera Avalon Interrupt Source component. 4. If you modified a BFM, generate the simulation model for the testbench system on the Qsys Generation tab. 5. Create a custom test program for the BFMs. 6. Compile and load the Qsys design and testbench in your simulator, and then run the simulation.

Adding Assertion Monitors

You can add monitors to Avalon-MM, AXI, and Avalon-ST interfaces in your system to verify protocol correctness and test coverage with a simulator that supports SystemVerilog assertions. 1 Modelsim Altera Edition does not support SystemVerilog assertions. If you want to use assertion monitors, you will need to use an advanced simulator such as Mentor Questasim, Synopsys VCS, or Cadence Incisive.

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Figure 710 demonstrates the use of monitors with an Avalon-MM monitor between the previously connected pcie_compiler bar1_0_Prefetchable Avalon-MM master interface and the dma_0 control_port_slave Avalon-MM slave interface.
Figure 710. Inserting an Avalon-MM Monitor between Avalon-MM Master and Slave Interfaces

Similarly, you can insert an Avalon-ST monitor between Avalon-ST source and sink interfaces.

Simulation Scripts
Qsys generates simulation scripts to script the simulation environment set up for Mentor Graphics Modelsim and Questasim, Synopsys VCS and VCS MX, Cadence Incisive Enterprise Simulator (NCSIM), and the Aldec Riviera-PRO Simulator. You can use the scripts to compile the required device libraries and system design files in the correct order and elaborate or load the top-level design for simulation. The simulation scripts provide the following variables that allow flexibility in your simulation environment:

TOP_LEVEL_NAMEIf the Qsys testbench system is not the top-level instance in your simulation environment because you instantiate the Qsys testbench within your own top-level simulation file, set the TOP_LEVEL_NAME variable to the top-level hierarchy name. QSYS_SIMDIRIf the simulation files generated by Qsys are not in the simulation working directory, use the QSYS_SIMDIR variable to specify the directory location of the Qsys simulation files. QUARTUS_INSTALL_DIR Points to the device family library.

Example 75 shows a simple top-level simulation HDL file for a testbench system pattern_generator_tb, which was generated for a Qsys system called pattern_generator. The top.sv file defines the top-level module that instantiates the pattern_generator_tb simulation model as well as a custom SystemVerilog test program with BFM transactions, called test_program.
Example 75. Top-level Simulation HDL File
module top(); pattern_generator_tb tb(); test_program pgm(); endmodule

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Refer to the following documents for simulation script examples:

ModelSim-Altera software, Mentor Graphics ModelSim support Synopsys VCS and VCS MX support Cadence Incisive Enterprise Simulator (IES) support Aldec Active-HDL and Rivera-PRO support

Simulating Software Running on a Nios II Processor

To simulate the software in a system driven by a Nios II embedded processor, generate the simulation model for a simple Qsys testbench system by completing the following steps: 1. On the Generation tab, set Create testbench Qsys system to Simple, BFMs for clocks and resets. 2. Set Create testbench simulation model to Verilog or VHDL. 3. Click Generate. Follow these steps to use the software build tools for simulation: 1. Open the Nios II Software Build Tools for Eclipse. 2. Set up an application project and board support package (BSP) for the <qsys_system> .sopcinfo file. 3. To optimize the BSP for simulation and disable hardware programming, right-click the BSP project and click Properties, and then click Nios II BSP Properties, and turn on ModelSim only, no hardware support. 4. To simulate, right-click the application project in Eclipse, point to Run as, and then click 4 Nios II ModelSim. The Run As Nios II ModelSim command sets up the ModelSim simulation environment, compiles and loads the Nios II software simulation. 5. To run the simulation in ModelSim, type run -all in the ModelSim transcript window. 6. If prompted, set ModelSim configuration settings and select the correct Qsys Testbench Simulation Package Descriptor (.spd) file, <qsys_system>_tb.spd. The .spd file is generated with the testbench simulation model for Nios II designs and specifies all the files required for the Nios II software simulation. f For more information about the Nios II SBT for Eclipse, refer to Getting Started with the Graphical User Interface in the Nios II Software Developers Handbook. For more information about the Nios II SBT command-line options, refer to Getting Started from the Command-Line in the Nios II Software Developer's Handbook.

System Examples
This section includes a detailed system example that demonstrates design hierarchy and the use of pipeline bridges, and an example that shows the use of instance parameters to control the instantiation of subcomponents in a hierarchical system.

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PCI Express Subsystem Example

Figure 711 shows the details of the PCI Express example subsystem, which is also illustrated at a high level in Figure 75 on page 717. In this example, an application running on the root complex processor programs the DMA controller. The DMA controllers Avalon-MM read and write master interfaces initiate transfers to and from the DDR3 memory and to the PCI Express Avalon-MM TX data port. The system exports the DMA master interfaces through an Avalon-MM pipeline bridge. As Figure 711 illustrates, all three masters connect to a single slave interface. During system generation, Qsys automatically inserts arbitration logic to control access to this slave interface. By default, the arbiter provides equal access to all requesting masters; however, you can weight the arbitration by changing the number of arbitration shares for the requesting masters. The second pipeline bridge allows an external master, such as a host processor, to also issue transactions to the CSR interfaces. f For more information, refer to Arbitration in the Qsys Interconnect chapter in volume 1 of the Quartus II Handbook.
Figure 711. PCI Express Subsystem

PCI Express Subsystem

DMA Controller
CSR Rd Wr
S M M

PCI Express IP Core

M CSR S CSR S Tx Data Cn

PCIe Link (exported to PCIe root port)

Avalon-MM PIpeline Bridge (Qsys)

M

Avalon-MM PIpeline Bridge (Qsys)

S

Cntl and Status Avalon-MM Slave (exported to Embedded Controller) DMA Avalon-MM Master (exported to DDR3 Controller)

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Figure 712 shows the Qsys representation of the PCI Express subsystem.
Figure 712. Qsys Representation of the PCI Express Subsystem

Ethernet Subsystem Example

Figure 713 expands the details of the Ethernet subsystem example from Figure 75. In this subsystem, the transmit (TX) DMA receives data from the DDR3 memory and writes it to the Altera Triple-Speed Ethernet IP core using an Avalon-ST source interface. The receive (RX) DMA accepts data from the Triple-Speed Ethernet IP core on its Avalon-ST sink interface and writes it to DDR3 memory. The read and write masters of both Scatter-Gather DMA controllers and the Triple-Speed Ethernet IP core connect to the DDR3 memory through an Avalon-MM pipeline bridge. This Ethernet example subsystem exports all three control and status interfaces through an Avalon-MM pipeline bridge, which connects to a controller outside of the Qsys system.
Figure 713. Scatter-Gather DMA-to-Ethernet Subsystem

Ethernet Subsystem
Qsys inserts arbitration logic
M M M

DDR3

Avalon-MM Pipeline Bridge M S (Qsys)

Scatter Gather TX Avalon-ST Src DMA S CSR

Snk

Cn

Ethernet

Triple Speed Ethernet

M M M

Scatter Gather DMA Snk CSR S

RX Avalon-ST

Src

CSR
S

Cn

Calibration

Avalon-MM Pipeline Bridge (Qsys)

S

CSR

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Figure 714 shows the Qsys representation of the Ethernet subsystem.

Figure 714. Qsys Representation of the Ethernet Subsystem

PCI Express to Ethernet Bridge Example

The PCI Express-to-Ethernet Bridge example in Figure 715 includes two clock domains and an Ethernet subsystem. The PCI Express and Ethernet subsystems run at 125 MHz. The DDR3 SDRAM controller runs at 200 MHz. Qsys automatically inserts clock crossing logic to synchronize the DDR3 SDRAM Controller with the PCI Express and Ethernet subsystems.
Figure 715. PCI Express-to-Ethernet Bridge Example System

Qsys System
Qsys inserts arbitration and Clock crossing logic (125 MHz-200MHz) PCI Express Subsystem 125 MHz
PCIe link Cn

DDR3 SDRAM
400 MHz

DDR3 SDRAM Controller

C M

CSR S

Avalon-MM PIpeline Bridge (Qsys)

M S to CPU

200 MHz

M DDR3

CSR

125 MHz

Calibration Cn

Ethernet Subsystem 125 MHz

Ethernet Cn

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Figure 716 shows the Qsys representation of the PCI Express-to-Ethernet Bridge example.
Figure 716. Qsys Representation of the Complete PCI Express to Ethernet Bridge

Pipeline Bridges
The PCI Express to Ethernet bridge example system uses several pipeline bridges. These bridges must be configured to accommodate the address range of all of connected components, including the components in the originating subsystem and the components in the next higher level of the system hierarchy. As the name suggests, the pipeline bridge inserts a pipeline stage between the connected components. Altera recommends registering signals at the subsystem interface level for the following reasons:

Registering interface signals decreases the amount of combinational logic that must be completed in one cycle, making it easier to meet timing constraints. Registering interface signals raises the potential frequency, or fMAX, of your design at the expense of an additional cycle of latency, which might adversely affect system throughput. The Quartus II incremental compilation feature can achieve better fMAX results if the subsystem boundary is registered.

f For more information about optimizing a Qsys design for performance using bridges and other techniques, refer to Optimizing System Performance for Qsys in volume 1 of the Quartus II Handbook. 1 AXI bridge components are not available in the Quartus II software, but you can connect AXI interfaces with other bridge types. Connections between AXI and Avalon interfaces are made without requiring the use of explicitly instantiated bridges; the interconnect provides all necessary bridging logic.For more information about AXI support, refer to the Qsys System Design Components chapter in volume 1 of the Quartus II Handbook.

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Hierarchical System Using Instance Parameters Example

You can use an instance parameter to control the implementation of system components from a higher-level Qsys system. You define instance parameters on the Instance Parameters tab in Qsys. In this example, a Qsys design called my_system.qsys has two instances of the same IP component, My_IP. My_IP is a Qsys component with a system identification parameter called MY_SYSTEM_ID. When my_system.qsys is instantiated within another higher-level Qsys system, the two My_IP subcomponents require different values for their MY_SYSTEM_ID parameters based on a value determined by the higher-level system. In this example, the value specified by the top-level system is designated top_id and in my_system.qsys, the component instance comp0 requires MY_SYSTEM_ID set to top_id + 1, and instance comp1 requires MY_SYSTEM_ID set to top_id + 2. The following _hw.tcl code defines the MY_SYSTEM_ID system ID parameter in the IP component My_IP:
add_parameter MY_SYSTEM_ID int 8 set_parameter_property MY_SYSTEM_ID DISPLAY_NAME \ MY_SYSTEM_ID_PARAM set_parameter_property MY_SYSTEM_ID UNITS None

To satisfy the design requirements for this example, you define an instance parameter in my_system.qsys that is set by the higher-level system, and then define an instance script to specify how the values of the parameters of the My_IP components instantiated in my_system.qsys are affected by the value set on the instance parameter. To do this, in Qsys, open the my_system.qsys Qsys system that instantiates the two instances of the My_IP components. On the Instance Parameters tab, create a parameter called system_id. For this example, you can set this parameter to be of type Integer and choose 0 as the default value. Next, you provide a Tcl Instance Script that defines how the value of the system_id parameter should affect the parameters of comp0 and comp1 subcomponents in my_system.qsys. The example script in Example 76gets the value of the parameter system_id from the top-level system and saves it as top_id, and then increments the value by 1 and 2. The script then uses the new calculated values to set the MY_SYSTEM_ID parameter in the My_IP component for the instances comp0 and comp1. The script uses informational messages to print the status of the parameter settings when the my_system.qsys system is added to the higher-level system.

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Example 76. Using an Instance Script To Set Parameters On Subcomponents

package require qsys 13.0 Set_module_property Composition_callback My_callback proc My_callback { } { # Get The Value Of System_id Parameter From The Higher-level System Set Top_id [Get_parameter_value System_id] # Print Info Message Send_message Info "System_id Value Specified: $top_id" # Use Above Value To Set Parameter Values For The Subcomponents Set Child_id_0 [Expr {$top_id + 1} ] Set Child_id_1 [Expr {$top_id + 2} ] # Set The Parameter Values On The Subcomponent Instances Set_instance_parameter_value Comp0 My_system_id $child_id_0 Set_instance_parameter_value Comp1 My_system_id $child_id_1 # Print Info Messages Send_message Info "System_id Value Used In Comp0: $child_id_0" Send_message Info "System_id Value Used In Comp1: $child_id_1" }

You can click Preview Instance to see a parameters panel that allows you to modify the parameter value interactively and see the effect of the scripts in the message panel which can be useful for debugging the script. In this example, if you change the parameter value in the Preview screen, the component generates messages to report the top-level ID parameter value and the parameter values used for the two instances of the component. h For more information on creating a parameter on the Instance Parameters tab, refer to Working with Instance Parameters in Qsys in Quartus II Help.

Using Qsys Command-Line with Utilities and Scripts

You can perform many of the functions available in the Qsys GUI from the commandline with the qsys-generate, qsys-script, ip-generate, and ip-make-simscript utilities. You run these command-line executables from the Quartus II installation directory, as follows: <Quartus II installation directory>\quartus\sopc_builder\bin You can use qsys-generate, ip-generate, and ip-make-simscript to generate Qsys output files outside of the Qsys GUI. You can use qsys-script to create and manipulate or manage a Qsys system with command-line scripting. The following subsections provide information about using Qsys from the command-line and with scripts. For command-line help listing options for these executables, type the following command: <Quartus II installation directory>\quartus\sopc_builder\bin\ <executable name> --help Example 77 below shows an example using Qsys command-line scripting.

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Example 77. Using an Instance Script To Display Component Names

qsys-script --script=my_script.tcl --system-file=fancy.qsys my_script.tcl contains: package require -exact qsys 13.0 # get all the instance names in the system and print them one by one set instances [ get_instances ] foreach instance $instances { send_message Info "$instance" }

For more information about Qsys utilities and scripting, including examples, refer to the Altera Wiki Qsys Scripts page.

Generating Qsys Systems with the qsys-generate Utility

You can use the qsys-generate utility to generate RTL for your Qsys system, to compile in Quartus II, simulation models and scripts, and to create testbench systems for testing your Qsys system in a simulator using BFMs. Output from the qsysgenerate command is the same as when generating using the Qsys GUI. When possible, you should use qsys-generate instead of ip-generate and ip-makesimscript. The command-line options for qsys-generate are simpler, and the generation options and output directory structure always match those from the Qsys GUI generation. The following is a list of options that you can use with the qsys-generate utility:

<1st arg file>Required. The name of the .qsys system file to generate. --synthesis=<VERILOG|VHDL>Optional. Creates synthesis HDL files that Qsys uses to compile the system in a Quartus II project. You must specify the preferred generation language for the top-level RTL file for the generated Qsys system. --block-symbol-fileOptional. Creates a block symbol file (.bsf) for the system. --simulation=<VERILOG|VHDL>Optional. Creates a simulation model for the system. The simulation model contains generated HDL files for the simulator, and may include simulation-only features. You must specify the preferred simulation language. --testbench=<SIMPLE|STANDARD>Optional. Creates a testbench system. The testbench system instantiates the original system, adding bus functional models to drive the top-level interfaces. Once generated, the bus functional models interact with the system in the simulator. --testbench-simulation=<VERILOG|VHDL>Optional. After creating the testbench system, also create a simulation model for the testbench system. --output-directory=<value>Optional. Sets the output directory. Each generation target is created in a subdirectory of the output directory. If you do not specify the output directory, a subdirectory of the current working directory matching the name of the system is used.

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--search-path=<value>Optional. If omitted, a standard default path is used. If provided, a comma-separated list of paths is searched. To include the standard path in your replacement, use "$", for example, "/extra/dir,$". --jvm-max-heap-size=<value>Optional. The maximum memory size that Qsys uses for allocations when running this tool. The value is specified as <size><unit> where unit can be m (or M) for multiples of megabytes or g (or G) for multiples of gigabytes. The default value is 512m.

Generating Qsys Systems with the ip-generate Utility

You use ip-generate to configure parameters and generate HDL and other output files for Qsys systems and IP cores. When you generate a system in the Qsys GUI, the generation output messages include the command-lines that you can use to run generation with the same settings using the ip-generate utility. For example, when you generate synthesis files for a system called test.qsys in c:/my_dir, Qsys outputs a message such as the following specifying the command-lines for the ip-generate utility: Info: ip-generate --project-directory=C:/my_dir / --outputdirectory=C:/my_dir/test/synthesis/ --file-set=QUARTUS_SYNTH --reportfile=sopcinfo:C:/my_dir/test.sopcinfo --reportfile=html:C:/my_dir/test.html --reportfile=qip:C:/my_dir/test/synthesis/test.qip --systeminfo=DEVICE_FAMILY="Stratix IV" --system-info=DEVICE=EP4S40G2F40I1 -system-info=DEVICE_SPEEDGRADE=1 --component-file=C:/my_dir/test.qsys The following is a list of options that you can use with the ip-generate utility:

--project-directory=<directory>Optional. Components are found in the locations relative to the project, if any. By default, the current directory '.' is used. To exclude any project directory, use ''. --output-directory=<directory>Optional. This directory will contain the output file set(s). The directory is created if required. If omitted, the current directory is used. --file-set=<QUARTUS_SYNTH | SIM_VERILOG | SIM_VHDL>Optional. Type of output to generate. QUARTUS_SYNTH produces HDL that is compiled by the Quartus II software integrated synthesis. SIM_VERILOG and SIM_VHDL produce simulation models in the respective languages. --report-file=<type><filename>Optional. Partial or complete path for the generated report file, for example, html:report.html. A partial path is relative to the current directory. To assign multiple files, use this option multiple times. The following are common report types.

Block Symbol File (.bsf) Hypertext Markup Language File (.html) Quartus II IP File (.qip) Quartus II Simulation IP File (.sip) SOPC Information File (.sopcinfo) Simulation Package Descriptor File (.spd)

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--standard-reportsOptional. Produce standard generated report files: .sopcinfo, and .qip files. --search-path=<value>Optional. If omitted, a standard default path is used. If provided, a comma-separated list of paths is searched. To include the standard installation directory path, use $, for example, /<directory path>/dir,$. You can also use any directory path, or a path to an .ipx file. Multiple directory references are separated with a comma. --component-file=<file>Optional. A file from which to extract an IP component or system, for example, "my_system.qsys" or "my_component_hw.tcl". --component-name=<value>Optional. The name of an IP component to instantiate, for example, "altera_avalon_uart". If a component file is specified, the component must be found within that file. --component-parameter=<value>Optional. A single value assignment for a component parameter, for example, "--component-param=WIDTH=11". To assign multiple parameters, use this option multiple times. --system-info=<parameter>=<value>Optional. A single value assignment, for example, "--system-info=DEVICE_FAMILY=Stratix IV". To assign multiple system parameters, use this option multiple times. Common parameters are: DEVICE_FAMILY, DEVICE, and DEVICE_SPEEDGRADE. --language=<value>Optional. Supported values are Verilog and VHDL, with Verilog as the default value. --jvm-max-heap-size=<value>Optional. The maximum memory size that Qsys uses for allocations when running this utility. The value is specified as <size><unit>, where unit can be m (or M) for multiples of megabytes or g (or G) for multiples of gigabytes. The default value is 512m.

Generating Qsys Simulation Scripts with the ip-make-simscript Utility

You can use the ip-make-simscript utility to create simulation scripts, and specify options related to simulation scripts that are not available in the Qsys GUI. qsysgenerate, by default, generates these simulation scripts; this utility is only necessary if you use the ip-generate flow. For example, you can use the --compile-to-work option of the ip-make-simscript command if you want to use a single directory for your simulation files rather than the default compilation structure. To use this utility, you must specify an .spd file that lists the required simulation files. The following is a list of options that you can use for the ip-make-simscript utility:

--spd=<file>Required. The .spd files describe the list of files to be compiled, and the memory models hierarchy. --output-directory=<directory>Optional. Directory path specifying the location of output files. If not specified, defaults to the directory from which the ip-make-simscript is run. --compile-to-workOptionalCompiles all design files to the default library, ../work. --use-relative-pathsOptional. Uses relative paths whenever possible.

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--naivelink-modesOptional. Generates files for Quartus II NativeLink RTL simulation. --jvm-max-heap-size=<value>Optional. The maximum memory size that the qsys-script tool uses. You specify this value as <size><unit> when unit is m or M for multiples of megabytes, or g or G for multiples of gigabytes.

Creating and Managing a System with qsys-script

You can use the qsys-script tool to create and manipulate a Qsys system with Tcl scripting commands. 1 You must provide a package version for the qsys-script. If you do not specify the --package-version=<value> qsys-script command, you must then provide a Tcl script and request the system scripting API directly with the package require -exact qsys <version> command. The following is a list of options that you can use with the qsys-script utility:

--system-file=<file>Optional. Specifies the path to a .qsys system file. This system is loaded before running scripting commands. --script=<file>Optional. A file containing Tcl scripting commands for creating or manipulating Qsys systems. If you specify both --cmd and --script, the --cmd commands are run before the script specified by --script. --cmd=<value>Optional. A string that contains Tcl scripting commands to create or manipulate a Qsys system. If you specify both --cmd and --script, the --cmd commands are run before the script specified by --script. --package-version=<value>Optional. Specifies which system scripting Tcl API version to use and determines the functionality and behavior of the Tcl commands. The Quartus II software supports the Tcl API scripting commands. If you do not specify the version on the command-line, your Tcl script must request the system scripting API directly with the package require -exact qsys <version> command. --helpOptional. Displays help for the qsys-script tool. --search-path=<value>Optional. If omitted, a standard default path is used. If provided, a comma-separated list of paths is searched. To include the standard path in your replacement, use "$", for example, /<directory path>/dir,$. Multiple directory references are separated with a comma. --jvm-max-heap-size=<value>Optional. The maximum memory size that is used by the qsys-script tool. You specify this value as <size><unit> where unit can be m or M for multiples of megabytes or g or G for multiples of gigabytes.

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Qsys Scripting Command Reference

Table 76 summarizes the Qsys scripting commands and provides a reference to the full command description.
Table 76. Qsys System Scripting Command Reference (Part 1 of 2) Command add_connection <start> [<end>] add_instance <name> <type> [<version>] add_interface <name> <type> <direction> auto_assign_base_addresses <instance> auto_assign_irqs <instance> auto_connect <element> create_system [<name>] get_composed_connection_parameter_value <instance> <childConnection> <parameter> get_composed_connection_parameters <instance> <childConnection> get_composed_connections <instance> get_composed_instance_assignment <instance> <childInstance> <key> get_composed_instance_assignments <instance> <childInstance> get_composed_instance_parameter_value <instance> <childInstance> <parameter> get_composed_instance_parameters <instance> <childInstance> get_composed_instances <instance> get_connection_parameter_property <connection> <parameter> <property> get_connection_parameter_value <connection> <parameter> get_connection_parameters <connection> get_connection_properties get_connection_property <connection> <property> get_connections [<element>] get_instance_assignment <instance> <key> get_instance_assignments <instance> get_instance_interface_assignment <instance> <interface> <key> get_instance_interface_assignments <instance> <interface> get_instance_interface_parameter_property <instance> <interface> <parameter> <property> get_instance_interface_parameter_value <instance> <interface> <parameter> get_instance_interface_parameters <instance> <interface> get_instance_interface_port_property <instance> <interface> <port> <property> get_instance_interface_ports <instance> <interface> get_instance_interface_properties get_instance_interface_property <instance> <interface> <property> get_instance_interfaces <instance> get_instance_parameter_property <instance> <parameter> <property> Full Description page 741 page 741 page 741 page 742 page 742 page 742 page 742 page 743 page 743 page 743 page 744 page 744 page 744 page 745 page 745 page 745 page 745 page 746 page 746 page 746 page 746 page 747 page 747 page 747 page 747 page 748 page 750 page 748 page 749 page 749 page 749 page 749 page 750 page 750

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Table 76. Qsys System Scripting Command Reference (Part 2 of 2) Command get_instance_parameter_value <instance> <parameter> get_instance_parameters <instance> get_instance_port_property <instance> <port> <property> get_instance_properties get_instance_property <instance> <property> get_instances get_interface_port_property <interface> <port> <property> get_interface_ports <interface> get_interface_properties get_interface_property <interface> <property> get_interfaces get_module_properties get_module_property <property> get_parameter_properties get_port_properties get_project_properties get_project_property <property> load_system <file> lock_avalon_base_address <instance.interface> preview_insert_avalon_streaming_adapters remove_connection <connection> remove_instance <instance> remove_interface <interface> save_system [<file>] send_message <level> <message> set_connection_parameter_value <connection> <parameter> <value> set_instance_parameter_value <instance> <parameter> <value> set_instance_property <instance> <property> <value> set_interface_property <interface> <property> <value> set_module_property <property> <value> set_project_property <property> <value> set_validation_property <property> <value> unlock_avalon_base_address <instance.interface> upgrade_sopc_system <filename> validate_connection <connection> validate_instance <instance> validate_instance_interface <instance> <interface> validate_system Full Description page 750 page 750 page 751 page 751 page 751 page 751 page 752 page 752 page 752 page 752 page 753 page 753 page 753 page 753 page 754 page 754 page 758 page 754 page 755 page 755 page 755 page 755 page 756 page 756 page 756 page 757 page 757 page 757 page 758 page 753 page 758 page 759 page 759 page 759 page 760 page 760 page 760 page 760

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Interface properties work differently for qsys scripting than with _hw.tcl scripting. In _hw.tcl, interfaces do not distinguish between properties and parameters; in qsys scripting, properties and parameters are unique.

add_connection
This command connects interfaces using an appropriate connection type. Interface names consist of a child instance name, followed by the name of an interface provided by that module, for example, mux0.out is the interface out on the instance named mux0.
add_connection Usage Returns Arguments Example add_connection <start> [<end>] None

start
end (optional)

The start interface to be connected, in <instance_name>.<interface_name> format. The end interface to be connected, <instance_name>.<interface_name>

add_connection dma.read_master sdram.s1

add_instance
This command adds an instance of a component, referred to as a child or child instance, to the system.
add_instance Usage Returns add_instance <name> <type> [<version>] None name Arguments type version (optional) Example Specifies a unique local name that you can use to manipulate the instance. This name is used in the generated HDL to identify the instance. The type refers to a kind of instance available in a library, for example altera_avalon_uart. The required version of the specified instance type. If no version is specified, the latest version is used.

add_instance uart_0 altera_avalon_uart

add_interface
This command adds an interface to your system, which you can use to export an interface from within the system. You specify the exported interface with the command set_interface_property EXPORT_OF <instance.interface>.
add_interface Usage Returns Arguments add_interface <name> <type> <direction> None name type direction Example The name of the interface that will be exported from the system The type of interface The interface direction

add_interface my_export conduit end set_interface_property my_export EXPORT_OF uart_0.external_connection

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auto_assign_base_addresses
This command assigns base addresses to memory-mapped interfaces on an instance in the system. Instance interfaces that are locked with lock_avalon_base_address command keep their addresses during address auto-assignment.
auto_assign_base_addresses Usage Returns Arguments Example auto_assign_base_addresses <instance> None instance The name of the instance with memory mapped interfaces auto_assign_base_addresses sdram

auto_assign_irqs
This command assigns interrupt numbers to all connected interrupt senders on an instance in the system.
auto_assign_irqs Usage Returns Arguments Example auto_assign_irqs <instance> None instance The name of the instance with an interrupt sender auto_assign_irqs sdram

auto_connect
This command creates connections from an instance or instance interface to matching interfaces in other instances in the system. For example, Avalon-MM slaves are connected to Avalon-MM masters.
auto_connect Usage Returns Arguments Example auto_connect <element> None element auto_connect sdram auto_connect uart_0.s1 The name of the instance interface, or the name of an instance

create_system
This command replaces the current system in the system script with a new system with the specified name.
create_system Usage Returns Arguments Example create_system [<name>] None name (optional) The name of the new system create_system my_new_system_name

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get_composed_connection_parameter_value
This command returns the value of a parameter in a connection in the subsystem, for an instance that contains a subsystem.
get_composed_connection_parameter_value Usage Returns Arguments get_composed_connection_parameter_value <instance> <childConnection> <parameter> String instance The parameter value The child instance containing a subsystem The name of the connection in the subsystem The name of the parameter to query on the connection

childConnection
parameter

Example

get_composed_connection_parameter_value subsystem_0 cpu.data_master/memory.s0 baseAddress

get_composed_connection_parameters
This command returns a list of parameters on a connection in the subsystem, for an instance that contains a subsystem.
get_composed_connection_parameters Usage Returns Arguments Example get_composed_connection_parameters <instance> <childConnection> String[] instance childConnection A list of parameter names The child instance containing a subsystem The name of the connection in the subsystem

get_composed_connection_parameters subsystem_0 cpu.data_master/memory.s0

get_composed_connections
This command returns a list of all connections in a subsystem, for an instance that contains a subsystem.
get_composed_connections Usage Returns Arguments Example get_composed_connections <instance> String[] instance A list of connection names in the subsystem. These connection names will not be qualified with the instance name. The child instance containing a subsystem

get_composed_connections subsystem_0

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get_composed_instance_assignment
This command returns the value of an assignment on an instance of a subsystem, for an instance that models a subsystem.
get_composed_instance_assignment Usage Returns Arguments get_composed_instance_assignment <instance> <childInstance> <key> String instance childInstance key Example The value of the assignment The child instance containing a subsystem The name of a child instance found in the subsystem The assignment key

get_composed_instance_assignment subsystem_0 video_0 "embeddedsw.CMacro.colorSpace"

get_composed_instance_assignments
This command returns a list of assignments on an instance of a subsystem, for an instance that contains a subsystem.
get_composed_instance_assignments Usage Returns Arguments Example get_composed_instance_assignments <instance> <childInstance> String[] instance childInstance A list of assignment names The child instance containing a subsystem The name of a child instance found in the subsystem

get_composed_instance_assignments subsystem_0 cpu

get_composed_instance_parameter_value
This command returns the value of a parameters on an instance in a subsystem, for an instance that contains a subsystem.
get_composed_instance_parameter_value Usage Returns Arguments get_composed_instance_parameter_value <instance> <childInstance> <parameter> String instance childInstance parameter Example The value of a parameter on an instance of a subsystem The child instance containing a subsystem The name of a child instance found in the subsystem The name of the parameter to query on an instance of a subsystem

get_composed_instance_parameter_value subsystem_0 cpu DATA_WIDTH

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get_composed_instance_parameters
This command returns a list of parameters on an instance of a subsystem, for an instance that contains a subsystem.
get_composed_instance_parameters Usage Returns Arguments Example get_composed_instance_parameters <instance> <childInstance> String[] instance childInstance A list of parameter names The child instance containing a subsystem The name of a child instance found in the subsystem

get_composed_instance_parameters subsystem_0 cpu

get_composed_instances
This command returns a list of child instances in the subsystem, for an instance that contains a subsystem.
get_composed_instances Usage Returns Arguments Example get_composed_instances <instance> String[] instance A list of instance names found in the subsystem The child instance containing a subsystem

get_composed_instances subsystem_0

get_connection_parameter_property
This command returns the value of a parameter property in a connection.
get_connection_parameter_property Usage Returns Arguments get_connection_parameter_property <connection> <parameter> <property> various connection parameter property Example The value of the parameter property The connection to query The name of the parameter The property of the connection

get_connection_parameter_property cpu.data_master/dma0.csr baseAddress UNITS

get_connection_parameter_value
This command gets the value of a parameter on the connection. Parameters represent aspects of the connection that can be modified once the connection is created, such as the base address for an Avalon-MM connection.
get_connection_parameter_value Usage Returns Arguments Example get_connection_parameter_value <connection> <parameter> various connection parameter The value of the parameter The connection to query The name of the parameter

get_connection_parameter_value cpu.data_master/dma0.csr baseAddress

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get_connection_parameters
This command returns a list of parameters found on a connection. The list of connection parameters is the same for all connections of the same type.
get_connection_parameters Usage Returns Arguments Example get_connection_parameters <connection> String[] connection A list of parameter names The connection to query

get_connection_parameters cpu.data_master/dma0.csr

get_connection_properties
This command returns a list of properties found on a connection. The list of connection properties is the same for all connections, regardless of type.
get_connection_properties Usage Returns Arguments Example get_connection_properties String[] None get_connection_properties A list of connection properties

get_connection_property
This command returns the value of a connection property.
get_connection_property Usage Returns Arguments Example get_connection_property <connection> <property> String connection property The value of a connection property The connection to query The name of the connection property

get_connection_property cpu.data_master/dma0.csr TYPE

get_connections
This command returns a list of connections in the system if no element is specified. If a child instance is specified, for example cpu, all connections to any interface on the instance are returned. If an interface on a child instance is specified, for example cpu.instruction_master, only connections to that interface are returned.
get_connections Usage Returns Arguments get_connections [<element>] String[] element (optional) get_connections Example get_connections cpu get_connections cpu.instruction_master A list of connections The name of a child instance, or the qualified name of an interface on a child instance

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get_instance_assignment
This command returns the value of an assignment on a child instance.
get_instance_assignment Usage Returns Arguments Example get_instance_assignment <instance> <key> String instance key The value of the specified assignment The name of the child instance The assignment key to query

get_instance_assignment video_processor embeddedsw.CMacro.colorSpace

get_instance_assignments
This command returns a list of assignment keys for any assignments defined for the instance.
get_instance_assignments Usage Returns Arguments Example get_instance_assignments <instance> String[] instance A list of assignment keys The name of the child instance

get_instance_assignments sdram

get_instance_interface_assignment
This command returns the value of an assignment on an interface of a child instance.
get_instance_interface_assignment Usage Returns Arguments get_instance_interface_assignment <instance> <interface> <key> String instance interface key Example The value of the specified assignment The name of the child instance The name of an interface on the child instance The assignment key to query

get_instance_interface_assignment sdram s1 embeddedsw.configuration.isFlash

get_instance_interface_assignments
This command returns the value of an assignment on an interface of a child instance.
get_instance_interface_assignments Usage Returns Arguments Example get_instance_interface_assignments <instance> <interface> String[] instance interface A list of assignment keys The name of the child instance The name of an interface on the child instance

get_instance_interface_assignments sdram s1

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get_instance_interface_parameter_property
This command returns the property value on a parameter in an interface of a child instance.
get_instance_interface_parameter_property Usage Returns Arguments get_instance_interface_parameter_property <instance> <interface> <parameter> <property> various instance interface parameter property Example The value of the parameter property The name of the child instance The name of an interface on the child instance The name of the parameter on the interface The name of the property on the parameter

get_instance_interface_parameter_property uart_0 s0 setupTime ENABLED

get_instance_interface_parameter_value
This command returns the value of a parameter of an interface in a child instance.
get_instance_interface_parameter_value Usage Returns Arguments get_instance_interface_parameter_value <instance> <interface> <parameter> various instance interface parameter Example The value of the parameter The name of the child instance The name of an interface on the child instance The name of the parameter on the interface

get_instance_interface_parameter_value uart_0 s0 setupTime

get_instance_interface_parameters
This command returns a list of parameters for an interface in a child instance.
get_instance_interface_parameters Usage Returns Arguments Example get_instance_interface_parameters <instance> <interface> String[] instance interface A list of parameter names for parameters in the interface The name of the child instance The name of an interface on the child instance

get_instance_interface_parameters uart_0 s0

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get_instance_interface_port_property
This command returns the property value of a port in the interface of a child instance.
get_instance_interface_port_property Usage Returns Arguments get_instance_interface_port_property <instance> <interface> <port> <property> various instance interface port property Example The value of the port property The name of the child instance The name of an interface on the child instance The name of the port in the interface The name of the property of the port

get_instance_interface_port_property uart_0 exports tx WIDTH

get_instance_interface_ports
This command returns a list of ports in an interface of a child instance.
get_instance_interface_ports Usage Returns Arguments Example get_instance_interface_ports <instance> <interface> String[] instance interface A list of port names found in the interface The name of the child instance The name of an interface on the child instance

get_instance_interface_ports uart_0 s0

get_instance_interface_properties
This command returns a list of properties that you can be query for an interface in a child instance.
get_instance_interface_properties Usage Returns Arguments Example get_instance_interface_properties String[] None get_instance_interface_properties A list of property names

get_instance_interface_property
This command returns the property value for an interface in a child instance.
get_instance_interface_property Usage Returns Arguments get_instance_interface_property <instance> <interface> <property> String instance interface property Example The value of the property The name of the child instance The name of an interface on the child instance The name of the property of the interface

get_instance_interface_property uart_0 s0 DESCRIPTION

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get_instance_interfaces
This command returns a list of interfaces in a child instance.
get_instance_interfaces Usage Returns Arguments Example get_instance_interfaces <instance> String[] instance A list of interface names The name of the child instance

get_instance_interfaces uart_0

get_instance_parameter_property
This command returns the value of a property on a parameter in a child instance.
get_instance_parameter_property Usage Returns Arguments get_instance_parameter_property <instance> <parameter> <property> various instance parameter property Example The value of the parameter property The name of the child instance The name of the parameter in the instance The name of the property of the parameter

get_instance_parameter_property uart_0 baudRate ENABLED

get_instance_parameter_value
This command returns the value of a property in a child instance.
get_instance_parameter_value Usage Returns Arguments Example get_instance_parameter_value <instance> <parameter> various instance parameter The value of the parameter The name of the child instance The name of the parameter in the instance

get_instance_parameter_value uart_0 baudRate

get_instance_parameters
This command returns a list of parameters in a child instance.
get_instance_parameters Usage Returns Arguments Example get_instance_parameters <instance> String[] instance A list of parameters in the instance The name of the child instance

get_instance_parameters uart_0

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get_instance_port_property
This command returns the value of a property of a port contained by an interface in a child instance.
get_instance_port_property Usage Returns Arguments get_instance_port_property <instance> <port> <property> various instance port property Example The value of the property for the port The name of the child instance The name of a port in one of the interfaces on the child instance The name of a property found on the port; DIRECTION, ROLE, WIDTH

get_instance_port_property uart_0 tx WIDTH

get_instance_properties
This command returns a list of properties for a child instance.
get_instance_properties Usage Returns Arguments Example get_instance_properties String[] None get_instance_properties A list of property names for the child instance

get_instance_property
This command returns the value of a property for a child instance.
get_instance_property Usage Returns Arguments Example get_instance_property <instance> <property> String instance property The value of the property The name of the child instance The name of a property found on the instance

get_instance_property cpu ENABLED

get_instances
This command returns a list of the instance names for all child instances in the system.
get_instances Usage Returns Arguments Example get_instances String[] None get_instances A list of child instance names

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get_interface_port_property
This command returns the value of a property of a port contained by one of the toplevel exported interfaces.
get_interface_port_property Usage Returns Arguments get_interface_port_property <interface> <port> <property> various interface port property Example The value of the property The name of a top-level interface on the system The name of a port found in the interface The name of a property found on the port

get_interface_port_property uart_exports tx DIRECTION

get_interface_ports
This command returns the names of all of the ports that have been added to an interface.
get_interface_ports Usage Returns Arguments Example get_interface_ports <interface> String[] interface A list of port names The name of a top-level interface on the system

get_interface_ports export_clk_out

get_interface_properties
This command returns the names of all the available interface properties. The list of interface properties is the same for all interface types.
get_interface_properties Usage Returns Arguments Example get_interface_properties String[] None get_interface_properties A list of interface properties

get_interface_property
This command returns the value of a property from the specified interface.
get_interface_property Usage Returns Arguments Example get_interface_property <interface> <property> various interface property The property value The name of a top-level interface on the system The name of the property, EXPORT_OF

get_interface_property export_clk_out EXPORT_OF

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get_interfaces
This command returns a list of top-level interfaces in the system.
get_interfaces Usage Returns Arguments Example get_interfaces String[] None get_interfaces A list of the top-level interfaces exported from the system

get_module_properties
This command returns the properties that you can manage for the top-level module.
get_module_properties Usage Returns Arguments Example get_module_properties String[] None get_module_properties A list of property names

get_module_property
This command returns the value of a top-level system property.
get_module_property Usage Returns Arguments Example get_module_property <property> String property The value of the property The name of the property to query; NAME

get_module_property NAME

get_parameter_properties
This command returns a list of properties that you can query on parameters. These properties can be queried on any parameter, such as parameters on instances, interfaces, instance interfaces, and connections.
get_parameter_properties Usage Returns Arguments Example get_parameter_properties String[] None get_parameter_properties A list of parameter properties

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get_port_properties
This command returns a list of properties that you can query on ports.
get_port_properties Usage Returns Arguments Example get_port_properties String[] None get_port_properties A list of port properties

get_project_properties
This command returns a list of properties that you can query for the Quartus II project.
get_project_properties Usage Returns Arguments Example get_project_properties String[] None get_project_properties A list of project properties

get_project_property
This command returns the value of a Quartus II project property.
get_project_property Usage Returns Arguments Example get_project_property <property> String property The value of the property The name of the project property; DEVICE_FAMILY

get_project_property DEVICE_FAMILY

load_system
This command loads a Qsys system from a file, and uses the system as the current system for scripting commands.
load_system Usage Returns Arguments Example load_system <file> None file The path to a .qsys file load_system example.qsys

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lock_avalon_base_address
This command prevents the memory-mapped base address from being changed for connections to an interface on an instance when the auto_assign_base_addresses or auto_assign_system_base_addresses commands are run.
lock_avalon_base_address Usage Returns Arguments Example lock_avalon_base_address <instance.interface> None instance.interface The qualified name of the interface of an instance, in <instance>.<interface> format

lock_avalon_base_address sdram.s1

preview_insert_avalon_streaming_adapters
This command runs the adapter insertion for Avalon-ST connections, which adapt connections with mismatched configuration, such as mismatched data widths.
preview_insert_avalon_streaming_adapters Usage Returns Arguments Example preview_insert_avalon_streaming_adapters None None preview_insert_avalon_streaming_adapters

remove_connection
This command removes a connection from the system.
remove_connection Usage Returns Arguments Example remove_connection <connection> None connection The name of the connection to remove remove_connection cpu.data_master/sdram.s0

remove_instance
This command removes a child instance from the system.
remove_instance Usage Returns Arguments Example remove_instance <instance> None instance The name of the child instance to remove remove_instance cpu

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remove_interface
This command removes an exported top-level interface from the system.
remove_interface Usage Returns Arguments Example remove_interface <interface> None interface The name of the exported top-level interface remove_interface clk_out

save_system
This command saves the current in-memory system to the named file. If the file is not specified, the system saves to the same file that was opened with the load_system command.
save_system Usage Returns Arguments Example save_system [<file>] None file (optional) save_system save_system example.qsys If present, the path of the .qsys file to save

send_message
This command sends a message to the user of the script. The message text is normally interpreted as HTML. You can use the <b> element to provide emphasis.
send_message Usage Returns send_message <level> <message> None The following message levels are supported:

ERRORProvides an error message. WARNINGProvides a warning message. INFOProvides an informational message. PROGRESSProvides a progress message. DEBUGProvides a debug message when debug mode is enabled.

Arguments

level

message Example

The text of the message.

send_message ERROR "The system is down!"

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set_connection_parameter_value
This command sets the parameter value for a connection.
set_connection_parameter_value Usage Returns Arguments set_connection_parameter_value <connection> <parameter> <value> None connection parameter value Example The connection The name of the parameter The new parameter value

set_connection_parameter_value cpu.data_master/dma0.csr baseAddress "0x000a0000"

set_instance_parameter_value
This command set the parameter value for a child instance. Derived parameters and SYSTEM_INFO parameters for the child instance can not be set with this command.
set_instance_parameter_value Usage Returns Arguments set_instance_parameter_value <instance> <parameter> <value> None instance parameter value Example The name of the child instance The name of the parameter The new parameter value

set_instance_parameter_value uart_0 baudRate 9600

set_instance_property
This command sets the property value of a child instance. Most instance properties are read-only and can only be set by the instance itself. The primary use for this command is to update the ENABLED parameter, which includes or excludes a child instance when generating the system.
set_instance_property Usage Returns Arguments set_instance_property <instance> <property> <value> None instance property value Example The name of the child instance The name of the property The new property value

set_instance_property cpu ENABLED false

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set_interface_property
This command sets the property value on an exported top-level interface. This command is used to set the EXPORT_OF property to specify which interface of a child instance is exported by the top-level interface.
set_interface_property Usage Returns Arguments set_interface_property <interface> <property> <value> None interface property value Example The name of an exported top-level interface The name of the property The new property value

set_interface_property clk_out EXPORT_OF clk.clk_out

set_module_property
This command sets the system property value, such as the name of the system using the NAME property.
set_module_property Usage Returns Arguments Example set_module_property <property> <value> None property value The name of the property The new property value

set_module_property NAME "new_system_name"

set_project_property
This command sets the project property value, such as the device family.
set_project_property Usage Returns Arguments Example set_project_property <property> <value> None property value The name of the property The new property value

set_project_property DEVICE_FAMILY "Cyclone IV GX"

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set_validation_property
This command sets a property that affects how and when validation is run during system scripting. To disable system validation after each scripting command, set AUTOMATIC_VALIDATION to false.
set_validation_property Usage Returns Arguments Example set_validation_property <property> <value> None property value The name of the property The new property value.

set_validation_property AUTOMATIC_VALIDATION false

unlock_avalon_base_address
This command allows the memory-mapped base address to be changed for connections to an interface on an instance when the auto_assign_base_addresses or auto_assign_system_base_addresses commands are run.
unlock_avalon_base_address Usage Returns Arguments Example unlock_avalon_base_address <instance.interface> None instance.interface The qualified name of the interface of an instance, in <instance>.<interface> format

unlock_avalon_base_address sdram.s1

upgrade_sopc_system
This command loads the specified .sopc file, which then upgrades the file as a Qsys-compatible system. Some child instances and interconnect are replaced so that the system functions in Qsys. You must save the new Qsys-compatible system with the save_system command.
upgrade_sopc_system Usage Returns Arguments Example upgrade_sopc_system <filename> None filename The path to the .sopc file being upgraded. The upgrade will move the .sopc file and related generation files to a backup directory.

upgrade_sopc_system old_system.sopc

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validate_connection
This command validates the specified connection, and returns the during validation messages.
validate_connection Usage Returns Arguments Example validate_connection <connection> String[] connection A list of messages produced validation The name of the connection to validate

validate_connection cpu.data_master/sdram.s1

validate_instance
This command validates the specified child instance, and returns the validation messages.
validate_instance Usage Returns Arguments Example validate_instance <instance> String[] instance A list of messages produced validation The name of the child instance to validate

validate_instance cpu

validate_instance_interface
This command validates an interface on a child instance, and returns the validation messages.
validate_instance_interface Usage Returns Arguments Example validate_instance_interface <instance> <interface> String[] instance interface A list of messages produced validation The name of a child instance The name of the instance on the child instance to validate

validate_instance_interface cpu data_master

validate_system
This command validates the system, and returns the validation messages.
validate_system Usage Returns Arguments Example validate_system String[] None validate_system A list of messages produced validation

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Document Revision History

Table 77 shows the revision history for this document.
Table 77. Document Revision History Date Version

Changes Added AMBA APB support. Added qsys-generate utility. Added VHDL BFM ID support. Added Creating Secure Systems (TrustZones). Added CMSIS Support for Qsys Systems With An HPS Component. Added VHDL language support options. Added AMBA AXI4 support. Added AMBA AX3I support. Added Preset Editor updates.

May 2013

13.0.0

November 2012 June 2012

12.1.0 12.0.0

Added command-line utilities, and scripts.

Added Synopsys VCS and VCS MX Simulation Shell Script. Added Cadence Incisive Enterprise (NCSIM) Simulation Shell Script. Added Using Instance Parameters and Example Hierarchical System Using Parameters. Added simulation support in Verilog HDL and VHDL. Added testbench generation support. Updated simulation and file generation sections.

November 2011

11.1.0

May 2011 December 2010

11.0.0 10.1.0

Initial release.

f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook Archive. m For more information about the benefits of using Qsys, refer to Five Reasons to Switch from SOPC Builder to Qsys on the Webcasts and Videos page of the Altera website.

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