LTC1661 Micropower Dual 10-Bit DAC in MSOP FEATURES
Tiny: Two 10-Bit DACs in an 8-Lead MSOP Half the Board Space of an SO-8 n Micropower: 60A per DAC Sleep Mode: 1A for Extended Battery Life n Rail-to-Rail Voltage Outputs Drive 1000pF n Wide 2.7V to 5.5V Supply Range n Double Buffered for Independent or Simultaneous DAC Updates n Reference Range Includes Supply for Ratiometric 0V-to-VCC Output n Reference Input Has Constant Impedance over All Codes (260k Typ)Eliminates External Buffers n 3-Wire Serial Interface with Schmitt Trigger Inputs n Differential Nonlinearity: 0.75LSB Max
n
DESCRIPTION
The LTC1661 integrates two accurate, serially addressable, 10-bit digital-to-analog converters (DACs) in a single tiny MS8 package. Each buffered DAC draws just 60A total supply current, yet is capable of supplying DC output currents in excess of 5mA and reliably driving capacitive loads up to 1000pF . Sleep mode further reduces total supply current to a negligible 1A. Linear Technologys proprietary, inherently monotonic voltage interpolation architecture provides excellent linearity while allowing for an exceptionally small external form factor. The double-buffered input logic provides simultaneous update capability and can be used to write to either DAC without interrupting sleep mode. Ultralow supply current, power-saving sleep mode and extremely compact size make the LTC1661 ideal for battery-powered applications, while its straightforward usability, high performance and wide supply range make it an excellent choice as a general purpose converter. For additional outputs and even greater board density, please refer to the LTC1660 micropower octal DAC for 10bit applications. For 8-bit applications, please consult the LTC1665 micropower octal DAC.
APPLICATIONS
n n n
n n
Mobile Communications Digitally Controlled Amplifiers and Attenuators Portable Battery-Powered Instruments Automatic Calibration for Manufacturing Remote Industrial Devices
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
BLOCK DIAGRAM
VOUT A 8 GND 7 VCC 6 VOUT B 5
Differential Nonlinearity (DNL)
0.75 LATCH LATCH LATCH 10-BIT DAC A LATCH 10-BIT DAC B 0.60 0.40 0.20 LSB CONTROL LOGIC ADDRESS DECODER SHIFT REGISTER 0 0.20 0.40 0.60 0.75 0 256 512 CODE 768 1023
1661 G02 1661 BD
1 CS/LD
2 SCK
3 DIN
4 REF
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LTC1661 ABSOLUTE MAXIMUM RATINGS
(Note 1)
VCC to GND............................................... 0.3V to 7.5V Logic Inputs to GND ................................ 0.3V to 7.5V VOUT A, VOUT B, REF to GND ............0.3V to VCC + 0.3V Maximum Junction Temperature...........................125C Storage Temperature Range................... 65C to 150C
Operating Temperature Range LTC1661C................................................ 0C to 70C LTC1661I............................................. 40C to 85C Lead Temperature (Soldering, 10 sec).................. 300C
PIN CONFIGURATION
TOP VIEW TOP VIEW CS/LD SCK DIN REF 1 2 3 4 8 7 6 5 VOUT A GND VCC VOUT B CS/LD 1 SCK 2 DIN 3 REF 4 8 7 6 5 VOUT A GND VCC VOUT B
MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125C, JA = 150C/W
N8 PACKAGE 8-LEAD PLASTIC DIP TJMAX = 150C, JA = 100C/W
ORDER INFORMATION
LEAD FREE FINISH LTC1661CMS8#PBF LTC1661IMS8#PBF LTC1661CN8#PBF LTC1661IN8#PBF TAPE AND REEL LTC1661CMS8#TRPBF LTC1661IMS8#TRPBF LTC1661CN8#TRPBF LTC1661IN8#TRPBF PART MARKING LTDV LTDW LTC1661CN8 LTC1661IN8 PACKAGE DESCRIPTION 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic DIP 8-Lead Plastic DIP TEMPERATURE RANGE 0C to 70C 40C to 85C 0C to 70C 40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
SYMBOL Accuracy Resolution Monotonicity DNL INL VOS FSE PSR Differential Nonlinearity Integral Nonlinearity Offset Error VOS Temperature Coefficient Full-Scale Error Full-Scale Error Temperature Coefficient Power Supply Rejection VREF = 2.5V VCC = 5V, VREF = 4.096V
l l
temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V, VREF VCC, VOUT unloaded unless otherwise noted.
PARAMETER CONDITIONS MIN 10 10 0.1 0.4 5 15 1 30 0.18 12 0.75 2 30 TYP MAX UNITS Bits Bits LSB LSB mV V/C LSB V/C LSB/V
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1V VREF VCC 0.1V (Note 2) 1V VREF VCC 0.1V (Note 2) 1V VREF VCC 0.1V (Note 2) Measured at Code 20
l l l l
LTC1661 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
SYMBOL PARAMETER Input Voltage Range Resistance Capacitance IREF VCC ICC Reference Current Positive Supply Voltage Supply Current Sleep Mode For Specified Performance VCC = 5V (Note 3) VCC = 5V (Note 3) Sleep Mode (Note 3) VOUT = 0V, VCC = VREF = 5V, Code = 1023 VOUT = VCC = VREF = 5V, Code = 0 Rising (Notes 4, 5) Falling (Notes 4, 5) To 0.5LSB (Notes 4, 5) Power Supply
l l l l
temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V, VREF VCC, VOUT unloaded unless otherwise noted.
CONDITIONS
l
MIN 0 140
TYP
MAX VCC
UNITS V k pF
Reference Input Active Mode
l l l
260 15 0.001 1 5.5 120 95 1 195 154 3 100 120
A V A A A mA mA V/s V/s s pF V V
2.7
DC Performance Short-Circuit Current Low Short-Circuit Current High AC Performance Voltage Output Slew Rate Voltage Output Settling Time Capacitive Load Driving Digital I/O VIH VIL ILK CIN Digital Input High Voltage Digital Input Low Voltage Digital Input Leakage Digital Input Capacitance VCC = 2.7V to 5.5V VCC = 2.7V to 3.6V VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V VIN = GND to VCC (Note 6)
l l l l l l l l
10 7
25 19 0.60 0.25 30 1000
2.4 2.0 0.8 0.6 10 10
V V A pF
TIMING CHARACTERISTICS l denotes the specifications which apply over the full operating temperature The
range, otherwise specifications are at TA = 25C.
SYMBOL t1 t2 t3 t4 t5 t6 t7 t9 t11 PARAMETER DIN Valid to SCK Setup DIN Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High SCK Low to CS/LD Low CS/LD High to SCK Positive Edge SCK Frequency (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) Square Wave (Note 6) VCC = 4.5V to 5.5V
l l l l l l l l l l
CONDITIONS
MIN 40 0 30 30 80 30 20 0 20
TYP
MAX
UNITS ns ns ns ns ns ns ns ns ns
16.7
MHz
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LTC1661 TIMING CHARACTERISTICS l denotes the specifications which apply over the full operating temperature The
range, otherwise specifications are at TA = 25C.
PARAMETER DIN Valid to SCK Setup DIN Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High SCK Low to CS/LD Low CS/LD High to SCK Positive Edge SCK Frequency SYMBOL t1 t2 t3 t4 t5 t6 t7 t9 t11 CONDITIONS (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) Square Wave (Note 6)
l l l l l l l l l l
MIN 60 0 50 50 100 50 30 0 30
TYP
MAX
UNITS ns ns ns ns ns ns ns ns ns
VCC = 2.7V to 5.5V
10
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Nonlinearity and monotonicity are dened from code 20 to code 1023 (full scale). See Applications Information.
Note 3: Digital inputs at 0V or VCC. Note 4: Load is 10k in parallel with 100pF. Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS, i.e., codes k = 102 and k = 922. Note 6: Guaranteed by design and not subject to test.
TIMING DIAGRAM
t1 t2 SCK t9 DIN t5 CS/LD
1661 TD
t3
t4
t6
t11 A3 t7 A2 A1 X1 X0
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LTC1661 TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL)
2.0 1.5 1.0 0.5 LSB LSB 0 0.5 1.0 1.5 2.0 0 256 512 CODE 768 1023
1661 G01
Differential Nonlinearity (DNL)
0.75 0.60 0.40 0.20 0 0.20 0.40 0.60 0.75 0 256 512 CODE 768 1023
1661 G02
Minimum Supply Headroom vs Load Current (Output Sourcing)
1400 1200 1000 VCC VOUT (mV) 800 600 55C 400 200 0 VREF = 4.096V VOUT < 1LSB CODE = 1023 125C 25C
|IOUT| (mA) (Sourcing)
10
1661 G03
Minimum VOUT vs Load Current (Output Sinking)
1400 1200 1000 VOUT (mV) VOUT (V) 800 600 400 200 0 25C 55C VCC = 5V CODE = 0 125C 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 0 2 4 6 8 10
1661 G04
Mid-Scale Output Voltage vs Load Current
VREF = VCC CODE = 512 VCC = 5.5V VOUT (V) 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 SOURCE 20 10 SINK 20 30
1661 G05
Mid-Scale Output Voltage vs Load Current
VREF = VCC CODE = 512 VCC = 3.6V VCC = 3V
VCC = 5V
VCC = 4.5V
VCC = 2.7V
1.0 15 12 8
SOURCE
SINK 8 12 15
1661 G06
|IOUT| (mA) (SINKING)
30
0 10 IOUT (mA)
4 0 4 IOUT (mA)
Load Regulation vs Output Current
2.0 1.5 1.0 VOUT (LSB) VOUT (LSB) 0.5 0 0.5 1.0 1.5 2.0 2 SOURCE 1 0 IOUT (mA) SINK 1 2
1661 G07
Load Regulation vs Output Current
2.0 1.5 1.0 VOUT (V) 0.5 0 0.5 1.0 1.5 2.0 500 SOURCE 0 IOUT (A) SINK 500
1661 G08
Large-Signal Step Response
5 VCC = VREF = 5V 10% TO CODE = 922 90% STEP
VCC = VREF = 5V CODE = 512
VCC = VREF = 3V CODE = 512
4 3 2 1 0 CODE = 102 0 20
40 60 TIME (s)
80
100
1661 G09
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LTC1661 TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Logic Input Voltage
1.0 0.8 SUPPLY CURRENT (mA) 0.6 0.4 0.2 0 ALL DIGITAL INPUTS SHORTED TOGETHER SUPPLY CURRENT (A) 150 140 130 120 110 100 90 80 70 60 0 1 2 3 4 LOGIC INPUT VOLTAGE (V) 5
1661 G10
Supply Current vs Temperature
VREF = VCC CODE = 1023
VCC = 5.5V VCC = 4.5V VCC = 3.6V VCC = 2.7V
50 55 35 15
5 25 45 65 85 105 125 TEMPERATURE (C)
1661 G11
PIN FUNCTIONS
CS/LD (Pin 1): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on DIN into the register. When CS/LD is pulled high, SCK is disabled and the operation(s) specified in the control code, A3-A0, is (are) performed. CMOS and TTL compatible. SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL compatible. DIN (Pin 3): Serial Interface Data Input. Input word data on the DIN pin is shifted into the 16-bit register on the rising edge of SCK. CMOS and TTL compatible. REF (Pin 4): Reference Voltage Input. 0V VREF VCC. VOUT A, VOUT B (Pin 8, Pin 5): DAC Analog Voltage Outputs. The output range is 1023 0 VOUTA,VOUTB VREF 1024 VCC (Pin 6): Supply Voltage Input. 2.7V VCC 5.5V. GND (Pin 7): System Ground.
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LTC1661 DEFINITIONS
Differential Nonlinearity (DNL): The difference between the measured change and the ideal 1LSB change for any two adjacent codes. The DNL error between any two codes is calculated as follows: V LSB DNL = OUT LSB where VOUT is the measured voltage difference between two adjacent codes. Full-Scale Error (FSE): The deviation of the actual full-scale voltage from ideal. FSE includes the effects of offset and gain errors (see Applications Information). Integral Nonlinearity (INL): The deviation from a straight line passing through the endpoints of the DAC transfer curve (endpoint INL). Because the output cannot go below zero, the linearity is measured between full scale and the lowest code which guarantees the output will be greater than zero. The INL error at a given input code is calculated as follows: Code VOUT VOS ( VFS VOS ) 1023 INL = LSB where VOUT is the output voltage of the DAC measured at the given input code. Least Significant Bit (LSB): The ideal voltage difference between two successive codes. LSB = VREF 1024
Resolution (n): Defines the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity. Voltage Offset Error (VOS): Nominally, the voltage at the output when the DAC is loaded with all zeros. A single supply DAC can have a true negative offset, but the output cannot go below zero (see Applications Information). For this reason, single supply DAC offset is measured at the lowest code that guarantees the output will be greater than zero.
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LTC1661 OPERATION
Transfer Function The transfer function for the LTC1661 is: k VOUT(DEAL) = VREF 1024 where k is the decimal equivalent of the binary DAC input code D9-D0 and VREF is the voltage at REF (Pin 6). Power-On Reset The LTC1661 positively clears the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. Power Supply Sequencing The voltage at REF (Pin 4) must not ever exceed the voltage at VCC (Pin 6) by more than 0.3V. Particular care should be taken in the power supply turn-on and turnoff sequences to assure that this limit is observed. See Absolute Maximum Ratings. Serial Interface See Table 1. The 16-bit Input word consists of the 4-bit Control code, the 10-bit Input code and two dont-care bits.
Table 1. LTC1661 Input Word
INPUT WORD A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 CONTROL CODE INPUT CODE DONT CARE
By selecting the appropriate 4-bit control code (see Table2) it is possible to perform single operations, such as loading one DAC or changing power-down status (sleep/wake). In addition, some Control codes perform two or more operations at the same time. For example, one such code loads DAC A, updates both outputs and wakes the part up. The DACs can be loaded separately or together, but the outputs are always updated together. Register Loading Sequence See Figure 1. With CS/LD held low, data on the DIN input is shifted into the 16-bit shift register on the positive edge of SCK. The 4-bit control code, A3-A0, is loaded first, then the 10-bit Input code, D9-D0, ordered MSB-to-LSB in each case. Two dont-care bits, X1 and X0, are loaded last. When the full 16-bit Input word has been shifted in, CS/LD is pulled high, causing the system to respond according to Table2. The clock is disabled internally when CS/LD is high. Note: SCK must be low when CS/LD is pulled low. Sleep Mode DAC control code 1110b is reserved for the special sleep instruction (see Table 2). In this mode, the digital parts of the circuit stay active while the analog sections are disabled; static power consumption is greatly reduced. The reference input and analog outputs are set in a high impedance state and all DAC settings are retained in memory so that when Sleep mode is exited, the outputs of DACs not updated by the wake command are restored to their last active state. Sleep mode is initiated by performing a load sequence using control code 1110b (the DAC input code D9-D0 is ignored). To save instruction cycles, the DACs may be prepared with new input codes during Sleep (control codes 0001b and 0010b); then, a single command (1000b) can be used both to wake the part and to update the output values.
After the Input word is loaded into the register (see Figure1), it is internally converted from serial to parallel format. The parallel 10-bit-wide input code data path is then buffered by two latch registers. The first of these, the input register, is used for loading new input codes. The second buffer, the DAC register, is used for updating the DAC outputs. Each DAC has its own 10bit input register and 10-bit DAC register.
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LTC1661 OPERATION
Table 2. DAC Control Functions
CONTROL A3 0 0 0 0 0 0 0 0 1 1 A2 0 0 0 0 1 1 1 1 0 0 A1 0 0 1 1 0 0 1 1 0 0 A0 0 1 0 1 0 1 0 1 0 1 No Change Load DAC A INPUT REGISTER STATUS No Change Load DAC A Load DAC B DAC REGISTER STATUS No Update No Update No Update Reserved Reserved Reserved Reserved Reserved Update Outputs Update Outputs Wake Wake Load Both DAC Regs with Existing Contents of Input Regs. Outputs Update. Part Wakes Up Load Input Reg A. Load DAC Regs with New Contents of Input Reg A and Existing Contents of Reg B. Outputs Update. Part Wakes Up Load Input Reg B. Load DAC Regs with Existing Contents of Input Reg A and New Contents of Reg B. Outputs Update. Part Wakes Up POWER-DOWN STATUS (SLEEP/WAKE) COMMENTS No Change No Change No Change No Operation. Power-Down Status Unchanged (Part Stays in Wake or Sleep Mode) Load Input Register A with Data. DAC Outputs Unchanged. Power-Down Status Unchanged Load Input Register B with Data. DAC Outputs Unchanged. Power-Down Status Unchanged
Load DAC B
Update Outputs
Wake
1 1 1 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 0 1 No Change No Change Load DACs A, B with Same 10-Bit Code
Reserved Reserved No Update No Update Update Outputs Wake Sleep Wake Part Wakes Up. Input and DAC Regs Unchanged. DAC Outputs Reflect Existing Contents of DAC Regs Part Goes to Sleep. Input and DAC Regs Unchanged. DAC Outputs Set to High Impedance State Load Both Input Regs. Load Both DAC Regs with New Contents of Input Regs. Outputs Update. Part Wakes Up
SCK
10
11
12
13
14
15
16
DIN
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X1
X0
CONTROL CODE
INPUT CODE INPUT WORD W0
DONT CARE
CS/LD
(SCK ENABLED)
(LTC1661 RESPONDS)
1661 F01
Figure 1. Register Loading Sequence
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LTC1661 OPERATION
Voltage Outputs Each of the rail-to-rail output amplifiers contained in the LTC1661 can typically source or sink up to 5mA (VCC=5V). The outputs swing to within a few millivolts of either supply when unloaded and have an equivalent output resistance of 85 (typical) when driving a load to the rails. The output amplifiers are stable driving capacitive loads up to 1000pF . A small resistor placed in series with the output can be used to achieve stability for any load capacitance. A 1F load can be successfully driven by inserting a 20 resistor in series with the VOUT pin. A 2.2F load needs only a 10 resistor, and a 10F electrolytic capacitor can be used without any resistor (the equivalent series resistance of the capacitor itself provides the required small resistance). In any of these cases, larger values of resistance, capacitance or both may be substituted for the values given. Rail-to-Rail Output Considerations In any rail-to-rail DAC, the output swing is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 2b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 2c. No full-scale limiting can occur if VREF is less than VCC FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.
VREF = VCC
POSITIVE FSE
OUTPUT VOLTAGE
INPUT CODE (2c) VREF = VCC
OUTPUT VOLTAGE
512 INPUT CODE (2a)
1023
OUTPUT VOLTAGE
NEGATIVE OFFSET
0V INPUT CODE (2b)
1661 F02
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (2a) Overall Transfer Function (2b) Effect of Negative Offset for Codes Near Zero Scale (2c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
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10
LTC1661 TYPICAL APPLICATIONS
5V 4 6 0.1F VH = 7.5V (FROM MAIN INPUT DAC) R2 50k R1 5k
DAC A CS/LD DIN SCK 1 3 2 DAC B LTC1661 U1
10V 8
0.1F VH = VH + VH 0.1F
VA1 = 2.5V
FOR EACH U1 AND U2 CODE A CODE B VH, VL 512 1023 250mV 512 512 0 512 0 250mV
1
2 R3 50k
U3A LT1368 4 5V
0.1F
5 VB1
R4 5k VH VL LOGIC DRIVE PIN DRIVER (1 0F N) VOUT
5V 4 6
0.1F
DAC B 1 3 2 DAC A LTC1661 U2
5 VB2
R5 50k 6
R6 5k 2.5V 250mV
7.5V 250mV
5 R7 50k R8 5k
U3B LT1368
VL = VL + VL 0.1F
VA2 = 2.5V
VA1 = VA2 = 2.5V VH = VH + R1 (VA1 VB1) R2 VL = VL + R1 (VA2 VB2) R2 FOR VALUES SHOWN, VH, VL ADJUSTMENT RANGE = 250mV VH, VL STEP SIZE = 500V
1661 F03
VL = 2.5V (FROM MAIN INPUT DAC)
Figure 3. Pin Driver VH and VL Adjustment in ATE Applications
VIN 4.3V 0.1F 0.1F 6 2 LTC1258-4.1 4 1 4.096V 3 2 1 4 REF DIN LTC1661 SCK CS/LD GND 7
1661 F04
VCC VOUTA
0V TO 4.096V (4mV/BIT)
VOUTB
T 0V TO 4.096V (4mV/BIT)
Figure 4. Using the LTC1258 and the LTC1661 In a Single Li-Ion Battery Application
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11
LTC1661 PACKAGE DESCRIPTION
(Reference LTC DWG # 05-08-1660 Rev F)
0.889 0.127 (.035 .005)
MS8 Package 8-Lead Plastic MSOP
5.23 (.206) MIN
3.20 3.45 (.126 .136)
3.00 0.102 (.118 .004) (NOTE 3)
0.42 0.038 (.0165 .0015) TYP
0.65 (.0256) BSC
7 6 5
0.52 (.0205) REF
RECOMMENDED SOLDER PAD LAYOUT
DETAIL A 0 6 TYP
0.254 (.010)
GAUGE PLANE
4.90 0.152 (.193 .006)
3.00 0.102 (.118 .004) (NOTE 4)
0.53 0.152 (.021 .006)
DETAIL A
1 1.10 (.043) MAX
2 3
4 0.86 (.034) REF
0.18 (.007)
SEATING PLANE
0.22 0.38 (.009 .015) TYP
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.65 (.0256) BSC
0.1016 0.0508 (.004 .002)
MSOP (MS8) 0307 REV F
N8 Package 8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.400* (10.160) MAX 8 7 6 5
.300 .325 (7.620 8.255)
.045 .065 (1.143 1.651)
.130 .005 (3.302 0.127)
.008 .015 (0.203 0.381)
.065 (1.651) TYP
.255 .015* (6.477 0.381) .120 (3.048) .020 MIN (0.508) MIN .018 .003 (0.457 0.076)
+.035 .325 .015 +0.889 8.255 0.381
4
N8 1002
.100 (2.54) BSC
INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
NOTE: 1. DIMENSIONS ARE
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12
LTC1661 REVISION HISTORY
REV A DATE 11/10 DESCRIPTION Removed typical values from Timing Characteristics section PAGE NUMBER 3, 4
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
13
LTC1661 TYPICAL APPLICATION
Pin Driver VH and VL Adjustment in ATE Applications
5V 4 6 0.1F VH = 7.5V (FROM MAIN INPUT DAC) R2 50k R1 5k
DAC A CS/LD DIN SCK 1 3 2 DAC B LTC1661 U1
10V 8
0.1F VH = VH + VH 0.1F
VA1 = 2.5V
FOR EACH U1 AND U2 CODE A CODE B VH, VL 512 1023 250mV 512 512 0 512 0 250mV
1
2 R3 50k
U3A LT1368 4 5V
0.1F
5 VB1
R4 5k VH VL LOGIC DRIVE PIN DRIVER (1 0F N) VOUT
5V 4 6
0.1F
DAC B 1 3 2 DAC A LTC1661 U2
5 VB2
R5 50k 6
R6 5k 2.5V 250mV
7.5V 250mV
5 R7 50k R8 5k
U3B LT1368
VL = VL + VL 0.1F
VA1 = VA2 = 2.5V VH = VH + R1 (VA1 VB1) R2 VL = VL + R1 (VA2 VB2) R2 FOR VALUES SHOWN, VH, VL ADJUSTMENT RANGE = 250mV VH, VL STEP SIZE = 500V
1661 F03
VA2 = 2.5V
VL = 2.5V (FROM MAIN INPUT DAC)
RELATED PARTS
PART NUMBER LTC1446/LTC1446L LTC1448 LTC1454/LTC1454L LTC1458/LTC1458L LTC1659 LTC1663 LTC1665/LTC1660 DESCRIPTION Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference Dual 12-Bit VOUT DAC in SO-8 Package Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package VCC: 2.7V to 5.5V Single 10-Bit VOUT DAC in SOT-23 Package Octal 8/10-Bit VOUT DAC in 16-Pin Narrow SSOP COMMENTS LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power Multiplying VOUT DAC. Output Swings from GND to REF . REF Input Can Be Tied to VCC VCC = 2.7V to 5.5V, Internal Reference, 60A VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
1661fa LT 1110 REV A PRINTED IN USA
14 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
www.linear.com
LINEAR TECHNOLOGY CORPORA TION 1999
