EE207: Digital Systems I, Semester I 2003/2004
CHAPTER 3 -iv: Combinational Logic Design (Section 3.8)
Overview
n
Binary Addition
n
Half Adder n Full Adder n Ripple Carry Adder n Carry Lookahead Adder
n
Decimal Addition (Section 3.12)
BCD Adder
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Chapter 3 -iv: Combinational Logic Design (3.8)
1-bit Adder
n n
Performs the addition of two binary bits. Four possible operations:
0+0= 0 0+0=0 n 0+1= 0+1=1 1 n 1+0= 1+0=1 1 n 1+1= 1+1=1 10
n
Circuit implementation requires 2 outputs; one to indicate the sum and another to indicate the carry .
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Half Adder
n n n n
Performs 11 -bit addition. Inputs: A0, B0 Outputs: S0, C1 Index indicates significance, 0 is for LSB and 1 is for the next higher significant bit. Boolean equations:
n n
A0 B0 S0 C1 0 0 1 1 0 1 0 1 0 1 1 1 0 0 0 1
Truth Table
S0 = A0B0+A 0B0 = A0 B0 C1 = A0B0
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Half Adder (cont.)
n n
S0 = A0B0+A0B0 = A0 B0 C1 = A0B0
Block Diagram
A0 C1 B0 A0 B0 S0
Logic Diagram
1 bit half adder S0
C1
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Chapter 3 -iv: Combinational Logic Design (3.8)
n-bit Addition
n
Design an nn-bit binary adder which performs the addition of two nn-bit binary numbers and generates a nn-bit sum and a carry out. out. Example: Let n=4
Cout C3 C2 C1 C0 A3 A2 A1 A0 +B3 B2 B1 B0 -------------S3 S2 S1 S0 1 1 0 1 0 1 1 0 1 +1 1 0 1 ---------1 0 1 0
This requires 33 -bit addition!
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Full Adder
n n
Full adder (for higherhigher-order bit addition) Combinational circuit that performs the additions of 3 bits (two bits and a carrycarryin bit)
Ai Bi Ci+1 1 bit full adder Si
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Ci
Full Adder (cont.)
The K-maps for Ci+1 :
Ai Bi Ci Ai 0 0 0 0 1 1 1 1 Bi 0 0 1 1 0 0 1 1 Ci 0 1 0 1 0 1 0 1 Si 0 1 1 0 1 0 0 1 Ci+1 0 0 0 1 0 1 1 1
0 0 1 0 0 1 1 1
Si:
Ai Bi Ci
0 1 0 1 1 0 1 0
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Chapter 3 -iv: Combinational Logic Design (3.8)
Full Adder (cont.)
nBoolean n
n
equations:
Ci+1 = AiBi + AiCi + BiCi Si = AiBi Ci + AiBiCi + AiBiCi + AiBiCi = Ai Bi Ci
nYou
can design full adder circuit directly from the above equations (requires 3 ANDs and 1 OR for C i+1 and 2 XORs for Si) nCan we do better?
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Full Adder using 2 Half Adders
A full adder can also be realized with two half adders and an OR gate, since Ci+1 can also be expressed as: Ci+1 = AiBi + Ai BiC i + AiBiCi = AiBi + (Ai Bi + AiBi)C i = AiBi + (Ai Bi)C i and Si = Ai Bi Ci
Ai Bi Si
Ci+1 Ci
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n-bit Combinational Adders
n n
Perform parallel multi multi- bit addition Ripple Carry Adder
n
Simple design n Time consuming. Why? (youll see in a bit!) More complex than rippleripple-carry adder n Reduces circuit delay
n
Carry Lookahead Adder
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n-bit Ripple Carry Adder
n
Constructed using n 1- bit full adder blocks in parallel. Cascade the full adders so that the carry out from one becomes the carry in to the next higher bit position.
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Example: 4-bit Ripple Carry Adder
C4 C3 C2 C1 C0 A3 A2 A1 A0 +B3 B2 B1 B0 -------------S3 S2 S1 S0
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Ripple Carry Adder Delay
n
Circuit delay in an nn-bit ripple carry adder is determined by the delay on the carry path from the LSB (C0) to the MSB (C (Cn). Let the delay in a 11-bit FA be ? . Then, the delay of an n-bit ripple carry adder is n? n? .
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Carry Lookahead Adder
n
Alternative design for a combinational n-bit adder. Practical design with reduced delay at the expense of more complex hardware. See Wakerly 5.10.4
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