CS 4200/5200 Computer Architecture I
MIPS Instruction Set Architecture
Dr. Xiaobo Zhou Department of Computer Science
CS420/520 Lec3.1
UC. Colorado Springs
Adapted from UCB97 & UCB03
Review: Organizational Trade-offs
CPU time = Seconds Program = Instructions x Cycles Program Instruction x Seconds Cycle
Application Programming Language Compiler ISA Datapath Control Function Units Transistors Wires Pins Cycle Time Instruction Mix CPI
CS420/520 Lec3.2
UC. Colorado Springs
Adapted from UCB97 & UCB03
Review: Amdahl's Law
ExTime after improvement = ExTime unaffected + Extime affected / amount of improvement Speedup due to enhancement E: ExTime w/o E Speedup(E) = -------------------ExTime w/ E = Performance w/ E --------------------------Performance w/o E
Suppose that enhancement E accelerates a fraction F of the task by a factor S, S and the remainder of the task is unaffected then, then ExTime(with E) = ((1-F) + F/S) X ExTime(without E) Speedup(with E) = ExTime(without E) = 1 ((1-F) + F/S) X ExTime(without E) (1-F) + F/S
1 v
CS420/520 Lec3.3
UC. Colorado Springs
Adapted from UCB97 & UCB03
Instruction Set Design
software
instruction set
hardware
An instruction is a binary code, which specifies a basic operation (e.g. add, subtract, and, or) for the computer Operation Code: defines the operation type Operands: operation source and destination
CS420/520 Lec3.4
UC. Colorado Springs
Adapted from UCB97 & UCB03
Levels of Representation
temp = v[k]; High Level Language Program Compiler Assembly Language Program Assembler Machine Language Program
1000 1000 1010 1010 1100 1111 1110 1100
v[k] = v[k+1]; v[k+1] = temp; lw $15, lw $16, sw $16, sw $15,
0100 0101 1010 0000 1111 1000 1111 1001
0($2) 4($2) 0($2) 4($2)
0000 0000 0101 1100 0000 1001 1000 0110 0000 1100 0000 1010 0000 0110 1001 1111
Machine Interpretation Control Signal Specification
CS420/520 Lec3.5 UC. Colorado Springs Adapted from UCB97 & UCB03
MIPS R2000 / R3000 Registers
MIPS (NEC, SGI, Sony, Nintendo), a typical of instructions after 1980s. 32-bit machine --> Programmable storage 31 x 32-bit GPRs (R0 = 0) 32 x 32-bit FP regs HI, LO, PC Big Endian Addressing modes: register immediate
r0 r1 r31 PC lo hi
2^32 x 4 bytes
0
displacement PC-relative pseudo-direct All instructions are 32-bit wide and must be aligned -- words must start at address that are multiple of 4.
CS420/520 Lec3.6 UC. Colorado Springs Adapted from UCB97 & UCB03
MIPS arithmetic instructions
Instruction add subtract add immediate sub immediate Example add $1,$2,$3 sub $1,$2,$3 addi $1,$2,100 subi $1,$2,100 Meaning $1 = $2 + $3 $1 = $2 $3 $1 = $2 + 100 $1 = $2 - 100 Comments 3 operands 3 operands + constant - constant
CS420/520 Lec3.7
UC. Colorado Springs
Adapted from UCB97 & UCB03
Example
E.g. f= (g+h) - (i+j), assuming f, g, h, i, j be assigned to $1, $2, $3, $4, $5
add $7, $2, $3 add $8, $4, $5 sub $1, $7, $8
// register $7 contains g+h // register $8 contains i+j // register $1 (f) gets the result
CS420/520 Lec3.8
UC. Colorado Springs
Adapted from UCB97 & UCB03
MIPS logic instructions
Instruction and or xor nor and imme. Example and $1,$2,$3 or $1,$2,$3 xor $1,$2,$3 nor $1,$2,$3 Meaning $1 = $2 & $3 $1 = $2 | $3 $1 = $2 $3 $1 = ~($2 |$3) Comment Logical AND Logical OR Logical XOR Logical NOR
andi $1,$2, 100 $1 = $2 & 100 AND constant
x 0 0 1 1
CS420/520 Lec3.9
y 0 1 0 1
x and y 0 0 0 1
x or y 0 1 1 1
x xor y 0 1 1 0
x nor y 1 0 0 0
Adapted from UCB97 & UCB03
UC. Colorado Springs
MIPS data transfer instructions
Instruction
LW $1, 30($2) LH $1, 40($3) LB $1, 40($3) SW $3, 500($4) SH $3, 502($2) SB $2, 41($3)
Comment
Load word Load half a word Load byte Store word Store half Store byte
I MIPS64: In MIPS64 LD (load (l d double d bl word) d) LD $1, 30($2) load a double-word SD $3, 500($4) store a double-word
CS420/520 Lec3.10
UC. Colorado Springs
Adapted from UCB97 & UCB03
Example Assume A is an array of 100 words, and compiler has associated the variables g and h with the register $1 and $2. Assume the base address of the array is in $3. Translate g = h + A[8] lw $4, 8($3); add $1, $2, $4; // $4 <-- A[8]
lw $4 $4, 32($3); add $1, $2, $4 A[12] = h+A[8]
CS420/520 Lec3.11
// $4 <-< A[8]
SW $1, 48($3)
Adapted from UCB97 & UCB03
UC. Colorado Springs
Example Assume A is an array of 100 words, and compiler has associated the variables g, h, and i with the register $1, $2, $5. Assume the base address of the array is in $3. Translate g = h + A[i] add $6, $5, $5; add $6, $6, $6; add $4, $3, $6; // $6 = 2i // $6 = 4i // $4 <---absolute mem. address of // A[i], used as new base // $7 = A[i] // g = h + A[i]
Adapted from UCB97 & UCB03
lw $7, 0 ($4); add $1, $2, $7;
CS420/520 Lec3.12
UC. Colorado Springs
MIPS branch, jump, compare instructions
Instruction branch on equal branch on not eq. Example Meaning beq $1,$2,100 if ($1 == $2) go to PC+4+100 Equal test; PC relative branch bne $1,$2,100 if ($1!= $2) go to PC+4+100 Not equal test; PC relative
branch on eq. to 0 beqz $1,100 if ($1==0) go to PC+4+100 Zero test; PC relative (pseudo-instruction; using $0) beq, bne, blt, blez, bgt, bgez jump jump register jump and link set on less than j 10000 go to 10000 Jump to target address jr $31 go to $31 For switch, procedure return jal 10000 $31 = PC + 4; go to 10000 For procedure call slt $1,$2,$3 if ($2 < $3) $1=1; else $1=0 Compare less than; 2s comp.
set less than imm. slti $1,$2,100 if ($2 < 100) $1=1; else $1=0 Compare < constant; 2s comp.
CS420/520 Lec3.13 UC. Colorado Springs Adapted from UCB97 & UCB03
Example if (i==j) go to L1; f = g+ h; f = f - i;
L1:
Assuming f, g, h, i, j ~ $1, $2, $3, $4, $5
i == j ? yes
L1:
beq $4, $5, L1 add $1, $2, $3 sub $1, $1, $4
no f=g+h
L1: f = f - i
CS420/520 Lec3.14
UC. Colorado Springs
Adapted from UCB97 & UCB03
Example Loop: g = g +A[i]; i = i+ j; if (i != h) go to Loop: Assuming variables g, h, i, j ~ $1, $2, $3, $4 and base address of array is in $5 Loop: add $7, $3, $3 add $7, $7, $7 add $7, $7, $5 lw $6, 0($7) add $1, $1, $6 // g= g+A[i] add $3, $3, $4 bne $3, $2, Loop;
CS420/520 Lec3.15 UC. Colorado Springs
g = g +A[i] i = i +j i != h ? no
Adapted from UCB97 & UCB03
yes
Example while (A[i]==k) i = i+j; Assume i, j, and k ~ $17, $18, $19 and base of A is in $3
A[i] == k ? no
Yes
i=i+j
Exit
CS420/520 Lec3.16
UC. Colorado Springs
Adapted from UCB97 & UCB03
Example while (A[i]==k) i = i+j; Assume i, j, and k ~ $17, $18, $19 and base of A is in $3 Loop: add $20, $17, $17 add $20, $20, $20 add $20, $20, $3 lw $21,0($20) bne $21, $21 $19, $19 Exit add $17, $17, $18 j Loop Exit:
CS420/520 Lec3.17 UC. Colorado Springs Adapted from UCB97 & UCB03
//exit loop if A[I] ! =k
MIPS Fields
R-format: Register (direct)
6
op
5
rs
5
rt
5
rd
5
shamt
6
funct
op: basic operation of the instruction, called opcode rs, the first register source operand rt: the second register source operand rd: the register destination operand shamt: shift amount funct: function, select the variant of the op field.
I-format: I Immediate di t
6
op
5
rs
5
rt
16
immediate
J-format:
jump
6
op
addr.
26
CS420/520 Lec3.18
UC. Colorado Springs
Adapted from UCB97 & UCB03
MIPS Addressing Modes/Instruction Formats
R-format: Register (direct)
6
op
5
rs
5
rt
5
rd
sht fun
I-format: I format: Immediate Base+offset displacement
register op rs rt immed
6
op
5
rs
5
rt
16
immed + immed + Memory y Memory
register PC-relative op rs PC rt
J-format:
pseudodirect
6
op
addr.
26
Memory
CS420/520 Lec3.19
UC. Colorado Springs
Adapted from UCB97 & UCB03
Example while (A[i]==k) i = i+j; Assume i, j, and k ~ $17, $18, $19 and base of A is in $3
Assume the loop is placed starting at loc 8000 Loop: add $20, $17, $17 8000: 0 17 17 20 0 32
add $20, $20, $20 add $20, $20, $3 lw $21,0($20) bne $21, $19, Exit add $17, $17, $18 j Loop Exit:
20
20
20 0
32
0 20 3 20 0 32 35 20 21 0 5 21 19 8 -> 2 0 17 18 17 0 32 2 8000 -> 2000
CS420/520 Lec3.20
UC. Colorado Springs
Adapted from UCB97 & UCB03
MIPS arithmetic & logical instructions
Instruction add subtract add immediate add unsigned subtract unsigned add imm. unsign. and or xor nor and immediate or immediate xor immediate Example add $1,$2,$3 sub $1,$2,$3 addi $1,$2,100 addu $1,$2,$3 subu $1,$2,$3 addiu $1,$2,100 and $1,$2,$3 or $1,$2,$3 xor $1,$2,$3 nor $1,$2,$3 andi $1,$2,10 ori $1,$2,10 xori $1, $2,10 Meaning $1 = $2 + $3 $1 = $2 $3 $1 = $2 + 100 $1 = $2 + $3 $1 = $2 $3 $1 = $2 + 100 $1 = $2 & $3 $1 = $2 | $3 $1 = $2 $3 $1 = ~($2 |$3) $1 = $2 & 10 $1 = $2 | 10 $1 = ~$2 &~10 Comments 3 operands; 3 operands; + constant; 3 operands; 3 operands; + constant; 3 reg. operands; 3 reg. operands; 3 reg. operands; 3 reg. operands; Logical AND reg, constant Logical OR reg, constant Logical XOR reg, constant
CS420/520 Lec3.21
UC. Colorado Springs
Adapted from UCB97 & UCB03
MIPS data transfer instructions
Instruction
LW $1, 30($2) LH $1, 40($3) LB $1, $1 40($3) SW $3, 500($4) SH $3, 502($2) SB $2, 41($3)
Comment
Load word Load half a word Load byte Store word Store half Store byte
In MIPS64: LD (load double word) LD $1, 30($2) load a double-word SD $3, 500($4) store a double-word
CS420/520 Lec3.22
UC. Colorado Springs
Adapted from UCB97 & UCB03
Compare and Branch
Compare and Branch BEQ rs, rt, offset BNE rs, rt, offset
if R[rs] == R[rt] then PC-relative branch <>
Compare to zero and branch BLEZ rs, offset if R[rs] <= 0 then PC-relative branch BGTZ rs, offset > BLT < BGEZ >= BLTZAL rs, offset if R[rs] < 0 then branch and link (into R 31) BGEZAL >=
CS420/520 Lec3.23
UC. Colorado Springs
Adapted from UCB97 & UCB03
Reading and Preview
Reading: CO 4: Chapter 2 (MIPS) CA 5: Appendix A (ISA)
CS420/520 Lec3.24
UC. Colorado Springs
Adapted from UCB97 & UCB03
