Rev.4.

3_00


CMOS SERIAL E
2
PROM
S-93C46B/56B/66B

Seiko Instruments Inc. 1
The S-93C46B/56B/66B is a high speed, low current
consumption, 1/2/4 K-bit serial E
2
PROM with a wide
operating voltage range. It is organized as 64-word

16-
bit, 128-word 16-bit, 256-word 16-bit, respectively.
Each is capable of sequential read, at which time
addresses are automatically incremented in 16-bit
blocks. The instruction code is compatible with the
NM93CS46/56/66.

Features
Low current consumption Standby: 1.5 A Max. (V
CC
= 5.5 V)
Operating: 0.8 mA Max. (V
CC
= 5.5 V)
0.4 mA Max. (V
CC
= 2.5 V)
Wide operating voltage range Read: 1.8 to 5.5 V (at 40 to +85C)
Write: 2.7 to 5.5 V (at 40 to +85C)
Sequential read capable
Write disable function when power supply voltage is low
Function to protect against write due to erroneous instruction recognition
Endurance: 10
7
cycles/word
*1
(at +25C) write capable,
10
6
cycles/word
*1
(at +85C)
3 10
5
cycles/word
*1
(at +105C)
*1. For each address (Word: 16 bits)
Data retention: 10 years (after rewriting 10
6
cycles/word at +85C)
S-93C46B: 1 K-bit NM93CS46 instruction code compatible
S-93C56B: 2 K-bit NM93CS56 instruction code compatible
S-93C66B: 4 K-bit NM93CS66 instruction code compatible
High-temperature operation: +105C Max. supported
(Only S-93Cx6BD0H-J8T2G, S-93Cx6BD0H-T8T2G)
Lead-free products

Packages
Drawing code
Package name
Package Tape Reel Land
8-Pin DIP DP008-F

8-Pin SOP(JEDEC) FJ008-A FJ008-D FJ008-D

8-Pin TSSOP FT008-A FT008-E FT008-E

SNT-8A PH008-A PH008-A PH008-A PH008-A


Caution This product is intended to use in general electronic devices such as consumer electronics,
office equipment, and communications devices. Before using the product in medical
equipment or automobile equipment including car audio, keyless entry and engine control
unit, contact to SII is indispensable.
CMOS SERIAL E
2
PROM
S-93C46B/56B/66B Rev.4.3_00

Seiko Instruments Inc. 2
Pin Configurations

8-Pin DIP
Top view
Table 1
Pin No. Symbol Description
1 CS Chip select input
2 SK Serial clock input
3 DI Serial data input
4 DO Serial data output
5 GND Ground
6 TEST
*1
Test
7 NC No connection
8 VCC Power supply
*1. Connect to GND or V
CC
.
Even if this pin is not connected, performance is not affected
so long as the absolute maximum rating is not exceeded.




1
2
3
4
8
7
6
5
VCC
NC
TEST
GND
CS
SK
DO
DI



Figure 1

S-93C46BD0I-D8S1G
S-93C56BD0I-D8S1G
S-93C66BD0I-D8S1G
Remark See Dimensions for details of the package drawings.






8-Pin SOP(JEDEC)
Top view
Table 2
Pin No. Symbol Description
1 CS Chip select input
2 SK Serial clock input
3 DI Serial data input
4 DO Serial data output
5 GND Ground
6 TEST
*1
Test
7 NC No connection
8 VCC Power supply
*1. Connect to GND or V
CC
.
Even if this pin is not connected, performance is not affected
so long as the absolute maximum rating is not exceeded.




1
2
3
4
8
7
6
5
VCC
NC
TEST
GND
CS
SK
DO
DI



Figure 2

S-93C46BD0I-J8T1G
S-93C46BD0H-J8T2G
S-93C56BD0I-J8T1G
S-93C56BD0H-J8T2G
S-93C66BD0I-J8T1G
S-93C66BD0H-J8T2G
Remark See Dimensions for details of the package drawings.






CMOS SERIAL E
2
PROM
Rev.4.3_00 S-93C46B/56B/66B

Seiko Instruments Inc. 3

8-Pin SOP(JEDEC) (Rotated)
Top view
Table 3
Pin No. Symbol Description
1 NC No connection
2 VCC Power supply
3 CS Chip select input
4 SK Serial clock input
5 DI Serial data input
6 DO Serial data output
7 GND Ground
8 TEST
*1
Test
*1. Connect to GND or V
CC
.
Even if this pin is not connected, performance is not affected
so long as the absolute maximum rating is not exceeded.




1
2
3
4
8
7
6
5
CS
SK
TEST
GND
DO
DI
VCC
NC



Figure 3

S-93C46BR0I-J8T1G
S-93C56BR0I-J8T1G
S-93C66BR0I-J8T1G
Remark See Dimensions for details of the package drawings.






8-Pin TSSOP
Top view
Table 4
Pin No. Symbol Description
1 CS Chip select input
2 SK Serial clock input
3 DI Serial data input
4 DO Serial data output
5 GND Ground
6 TEST
*1
Test
7 NC No connection
8 VCC Power supply
*1. Connect to GND or V
CC
.
Even if this pin is not connected, performance is not affected
so long as the absolute maximum rating is not exceeded.




1
2
3
4
8
7
6
5
VCC
NC
TEST
GND
CS
SK
DO
DI



Figure 4

S-93C46BD0I-T8T1G
S-93C46BD0H-T8T2G
S-93C56BD0I-T8T1G
S-93C56BD0H-T8T2G
S-93C66BD0I-T8T1G
S-93C66BD0H-T8T2G

Remark See Dimensions for details of the package drawings.

CMOS SERIAL E
2
PROM
S-93C46B/56B/66B Rev.4.3_00

Seiko Instruments Inc. 4

SNT-8A
Top view
Table 5
Pin No. Symbol Description
1 CS Chip select input
2 SK Serial clock input
3 DI Serial data input
4 DO Serial data output
5 GND Ground
6 TEST
*1
Test
7 NC No connection
8 VCC Power supply
*1. Connect to GND or V
CC
.
Even if this pin is not connected, performance is not affected so
long as the absolute maximum rating is not exceeded.



1
2
3
4
8
7
6
5
VCC
NC
TEST
GND
CS
SK
DI
DO



Figure 5

S-93C46BD0I-I8T1G
S-93C56BD0I-I8T1G
S-93C66BD0I-I8T1G
Remark See Dimensions for details of the package drawings.





CMOS SERIAL E
2
PROM
Rev.4.3_00 S-93C46B/56B/66B

Seiko Instruments Inc. 5
Block Diagram

Memory array
Data register
Address
decoder
Mode decode logic
Clock pulse
monitoring circuit
Output buffer
VCC

GND
DO
DI
CS
Clock generator
Voltage detector
SK


Figure 6

CMOS SERIAL E
2
PROM
S-93C46B/56B/66B Rev.4.3_00

Seiko Instruments Inc. 6
Instruction Sets
1. S-93C46B
Table 6
Instruction Start Bit
Operation
Code
Address Data
SK input clock 1 2 3 4 5 6 7 8 9 10 to 25
READ (Read data) 1 1 0 A5 A4 A3 A2 A1 A0 D15 to D0

Output
*1

WRITE (Write data) 1 0 1 A5 A4 A3 A2 A1 A0 D15 to D0 Input
ERASE (Erase data) 1 1 1 A5 A4 A3 A2 A1 A0
WRAL (Write all) 1 0 0 0 1 x x x x D15 to D0 Input
ERAL (Erase all) 1 0 0 1 0 x x x x
EWEN (Write enable) 1 0 0 1 1 x x x x
EWDS (Write disable) 1 0 0 0 0 x x x x
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.

Remark x: Dont care


2. S-93C56B

Table 7
Instruction Start Bit
Operation
Code
Address Data
SK input clock
1 2 3 4 5 6 7 8 9 10 11 12 to 27
READ (Read data) 1 1 0
x A6 A5 A4 A3 A2 A1 A0
D15 to D0

Output
*1
WRITE (Write data) 1 0 1
x A6 A5 A4 A3 A2 A1 A0
D15 to D0 Input
ERASE (Erase data) 1 1 1
x A6 A5 A4 A3 A2 A1 A0

WRAL (Write all) 1 0 0 0 1
x x x x x x
D15 to D0 Input
ERAL (Erase all) 1 0 0 1 0
x x x x x x

EWEN (Write enable) 1 0 0 1 1
x x x x x x

EWDS (Write disable) 1 0 0 0 0
x x x x x x

*1. When the 16-bit data in the specified address has been output, the data in the next address is output.

Remark x: Dont care
CMOS SERIAL E
2
PROM
Rev.4.3_00 S-93C46B/56B/66B

Seiko Instruments Inc. 7

3. S-93C66B
Table 8
Instruction Start Bit
Operation
Code
Address Data
SK input clock 1 2 3 4 5 6 7 8 9 10 11 12 to 27
READ (Read data) 1 1 0
A7 A6 A5 A4 A3 A2 A1 A0
D15 to D0

Output
*1
WRITE (Write data) 1 0 1
A7 A6 A5 A4 A3 A2 A1 A0
D15 to D0 Input
ERASE (Erase data) 1 1 1
A7 A6 A5 A4 A3 A2 A1 A0

WRAL (Write all) 1 0 0 0 1
x x x x x x
D15 to D0 Input
ERAL (Erase all) 1 0 0 1 0
x x x x x x

EWEN (Write enable) 1 0 0 1 1
x x x x x x

EWDS (Write disable) 1 0 0 0 0
x x x x x x

*1. When the 16-bit data in the specified address has been output, the data in the next address is output.

Remark x: Dont care

CMOS SERIAL E
2
PROM
S-93C46B/56B/66B Rev.4.3_00

Seiko Instruments Inc. 8
Absolute Maximum Ratings
Table 9
Item Symbol Ratings Unit
Power supply voltage V
CC
0.3 to +7.0 V
Input voltage V
IN
0.3 to V
CC
+0.3 V
Output voltage V
OUT
0.3 to V
CC
V
Operating ambient temperature T
opr
40 to +105 C
Storage temperature T
stg
65 to +150 C
Caution The absolute maximum ratings are rated values exceeding which the product could
suffer physical damage. These values must therefore not be exceeded under any
conditions.



Recommended Operating Conditions
Table 10
40 to +85C +85 to +105C
Item Symbol Conditions
Min. Typ. Max. Min. Typ. Max.
Unit
READ/EWDS 1.8 5.5 4.5 5.5 V
Power supply voltage V
CC WRITE/ERASE/
WRAL/ERAL/EWEN
2.7 5.5 4.5 5.5 V
V
CC
= 4.5 to 5.5 V 2.0 V
CC
2.0 V
CC
V
V
CC
= 2.7 to 4.5 V 0.8 V
CC
V
CC
V High level input voltage V
IH

V
CC
= 1.8 to 2.7 V 0.8 V
CC
V
CC
V
V
CC
= 4.5 to 5.5 V 0.0 0.8 0.0 0.8 V
V
CC
= 2.7 to 4.5 V 0.0 0.2 V
CC
V Low level input voltage V
IL

V
CC
= 1.8 to 2.7 V 0.0 0.15 V
CC
V



Pin Capacitance
Table 11
(Ta = 25C, f = 1.0 MHz, V
CC
= 5.0 V)
Item Symbol Conditions Min. Typ. Max. Unit
Input Capacitance C
IN
V
IN
= 0 V 8 pF
Output Capacitance C
OUT
V
OUT
= 0 V 10 pF



Endurance
Table 12
Item Symbol
Operating
Temperature
Min. Typ. Max. Unit
40 to +85C 10
6

Endurance N
W

+85 to +105C 3 10
5

cycles/word
*1
*1. For each address (Word: 16 bits)
CMOS SERIAL E
2
PROM
Rev.4.3_00 S-93C46B/56B/66B

Seiko Instruments Inc. 9
DC Electrical Characteristics

Table 13
40 to +85C +85 to +105C
V
CC
= 4.5 to 5.5 V V
CC
= 2.5 to 4.5 V V
CC
= 1.8 to 2.5 V V
CC
= 4.5 to 5.5 V
Item Symbol Conditions
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Unit
Current
consumption
(READ)
I
CC1
DO no load 0.8 0.5 0.4 0.8 mA

Table 14
40 to +85C +85 to +105C
V
CC
= 4.5 to 5.5 V V
CC
= 2.7 to 4.5 V V
CC
= 4.5 to 5.5 V
Item Symbol Conditions
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Unit
Current consumption
(WRITE)
I
CC2
DO no load 2.0 1.5 2.0 mA

Table 15
40 to +85C +85 to +105C
V
CC
= 4.5 to 5.5 V V
CC
= 2.5 to 4.5 V V
CC
= 1.8 to 2.5 V V
CC
= 4.5 to 5.5 V Item Symbol Conditions
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Unit
Standby current
consumption
I
SB
CS = GND, DO = Open,
Other inputs to
V
CC
or GND
1.5 1.5 1.5 1.5
A
Input leakage
current
I
LI
V
IN
= GND to V
CC
0.1 1.0 0.1 1.0 0.1 1.0 0.1 1.0
A
Output leakage
current
I
LO

V
OUT
= GND to V
CC
0.1 1.0 0.1 1.0 0.1 1.0 0.1 1.0
A
I
OL
= 2.1 mA 0.4 0.4 V
Low level output
voltage
V
OL

I
OL
= 100 A 0.1 0.1 0.1 0.1 V
I
OH
= 400 A 2.4 2.4 V
I
OH
= 100 A V
CC
0.3 V
CC
0.3 V
CC
0.3 V
High level output
voltage
V
OH

I
OH
= 10 A V
CC
0.2 V
CC
0.2 V
CC
0.2 V
CC
0.2 V
Write enable latch
data hold voltage
V
DH

Only when write
disable mode
1.5 1.5 1.5 1.5
V

CMOS SERIAL E
2
PROM
S-93C46B/56B/66B Rev.4.3_00

Seiko Instruments Inc. 10
AC Electrical Characteristics

Table 16 Measurement Conditions
Input pulse voltage 0.1 V
CC
to 0.9 V
CC
Output reference voltage 0.5 V
CC
Output load 100 pF

Table 17
40 to +85C +85 to +105C
V
CC
= 4.5 to 5.5 V V
CC
= 2.5 to 4.5 V V
CC
= 1.8 to 2.5 V V
CC
= 4.5 to 5.5 V
Item Symbol
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Unit
CS setup time

t
CSS
0.2 0.4 1.0 0.2 s
CS hold time

t
CSH
0 0 0 0 s
CS deselect time t
CDS
0.2 0.2 0.4 0.2 s
Data setup time t
DS
0.1 0.2 0.4 0.1 s
Data hold time t
DH
0.1 0.2 0.4 0.1 s
Output delay time t
PD
0.4 0.8 2.0 0.6 s
Clock frequency
*1
f
SK
0 2.0 0 0.5 0 0.25 0 1.0 MHz
SK clock time L
*1
t
SKL
0.1 0.5 1.0 0.25 s
SK clock time H
*1
t
SKH
0.1 0.5 1.0 0.25 s
Output disable time t
HZ1
,

t
HZ2
0 0.15 0 0.5 0 1.0 0 0.15 s
Output enable time t
SV
0 0.15 0 0.5 0 1.0 0 0.15 s
*1. The clock cycle of the SK clock (frequency: f
SK
) is 1/f
SK
s. This clock cycle is determined by a combination
of several AC characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle
(1/f
SK
) cannot be made equal to t
SKL
(Min.) + t
SKH
(Min.).

Table 18
40 to +85C +85 to +105C
V
CC
= 2.7 to 5.5 V V
CC
= 4.5 to 5.5 V
Item Symbol
Min. Typ. Max. Min. Typ. Max.
Unit
Write time t
PR
4.0 8.0 4.0 8.0 ms


CMOS SERIAL E
2
PROM
Rev.4.3_00 S-93C46B/56B/66B

Seiko Instruments Inc. 11



t SKH
t CDS tCSS
CS
Valid data Valid data
DI
tSKL
SK
t SV
t HZ2
tCSH
t HZ1
t PD
tPD
tDS tDH t DS t DH
Hi-Z Hi-Z
Hi-Z
DO
DO
(READ)
(VERIFY)
Hi-Z
*1

1/f
SK
*2



*1. Indicates high impedance.
*2. 1/f
SK
is the SK clock cycle. This clock cycle is determined by a combination of several AC
characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle
(1/f
SK
) cannot be made equal to t
SKL
(Min.) + t
SKH
(Min.).

Figure 7 Timing Chart
CMOS SERIAL E
2
PROM
S-93C46B/56B/66B Rev.4.3_00

Seiko Instruments Inc. 12
Operation
All instructions are executed by inputting DI in synchronization with the rising edge of SK after CS goes
high. An instruction set is input in the order of start bit, instruction, address, and data.
Instruction input finishes when CS goes low. A low level must be input to CS between commands during
t
CDS
. While a low level is being input to CS, the S-93C46B/56B/66B is in standby mode, so the SK and DI
inputs are invalid and no instructions are allowed.



Start Bit
A start bit is recognized when the DI pin goes high at the rise of SK after CS goes high. After CS goes high,
a start bit is not recognized even if the SK pulse is input as long as the DI pin is low.

1. Dummy clock
SK clocks input while the DI pin is low before a start bit is input are called dummy clocks. Dummy
clocks are effective when aligning the number of instruction sets (clocks) sent by the CPU with those
required for serial memory operation. For example, when a CPU instruction set is 16 bits, the number
of instruction set clocks can be adjusted by inserting a 7-bit dummy clock for the S-93C46B and a 5-bit
dummy clock for the S-93C56B/66B.

2. Start bit input failure
When the output status of the DO pin is high during the verify period after a write operation, if a high
level is input to the DI pin at the rising edge of SK, the S-93C46B/56B/66B recognizes that a start bit
has been input. To prevent this failure, input a low level to the DI pin during the verify operation
period (refer to 4.1 Verify operation).

When a 3-wire interface is configured by connecting the DI input pin and DO output pin, a period in
which the data output from the CPU and the serial memory collide may be generated, preventing
successful input of the start bit. Take the measures described in 3-Wire Interface (Direct
Connection between DI and DO).

CMOS SERIAL E
2
PROM
Rev.4.3_00 S-93C46B/56B/66B

Seiko Instruments Inc. 13

3. Reading (READ)
The READ instruction reads data from a specified address.
After CS has gone high, input an instruction in the order of the start bit, read instruction, and address.
Since the last input address (A
0
) has been latched, the output status of the DO pin changes from high
impedance (Hi-Z) to low, which is held until the next rise of SK. 16-bit data starts to be output in
synchronization with the next rise of SK.

3. 1 Sequential read
After the 16-bit data at the specified address has been output, inputting SK while CS is high
automatically increments the address, and causes the 16-bit data at the next address to be output
sequentially. The above method makes it possible to read the data in the whole memory space.
The last address (A
n
A
1
A
0
= 1 1 1) rolls over to the top address (A
n
A
1
A
0
= 0 0 0).


D 15 D15 D14
D14 D13 D 14 D13 D0 D1 D2
D 15 0 D 0 D 1 D 2 D13
A 1 A 2 A3 A 4 A 5 0 1 <1> A 0
SK
DI
CS
DO
ADRINC
Hi-Z
28 27 26 25 24 23 12 11 10 9 8 7 6 5 4 3 2 1 44 43 42 41 40 39
ADRINC
Hi-Z


Figure 8 Read Timing (S-93C46B)



SK
D13 D 15 0 D14 D14 D13 D0 D1 D2 D15 D 14 D 0 D 1 D2 D 13 D 15
41 40 43 44 42 28 27 26 25 24
A3 A 4 A 5 A 0 A 1 A 2 DI
13 11 10 9 8 7 6 5 4 3 2 1 12
CS
DO
A 6
45 29 14
Hi-Z Hi-Z
0 1 <1>
ADRINC ADRINC
X: S-93C56B
A7: S-93C66B



Figure 9 Read Timing (S-93C56B, S-93C66B)



CMOS SERIAL E
2
PROM
S-93C46B/56B/66B Rev.4.3_00

Seiko Instruments Inc. 14

4. Writing (WRITE, ERASE, WRAL, ERAL)
A write operation includes four write instructions: data write (WRITE), data erase (ERASE), chip write
(WRAL), and chip erase (ERAL).
A write instruction (WRITE, ERASE, WRAL, ERAL) starts a write operation to the memory cell when a
low level is input to CS after a specified number of clocks have been input. The SK and DI inputs are
invalid during the write period, so do not input an instruction.
Input an instruction while the output status of the DO pin is high or high impedance (Hi-Z).
A write operation is valid only in program enable mode (refer to 5. Write enable (EWEN) and write
disable (EWDS)).

4. 1 Verify operation
A write operation executed by any instruction is completed within 8 ms (write time t
PR
: typically 4
ms), so if the completion of the write operation is recognized, the write cycle can be minimized. A
sequential operation to confirm the status of a write operation is called a verify operation.

(1) Operation
After the write operation has started (CS = low), the status of the write operation can be verified
by confirming the output status of the DO pin by inputting a high level to CS again. This
sequence is called a verify operation, and the period that a high level is input to the CS pin after
the write operation has started is called the verify operation period.
The relationship between the output status of the DO pin and the write operation during the
verify operation period is as follows.
DO pin = low: Writing in progress (busy)
DO pin = high: Writing completed (ready)

(2) Operation example
There are two methods to perform a verify operation: Waiting for a change in the output status
of the DO pin while keeping CS high, or suspending the verify operation (CS = low) once and
then performing it again to verify the output status of the DO pin. The latter method allows the
CPU to perform other processing during the wait period, allowing an efficient system to be
designed.

Caution 1. Input a low level to the DI pin during a verify operation.
2. If a high level is input to the DI pin at the rise of SK when the output status of the DO
pin is high, the S-93C46B/56B/66B latches the instruction assuming that a start bit has
been input. In this case, note that the DO pin immediately enters a high-impedance
(Hi-Z) state.


CMOS SERIAL E
2
PROM
Rev.4.3_00 S-93C46B/56B/66B

Seiko Instruments Inc. 15

4. 2 Writing data (WRITE)
To write 16-bit data to a specified address, change CS to high and then input the WRITE
instruction, address, and 16-bit data following the start bit. The write operation starts when CS
goes low. There is no need to set the data to 1 before writing. If the clocks more than the specified
number have been input, the clock pulse monitoring circuit cancels the WRITE instruction. For
details of the clock pulse monitoring circuit, refer to Function to Protect Against Write due to
Erroneous Instruction Recognition.


HZ1
A5 A3 A2 A1 A0 D15 A4
1 3 4 5 6 7 8 9 10 2
0 1 <1>
25
t CDS
Verify
Busy
Standby
t SV t
Ready
t PR
Hi-Z
CS
SK
DI
DO
Hi-Z
D0


Figure 10 Data Write Timing (S-93C46B)


<1>
R eady
Busy
t PR
t SV
t CDS
27 1 2 3 4 5 6 7 8 9 10 11 12
0 1 D0 A6 A5 A4 A3 A2 A1 A0 D15
CS
SK
DI
DO
Hi-Z
Verify
Standby
Hi-Z
t HZ1
x : S-93C56B
A7: S-93C66B


Figure 11 Data Write Timing (S-93C56B, S-93C66B)



CMOS SERIAL E
2
PROM
S-93C46B/56B/66B Rev.4.3_00

Seiko Instruments Inc. 16

4. 3 Erasing data (ERASE)
To erase 16-bit data at a specified address, set all 16 bits of the data to 1, change CS to high, and
then input the ERASE instruction and address following the start bit. There is no need to input data.
The data erase operation starts when CS goes low. If the clocks more than the specified number
have been input, the clock pulse monitoring circuit cancels the ERASE instruction. For details of
the clock pulse monitoring circuit, refer to Function to Protect Against Write due to
Erroneous Instruction Recognition.


Verify
t SV
SK
DI
A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9
CS
DO
t CDS
t PR
Busy
Hi-Z
Standby
Hi-Z
t HZ1
<1>
1 A0
Ready
1


Figure 12 Data Erase Timing (S-93C46B)


Ready
t CDS
t SV
Hi-Z
t HZ1
t PR
SK
DI
<1>
A6 A5 A4 A3 A2 A1 A0
1 2 3 4 5 6 7 8 9 10 11
CS
DO
Busy
Verify
Standby
Hi-Z
1 1
x : S-93C56B
A7: S-93C66B


Figure 13 Data Erase Timing (S-93C56B, S-93C66B)



CMOS SERIAL E
2
PROM
Rev.4.3_00 S-93C46B/56B/66B

Seiko Instruments Inc. 17

4. 4 Writing to chip (WRAL)
To write the same 16-bit data to the entire memory address space, change CS to high, and then
input the WRAL instruction, an address, and 16-bit data following the start bit. Any address can be
input. The write operation starts when CS goes low. There is no need to set the data to 1 before
writing. If the clocks more than the specified number have been input, the clock pulse monitoring
circuit cancels the WRAL instruction. For details of the clock pulse monitoring circuit, refer to
Function to Protect Against Write due to Erroneous Instruction Recognition.


2 3 4 5 6 7 8 9 10 1
SK
DI
t CDS
t SV t HZ1
Hi-Z
t PR
CS
DO
B usy
Verify
Standby
Hi-Z
25
<1> 0 D0
R eady
0 0 1
4Xs
D15


Figure 14 Chip Write Timing (S-93C46B)


Verify
2 3 4 5 6 7 8 9 10 1
SK
DI
t CDS
t SV t HZ1
Hi-Z
t PR
CS
DO
B usy
Standby
Hi-Z
11 12 27
<1> 0 D0
R eady
0 0 1
6Xs
D15


Figure 15 Chip Write Timing (S-93C56B, S-93C66B)


CMOS SERIAL E
2
PROM
S-93C46B/56B/66B Rev.4.3_00

Seiko Instruments Inc. 18

4. 5 Erasing chip (ERAL)
To erase the data of the entire memory address space, set all the data to 1, change CS to high, and
then input the ERAL instruction and an address following the start bit. Any address can be input.
There is no need to input data. The chips erase operation starts when CS goes low. If the clocks
more than the specified number have been input, the clock pulse monitoring circuit cancels the
ERAL instruction. For details of the clock pulse monitoring circuit, refer to Function to Protect
Against Write due to Erroneous Instruction Recognition.


t CDS
4Xs
0 1 0
8 7 6 5 4 3 2 1
<1> 0
t PR
Hi-Z
t HZ1
R eady
B usy
t SV
Standby
Verify
9
SK
DI
CS
DO


Figure 16 Chip Erase Timing (S-93C46B)



7 6 5 4 3 2 1 9 8
CS
SK
DI
DO
t CDS
t SV
R eady
B usy
t HZ1
Hi-Z
t PR
11
6Xs
0 1 0 <1> 0
Standby
Verify
10


Figure 17 Chip Erase Timing (S-93C56B, S-93C66B)




CMOS SERIAL E
2
PROM
Rev.4.3_00 S-93C46B/56B/66B

Seiko Instruments Inc. 19

5. Write enable (EWEN) and write disable (EWDS)
The EWEN instruction is an instruction that enables a write operation. The status in which a write
operation is enabled is called the program enable mode.
The EWDS instruction is an instruction that disables a write operation. The status in which a write
operation is disabled is called the program disable mode.
After CS goes high, input an instruction in the order of the start bit, EWEN or EWDS instruction, and
address (optional). Each mode becomes valid by inputting a low level to CS after the last address
(optional) has been input.


5 4 3 2 1 9 8 7 6 SK
DI
CS
4Xs
11 = EWEN
00 = EWDS
0 <1> 0
Standby


Figure 18 Write Enable/Disable Timing (S-93C46B)



DI
SK
6 5 4 3 2 1 9 8 11 10 7
CS
6Xs
11 = EWEN
00 = EWDS
0
<1>
0
Standby


Figure 19 Write Enable/Disable Timing (S-93C56B, S-93C66B)

(1) Recommendation for write operation disable instruction
It is recommended to implement a design that prevents an incorrect write operation when a write
instruction is erroneously recognized by executing the write operation disable instruction when
executing instructions other than write instruction, and immediately after power-on and before
power off.

CMOS SERIAL E
2
PROM
S-93C46B/56B/66B Rev.4.3_00

Seiko Instruments Inc. 20
Write Disable Function when Power Supply Voltage is Low

The S-93C46B/56B/66B provides a built-in detector to detect a low power supply voltage and disable
writing. When the power supply voltage is low or at power application, the write instructions (WRITE,
ERASE, WRAL, and ERAL) are cancelled, and the write disable state (EWDS) is automatically set. The
detection voltage is 1.75 V typ., the release voltage is 2.05 V typ., and there is a hysteresis of about 0.3 V
(refer to Figure 20). Therefore, when a write operation is performed after the power supply voltage has
dropped and then risen again up to the level at which writing is possible, a write enable instruction (EWEN)
must be sent before a write instruction (WRITE, ERASE, WRAL, or ERAL) is executed.
When the power supply voltage drops during a write operation, the data being written to an address at that
time is not guaranteed.

Release voltage (+V
DET
)
2.05 V Typ.
Power supply voltage
Hysteresis
About 0.3 V
Detection voltage (V
DET
)
1.75 V Typ.
Write instruction cancelled
Write disable state (EWDS) automatically set


Figure 20 Operation when Power Supply Voltage is Low
CMOS SERIAL E
2
PROM
Rev.4.3_00 S-93C46B/56B/66B

Seiko Instruments Inc. 21
Function to Protect Against Write due to Erroneous Instruction Recognition

The S-93C46B/56B/66B provides a built-in clock pulse monitoring circuit which is used to prevent an
erroneous write operation by canceling write instructions (WRITE, ERASE, WRAL, and ERAL) recognized
erroneously due to an erroneous clock count caused by the application of noise pulses or double counting
of clocks.
Instructions are cancelled if a clock pulse more or less than specified number decided by each write
operation (WRITE, ERASE, WRAL, or ERAL) is detected.

<Example> Erroneous recognition of program disable instruction (EWDS) as erase instruction (ERASE)

1 3 4 5 6 7 2 8 9
CS
SK
DI
Input EWDS instruction
Erroneous recognition as
ERASE instruction due to
noise pulse
1 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1 0
Noise pulse
Example of S-93C46B
1
In products that do not include a clock pulse monitoring circuit, FFFF is
mistakenly written on address 00h. However the S-93C46B detects the overcount
and cancels the instruction without performing a write operation.


Figure 21 Example of Clock Pulse Monitoring Circuit Operation

CMOS SERIAL E
2
PROM
S-93C46B/56B/66B Rev.4.3_00

Seiko Instruments Inc. 22
3-Wire Interface (Direct Connection between DI and DO)
There are two types of serial interface configurations: a 4-wire interface configured using the CS, SK, DI,
and DO pins, and a 3-wire interface that connects the DI input pin and DO output pin.
When the 3-wire interface is employed, a period in which the data output from the CPU and the data output
from the serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect
the DI and DO pins of the S-93C46B/56B/66B via a resistor (10 to 100 k) so that the data output from the
CPU takes precedence in being input to the DI pin (refer to Figure 22 Connection of 3-Wire Interface).

CPU
DI
SIO
DO
S-93C46B/56B/66B
R: 10 to 100 k


Figure 22 Connection of 3-Wire Interface



I/O Pins

1. Connection of input pins
All the input pins of the S-93C46B/56B/66B employ a CMOS structure, so design the equipment so that
high impedance will not be input while the S-93C46B/56B/66B is operating. Especially, deselect the CS
input (a low level) when turning on/off power and during standby. When the CS pin is deselected (a low
level), incorrect data writing will not occur. Connect the CS pin to GND via a resistor (10 to 100 k pull-
down resistor). To prevent malfunction, it is recommended to use equivalent pull-down resistors for
pins other than the CS pin.

2. Input and output pin equivalent circuits
The following shows the equivalent circuits of input pins of the S-93C46B/56B/66B. None of the input
pins incorporate pull-up and pull-down elements, so special care must be taken when designing to
prevent a floating status.
Output pins are high-level/low-level/high-impedance tri-state outputs. The TEST pin is disconnected
from the internal circuit by a switching transistor during normal operation. As long as the absolute
maximum rating is satisfied, the TEST pin and internal circuit will never be connected.

CMOS SERIAL E
2
PROM
Rev.4.3_00 S-93C46B/56B/66B

Seiko Instruments Inc. 23

2. 1 Input pin


CS


Figure 23 CS Pin



SK, DI


Figure 24 SK, DI Pin



TEST


Figure 25 TEST Pin
CMOS SERIAL E
2
PROM
S-93C46B/56B/66B Rev.4.3_00

Seiko Instruments Inc. 24

2. 2 Output pin


DO
Vcc


Figure 26 DO Pin


3. Input pin noise elimination time
The S-93C46B/56B/66B include a built-in low-pass filter to eliminate noise at the SK, DI, and CS pins.
This means that if the supply voltage is 5.0 V (at room temperature), noise with a pulse width of 20 ns
or less can be eliminated.
Note, therefore, the noise with a pulse width of more than 20 ns will be recognized as a pulse if the
voltage exceeds V
IH
/V
IL
.



Precaution
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
SII claims no responsibility for any and all disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
CMOS SERIAL E
2
PROM
Rev.4.3_00 S-93C46B/56B/66B

Seiko Instruments Inc. 25
Characteristics (Typical Data)
1. DC Characteristics
1. 1 Current consumption (READ) I
CC1

vs. ambient temperature Ta
1. 2 Current consumption (READ) I
CC1

vs. ambient temperature Ta

Ta (C)
0.4
0.2
VCC = 5.5 V
fSK = 2 MHz
DATA = 0101
0
40 0 85
ICC1
(mA)


Ta (C)
0.4
0.2
V
CC
= 3.3 V
f
SK
= 500 kHz
DATA = 0101
0
40 0 85
I
CC1

(mA)


1. 3 Current consumption (READ) I
CC1

vs. ambient temperature Ta
1. 4 Current consumption (READ) I
CC1

vs. power supply voltage V
CC


ICC1
(mA)
Ta (C)
0.4
0.2
VCC = 1.8 V
fSK = 10 kHz
DATA = 0101
0
40 0 85


1 MHz

500 kHz
I
CC1

(mA)
0.4
0.2
0
2 3 4 5 6 7
Ta = 25C
f
SK
= 1 MHz, 500 kHz
DATA = 0101
V
CC
(V)


1. 5 Current consumption (READ) I
CC1

vs. power supply voltage V
CC

1. 6 Current consumption (READ) I
CC1

vs. Clock frequency f
SK


100 kHz
10 kHz
I
CC1

(mA)
0.4
0.2
0
2 3 4 5 6 7
V
CC
(V)
Ta = 25C
f
SK
= 100 kHz, 10 kHz
DATA = 0101


I
CC1

(mA)
0.4
0.2
0
V
CC
= 5.0 V
Ta = 25C
1 M 2M 10M 10 k 100 k
f
SK
(Hz)

CMOS SERIAL E
2
PROM
S-93C46B/56B/66B Rev.4.3_00

Seiko Instruments Inc. 26

1. 7 Current consumption (WRITE) I
CC2

vs. ambient temperature Ta
1. 8 Current consumption (WRITE) I
CC2

vs. ambient temperature Ta

Ta (C)
1.0
0.5
VCC = 5.5 V
0
40 0 85
ICC2
(mA)


I
CC2

(mA)
Ta (C)
1.0
0.5
V
CC
= 3.3 V
0
40 0 85


1. 9 Current consumption (WRITE) I
CC2

vs. ambient temperature Ta
1. 10 Current consumption (WRITE) I
CC2

vs. power supply voltage V
CC


Ta (C)
1.0
0.5
VCC = 2.7 V
0
40 0 85
ICC2
(mA)

1.0
0.5
0
2 3 4 5 6 7
Ta = 25C
VCC (V)
ICC2
(mA)


1. 11 Current consumption in standby mode I
SB

vs. ambient temperature Ta
1. 12 Current consumption in standby mode I
SB

vs. power supply voltage V
CC


Ta (C)
1.0
0.5
V
CC
= 5.5 V
CS = GND
0
40 0 85
I
SB

(A)


I
SB

(A)
1.0
0.5
0
2 3 4 5 6 7
Ta = 25C
CS = GND
V
CC
(V)

CMOS SERIAL E
2
PROM
Rev.4.3_00 S-93C46B/56B/66B

Seiko Instruments Inc. 27

1. 13 Input leakage current I
LI

vs. ambient temperature Ta
1. 14 Input leakage current I
LI

vs. ambient temperature Ta

1.0
0.5
V
CC
=5.5 V
CS, SK, DI,
TEST=0 V
0
-40 0 85
l
LI

(A)
Ta (C)

Ta (C)
1.0
0.5
0
40 0 85
V
CC
= 5.5 V
CS, SK, DI,
TEST = 5.5 V
ILI
(A)


1. 15 Output leakage current I
LO

vs. ambient temperature Ta
1. 16 Output leakage current I
LO

vs. ambient temperature Ta

Ta (C)
1.0
0.5
VCC = 5.5 V
DO = 0 V
0
40 0 85
ILO
(A)


Ta (C)
1.0
0.5
V
CC
= 5.5 V
DO = 5.5 V
0
40 0 85
I
LO

(A)


1. 17 High-level output voltage V
OH

vs. ambient temperature Ta
1. 18 High-level output voltage V
OH

vs. ambient temperature Ta

Ta (C)
4.6
4.4
V
CC
= 4.5 V
I
OH
= 400 A
40 0 85
V
OH

(V)
4.2

Ta (C)
2.7
2.6
V
CC
= 2.7 V
I
OH
= 100 A
40 0 85
V
OH
(V)
2.5

CMOS SERIAL E
2
PROM
S-93C46B/56B/66B Rev.4.3_00

Seiko Instruments Inc. 28

1. 19 High-level output voltage V
OH

vs. ambient temperature Ta
1. 20 High-level output voltage V
OH

vs. ambient temperature Ta

Ta (C)
2.5
2.4
VCC = 2.5 V
IOH = 100 A
40 0 85
VOH
(V)
2.3


Ta (C)
1.9
1.8
V
CC
= 1.8 V
I
OH
= 10 A
40 0 85
V
OH

(V)
1.7


1. 21 Low-level output voltage V
OL

vs. ambient temperature Ta
1. 22 Low-level output voltage V
OL

vs. ambient temperature Ta

Ta (C)
0.3
0.2
VCC = 4.5 V
IOL = 2.1 mA
40 0 85
VOL
(V)
0.1


Ta (C)
0.03
0.02
VCC = 1.8 V
IOL = 100 A
40 0 85
VOL
(V)
0.01


1. 23 High-level output current I
OH

vs. ambient temperature Ta
1. 24 High-level output current I
OH

vs. ambient temperature Ta

Ta (C)
20.0
10.0
VCC = 4.5 V
VOH = 2.4 V
0
40 0 85
IOH
(mA)


Ta (C)
2
1
V
CC
= 2.7 V
V
OH
= 2.4 V
0
40 0 85
I
OH

(mA)


CMOS SERIAL E
2
PROM
Rev.4.3_00 S-93C46B/56B/66B

Seiko Instruments Inc. 29

1. 25 High-level output current I
OH

vs. ambient temperature Ta
1. 26 High-level output current I
OH

vs. ambient temperature Ta

Ta (C)
2
1
VCC = 2.5 V
VOH = 2.2 V
0
40 0 85
IOH
(mA)


Ta (C)
1.0
0.5
VCC = 1.8 V
VOH = 1.6 V
0
40 0 85
IOH
(mA)


1. 27 Low-level output current I
OL

vs. ambient temperature Ta
1. 28 Low-level output current I
OL

vs. ambient temperature Ta

Ta (C)
20
10
V
CC
= 4.5 V
V
OL
= 0.4 V
0
40 0 85
I
OL

(mA)


Ta (C)
1.0
0.5
V
CC
= 1.8 V
V
OL
= 0.1 V
0
40 0 85
I
OL

(mA)


1. 29 Input inverted voltage V
INV

vs. power supply voltage V
CC

1. 30 Input inverted voltage V
INV
vs. ambient temperature Ta

3.0
1.5
0
1 2 3 4 5 6
Ta = 25C
CS, SK, DI
VCC (V)
VINV
(V)
7


Ta (C)
3.0
2.0
V
CC
= 5.0 V
CS, SK, DI
0
40 0 85
V
INV
(V)

CMOS SERIAL E
2
PROM
S-93C46B/56B/66B Rev.4.3_00

Seiko Instruments Inc. 30

1. 31 Low supply voltage detection voltage V
DET

vs. ambient temperature Ta
1. 32 Low supply voltage release voltage +V
DET
vs. ambient temperature Ta
Ta (C)
2.0
1.0
0
40 0 85
VDET
(V)

Ta (C)
2.0
1.0
0
40 0 85
+VDET
(V)


CMOS SERIAL E
2
PROM
Rev.4.3_00 S-93C46B/56B/66B

Seiko Instruments Inc. 31

2. AC Characteristics
2. 1 Maximum operating frequency f
MAX.

vs. power supply voltage V
CC

2. 2 Write time t
PR

vs. power supply voltage V
CC

10k
2 3 4 5
Ta = 25C
V
CC
(V)
f
MAX.
(Hz)
1
100k
1M
2M

4
2
2 3 4 5 6 7
Ta = 25C
V
CC
(V)
t
PR

(ms)
1


2. 3 Write time t
PR

vs. ambient temperature Ta
2. 4 Write time t
PR

vs. ambient temperature Ta

Ta (C)
6
4
VCC = 5.0 V
40 0 85
2
tPR
(ms)


Ta (C)
6
4
V
CC
= 3.0 V
40 0 85
2
t
PR

(ms)



2. 5 Write time t
PR

vs. ambient temperature Ta
2. 6 Data output delay time t
PD

vs. ambient temperature Ta

Ta (C)
6
4
VCC = 2.7 V
40 0 85
2
tPR
(ms)


Ta (C)
0.3
0.2
VCC = 4.5 V
40 0 85
0.1
tPD
(s)

CMOS SERIAL E
2
PROM
S-93C46B/56B/66B Rev.4.3_00

Seiko Instruments Inc. 32


2. 7 Data output delay time t
PD

vs. ambient temperature Ta
2. 8 Data output delay time t
PD

vs. ambient temperature Ta

Ta (C)
0.6
0.4
VCC = 2.7 V
40 0 85
0.2
tPD
(s)


Ta (C)
1.5
1.0
VCC = 1.8 V
40 0 85
0.5
tPD
(s)

CMOS SERIAL E
2
PROM
Rev.4.3_00 S-93C46B/56B/66B

Seiko Instruments Inc. 33
Product Name Structure


S-93CxxB x 0 x - xxxx G
Package name (abbreviation) and IC packing specifications
D8S1: 8-Pin DIP, Tube
J8T1: 8-Pin SOP(JEDEC), Tape
J8T2: 8-Pin SOP(JEDEC), Tape, +105C Max.supported
T8T1: 8-Pin TSSOP, Tape
T8T2: 8-Pin TSSOP, Tape, +105C Max. supported
I8T1: SNT-8A, Tape

Operation temperature
I: 40 to +85C
H: 40 to +105C (Only 8-Pin SOP(JEDEC) , 8-Pin TSSOP)

Fixed

Pin assignment
D: 8-Pin DIP
8-Pin SOP(JEDEC)
8-Pin TSSOP
SNT-8A
R: 8-Pin SOP(JEDEC) (Rotated)

Product name
S-93C46B : 1 K-bit
S-93C56B : 2 K-bit
S-93C66B : 4 K-bit


No.
TTLE
SCALE
UNT mm
Sei ko nstruments nc.
DP8-F-PKG Dimensions
No. DP008-F-P-SD-3.0
DP008-F-P-SD-3.0
0.480.1
2.54
0.89 1.3
0 to 15
0.25
+0.11
-0.05
7.62
9.6(10.6max.)
1 4
5
8
No. FJ008-A-P-SD-2.1
No.
TTLE
SCALE
UNT mm
SOP8J-D-PKG Dimensions
Sei ko nstruments nc.
FJ008-A-P-SD-2.1
0.40.05 1.27
0.200.05
5.020.2
1 4
8 5
No.
TTLE
SCALE
UNT mm
5
8 1
4
2.00.05
1.550.05 0.30.05
2.10.1
8.00.1
5max.
6.70.1
2.00.05
Sei ko nstruments nc.
Feed direction
4.00.1(10 pitches:40.00.2)
SOP8J- D- Car r i er Tape
No. FJ008-D-C-SD-1.1
FJ008-D-C-SD-1.1
No.
TTLE
SCALE
UNT mm
QTY.
2,000
20.5
13.50.5
60
20.5
130.2
210.8
Sei ko nstruments nc.
Enlarged drawing in the central part
SOP8J- D- Reel
No. FJ008-D-R-SD-1.1
FJ008-D-R-SD-1.1
No.
TTLE
SCALE
UNT
mm
Sei ko nstruments nc.
TSSOP8-E-PKG Dimensions
No. FT008-A-P-SD-1.1
FT008-A-P-SD-1.1
0.170.05
3.00
+0.3
-0.2
0.65
0.20.1
1
4
5
8
No.
TTLE
SCALE
UNT
mm
Sei ko nstruments nc.
1.550.05
2.00.05
8.00.1
1.55
+0.1
-0.05
(4.4)
0.30.05
1
4 5
8
4.00.1
Feed direction
TSSOP8- E- Car r i er Tape
No. FT008-E-C-SD-1.0
FT008-E-C-SD-1.0
+0.4
-0.2
6.6
No.
TTLE
SCALE
UNT
mm
Sei ko nstruments nc.
Enlarged drawing in the central part
No. FT008-E-R-SD-1.0
20.5
130.5
210.8
13.41.0
17.51.0
3,000 QTY.
TSSOP8- E- Reel
FT008-E-R-SD-1.0
1.970.03
0.20.05
0.480.02
0.08
No.
TTLE
SCALE
UNT mm
Sei ko nstruments nc.
SNT-8A-A-PKG Dimensions
PH008-A-P-SD-2.0
No. PH008-A-P-SD-2.0
0.5
+0.05
-0.02 1 2 3 4
5 6 7 8
No.
TTLE
SCALE
UNT mm
Sei ko nstruments nc.
PH008-A-C-SD-1.0
SNT- 8A- A- Car r i er Tape
No. PH008-A-C-SD-1.0
Feed direction
4.00.1 2.00.05
4.00.1
1.5
+0.1
-0
0.50.1
2.250.05
0.650.05
0.250.05
2 1 3 4
7 8 6 5
5
12.5max.
9.00.3
130.2
(60) (60)
Enlarged drawing in the central part
QTY.
PH008-A-R-SD-1.0 No.
TTLE
SCALE
UNT mm
Sei ko nstruments nc.
SNT-8A-A-Reel
No. PH008-A-R-SD-1.0
5,000
No.
TTLE
SCALE
UNT mm
SNT-8A-A-Land Recommendation
Sei ko nstruments nc.
PH008-A-L-SD-3.0
0.3 0.2 0.3 0.2 0.3
0.52
2.01
0.52
No. PH008-A-L-SD-3.0
0.3
0.2
Caution Making the wire pattern under the package is possible. However, note that the package
may be upraised due to the thickness made by the silk screen printing and of a solder
resist on the pattern because this package does not have the standoff.
The information described herein is subject to change without notice.
Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.
When the products described herein are regulated products subject to the Wassenaar Arrangement or other
agreements, they may not be exported without authorization from the appropriate governmental authority.
Use of the information described herein for other purposes and/or reproduction or copying without the
express permission of Seiko Instruments Inc. is strictly prohibited.
The products described herein cannot be used as part of any device or equipment affecting the human
body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus
installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc.
Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.