White Paper

Design Practices and Strategies for Efcient

Signal Integrity Closure
Richard Nouri, Senior Design Consultant, Synopsys Professional Services
Todd Beck, Senior Design Consultant, Synopsys Professional Services
Jennifer Pyon, Corporate Applications Engineer, Synopsys
February 2005
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2007 Synopsys, Inc.
Signal integrity (SI) issues such as crosstalk delay and noise become critical for system-on-chip (SoC)
designs at about the 150-nanometer (nm) technology node and unavoidable at 130-nm and below. These
SI issues can lead to major timing-closure difcultiesand thus tapeout schedule delaysif left to the
nal stages of physical design, and ultimately can cause chip failures and poor manufacturing yield unless
addressed in the design cycle. Fortunately, several years of experience with SI at very deep submicron
geometries have led to efcient methodologies throughout the design ow for preventing, detecting and
xing SI effects.
Given the extent of the SI design challenge, designers must take steps to ensure signal integrity throughout
the design cycle. An integrated SI sub-ow, such as Synopsys Galaxy SI ow, provides a comprehensive
approach from design planning to post-GDSII ECOs. A dedicated sub-ow addresses SI with prevention,
analysis and repair methodologies utilizing SI-aware placement, routing and static timing signoff. An
effective approach to SI also comprehends good design practices in oorplanning, power planning and
constraining.
The information that follows in this Synopsys Professional Services white paper focuses on best practices
in applying the SI sub-ow throughout the design cycle for achieving an SI-clean tape-out in the shortest
amount of time. The techniques described herein have proven effective in achieving SI closure in a
predictable manner. Some specic SI issues cannot be detected until after detail routing, when designers
least want to nd major timing problems. However, steps can be taken earlier in the ow to greatly reduce
the potential for SI problems. Figure 1 shows the key SI-related design and analysis tasks in the design
ow. The emphasis in this white paper is on prevention methods that minimize last-minute timing iterations.
Figure 1: The methods for preventing, detecting and xing signal integrity (SI) problems affect
every phase of the design ow.
Figure 2 gives a broad view of a typical SoC design ow from an SI perspective. Note that it shows many
designers do not begin serious SI work until after detailed routing. At very deep submicron process nodes,
this approach will almost certainly lead to numerous engineering change order (ECO) cycles at the end of
the ow to x SI problems. To avoid this series of late iterations, measures must be taken to prevent the
problems earlier in the design process.
Design planning
Route congestion reduction
Clock-tree spacing/shielding
Block shielding
SI-aware placement
Clock-tree preroute/spacing/shielding
Crosstalk-aware detail route
Driver resizing
Spacing
Bufer insertion and load isolation
Timing constraining
Driver sizing
Bottleneck analysis
ECO forwarding
ILM modeling
Synthesis and
physical synthesis
Place and route
SI analysis
SI ECOs
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Last-minute SI panic is typically seen in aggressive projects that focus most of the effort on reaching RTL
freeze and generating a netlist as quickly as possible. As a result, design teams may not spend enough
time on backend design planning (for power, clock tree, signals) and does not take the time for a (pipe
cleaning) test design that is representative of the nal design intent to discover problem areas. Such
projects often fail to have clear sign-off criteria and do not have enough timing budget to tradeoff when SI
problems arise. The schedule may not include time for ECOs or allow time to rework part of the ow, so the
team rushes through each ECO, hoping each will be the last.
Beginning with design planning and a sound SI strategy may make the schedule longer, but the schedule
will be reliable and timing closure more predictable.
Figure 2: The signal integrity ECO loop begins after detail route, when specic crosstalk issues can be analyzed. Within the loop,
the layout parasitics are extracted and the timing/noise effects are calculated by a static timing analyzer.
Without thorough design planning to avoid many SI issues, signicant timing and noise problems must be xed in
the layout making the loop very time consuming.
Signal Integrity Background
Signal integrity generally covers several types of issues that can cause signals to behave in unexpected
ways:
Timing changes due to crosstalk
Noise (glitches) due to crosstalk
Voltage (IR) drop
Electromigration
The main thrust of SI efforts is to prevent crosstalk from causing failures, either due to changing
signal timing or noise that changes logic states. Crosstalk occurs when energy from one or more nets
(aggressors) couples capacitively to another net (the victim). Parasitic capacitance becomes a bigger
problem as process geometries get smaller because metal traces are narrower, taller and closer together.
Additionally, larger chips mean that traces may run parallel for longer distances.

Signal
Integrity
ECO Loop
Design placement
Optimization
Clock tree synthesis
Post CTS optimization
Detailed route
Extraction
Crosstalk delay analysis
Crosstalk delay clean?
Crosstalk fx ECOs
ECO route
Done
No
Yes
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Figure 3 illustrates capacitive coupling and the crosstalk-induced timing changes that may result. Crosstalk
can increase or decrease delay, depending on whether the victim and aggressor nets are switching in the
same direction or different directions.

Figure 3: Most signal integrity work involves reducing delays or noise due to crosstalk between two or more nets.
The crosstalk occurs because of capacitive coupling between the nets.
Crosstalk can also induce a glitch when aggressors switch on a quiet victim net. While the capacitive
coupling that causes both the timing and glitch problems is the same, somewhat different methods are
used to detect the problems. In either case, the parasitic capacitance by itself is not regarded as a problem
unless it causes harmful timing changes or glitches.
Detecting SI problems therefore involves two steps: parasitics extraction and crosstalk-aware timing
analysis. In the extraction step, a tool such as Synopsys Star-RCXT analyzes the interconnects to
determine the parasitic capacitances for each section of interconnect. Theoretically, an extraction tool
would use the design rules for a given fabrication process and the properties of the materials to perform
3D electromagnetic eld calculations for each section of interconnect relative to all nearby sections of
interconnect. Performing such calculations using SPICE would take a very long time and be impractical.
Real-world extraction tools use 2.5D analysis (approximating depth) and statistical methods to calculate
parasitic values fairly quickly. Extraction achieves reasonable accuracy only after detail routing, when all the
interconnect relationships are dened. However, it is possible to estimate parasitics based on global routing
(more on this later). Even after detail routing, the extraction process has inherent inaccuracies that depend
on the process geometries, among other factors. It is important to know the accuracy limits of the extractor
and set margins accordingly.
The second step in detecting SI problems is to analyze the signals on adjacent nets to see if their
capacitive coupling results in timing errors or glitches. Multiple tools perform this analysis, including
Synopsys PrimeTime

SI (PTSI) and Astro.

Voltage drop and electromigration affect signal integrity indirectly. IR drop is a power routing problem
that occurs due to the resistance of a long power rail. The sagging power voltage reduces noise margins
and can cause sections of logic to slow down. Electromigration is a destruction of the interconnect metal
that results from the current density being too high for a given metal width. Over time, the interconnect
resistance increases, causing signal timing changes, or the interconnect may fail altogether. For information
on preventing these problems, please consult the Synopsys Professional Services white paper Design
Planning Strategies to Improve Physical Design FlowsFloorplanning and Power Planning (http://www.
synopsys.com/cgi-bin/sps/wp/dps/paper1.cgi).
Cross-coupled stage
Aggressor
Victim
Voltage
Aggressor
Victim
Time
Noise-induced
malfunction
C
s
C
w
2007 Synopsys, Inc.
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Preventing SI Problems in Design Planning
Some methods for preventing SI problems are simply good design practice, especially with regard to
careful oorplanning and power planning. For example, adjusting placement to minimize the distance
between drivers and pins is especially important for SI, as is avoiding long wires that could cause cross-
coupling problems. (A specic method is to use the max _ net _ length rule during optimization in
Physical Compiler

and Astro.) Even more important is the need to do everything possible to reduce routing
congestion, which helps reduce crosstalk. Easing congestion across the entire design and in specic local
areas also makes SI problems easier to x later because space is available for moving victim and aggressor
traces apart.
How much extra space is enough? The design planning white paper mentioned earlier provides some
rules of thumb and also makes clear that the rules have to suit the application. The SI problems that occur
in designs at 130-nm and smaller make the design-planning rules increasingly stringent. Floorplanning
is vital for reducing long channels and congestion in general, always keeping the idea of maximizing
resources in mind to prevent SI problems. Methods such as shielded feed-throughs help. More fundamental
is the consideration of placement utilization as it relates to design size. More cells generally mean more
congestion. Utilizing area recovery is therefore important, but this method has to be applied carefully to
paths that are close to zero slack because they could become SI victims.
It is useful to take advantage of tool capabilities such as congestion-driven placement in Physical Compiler
(physopt timing _ driven _ congestion). Astro post-placement optimization (astPostPS1) is
another option. This capability includes congestion-based coupling capacitance and noise estimation.
When it comes to design planning for preventing SI problems, clock trees deserve special care. Their
many levels of logic pose particular risks for crosstalk because each level may experience only a small
amount of crosstalk-induced delay that accumulates to cause timing errors. Additionally, clock networks
can be difcult to x after routing. It is therefore worthwhile during oorplanning to triple-space clock
network tracks, shield clock traces, constrain clocks to separate metal layers, and/or use higher-layer
metal. However, triple spacing may not be sufcient, and shielding may lead to additional delay. Controlling
transition time in synthesis is a good idea to scale-up drivers, as is the use of inverters and balanced
buffers to minimize rise-versus-fall skew.
Power planning can also play a big role in helping to avoid congestion and thus minimize noise. Power
Network Analysis (PNA) in Jupiter can help reduce local congestion.
Especially large designs may benet from the use of a shielded hierarchical design ow. When designs are
as big as 1.5M instances, the shielded ow is helpful for avoiding memory- and compute-capacity issues.
By not running top-level nets over or near blocks (within 10 microns), this ow prevents SI interactions
between block and top-level nets. Using this approach eliminates the need to run SI-related analyses for
the entire attened design. Analyzing each block separately detects all possible SI problems.
If some nets must pass over a block, it is better to design that block from the beginning with feed-throughs.
These nets are put through the block with buffers and appropriate constraints, and treated like any other
signal nets when analyzing the block.
Synthesis and Constraining Methods for Avoiding SI Issues
From initial synthesis through the rest of the design ow, SI problems can be minimized by following a rule
of thumb that is good for dealing with all kinds of timing issues: start with healthy timing margins that can
be progressively relaxed over the course of the design ow. The actual margins depend on the specic
design and library in use, but for typical designs, somewhere around 20 to 25 percent might be reasonable
in Design Compiler

, 15 to 17 percent in Physical Compiler, 10 to 12 percent in Astro, and 7 to 10 percent

at sign-off. For designs with clock speeds greater than about 500 MHz, these margins might begin at 10
to 15 percent for Design Compiler and range down to 3 to 5 percent at sign-off. Whatever the specic
percentages used, the progressive reduction in margins reects the ows increasing accuracy as the
design moves toward tape out.
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2007 Synopsys, Inc.
Realistic timing margins are especially important in SI work to account for the nature of the timing issues
involved in known inaccuracies of extraction, Nonlinear Delay Models (NLDMs), simulation results versus
SPICE, IR drop, and other factors that contribute to on-chip variation (OCV). In addition to fundamental
inaccuracies, the statistical methods used in parasitics extraction may cause slightly different results
from one run to another. After the design has been changed in one area, a timing error may appear in an
untouched area. But if this timing error is within the extraction tools statistical accuracy, the timing margins
can cover for the problem, and the error can be ignored.
In general, the inaccuracies from all sources must be summed, and the overall design margin set
accordingly. Note that some libraries have 5 to 10 percent timing margin built-in, so additional margining
during signoff may be excessive. Unfortunately, information on library margins is often unavailable, whether
the libraries are characterized internally or acquired from a third party. As with all SI tradeoffs, pessimism is
the default position, yet the basic relationship between bigger margins and higher area penalties needs to
constrain the inclination toward excessive margins.
Note that margins are especially critical at 90-nm and below. At 90-nm, most paths show some amount
of SI-related delay. Whether three, ve or 10 ps, these delays seem to affect the entire design. The more
gates in a path, the more time is lost, so that the many small delays can add up to big problems. This
pervasive effect is not usually seen in 130-nm designs, where many nets may have SI-related timing errors,
but most nets have no detectable SI problems.
It is impossible to x every SI problems in a 90-nm design, so margins must be big enough to account
for the added delays. As described earlier, setting margins higher at the beginning of the ow and
progressively relaxing them works well.
In addition to general-purpose methods that prevent or minimize the impact of all timing issues, it is useful
to take advantage of a methodology specically targeted at reducing the likelihood of SI problems. This
approach is based on the understanding that stronger drivers make nets less susceptible to aggressors.
The use of stronger drivers can be encouraged by setting aggressive transition times, and a good initial
rule of thumb is 1 ns or less for max _ transition time in Design Compiler or Physical Compiler, although
especially slow designs may need to aim at even larger values. Basically, max _ transition needs to
parallel library characterization values, and most libraries have index points upwards of 1 ns.
Experiments with max _ transition constraints have shown that as the values get smaller, area gradually
increases until a pointa knee in the curveat which area increases dramatically. The ideal setting for
max _ transition is just above this knee. In some 90-nm designs, that point is below 400 ps, so the
range between 1 ns and 500 ps may be good. The tradeoffs with this technique are that stronger drivers
take more area and power, and the driven nets are more likely to become crosstalk aggressors themselves.
Also note that slow transition times can make SI analysis more pessimistic because arrival times are longer
and therefore create bigger timing windows in which the net is susceptible to problems. As with general
timing margins, max _ transition constraints can be set aggressively at the placement/optimization
stage and relaxed a little at the post-route stage.
SI Prevention in Physical Synthesis and Routing
As mentioned earlier, the best way to prevent crosstalk problems is to maximize area and routing resources.
It can be helpful to keep this principle in mind when applying timing/area constraints in physical synthesis.
For example, the impact of aggressive max _ transition time constraints can be minimized by targeting
them to timing-critical paths. Even with good prevention techniques, typical crosstalk-induced delays in the
critical paths of 90-nm designs are around 15 percent of the clock period (as seen after routing). Applying
more aggressive max _ transition time constraints only to those paths can reduce the likelihood
that they will become crosstalk victims, while avoiding the increase in area that would occur if the more
aggressive constraints were applied to nets that are not in the critical range. This approach also helps limit
the strength of potential aggressor nets.
2007 Synopsys, Inc.
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Another good technique for controlling area increases due to tight constraints is to apply area recovery
during optimization. At the same time, it is necessary to avoid downsizing drivers of nets in the critical
timing range (nets that have positive slack ranging from 0 to 15 percent of the clock period) because these
nets may become crosstalk victims. In Physical Compiler, it is possible to accomplish these goals by using
thearea _ recovery option in the physopt command with the area _ critical _ range.
In the Synopsys SI sub-ow, crosstalk prevention continues into the routing stage with efforts to avoid very
dense routing areas. Based on estimations of coupling capacitance or actual noise calculations, the router
should be able to estimate routing resources and allocate the net routing appropriately. The basic technique
is to spread out the wires within the same Gcell and among different Gcells to reduce the routing density,
usually in the global routing stage.
During track assignment, similar estimations can be done to identify high-noise nets. Based on these
estimations, the router attempts to avoid long parallel wires among the potential victim and aggressor nets.
Static SI Analysis
After detail routing, the extraction tool provides accurate parasitics values that are used for crosstalk delay
analysis in a tool such as PrimeTime-SI. Before looking at procedures for using the tool to nd SI problems,
however, be aware of the ideal approach: Run PTSI on a PT-clean design. In other words, address regular
timing violations before analyzing SI errors. Otherwise, regular timing violations may cause unnecessary
analysis in PTSI, and in some cases crosstalk noise may mask regular setup and hold violations.
In practice, it may not be meaningful to insist on distinguishing regular setup and hold violations from
those caused by SI issues. Timing violations have to be xed, whatever their source. The ECO process goes
back and forth with many handoffs, so it is sometimes impractical to treat regular and SI violations serially.
PTSI analyzes both timing errors and noise due to crosstalk as well as IR drop. It calculates noise bumps
based on the steady-state behavior of a victim driver rather than the victims switching behavior. The
primary set of parameters is the I/V curve data from the library model. (For more information, see the
library section later in this paper.) Although switching behavior is not included in noise analysis, the tool
uses methods such as arrival-window analysis and logical correlation to improve accuracy. User-dened
exclusion directives are also available. Bear in mind that the height of a noise bump is only part of the
equation. The bumps energy (determined by both height and width) actually determines the effect of the
noise on logic cells.
As for crosstalk-induced timing-error detection, a critical aspect of this work is correct settings in static
timing analysis (STA) and extraction. (Note that the parasitic ltering and electrical ltering that was
performed by PTSI has now been reduced to electrical ltering. This change has the effect of setting
parasitic ltering limits to zero, which has proven to work best in practice.) To apply electrical ltering with
PTSI and Star-RCXT, users specify values for the ltering, net reselection, and analysis exit criteria as
described below.
The ltering steps improve runtime performance by removing inuences that have a negligible impact
on timing, based on a set of threshold criteria. Electrical ltering removes some inconsequential noise
bumps, and the settings are based on the process technology and standard cell library. Note that using
the Synopsys Binary Parasitic Format (SBPF) rather than the ASCII spef signicantly reduces le size and
parasitics load times.
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SI Analysis Methodology
Due to the complexity of crosstalk delay analysis, static timing analysis must use an iterative process to
evaluate all of the possible timing relationships among all possible aggressors and victims. Aggressor nets
may be victims of other aggressors, for example. Because such an analysis would take far too long to cover
every possible combination of nets in a large design, a practical analysis focuses on victims that show a
substantial change due to crosstalk.
In the iterative crosstalk delay analysis, the rst iteration analyzes all nets without considering timing
windows. This iteration is thus the most pessimistic. Subsequent iterations reduce the pessimism by
considering the timing relationship between victims and aggressors. The net reselection criteria determine
which nets are analyzed in the next iteration. The exit criteria determine when the tool should stop rening
victim/aggressor timing relationships and end the analysis.
Nets retain their crosstalk delta delays from the iteration in which they were last evaluated. Since
reselection reduces analysis pessimism by rening victim/aggressor timing relationships, nets that pass
through more iterations have less pessimistic delay values. Analyzing more nets in more iterations can thus
reduce the number of nets that need to be xed, but analysis runtimes can become prohibitive.
PTSI provides several mechanisms for controlling net reselection. Specifying paths with negative slack
(slack _ mode _ reselection) ensures that all nets on violating timing paths are reselected for further
renement in the next iteration. This choice does not cover unconstrained but relevant nets such as clock
nets, but the latest version of PTSI has a command to reselect clock networks by setting si _ xtalk _
reselect _ clock _ network true. This command is useful because reselection based on a certain
amount of change in stage delay (delta _ delay _ reselection) can cover clock nets but also reselects
many non-critical nets.
PTSI also provides several mechanisms for controlling exit criteria. A simple approach is to specify a xed
number of iterations based on the following experiment. While analyzing one design block, track the net
reselection statistics to see when the number of reselected nets no longer declines signicantly. If that
point is at the third iteration (which is usually the case), set the exit criteria to three iterations for the other
blocks in the design.
Before accepting the static timing analysis (STA) results as the nal word about which nets need to be
xed, note that multiple endpoints that violate in STA may be caused by the crosstalk delay on a single
victim net. Using a script to lter the STA results can thus simplify timing closure. For each violating
endpoint, the script should identify all the nets whose crosstalk delta delays add up to the slack by which
the endpoint violates. Reducing the crosstalk delta delays for those nets to zero will eliminate the violation
of the endpoint. After processing all violating endpoints, the script must uniquify the identied nets and sort
them by frequency of occurrence on paths and crosstalk delta delay. It is then clear which nets actually
need to be xed.
A new technique that is useful in certain situations is path-based analysis, which is available in the
PrimeTime 2004.06 release. Without this approach, timing analysis uses worst-slew propagation to
calculate delay at each stage in a path, so the result at the output is the most pessimistic view. In contrast,
path-based analysis uses the actual slew at each stage in the path, so the resulting slack is more realistic.
Additionally, considering a single path eliminates the need to propagate arrival windows down the path.
Instead, the tool considers the SI effects of a single edge propagating down the path, thus reducing or
eliminating many crosstalk inuences that would fall within the arrival windows and contribute to worst-case
delay.
To run path-based analysis, it is necessary to obtain the worst setup path for the endpoint of interest,
recalculate the path using get _ recalculated _ timing _ paths, and store the resulting modied path
object back into a variable. The report _ timing command can then generate a list of the delay values for
the newly recalculated timing path. For example:
2007 Synopsys, Inc.
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set endpoint [get _ pins {valid _ reg/D}]
set path [get _ timing _ paths -to $endpoint]
set path [get _ recalculated _ timing _ paths $path]
report _ timing $path
This process is incomplete, however, because even if the worst path to the endpoint passes timing, it is still
possible for the next-worst path to fail. The analysis must expand to nd all the possible paths and evaluate
them. The analysis can then be applied to the entire design. (Please consult the following article for details
on this process: https://solvnet.synopsys.com/retrieve/012134.html.)
Because path-based analysis requires manual intervention and is much more compute intensive than
regular analysis, it might be more practical to apply the method only to paths that have difcult-to-x SI
problems. Removing some pessimism may reveal that a paths SI delay is not signicant after all and save a
great deal of unnecessary repair work.
Using ILMs to Decrease Run Times
Another methodology that may help simplify SI analysis in the Synopsys SI sub-ow is the use of Interface
Logic Models (ILMs). These models provide a way to reduce PTSI run times by eliminating some circuit
detail. ILMs are often used in hierarchical design to speed up STA. For more information about ILMs in this
application, please see the Synopsys Professional Services white paper Hierarchical Design Techniques
(http://www.synopsys.com/cgi-bin/sps/wp/hdt/paper1.cgi).
ILMs reduce the complexity of a logic block by modeling only the blocks input and output paths. For most
designs, this modeling dramatically decreases the amount of logic that must be timed at an ASICs top level
and thus reduces STA memory requirements and run times.
SI-aware ILMs enable full-chip SI sign-off by preserving the necessary aggressors on interface logic.
Figure 4 shows how nets that have signicant capacitive coupling are kept in an SI-aware ILM even when
they are not necessary for interface timing. The following PTSI command creates an SI-aware ILM for a
logic block:
create _ ilm include xtalk _ pins
Figure 4: Although Interface Logic Models (ILMs) usually preserve only the functionality and interface logic of a block, SI-aware
ILMs also include nets that are crosstalk victims or aggressors.
PTSI also needs arrival times and transitions to calculate crosstalk deltas correctly in the top-level STA. A
tcl script is written out with the ILM to back-annotate this information:
write _ arrival _ annotations
Coupling net inside block ILM with SI
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In the annotations le, the arrival windows are specied relative to a reference pin in the ILM that
automatically takes into account the clock latency when the ILM is instantiated at the top level. As usual,
the design has to be in on _ chip _ variation mode to allow the annotation of arrival windows:
set _ operating _ conditions -analysis _ type on _ chip _ variation
The instance names in the annotations le are written relative to ILM instance. To source the annotations
le at top level, change the current_instance accordingly:
set BlockList {block _ a block _ b block _ c}
foreach Block $BlockList {
set _ flename ./${Block}/ilm.pt.gz
foreach _ in _ coll _ inst [get _ cells * -flter ref _ name==$Block] {
set _ inst _ name [get _ att $ _ inst full _ name]
current _ instance $ _ inst _ name
source ${ _ flename}.gz
current _ instance
}
}
Additionally, link the top level with
link keep _ sub _ designs
Otherwise sub-designs are removed and pins in the current_instance cannot be found.
As with any ILMs, SI-aware ILMs must be validated before use. If a model does not meet timing tolerances,
the full block must be substituted in top-level STA.
The need to analyze the entire design at at the end of the process may limit the usefulness of SI-aware
ILMs for very large designs. Even for smaller designs, waiting until this nal at analysis to x the last SI
problems can be problematic. An alternative is to use the shielded hierarchical design approach described
earlier in this paper.
Post-Route SI Problem Fixing
As with all design methodologies, a primary goal of SI problem xing is to minimize the number of iterations
through the sub-ow. Three main steps are required for a complete iteration through this part of the ow:
parasitics extraction, static timing analysis and design changes intended to x problems. No matter how
well integrated these steps are, the full sub-ow is required to ensure that SI problems are xed. Note,
however, that incremental what-if modeling of xes in STA can save a great deal of time by showing that
a x will probably work. Iterating back through the sub-ow veries whether the x worked and whether it
caused other timing problems.
For automatic repair of SI problems at the sign-off stage, PTSI drives Astro with a constraints le that
identies nets on which PTSI has detected violations. The Astro router can x SI problems by spacing
nets further apart to minimize cross-coupling among nets for the higher-ranked victim and aggressor
pairs. Additional sign-off xing can be done using buffering solutions such as upsizing/downsizing drivers
and/or inserting buffers. It may be necessary to apply these techniques to a few nets manually, however,
due to the different requirements of the sign-off and implementation tasks. As a consequence of these
differences, Astro shares a common delay calculation with PTSI for analysis but requires a faster method
for incremental optimization.
An SI sign-off ow is therefore needed to address situations in which PTSI detects violations that Astro
does not see. Semi-automatic tcl scripts are available for running the following sign-off ow.
2007 Synopsys, Inc.
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First, PTSI provides incremental update capabilities for timing/SI issues to speed up the sign-off ow.
Specically, PTSIs SI bottleneck analysis (report _ si _ bottleneck) closely resembles its regular
timing bottleneck analysis. In the SI bottleneck analysis, PTSI reports the most problematic nets with
respect to both crosstalk delay and noise, thus simplifying the task of identifying which nets to x.
Further, what-if analysis in PTSI helps with problem resolution. Insert _ buffer and size _ cell
provide the ability to change the netlist, and subsequent write _ changes generates the change that was
tried in the pt _ shell. The additional command set _ coupling _ separation assumes the effect of
net spacing in PTSI.
After the use of these commands, PTSI generates a timing report that reects the changes. The results
can be taken into Astro to perform ECO placement and routing. Finally, Star-RCXT extraction provides the
nal parasitic data for the nal STA in PTSI.
If necessary, SI problems can also be xed manually. Spacing nets further apart is the least disturbing
method, but it may not work in highly congested areas (exactly the areas where crosstalk tends to occur
most). Even without PTSI modeling, experiments with the target technology can quickly show how much
delta delay can be xed. Double-spacing a net may correct 20 to 25 ps of delay at 130-nm, for example.
Upsizing drivers may be straightforward if it does not affect net spacing. Buffer insertion usually has a
greater impact on placement and is often needed. It may also be feasible to downsize the driver on the
aggressor net. Although this last method may cause other problems, it does work well for xing hold
violations.
Library Considerations
The right library characterizations are crucial to getting accurate results from PTSI. The characterizations
for SI work go beyond those needed for synthesis or regular STA because PTSI needs to create driver
models that are more sensitive to analog parameters. Important characterization factors include:
Characterization at 30 and 70 percent of the rail-swing points (at least) for 130-nm and under. Some
libraries are characterized at the 30/70 trip points but are then extrapolated to 10/90.
Indexes in nonlinear-delay look-up tables (e.g., cell and transition) should span the range of operation,
especially for IO libraries, and include a sufcient number of table entries. Inaccuracies occur when PTSI
has to extrapolate too far beyond the given range or interpolate too far between data points.
Libraries must enable the attribute that allows reports of delay calculations on library cells. Add this
attribute to the library source or have the library vendor do it.
To verify a design under typical/max process conditions, re-characterize libraries when only typ/typ
and max/max libraries are available. The alternative approach of timing derating introduces too many
inaccuracies.
Aside from these considerations, libraries can support the calculation of crosstalk delays with no more
than the dynamic switching resistance information already captured in the synthesis libraries. But for
calculations of crosstalk noise or IR drop delay, libraries need additional data.
Noise (glitch) analysis requires static resistance information on drivers, which is best captured using I/V
curves. Additionally, noise immunity curves allow the tool to determine whether a particular glitch will cause
a failure. These curves can be added to libraries in table or equation format. Finally, noise propagation
information allows the tool to determine whether a glitch will cause the wrong logic value to be latched at
a downstream register. The Liberty library format can capture all of this data in table format (non-linear
delay model, NLDM), equation format (scalable polynomial-delay model, SPDM) or a combination of both.
To support IR drop analysis for IR drop less than 5 to 10 percent of V
DD
, Liberty NLDM-based libraries
can use voltage k-factors. (Typical design rules limit IR drop to less than 10 percent of VDD throughout
the design.) When IR drop exceeds 10 percent of V
DD
, SPDMs can be used for higher accuracy. The delay
analysis also requires cell-specic IR drop data from a high-accuracy power rail analysis tool.

12
2007 Synopsys, Inc.
Staying Ahead of SI Problems
Signal integrity assurance is evolving rapidly as experience grows and more designs require SI-aware
timing closure to guarantee success. To take advantage of the best SI solutions, it is vital to keep up with
the latest methodologies and use the latest design ows. Shrinking process geometries mean that an
ever-increasing number of SI issues will require attention. The methodologies now in place for prevention,
detection, and repair furnish a good foundation from which to move forward with predictable signal
integrity closure.
Figure 5: Synopsys Galaxy SI sub-ow provides an integrated platform with comprehensive SI support at all stages of the
design ow, from implementation to sign-off. Common libraries, constraints, and database within Galaxy SI enable designers to
progressively eliminate problems as they move from design planning to placement
to routing and sign-off, resulting in faster SI closure.
About Synopsys Professional Services
Synopsys Professional Services provides a broad range of consulting and design services to chip
developers worldwide to help them achieve success in their design programs. These services address all
critical phases of the SoC development process and are tightly aligned with Synopsys EDA tools and IP
products to help customers accelerate their learning curves, develop and deploy advanced methodologies,
and achieve successful tape-outs. We offer customers a variety of engagement models to address their
project-specic and long-term design needs. For more information on Synopsys Professional Services visit
our website at www.synopsys.com/sps .
SI Closure
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700 East Middleeld Road, Mountain View, CA 94043 T 650 584 5000 www.synopsys.com
2007 Synopsys, Inc. Synopsys, the Synopsys logo, Design Compiler, Physical Compiler, VCS, PrimePower, and HSPICE are
registered trademarks and Power Compiler and Astro are trademarks of Synopsys, Inc. All other products or service names
mentioned herein are trademarks of their respective holders and should be treated as such.
Printed in the U.S. A. 03/07.CE.WO.07-15384
References
Hierarchical Integration and STA with ILMs Using PTSI
http://wwwin.synopsys.com/sps/docs/marketing/techpapers/7_snugeu03_hierarchical.pdf
SNUG Europe 2003
Cole OBerry, John Pedicone, Synopsys Professional Services
Greg Guiher, Northrup Grumman
An Application of Crosstalk Prevention and Analysis to the Design of a Deep Sub-micron ASIC
http://wwwin.synopsys.com/sps/docs/marketing/techpapers/11_designcon03_crosstalk.pdf
DesignCon 2003
Kwamina Ewusie, Richard Nouri, Bill Sicaras, Synopsys Professional Services
PTSI Methodology and Results for Hierarchical 2M Gate ASIC
http://wwwin.synopsys.com/sps/docs/marketing/techpapers/2_snugeu03_hierarchical-cs.pdf
SNUG Europe 2003
Devaloy Muniz, John Pedicone, Synopsys Professional Services
Greg Guiher, Northrop Grumman