GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 64

UNIT 4
ANALOG CIRCUITS

2013
4.1

ONE MARK

In the circuit shown below what is the output voltage ^Vouth if a

silicon transistor Q and an ideal op-amp are used?
4.4

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(A)  15 V
(C)  0.7 V
4.2

(B)  0.7 V
(D)  15 V

4.5

In a voltage-voltage feedback as shown below, which one of the

following statements is TRUE if the gain k is increased?

(A) The input

es
(B) The input
increases
(C) The input
decreases
(D) The input
es

4.3

(B) 125 and 250

(C) 250 and 125

(D) 250 and 250

The ac schematic of an NMOS common-source state is shown in the

figure below, where part of the biasing circuits has been omitted for
simplicity. For the n -channel MOSFET M, the transconductance
gm  1 mA/V , and body effect and channel length modulation effect
are to be neglected. The lower cutoff frequency in HZ of the circuit
is approximately at

(A) 8

(B) 32

(C) 50

(D) 200

In the circuit shown below the op-amps are ideal. Then, Vout in Volts
is

impedance increases and output impedance decreas-

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impedance increases and output impedance also

impedance decreases and output impedance also

(A) 4
(C) 8

impedance decreases and output impedance increas4.6

2013

(A) 125 and 125

TWO MARKS

In the circuit shown below, the knee current of the ideal Zener
dioide is 10 mA. To maintain 5 V across RL , the minimum value of
RL in 8 and the minimum power rating of the Zener diode in mW
, respectively, are

(B) 6
(D) 10

In the circuit shown below, Q1 has negligible collector-to-emitter

saturation voltage and the diode drops negligible voltage across it
under forward bias. If Vcc is  5 V , X and Y are digital signals with
0 V as logic 0 and Vcc as logic 1, then the Boolean expression for Z is

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 65

The current in the circuit is

(A) 10 mA
(C) 6.67 mA
(A) XY
(C) XY
4.7

(B) XY
(D) XY

4.11

The diodes and capacitors in the circuit shown are ideal. The voltage
v (t) across the diode D1 is

A voltage 1000 sin Xt Volts is applied across YZ . Assuming ideal

diodes, the voltage measured across WX in Volts, is

(A) cos (Xt)  1

(A) sin Xt
(C) ^sin Xt  sin Xt h /2
4.8

(B) _sin Xt  sin Xt i /2

(D) 0 for all t

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In the circuit shown below, the silicon npn transistor Q has a

very high value of C . The required value of R2 in k8 to produce
IC  1 mA is

(A) 20

(B) 30

(C) 40

(D) 50

2012

(B) sin (Xt)

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(C) 1  cos (Xt)

4.12

4.9

(B) 9.3 mA
(D) 6.2 mA

The impedance looking into nodes 1 and 2 in the given circuit is

(A) 50 8
(C) 5 k8

(B) 100 8
(D) 10.1 k8

2012

ONE MARK

The current ib through the base of a silicon npn transistor is

1  0.1 cos (10000Qt) mA At 300 K, the rQ in the small signal model
of the transistor is

(D) 1  sin (Xt)

4.13

The circuit shown is a

1
rad/s
(R1  R2) C
(B) high pass filter with f3dB  1 rad/s
R1 C
(C) low pass filter with f3dB  1 rad/s
R1 C
1
(D) high pass filter with f3dB 
rad/s
(R1  R2) C
(A) low pass filter with f3dB 

(A) 250 8
(C) 25 8
4.10

(B) 27.5 8
(D) 22.5 8

The i -v characteristics of the diode in the circuit given below are

v  0.7 A, v $ 0.7 V
i  * 500
0A
v  0. 7 V

4.14

The voltage gain Av of the circuit shown below is

TWO MARKS

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 66

and the threshold voltage VT  1 V . The voltage Vx at the source of

the upper transistor is

(A) Av . 200
(C) Av . 20

(B) Av . 100
(D) Av . 10

(A) 1 V
(C) 3 V
4.18

2011
4.15

ONE MARK

In the circuit shown below, capacitors C1 and C2 are very large and
are shorts at the input frequency. vi is a small signal input. The gain
magnitude vo at 10 M rad/s is
vi

(B) 2 V
(D) 3.67 V

For the BJT,

in the circuit shown below,
Q1
C  3, VBEon  0.7 V, VCEsat  0.7 V . The switch is initially closed.
At time t  0 , the switch is opened. The time t at which Q1 leaves
the active region is

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(A) 10 ms
(C) 50 ms
4.19

(B) 25 ms
(D) 100 ms

For a BJT, the common base current gain B  0.98 and the collector
base junction reverse bias saturation current ICO  0.6 NA . This
BJT is connected in the common emitter mode and operated in the
active region with a base drive current IB  20 NA . The collector
current IC for this mode of operation is
(A) 0.98 mA
(B) 0.99 mA
(C) 1.0 mA
(D) 1.01 mA

Statement for Linked Answer Questions: 4.6 & 4.7

(A) maximum
(C) unity
4.16

The circuit below implements a filter between the input current ii

and the output voltage vo . Assume that the op-amp is ideal. The
filter implemented is a

(A) low pass filter

(C) band stop filter
2011
4.17

(B) minimum
(D) zero

(B) band pass filter

(D) high pass filter
TWO MARKS

In the circuit shown below, for the MOS transistors, Nn Cox  100 NA/V 2

In the circuit shown below, assume that the voltage drop

across a forward biased diode is 0.7 V. The thermal voltage
Vt  kT/q  25 mV . The small signal input vi  Vp cos ^Xt h where
Vp  100 mV.

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GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

4.20

4.21

The bias current IDC through the diodes is

(A) 1 mA
(B) 1.28 mA

2010

(C) 1.5 mA

(D) 2 mA

Common Data For Q. 4.11 & 4.12 :

The ac output voltage vac is

(A) 0.25 cos ^Xt h mV
(C) 2 cos (Xt) mV

(B) 1 cos (Xt) mV

(D) 22 cos (Xt) mV

Consider the common emitter amplifier shown below with the following circuit parameters:
C  100, gm  0.3861 A/V, r0  259 8, RS  1 k8, RB  93 k8,
RC  250 k8, RL  1 k8, C1  3 and C2  4.7 NF

2010
4.22

Page 67

TWO MARKS

ONE MARK

The amplifier circuit shown below uses a silicon transistor. The

capacitors CC and CE can be assumed to be short at signal frequency
and effect of output resistance r0 can be ignored. If CE is disconnected
from the circuit, which one of the following statements is true

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(A) The input resistance Ri increases and magnitude of voltage

gainAV decreases
(B) The input resistance Ri decreases and magnitude of voltage
gain AV increases
(C) Both input resistance Ri and magnitude of voltage gain AV
decreases

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4.25

4.26

(D) Both input resistance Ri and the magnitude of voltage gain

AV increases
4.23

In the silicon BJT circuit shown below, assume that the emitter
area of transistor Q1 is half that of transistor Q2

The value of current Io is approximately

(A) 0.5 mA
(B) 2 mA
(C) 9.3 mA
(D) 15 mA
4.24

Assuming the OP-AMP to be ideal, the voltage gain of the amplifier

shown below is

(A)  R2
R1
R2 || R 3
(C) 
R1

(B)  R 3
R1
(D) b R2  R 3 l
R1

4.27

The resistance seen by the source vS is

(A) 258 8
(B) 1258 8
(C) 93 k8
(D) 3
The lower cut-off frequency due to C2 is
(A) 33.9 Hz
(B) 27.1 Hz
(C) 13.6 Hz
(D) 16.9 Hz
The transfer characteristic for the precision rectifier circuit shown
below is (assume ideal OP-AMP and practical diodes)

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

2009
4.28

TWO MARKS

Page 68

4.30

In the circuit below, the diode is ideal. The voltage V is given by

For small increase in VG beyond 1V, which of the following gives the
correct description of the region of operation of each MOSFET
(A) Both the MOSFETs are in saturation region
(B) Both the MOSFETs are in triode region
(C) n-MOSFETs is in triode and p MOSFET is in saturation
region
(D) n- MOSFET is in saturation and p MOSFET is in triode
region

(A) min (Vi, 1)

(C) min ( Vi, 1)
4.29

(B) max (Vi, 1)

(D) max ( Vi, 1)

4.31

In the following a stable multivibrator circuit, which properties of

v0 (t) depend on R2 ?

4.32

Estimate the output voltage V0 for VG  1.5 V. [Hints : Use the

appropriate current-voltage equation for each MOSFET, based on
the answer to Q.4.16]
(B) 4  1
(A) 4  1
2
2
3
(C) 4 
(D) 4  3
2
2
In the circuit shown below, the op-amp is ideal, the transistor has
VBE  0.6 V and C  150 . Decide whether the feedback in the circuit
is positive or negative and determine the voltage V at the output of
the op-amp.

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(A) Positive feedback, V  10 V
(B) Positive feedback, V  0 V
(C) Negative feedback, V  5 V
(D) Negative feedback, V  2 V
4.33

A small signal source Vi (t)  A cos 20t  B sin 106 t is applied to a

transistor amplifier as shown below. The transistor has C  150 and
hie  38 . Which expression best approximate V0 (t)

(A) Only the frequency

(B) Only the amplitude
(C) Both the amplitude and the frequency
(D) Neither the amplitude nor the frequency

Statement for Linked Answer Question 4.16 and 4.17

Consider for CMOS circuit shown, where the gate voltage v0 of
the n-MOSFET is increased from zero, while the gate voltage of
the p MOSFET is kept constant at 3 V. Assume, that, for both
transistors, the magnitude of the threshold voltage is 1 V and the
product of the trans-conductance parameter is 1mA. V - 2

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GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 69

4.37

(A) 0 V

(B) 0.1 V

(C) 0.7 V

(D) 1.1 V

The OPAMP circuit shown above represents a

(A) V0 (t)  1500 (A cos 20t  B sin 106 t)

(B) V0 (t) =  1500( A cos 20t + B sin 106 t)
(C) V0 (t)  1500B sin 106 t
(D) V0 (t)  150B sin 106 t
2008
4.34

ONE MARK

In the following limiter circuit, an input voltage Vi  10 sin 100Qt

is applied. Assume that the diode drop is 0.7 V when it is forward
biased. When it is forward biased. The zener breakdown voltage is
6.8 V
The maximum and minimum values of the output voltage respectively are

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(A) 6.1 V,  0.7 V

(C) 7.5 V,  0.7 V
2008
4.35

(B) 0.7 V,  7.5 V

(D) 7.5 V,  7.5 V

4.38

TWO MARSK

(B) low pass filter

(C) band pass filter

(D) band reject filter

Two identical NMOS transistors M1 and M2 are connected as shown

below. Vbias is chosen so that both transistors are in saturation. The
equivalent gm of the pair is defied to be 2Iout at constant Vout
2Vi
The equivalent gm of the pair is

For the circuit shown in the following figure, transistor M1 and M2

are identical NMOS transistors. Assume the M2 is in saturation and
the output is unloaded.

4.39

4.36

(A) high pass filter

The current Ix is related to Ibias as

(B) Ix  Ibias
(A) Ix  Ibias  Is
(D) Ix  Ibias  Is
(C) Ix  Ibias  cVDD  Vout m
RE
Consider the following circuit using an ideal OPAMP. The I-V
V
characteristic of the diode is described by the relation I  I 0 _eV  1i
where VT  25 mV, I0  1N A and V is the voltage across the diode
(taken as positive for forward bias). For an input voltage Vi  1 V
, the output voltage V0 is
t

(A) the sum of individual gm ' s of the transistors

(B) the product of individual gm s of the transistors
(C) nearly equal to the gm of M1
g
(D) nearly equal to m of M2
g0
Consider the Schmidt trigger circuit shown below
A triangular wave which goes from -12 to 12 V is applied to the
inverting input of OPMAP. Assume that the output of the OPAMP swings from +15 V to -15 V. The voltage at the non-inverting
input switches between

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

(A)  12V to +12 V

(C) -5 V to +5 V

Page 70

(B) -7.5 V to 7.5 V

(D) 0 V and 5 V

Statement for Linked Answer Question 3.26 and 3.27:

In the following transistor circuit, VBE  0.7 V, r3  25 mV/IE , and
C and all the capacitances are very large
(A) -2 V
(C) -0.5 V
4.45

4.40

The value of DC current IE is

(A) 1 mA
(C) 5 mA

(B) 2 mA
(D) 10 mA

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4.41

4.43

(A) cut-off

(B) saturation

(C) normal active

(D) reverse active

In the Op-Amp circuit shown, assume that the diode current

follows the equation I  Is exp (V/VT ). For Vi  2V, V0  V01, and for
Vi  4V, V0  V02 .
The relationship between V01 and V02 is

(A) V02  2 Vo1

(C) Vo2 = Vo1 1n2

ONE MARK

The correct full wave rectifier circuit is

4.47

(B) Vo2  e2 Vo1

(D) Vo1  Vo2 = VT 1n2

In the CMOS inverter circuit shown, if the trans conductance

parameters of the NMOS and PMOS transistors are
W
kn  kp  Nn Cox Wn  NCox p  40NA/V2
Ln
Lp
and their threshold voltages ae VTHn  VTHp  1 V the current I is

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In a transconductance amplifier, it is desirable to have

(A) a large input resistance and a large output resistance
(B) a large input resistance and a small output resistance
(C) a small input resistance and a large output resistance
(D) a small input resistance and a small output resistance
2007

4.44

For the BJT circuit shown, assume that the C of the transistor is
very large and VBE  0.7 V. The mode of operation of the BJT is

The mid-band voltage gain of the amplifier is approximately

(A) -180
(B) -120
(C) -90
(D) -60
2007

4.42

4.46

(B) -1 V
(D) 0.5 V

TWO MARKS

For the Op-Amp circuit shown in the figure, V0 is

(A) 0 A
(C) 45 NA
4.48

(B) 25 NA
(D) 90 NA

For the Zener diode shown in the figure, the Zener voltage at knee is
7 V, the knee current is negligible and the Zener dynamic resistance

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 71

is 10 8. If the input voltage (Vi) range is from 10 to 16 V, the output

voltage (V0) ranges from
4.54

(A) 7.00 to 7.29 V

(B) 7.14 to 7.29 V

(C) 7.14 to 7.43 V

(D) 7.29 to 7.43 V

(A) 0 Volt

(B) 6.3 Volt

(C) 9.45 Volts

(D) 10 Volts

For the circuit shown below, assume that the zener diode is ideal
with a breakdown voltage of 6 volts. The waveform observed across
R is

Statement for Linked Answer Questions 4.35 & 4.36:

Consider the Op-Amp circuit shown in the figure.

4.49

4.50

The transfer function V0 (s)/ Vi (s) is

(B) 1  sRC
(A) 1  sRC
1  sRC
1  sRC
1
1
(C)
(D)
1  sRC
1  sRC

4.52

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ONE MARK

The input impedance (Zi) and the output impedance (Z0) of an ideal
trans-conductance (voltage controlled current source) amplifier are
(B) Zi  0, Z0  3
(A) Zi  0, Z0  0
(C) Zi  3, Z0  0
(D) Zi  3, Z0  3
An n-channel depletion MOSFET has following two points on its
ID  VGs curve:
(i) VGS  0 at ID  12 mA and
(ii) VGS  6 Volts at ID  0 mA
Which of the following Q point will given the highest trans conductance gain for small signals?
(B) VGS  3 Volts
(A) VGS  6 Volts
(C) VGS  0 Volts
(D) VGS  3 Volts
2006

4.53

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If Vi  V1 sin (Xt) and V0  V2 sin (Xt  G), then the minimum and
maximum values of G (in radians) are respectively
(B) 0 and Q
(A)  Q and Q
2
2
2
(C)  Q and 0
(D)  Q and 0
2
2006

4.51

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TWO MARKS

For the circuit shown in the following figure, the capacitor C is

initially uncharged. At t  0 the switch S is closed. The Vc across
the capacitor at t  1 millisecond is
In the figure shown above, the OP-AMP is supplied with ! 15V .

Common Data For Q. 4.41, 4.42 and 4.43 :

In the transistor amplifier circuit shown in the figure below, the
transistor has the following parameters:
CDC  60 , VBE  0.7V, hie 3
The capacitance CC can be assumed to be infinite.
In the figure above, the ground has been shown by the symbol 4

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

4.55

Under the DC conditions, the collector-or-emitter voltage drop is

(A) 4.8 Volts
(B) 5.3 Volts
(C) 6.0 Volts

4.56

Page 72

(D) 6.6 Volts

4.61

If CDC is increased by 10%, the collector-to-emitter voltage drop

(A) increases by less than or equal to 10%

(C) 40 k8

(D) infinite

The effect of current shunt feedback in an amplifier is to

(A) increase the input resistance and decrease the output resistance

(D) decrease the input resistance and increase the output resistance

(D) decreases by more than 10%

The small-signal gain of the amplifier vc is
vs

4.62

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(A) -10
(C) 5.3

(B) 10 k8

(B) increases both input and output resistance

(C) decrease both input and output resistance

(B) decreases by less than or equal to 10%

(C) increase by more than 10%

4.57

(A) 30 k8
4

2005
4.63

(B) -5.3
(D) 10
4.64

Common Data For Q. 4.44 & 4.45:

The cascade amplifier is a multistage configuration of

(A) CC  CB
(B) CE  CB
(C) CB  CC
(D) CE  CC

A regulated power supply, shown in figure below, has an unregulated input (UR) of 15 Volts and generates a regulated output Vout .
Use the component values shown in the figure.

In an ideal differential amplifier shown in the figure, a large value

of (RE ).
(A) increase both the differential and common - mode gains.
(B) increases the common mode gain only.
(C) decreases the differential mode gain only.
(D) decreases the common mode gain only.
For an npn transistor connected as shown in figure VBE  0.7 volts.
Given that reverse saturation current of the junction at room
temperature 300 K is 10 - 13 A, the emitter current is

(A) 30 mA
(C) 49 mA
4.65

4.58

4.59

The power dissipation across the transistor Q1 shown in the figure is

(A) 4.8 Watts
(B) 5.0 Watts
(C) 5.4 Watts
(D) 6.0 Watts

(B) 39 mA
(D) 20 mA

The voltage e0 is indicated in the figure has been measured by an

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ideal voltmeter. Which of the following can be calculated ?

If the unregulated voltage increases by 20%, the power dissipation

across the transistor Q1
(A) increases by 20%
(B) increases by 50%
(C) remains unchanged
(D) decreases by 20%
2005

4.60

TWO MARKS

ONE MARK

The input resistance Ri of the amplifier shown in the figure is

(A) Bias current of the inverting input only
(B) Bias current of the inverting and non-inverting inputs only

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 73

(C) Input offset current only

(D) Both the bias currents and the input offset current
4.66

The Op-amp circuit shown in the figure is filter. The type of filter
and its cut. Off frequency are respectively

4.70

(A) high pass, 1000 rad/sec.

(C) high pass, 1000 rad/sec
4.67

(B) Low pass, 1000 rad/sec

(D) low pass, 10000 rad/sec

The circuit using a BJT with C  50 and VBE  0.7V is shown in

the figure. The base current IB and collector voltage by VC and
respectively

4.71

Zi and Z0 of the circuit are respectively

(B) 2 M8 and 20 k8
(A) 2 M8 and 2 k8
11
(C) infinity and 2 M8
(D) infinity and 20 k8
11
ID and VDS under DC conditions are respectively
(A) 5.625 mA and 8.75 V
(B) 1.875 mA and 5.00 V
(C) 4.500 mA and 11.00 V
(D) 6.250 mA and 7.50 V

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(A) 43 NA and 11.4 Volts

(C) 45 NA and 11 Volts
4.68

The Zener diode in the regulator circuit shown in the figure has a
Zener voltage of 5.8 volts and a zener knee current of 0.5 mA. The
maximum load current drawn from this current ensuring proper
functioning over the input voltage range between 20 and 30 volts, is

(A) 23.7 mA
(C) 13.7 mA
4.69

(B) 40 NA and 16 Volts

(D) 50 NA and 10 Volts

(B) 14.2 mA
(D) 24.2 mA

Both transistors T1 and T2 show in the figure, have a C  100 ,

threshold voltage of 1 Volts. The device parameters K1 and K2 of
T1 and T2 are, respectively, 36 NA/V2 and 9 NA/V 2 . The output
voltage Vo i s

(A) 1 V
(C) 3 V

(B) 2 V
(D) 4 V

Common Data For Q. 4.58, 4.59 and 4.60 :

Given, rd  20k8 , IDSS  10 mA, Vp  8 V

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4.72

Transconductance in milli-Siemens (mS) and voltage gain of the

amplifier are respectively
(A) 1.875 mS and 3.41
(B) 1.875 ms and -3.41
(C) 3.3 mS and -6

4.73

(D) 3.3 mS and 6

Given the ideal operational amplifier circuit shown in the figure

indicate the correct transfer characteristics assuming ideal diodes
with zero cut-in voltage.

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

2004
4.74

Page 74

ONE MARK

An ideal op-amp is an ideal

(A) voltage controlled current source
(B) voltage controlled voltage source
(C) current controlled current source
(D) current controlled voltage source

4.75

Voltage series feedback (also called series-shunt feedback) results in

(A) increase in both input and output impedances
(B) decrease in both input and output impedances

(A) 1 NF
2Q
1
NF
(C)
2Q 6

(C) increase in input impedance and decrease in output impedance

(D) decrease in input impedance and increase in output impedance
4.76

The circuit in the figure is a

4.79

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(A) low-pass filter

(B) high-pass filter

(C) band-pass filter

(D) band-reject filter

2004
4.77

4.78

4.81

TWO MARKS

A bipolar transistor is operating in the active region with a collector

current of 1 mA. Assuming that the C of the transistor is 100 and
the thermal voltage (VT ) is 25 mV, the transconductance (gm) and
the input resistance (rQ) of the transistor in the common emitter
configuration, are
(A) gm  25 mA/V and rQ  15.625 k8
(B) gm  40 mA/V and rQ  4.0 k8
(C) gm  25 mA/V and rQ  2.5 k 8
(D) gm  40 mA/V and rQ  2.5 k8
The value of C required for sinusoidal oscillations of frequency 1
kHz in the circuit of the figure is

(D) 2Q 6 NF

In the op-amp circuit given in the figure, the load current iL is

(A)  Vs
R2
(C)  Vs
RL
4.80

(B) 2Q NF

(B) Vs
R2
(D) Vs
R1

In the voltage regulator shown in the figure, the load current can
vary from 100 mA to 500 mA. Assuming that the Zener diode is ideal
(i.e., the Zener knee current is negligibly small and Zener resistance
is zero in the breakdown region), the value of R is

(A) 7 8
(B) 70 8
70
(D) 14 8
(C)
8
3
In a full-wave rectifier using two ideal diodes, Vdc and Vm are the dc
and peak values of the voltage respectively across a resistive load. If
PIV is the peak inverse voltage of the diode, then the appropriate

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4.82

relationships for this rectifier are

(A) Vdc  Vm , PIV  2Vm
(B) Idc  2 Vm , PIV  2Vm
Q
Q
V
V
m
m
(C) Vdc  2 , PIV  Vm
(D) Vdc , PIV  Vm
Q
Q
Assume that the C of transistor is extremely large and VBE  0.7V, IC
and VCE in the circuit shown in the figure

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 75

resistance of the current-shunt negative feedback amplifier using the

above amplifier with a feedback factor of 0.2, is
(B) 1 k8
(A) 1 k8
5
11
(C) 5 k8
4.89

(A) IC  1 mA, VCE  4.7 V

(C) IC  1 mA, VCE  2.5 V

(B) IC  0.5 mA, VCE  3.75 V

(D) IC  0.5 mA, VCE  3.9 V

2003
4.83

4.84

In the amplifier circuit shown in the figure, the values of R1 and R2

are such that the transistor is operating at VCE  3 V and IC  1.5
mA when its C is 150. For a transistor with C of 200, the operating
point (VCE , IC ) is

ONE MARK

Choose the correct match for input resistance of various amplifier

configurations shown below :
Configuration
Input resistance
CB : Common Base
LO : Low
CC : Common Collector
MO : Moderate
CE : Common Emitter
HI : High
(A) CB  LO, CC  MO, CE  HI
(B) CB  LO, CC  HI, CE  MO
(C) CB  MO, CC  HI, CE  LO
(D) CB  HI, CC  LO, CE  MO

(A) (2 V, 2 mA)

(B) (3 V, 2 mA)

(C) (4 V, 2 mA)

(D) (4 V, 1 mA)

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The circuit shown in the figure is best described as a

4.90

(A) bridge rectifier

(C) frequency discriminator
4.85

The oscillator circuit shown in the figure has an ideal inverting

amplifier. Its frequency of oscillation (in Hz) is

(B) ring modulator

(D) voltage double

If the input to the ideal comparators shown in the figure is a

sinusoidal signal of 8 V (peak to peak) without any DC component,
then the output of the comparators has a duty cycle of
1
(2Q 6 RC)
1
(C)
( 6 RC)
(A)
(A) 1/2
(C) 1/6

4.86

4.87

(B) 1/3
(D) 1/2

4.91

If the differential voltage gain and the common mode voltage gain
of a differential amplifier are 48 dB and 2 dB respectively, then
common mode rejection ratio is
(A) 23 dB
(B) 25 dB
(C) 46 dB
(D) 50 dB
Generally, the gain of a transistor amplifier falls at high frequencies
due to the
(A) internal capacitances of the device
(B) coupling capacitor at the input
(C) skin effect
(D) coupling capacitor at the output
2003

TWO MARKS

An amplifier without feedback has a voltage gain of 50, input

resistance of 1 k 8 and output resistance of 2.5 k8. The input

(B)

1
(2QRC)

(D)

6
(2QRC)

The output voltage of the regulated power supply shown in the

figure is

(A) 3 V
(C) 9 V
4.92

4.88

(D) 11 k8

(B) 6 V
(D) 12 V

If the op-amp in the figure is ideal, the output voltage Vout will be
equal to

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

(A) 1 V
(C) 14 V
4.93

(B) 6 V
(D) 17 V

Three identical amplifiers with each one having a voltage gain of 50,
input resistance of 1 k8 and output resistance of 250 8 are cascaded.
The opened circuit voltages gain of the combined amplifier is
(A) 49 dB
(B) 51 dB
(C) 98 dB

4.94

Page 76

(D) 102 dB

An ideal sawtooth voltages waveform of frequency of 500 Hz and

amplitude 3 V is generated by charging a capacitor of 2 NF in every
cycle. The charging requires
(A) Constant voltage source of 3 V for 1 ms

2002
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(B) Constant voltage source of 3 V for 2 ms
(C) Constant voltage source of 1 mA for 1 ms
(D) Constant voltage source of 3 mA for 2 ms
2002
4.95

In a negative feedback amplifier using voltage-series (i.e. voltagesampling, series mixing) feedback.
(A) Ri decreases and R0 decreases
(B) Ri decreases and R0 increases
(C) Ri increases and R0 decreases
(D) Ri increases and R0 increases
(Ri and R0 denote the input and output resistance respectively)

4.96

4.97

The circuit in the figure employs positive feedback and is

intended to generate sinusoidal oscillation. If at a frequency
V (f) 1
 +0c, then to sustain oscillation at this frequency
f0, B (f)  3 f
V0 (f)
6

(A) R2  5R1
(C) R2  R1
6

ONE MARK
4.99

A 741-type opamp has a gain-bandwidth product of 1 MHz. A noninverting amplifier suing this opamp and having a voltage gain of 20
dB will exhibit a -3 dB bandwidth of
(A) 50 kHz
(B) 100 kHz
1000
kHz
(D) 1000 kHz
(C)
7.07
17
Three identical RC-coupled transistor amplifiers are cascaded. If
each of the amplifiers has a frequency response as shown in the
figure, the overall frequency response is as given in

(B) R2  6R1
(D) R2  R1
5

An amplifier using an opamp with a slew-rate SR  1 V/N sec has

a gain of 40 dB. If this amplifier has to faithfully amplify sinusoidal
signals from dc to 20 kHz without introducing any slew-rate induced
distortion, then the input signal level must not exceed.
(A) 795 mV
(B) 395 mV
(C) 79.5 mV

4.100

TWO MARKS

(D) 39.5 mV

A zener diode regulator in the figure is to be designed to meet the

specifications: IL  10 mA V0  10 V and Vin varies from 30 V to 50
V. The zener diode has Vz  10 V and Izk (knee current) =1 mA. For

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satisfactory operation

(A) R # 18008
(C) 37008 # R # 40008
4.101

(B) 20008 # R # 22008

(D) R $ 40008

The voltage gain Av  v0 of the JFET amplifier shown in the figure

vt
is IDSS  10 mA Vp  5 V(Assume C1, C2 and Cs to be very large

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 77

(D) Pz  115 mW, PT  11.9 W

4.107

(A) +16

(B) -16

(C) +8

(D) -6

2001
4.102

(C) gm rQ
4.103

4.104

gm
r
gm
(D)
rQ

(B)

4.108

Thee ideal OP-AMP has the following characteristics.

(B) Ri  0, A  3, R0  0
(A) Ri  3, A  3, R0  0
(C) Ri  3, A  3, R0  3
(D) Ri  0, A  3, R0  3

4.106

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of 100.

TWO MARKS

An npn BJT has gm  38 mA/V, C N  10

F, C Q  4 # 1013 F,
and DC current gain C0  90 . For this transistor fT and fC are
(A) fT  1.64 # 108 Hz and fC  1.47 # 1010 Hz
(B) fT  1.47 # 1010 Hz and fC  1.64 # 108 Hz
(C) fT  1.33 # 1012 Hz and fC  1.47 # 1010 Hz
(D) fT  1.47 # 1010 Hz and fC  1.33 # 1012 Hz

The inverting OP-AMP shown in the figure has an open-loop gain

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binding form. Each unit of Book is in separate binding.

Consider the following two statements :

Statement 1 :
A stable multi vibrator can be used for generating square wave.
Statement 2:
Bistable multi vibrator can be used for storing binary information.
(A) Only statement 1 is correct
(B) Only statement 2 is correct
(C) Both the statements 1 and 2 are correct
(D) Both the statements 1 and 2 are incorrect
2001

4.105

(A) Hartely oscillator with foscillation  79.6 MHz

(B) Colpitts oscillator with foscillation  50.3 MHz
(C) Hartley oscillator with foscillation  159.2 MHz
(D) Colpitts oscillator with foscillation  159.3 MHz

ONE MARK

The current gain of a BJT is

(A) gm r0

The oscillator circuit shown in the figure is

The closed-loop gain V0 is

Vs
(A)  8
(C)  10

14

4.109

The transistor shunt regulator shown in the figure has a regulated

output voltage of 10 V, when the input varies from 20 V to 30 V.
The relevant parameters for the zener diode and the transistor are
: Vz  9.5 , VBE  0.3 V, C  99 , Neglect the current through RB .
Then the maximum power dissipated in the zener diode (Pz ) and the
transistor (PT ) are

In the figure assume the OP-AMPs to be ideal. The output v0 of

the circuit is

(A) 10 cos (100t)

t

(C) 10 - 4
2000
4.110

(A) Pz  75 mW, PT  7.9 W

(B) Pz  85 mW, PT  8.9 W
(C) Pz  95 mW, PT  9.9 W

(B)  9
(D)  11

cos (100U) dU

(B) 10

cos (100U) dU

(D) 10 - 4 d cos (100t)

dt
ONE MARK

In the differential amplifier of the figure, if the source resistance of

the current source IEE is infinite, then the common-mode gain is

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

(A) zero
(C) indeterminate
4.111

4.113

4.114

(A) precision integrator

(B) infinite
(D) Vin1  Vin2
2VT

(A) -1 V

(B) 2 V

(C) +1 V

(D) +15 V

Introducing a resistor in the emitter of a common amplifier stabilizes

the dc operating point against variations in
(A) only the temperature
(B) only the C of the transistor
(D) none of the above
(C) both temperature and C
The current gain of a bipolar transistor drops at high frequencies
because of
(A) transistor capacitances
(B) high current effects in the base
(C) parasitic inductive elements
(D) the Early effect

(B) Hartely oscillator

(C) Butterworth high pass filter (D) Wien-bridge oscillator

4.116

In the circuit of the figure, V0 is

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4.112

Page 78

Assume that the op-amp of the figure is ideal. If vi is a triangular

wave, then v0 will be

(A) square wave

(C) parabolic wave
4.117

(B) triangular wave

(D) sine wave

The most commonly used amplifier is sample and hold circuits is

(A) a unity gain inverting amplifier
(B) a unity gain non-inverting amplifier
(C) an inverting amplifier with a gain of 10
(D) an inverting amplifier with a gain of 100
2000

4.118

TWO MARKS

In the circuit of figure, assume that the transistor is in the active

region. It has a large C and its base-emitter voltage is 0.7 V. The
value of Ic is

If the op-amp in the figure, is ideal, then v0 is

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(A) zero
(C)  (V1  V2) sin Xt
4.115

(B) (V1  V2) sin Xt

(D) (V1  V2) sin Xt

The configuration of the figure is a

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 79

4.125

A dc power supply has a no-load voltage of 30 V, and a full-load

voltage of 25 V at a full-load current of 1 A. Its output resistance
and load regulation, respectively, are
(A) 5 8 and 20%
(B) 25 8 and 20%
(C) 5 8 and 16.7%
(D) 25 8 and 16.7%
1998

4.126

(A) Indeterminate since Rc is not given (B) 1 mA

(C) 5 mA
(D) 10 mA
4.119

4.122

4.123

Negative feedback in an amplifier

(A) reduces gain
(B) increases frequency and phase distortions
(C) reduces bandwidth
(D) increases noise

(D) voltage shunt

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4.127

4.128

In the cascade amplifier shown in the given figure, if the commonemitter stage (Q1) has a transconductance gm1 , and the common
base stage (Q2) has a transconductance gm2 , then the overall
transconductance g ( i 0 /vi) of the cascade amplifier is

(B) gm2
g
(D) m2
2

4.129

4.130

Crossover distortion behavior is characteristic of

(A) Class A output stage
(B) Class B output stage
(C) Class AB output stage
(D) Common-base output stage
1999

4.124

(B) current shunt

(C) voltage series

ONE MARK

The first dominant pole encountered in the frequency response of a

compensated op-amp is approximately at
(A) 5 Hz
(B) 10 kHz
(C) 1 MHz
(D) 100 MHz

(A) gm1
g
(C) m1
2

(A) current series

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(B) 5 mV
(D) +50 V or -50 V

1999

4.121

The circuit of the figure is an example of feedback of the following

type

If the op-amp in the figure has an input offset voltage of 5 mV and

an open-loop voltage gain of 10000, then v0 will be

(A) 0 V
(C) + 15 V or -15 V

4.120

ONE MARK

From a measurement of the rise time of the output pulse of an

amplifier whose is a small amplitude square wave, one can estimate
the following parameter of the amplifier
(A) gain-bandwidth product
(B) slow rate
(C) upper 3dB frequency
(D) lower 3dB frequency
The emitter coupled pair of BJTs given a linear transfer relation
between the differential output voltage and the differential output
voltage and the differential input voltage Vid is less B times the
thermal voltage, where B is
(A) 4
(B) 3
(C) 2
(D) 1
In a shunt-shunt negative feedback amplifier, as compared to the
basic amplifier
(A) both, input and output impedances,decrease
(B) input impedance decreases but output impedance increases
(C) input impedance increase but output
(D) both input and output impedances increases.
1998

TWO MARK

An amplifier has an open-loop gain of 100, an input impedance of

1 k8,and an output impedance of 100 8. A feedback network with
a feedback factor of 0.99 is connected to the amplifier in a voltage
series feedback mode. The new input and output impedances,
respectively, are
(A) 10 8 and 18
(B) 10 8 and 10 k8
(C) 100 k8 and 1 8
(D) 100 k8 and 1 k8

In a differential amplifier, CMRR can be improved by using an

increased
(A) emitter resistance
(B) collector resistance
(C) power supply voltages
(D) source resistance

4.131

TWO MARKS

A multistage amplifier has a low-pass response with three real poles

at s  X1  X2 and X3 . The approximate overall bandwidth B of the
amplifier will be given by
(B) 1  1  1  1
(A) B  X1  X2  X3
X1 X2 X3
B
(C) B  (X1  X2  X3) 1/3

(D) B 

X12  X22  X23

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

4.132

One input terminal of high gain comparator circuit is connected to

ground and a sinusoidal voltage is applied to the other input. The
output of comparator will be
(A) a sinusoid
(B) a full rectified sinusoid
(C) a half rectified sinusoid

4.133

4.134

Page 80

(D) a square wave

In a series regulated power supply circuit, the voltage gain Av of the

pass transistor satisfies the condition
(B) 1  Av  3
(A) Av " 3
(C) Av . 1
(D) Av  1
For full wave rectification, a four diode bridge rectifier is claimed to
have the following advantages over a two diode circuit :
(A) less expensive transformer,

(A) decrease the voltage gain and decrease the input impedance
(B) increase the voltage gain and decrease the input impedance

(B) smaller size transformer, and

(C) suitability for higher voltage application.

(D) increase the voltage gain and increase the input impedance

(C) decrease the voltage gain and increase the input impedance

4.138

Of these,
(A) only (1) and (2) are true
(B) only (1) and (3) are true

(B) a common base stage followed by an emitter follower

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(C) an emitter follower stage followed by a common base stage

(D) a common base stage followed by a common emitter stage
4.139

4.136

1997

In the MOSFET amplifier of the figure is the signal output V1 and

V2 obey the relationship

(A) V1  V2
2

(B) V1 V2
2

(C) V1  2V2

(D) V1  2V2

4.140

4.141

ONE MARK

In the BJT amplifier shown in the figure is the transistor is based in

the forward active region. Putting a capacitor across RE will

TWO MARKS

In the circuit of in the figure is the current iD through the ideal

diode (zero cut in voltage and forward resistance) equals

(A) 0 A
(C) 1 A

For small signal ac operation, a practical forward biased diode can

be modelled as
(A) a resistance and a capacitance in series
(B) an ideal diode and resistance in parallel
(C) a resistance and an ideal diode in series
(D) a resistance
1997

4.137

In a common emitter BJT amplifier, the maximum usable supply

voltage is limited by
(A) Avalanche breakdown of Base-Emitter junction
(B) Collector-Base breakdown voltage with emitter open (BVCBO)
(C) Collector-Emitter breakdown voltage with base open (BVCBO)
(D) Zener breakdown voltage of the Emitter-Base junction

(C) only (2) and (3) are true

(D) (1), (2) as well as (3) are true
4.135

A cascade amplifier stags is equivalent to

(A) a common emitter stage followed by a common base stage

(B) 4 A
(D) None of the above

The output voltage V0 of the circuit shown in the figure is

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GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

(A)  4 V
(C) 5 V
4.142

A half wave rectifier uses a diode

voltage is Vm sin Xt and the load
is given by
(A) Vm
2 RL
2
V
m
(C)
Q

Page 81

(B) 6 V
(D)  5.5 V
with a forward resistance Rf . The
resistance is RL . The DC current
Vm
Q (R f  RL)
(D) Vm
RL
(B)

(A) gm1
(C) gm2
4.147

1996
4.143

In the circuit of the given figure, assume that the diodes are ideal
and the meter is an average indicating ammeter. The ammeter will
read

(A) 0.4 2 A
(C) 0.8 A
Q
4.144

ONE MARK

(B) 0.4 A
(D) 0.4 mamp
Q

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(B) an inverting amplifier

(D) a Schmitt trigger

1996
4.145

Value of R in the oscillator circuit shown in the given figure, so

chosen that it just oscillates at an angular frequency of X. The value
of X and the required value of R will respectively be

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form. But at NODIA Online Store book is available in 10 book
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The circuit shown in the figure is that of

(A) a non-inverting amplifier

(C) an oscillator

(B) 0.5 gm1

(D) 0.5 gm2

TWO MARKS

In the circuit shown in the given figure N is a finite gain amplifier

with a gain of k , a very large input impedance, and a very low
output impedance. The input impedance of the feedback amplifier
with the feedback impedance Z connected as shown will be
(A) 105 rad/ sec, 2 # 10 4 8
(C) 2 # 10 4 rad/ sec, 105 8
4.148

(A) Z b1  1 l
k
(C) Z
(k  1)
4.146

(B) Z (1  k)
(D) Z
(1  k)

(B) 2 # 10 4 rad/ sec, 2 # 10 4 8

(D) 105 rad/ sec, 105 8

A zener diode in the circuit shown in the figure is has a knee current
of 5 mA, and a maximum allowed power dissipation of 300 mW
. What are the minimum and maximum load currents that can
be drawn safely from the circuit, keeping the output voltage V0
constant at 6 V?

A Darlington stage is shown in the figure. If the transconductance of

c
Q1 is gm1 and Q2 is gm2 , then the overall transconductance gmc ;T i cc E
vbe
is given by

(A) 0 mA, 180 mA

(C) 10 mA, 55 mA

(B) 5 mA, 110 mA

(D) 60 mA, 180 mA

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 82

***********

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GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 83

SOLUTIONS
4.1

(1)
Since, voltage across zener diode is 5 V so, current through 100 8
resistor is obtained as
Is  10  5  0.05 A
100
Therefore, the load current is given by
IL  5
RL
Since, for proper operation, we must
have
IZ $ Iknes
So, from Eq. (1), we write
0.05 A  5 $ 10 mA
RL
50 mA  5 $ 10 mA
RL
40 mA $ 5
RL
3
40 # 10 $ 5
RL

Option (B) is correct.

For the given ideal op-amp, negative terminal will be also ground
(at zero voltage) and so, the collector terminal of the BJT will be
at zero voltage.
VC  0 volt
The current in 1 k8 resistor is given by
I  5  0  5 mA
1 k8

i.e.,

This current will flow completely through the BJT since, no current will flow into the ideal op-amp ( I/P resistance of ideal opamp is infinity). So, for BJT we have
VC  0
VB  0
IC  5 mA
i.e.,the base collector junction is reverse biased (zero voltage)
therefore, the collector current (IC ) can have a value only if baseemitter is forward biased. Hence,
VBE  0.7 volts
&
VB  VE  0.7
&
0  Vout  0.7
or,
Vout  0.7 volt
4.2

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1
# RL
5
40 # 103
5
#
R
L
40 # 103
or,
125 8 # RL
Therefore, minimum value of RL  125 8
Now, we know that power rating of Zener diode is given by
PR  VZ IZ^maxh
IZ^maxh is maximum current through zener diode in reverse bias.
Maximum currrent through zener diode flows when load current is
zero. i.e.,
IZ^maxh  Is  10  5  0.05
100
Therefore,
PR  5 # 0.05 W
 250 mW

Option (A) is correct.

The i/p voltage of the system is given as
Vin  V1  Vf
 V1  k Vout

 V1  k A 0 V1
^Vout  A 0 V1h
 V1 ^1  k A 0h
Therefore, if k is increased then input voltage is also increased so,
the input impedance increases. Now, we have
Vout  A 0 V1
Vin
 A0
^1  k A 0h
 A 0 Vin
^1  k A 0h
Since, Vin is independent of k when seen from output mode, the
output voltage decreases with increase in k that leads to the decrease
of output impedance. Thus, input impedance increases and output
impedance decreases.
4.3

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4.4

Option (A) is correct.

For the given circuit, we obtain the small signal model as shown in
figure below :

Option (B) is correct.

We obtain the node voltage at V1 as

V1 
V1
 gm Vi  0
RD R  1
L
sC
&
From the circuit, we have
or,

Is  IZ  I L
IZ  Is  I L

V1 

 gm Vi
1 
1
RD R  1
L
sC

Therefore, the output voltage V0 is obtained as

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

V0  V1 RL
RL  1
sC


RL
RL  1
sC

4.6

 gm Vi
J
K 1
1

K RD
K
RL  1
sC
L

so, the transfer function is

V0   RD RL sCgm
Vi
1  sC ^RD  RL h
1
Then, we have the pole at X 
C ^RD  RL h
It gives the lower cutoff frequency of transfer function.
1
i.e.,
X0 
C ^RD  RL h
1
or,
f0 
2QC ^RD  RL h
1

2Q # 106 # 20 # 103
 7.97
. 8 Hz
4.5

Page 84

N
O
O
O
P

Logic 0 means voltage is v  0 volt and logic 1 means voltage is

5 volt
For x  0 , y  0 , Transistor is at cut off mode and diode is forward
biased. Since, there is no drop across forward biased diode.
So,
Z Y0
For x  0 , y  1, Again Transistor is in cutoff mode, and diode is
forward biased. with no current flowing through resistor.
So,
Z Y1
For x  1, y  0 , Transistor is in saturation mode and so, z directly
connected to ground irrespective of any value of Y .
i.e.,
Z  0 (ground)
Similarly for X  Y  1
Z  0 (ground)
Hence, from the obtained truth table, we get
Z XY

Option (C) is correct.

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Option (B) is correct.

For the given circuit, we can make the truth table as below
X
Y
Z
0
0
0
0
1
1
1
0
0
1
1
0

4.7

Option (D) is correct.

Given, the input voltage
VYZ  100 sin Xt

For  ve half cycle

VYZ  0
i.e., VY is a higher voltage than VZ
So, the diode will be in cutoff region. Therefore, there will no voltage difference between X and W node.
i.e.,
VWX  0
Now, for  ve half cycle all the four diodes will active and so, X
and W terminal is short circuited
For the given ideal op-Amps we can assume
V 2  V 2  V2 (ideal)
V 1  V 1  V1 (ideal)
So, by voltage division
V1  Vout # 1
2
Vout  2V1
and, as the I/P current in Op-amp is always zero therefore, there
will be no voltage drop across 1 K8 in II op-amp
i.e.,
V2  1 V
Therefore,
V1  V2  V2  ^ 2h
1
1
&
V1  1  1  2
or,
V1  4
Hence,
Vout  2V1  8 volt

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i.e.,
Hence,
4.8

VWX  0
VWX  0 for all t

Option (C) is correct.

The equivalent circuit can be shown as

VTh  VCC

R2
R1  R 2

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 85

3R2
R1  R 2
and
RTh  R2 R1
R 2  R1
Since, IC  CIB has C . 3 (very high) so, IB is negative in
comparison to IC . Therefore, we can write the base voltage
VB  VTh
So,
VTh  0.7  IC RE  0


or,
or,
or,
or,
Hence,
4.9

4.10

3R2  0.7  103 500  0

^
h^ h
R1  R 2
3R 2
 0. 7  0 . 5
60 k8  R2

The peak rectifier adds  1 V to peak voltage, so overall peak voltage

lowers down by  1 volt.
So,
vo  cos Xt  1
4.12

3R2  ^60 k8h^1.2h  1.2R2

Option (A) is correct.

We put a test source between terminal 1, 2 to obtain equivalent
impedance

1.8R2  ^60 k8h # ^1.2h

R2  60 # 1.2  40 k8
1. 8

Option (C) is correct.

Given
ib  1  0.1 cos (1000Qt) mA
So,
IB  DC component of ib
 1 mA
In small signal model of the transistor
CVT
VT " Thermal voltage
rQ 
IC
IC  I
 VT  VT
B
IB
C
IC /C
 VT
IB
mV  25 8
25
So,
rQ 
VT  25 mV, IB  1 mA
1 mA
Option (D) is correct.
Let v  0.7 V and diode is forward biased. By applying Kirchoffs
voltage law

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10  i # 1k  v  0
v

0.7 (1000)  v  0
10  :
500 D

ZTh  Vtest
Itest

10  (v  0.7) # 2  v  0
10  3v  1.4  0

So,
4.11

v  11.4  3.8 V > 0.7

3
i  v  0.7  3.8  0.7  6.2 mA
500
500

Applying KCL at top right node

Vtest  Vtest  99I  I
test
b
9 k  1k 100
Vtest  Vtest  99I  I
test
b
10 k 100
...(i)

(Assumption is true)

Option (A) is correct.

The circuit composed of a clamper and a peak rectifier as shown.

But

Clamper clamps the voltage to zero voltage, as shown

4.13

Ib  Vtest Vtest
9k  1k
10k

Substituting Ib into equation (i), we have

Vtest  Vtest  99Vtest  I
test
10 k 100
10 k
100Vtest  Vtest  I
test
10 # 103 100
2Vtest  I
test
100
ZTh  Vtest  50 8
Itest
Option (B) is correct.
First we obtain the transfer function.

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 86

IC - IE  13.7  VC  (C  1) IB
12k
13.7  VC  100I
...(ii)
B
12 # 103
Solving equation (i) and (ii),
IB  0.01 mA
Small Signal Analysis :
Transforming given input voltage source into equivalent current
source.

0  Vi (jX) 0  Vo (jX)

0
1 R
R2
1
jXC
Vo (jX)
 Vi (jX)

1 R
R2
1
jXC
Vi (jX) R2
R1  j 1
XC
1 " 3, so V  0
o
XC

Vo (jX) 
At X " 0 (Low frequencies),

This is a shunt-shunt feedback amplifier.

Given parameters,
rQ  VT  25 mV  2.5 k8
IB
0.01 mA
C
100
 0.04 s
gm  
rQ 2.5 # 1000
Writing KCL at output node
v0  g v  v0  vQ  0
m Q
RC
RF
1
1

 v Q :gm  1 D  0
v0 :
RC RF D
RF
Substituting RC  12 k8, RF  100 k8, gm  0.04 s
v 0 (9.33 # 105)  v Q (0.04)  0

At X " 3 (higher frequencies)

1 " 0, so V (jX)  R2 V (jX)
o
R1 i
XC

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The filter passes high frequencies so it is a high pass filter.
H (jX)  Vo   R2
Vi
R1  j 1
XC
R
R

2
2

H (3) 
R1
R1
At 3 dB frequency, gain will be

6H (3)@

v 0  428.72VQ
...(i)
Writing KCL at input node
vi  v Q  v Q  v Q  vo
Rs
Rs rQ
RF
vi  v 1  1  1  v 0
Q:
Rs
Rs rQ RF D RF
vi  v (5.1 104)  v 0
#
Q
Rs
RF
Substituting VQ from equation (i)

2 times of maximum gain

H ^ jX0h  1 H (3)
2
R2
 1 b R2 l
2 R1
R 12  21 2
X0 C

So,

vi   5.1 # 104 v  v 0
0
428.72
Rs
RF

2R  R  21 2
X0 C
1
2
R1  2 2
X C
X0  1
R1 C
2
1

4.14

2
1

vi
 1.16 # 106 v 0  1 # 105 v 0
10 # 103

Rs  10 k8

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Option (D) is correct.

DC Analysis :

(source resistance)
vi
 1.116 # 105
10 # 103
1
- 8.96
Av  v 0 
vi
10 # 103 # 1.116 # 105
4.15

Using KVL in input loop,

VC  100IB  0.7  0
VC  100IB  0.7

...(i)

Option (A) is correct.

For the parallel RLC circuit resonance frequency is,
1
Xr  1 
 10 M rad/s
LC
10 # 106 # 1 # 109
Thus given frequency is resonance frequency and parallel RLC
circuit has maximum impedance at resonance frequency

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 87

Gain of the amplifier is gm # (ZC RL) where ZC is impedance of

parallel RLC circuit.
At X  Xr , ZC  R  2 k8  ZC max .
Hence at this frequency (Xr ), gain is
Gain X  X  gm (ZC RL)  gm (2k 2k)  gm # 103 which is
maximum. Therefore gain is maximum at Xr  10 M rad/ sec .
r

4.16

In active region, for common emitter amplifier,

...(1)
IC  CIB  (1  C) ICO
Substituting ICO  0.6 NA and IB  20 NA in above eq we have,
IC  1.01 mA
4.19

Option (D) is correct.

The given circuit is shown below :

Option (C) is correct.

In active region
VBEon  0.7 V
Emitter voltage
VE  VB  VBEon  5.7 V
V  ( 10)  5.7  ( 10)
Emitter Current

 1 mA
IE  E
4.3k
4.3k
Now
IC . IE  1 mA
Applying KCL at collector
i1  0.5 mA
i1  C dVC
dt
1
VC  # i1 dt  i1 t
C
C

Since
or

From diagram we can write

Ii  Vo  Vo
R1 sL1

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Transfer function

or

H (s)  Vo  sR1 L1
I1 R1  sL1
jXR1 L1
H (jX) 
R1  jXL1

At X  0
At X  3
4.17

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H (jX)  0
H (jX)  R1  constant .

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Hence HPF.

Option (C) is correct.

Given circuit is shown below.

with time, the capacitor charges and voltage across collector changes
from 0 towards negative.
When saturation starts,
VCE  0.7 & VC  5 V (across
capacitor)
Thus from (1) we get,
 5  0.5 mA T
5 NA

For transistor M2 ,
VGS  VG  VS  Vx  0  Vx
VDS  VD  VS  Vx  0  Vx
Since VGS  VT  Vx  1  VDS , thus M2 is in saturation.
By assuming M1 to be in saturation we have
IDS (M )  IDS (M )
Nn C 0x
N C
(4) (5  Vx  1) 2  n 0x 1 (Vx  1) 2
2
2
1

or
Taking positive root,

or
4.20

4 (4  Vx ) 2  (Vx  1) 2
2 (4  Vx )  ! (Vx  1)
4.21

8  2Vx  Vx  1
Vx  3 V
At Vx  3 V for M1,VGS  5  3  2 V  VDS . Thus our assumption
is true and Vx  3 V .
4.18

...(1)

Option (D) is correct.

We have
Now

B  0.98
C  B  4.9
1B

6
T  5 # 5 # 10
 50 m sec
0.5 # 103

Option (A) is correct.

The current flows in the circuit if all the diodes are forward biased.
In forward biased there will be 0.7 V drop across each diode.
12.7  4 (0.7)
Thus
 1 mA
IDC 
9900
Option (B) is correct.
The forward resistance of each diode is
r  VT  25 mV  25 8
IC
1 mA
4 (r)
Thus
Vac  Vi # e
4 (r)  9900 o
 100 mV cos (Xt) 0.01
 1 cos (Xt) mV

4.22

Option (A) is correct.

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

The equivalent circuit of given amplifier circuit (when CE is

connected, RE is short-circuited)

Page 88

4.24

Option (A) is correct.

The circuit is as shown below :

Ri  RB || r Q
Voltage gain
AV  gm RC
Now, if CE is disconnected, resistance RE appears in the circuit
Input impedance

So,
or
4.25

Input impedance

Input resistance seen by source vs

R in  vs  Rs  Rs || rs
is
 (1000 8)  (93 k8 || 259 8)  1258 8
4.26

Input impedance increases

4.23

Option (B) is correct.

By small signal equivalent circuit analysis

R in  RB || [rQ  (C  1)] RE

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AV 

Voltage gain

0  Vi  0  Vo  0
R1
R2
Vo  R2
R1
Vi

gm RC
1  gm R E

fo 

Voltage gain decreases.

The circuit is as shown below :

4.27

VB  10  ( 0.7)  9.3 V
Collector current
I1 

0  ( 9.3)
 1 mA
(9.3 k8)

C 1  700 (high), So IC . IE
Applying KCL at base we have
1  IE  IB  IB
1  (C 1  1) IB  IB  IB
1

1  (700  1  1)

IB
 IB
2

IB . 2
702
2

I 0  IC  C 2 : IB  715 # 2 . 2 mA
702
2

1
2Q (RC  RL) C2

fo
1

 271 Hz
2 # 3.14 # 1250 # 4.7 # 106
Lower cut-off frequency
f
fL . o  271  27.1 Hz
10
10

Option (B) is correct.

Since, emitter area of transistor Q1 is half of transistor Q2 , so current
IE  1 IE and IB  1 IB
2
2
1

Option (B) is correct.

Cut-off frequency due to C2

Option (B) is correct.

The circuit is as shown below

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GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 89

I  20  0  Vi  0  5  Vi
4R
R
R
If I  0, diode D2 conducts
So, for 5  VI  0 & VI   5, D2 conducts
2
Equivalent circuit is shown below

IC  10  5  1 mA
5k

Thus

Current

IE  IC
VE  IE RE  1m # 1.4k  1.4V
 0. 6  1 . 4  2 V
Thus the feedback is negative and output voltage is V  2V .
4.33

Option (D) is correct.

The output voltage is
V0  Ar Vi .

hfe RC
Vi
hie

Here RC  3 8 and hie  3 k8

V0 .  150 # 3k Vi
3k

Thus
Output is Vo  0 . If I  0 , diode D2 will be off
5  VI  0 & V   5, D is off
I
2
R
The circuit is shown below

. 150 (A cos 20t  B sin 106 t)

Since coupling capacitor is large so low frequency signal will be
filtered out, and best approximation is
V0 . 150B sin 106 t
4.34

0  Vi  0  20  0  Vo  0
R
4R
R

4.28

4.29

4.30

4.31
4.32

or

Vo  Vi  5

At Vi  5 V,
At Vi  10 V,

Vo  0
Vo  5 V

Option (A) is correct.

Let diode be OFF. In this case 1 A current will flow in resistor and
voltage across resistor will be V  1.V
Diode is off, it must be in reverse biased, therefore
Vi  1  0 Vi  1
Thus for Vi  1 diode is off and V  1V
Option (B) and (C) doesnt satisfy this condition.
Let Vi  1. In this case diode will be on and voltage across diode will
be zero and V  Vi
Thus
V  min (Vi, 1)

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For the positive half of Vi , the diode D1 is forward bias, D2 is reverse
bias and the zener diode is in breakdown state because Vi  6.8 .
Thus output voltage is
V0  0.7  6.8  7.5 V
For the negative half of Vi, D2 is forward bias thus
Then
V0  0.7 V
4.35

Option (C) is correct.

Option (B) is correct.

By Current mirror,

^ L h2
Ibias
W
^ L h1
W

Ix 

Since MOSFETs are identical,

W
W
Thus
b L l b L l
2
2

Option (A) is correct.

The R2 decide only the frequency.
Option (D) is correct.
For small increase in VG beyond 1 V the n  channel MOSFET goes
into saturation as VGS  ive and p  MOSFET is always in active
region or triode region.

Option (C) is correct.

Hence
4.36

Ix  Ibias

Option (B) is correct.

The circuit is using ideal OPAMP. The non inverting terminal of
OPAMP is at ground, thus inverting terminal is also at virtual
ground.

Option (D) is correct.

The circuit is shown in fig below

Thus current will flow from -ive terminal (0 Volt) to -1 Volt source.
Thus the current I is
0  ( 1)
I 
 1
100k
100k
The voltage at non inverting terminal is 5 V because OP AMP is
ideal and inverting terminal is at 5 V.

The current through diode is

I  I 0 _eV  1i
V

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 90

Now VT  25 mV and I0  1 NA
Thus
or
Now
V
4.37

V
I  106 8e 25 # 10  1B  1 5
10
V  0.06 V
V0  I # 4k  V  1 # 4k  0.06  0.1
100k
3

The Thevenin resistance and voltage are

VTH  10 # 9  3 V
10  20
and total
RTH  10k # 20k  6.67 k8
10k  20k

Option (B) is correct.

The circuit is using ideal OPAMP. The non inverting terminal of
OPAMP is at ground, thus inverting terminal is also at virtual
ground.

Since C is very large, therefore IB is small and can be ignored

Thus
IE  VTH  VBE  3  0.7  1 mA
RE
2. 3 k
4.41

Option (D) is correct.

The small signal model is shown in fig below

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gm 

Vo  gm VQ # (3k 3k )
 1 Vin (1.5k)
25

Thus we can write

vi

R1  sL
or

v
R2
sR2 C2 + 1

v0 
R2
vi
(R1  sL)( sR2 C2  1)

or
4.42

and from this equation it may be easily seen that this is the standard form of T.F. of low pass filter
K
H (s) 
(R1  sL)( sR2 C2  1)
and form this equation it may be easily seen that this is the standard form of T.F. of low pass filter
H (s)  2 K
as  bs  b
4.38

4.39

4.43

Option ( ) is correct.
The current in both transistor are equal. Thus gm is decide by M1.
Hence (C) is correct option.
Option (C) is correct.
Let the voltage at non inverting terminal be V1, then after applying
KCL at non inverting terminal side we have
15  V1  V0  V1  V1  ( 15)
10
10
10
V
0
or
V1 
3

IC
 1m  1 A/V
VT
25m
25

VQ  Vin

 60Vin
Am  Vo  60
Vin

Option (C) is correct.

The circuit shown in (C) is correct full wave rectifier circuit.

Option (A) is correct.

In the transconductance amplifier it is desirable to have large input
resistance and large output resistance.

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4.44

Option (C) is correct.

We redraw the circuit as shown in fig.

If V0 swings from -15 to +15 V then V1 swings between -5 V to +5

V.
4.40

IC . IE

Option (A) is correct.

For the given DC values the Thevenin equivalent circuit is as follows
Applying voltage division rule
v+  0.5 V

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

v+  vv -  0. 5 V
i  1  0.5  0.5 mA
1k
 v0  0.5 mA
0
.
5
i 
2k

We know that
Thus
Now
and

v0  0.5  1  0.5 V

or
4.45

Page 91

The range of current through 200 k8 is

3  15 mA to 9  45 mA
200k
200k
The range of variation in output voltage
15m # RZ = 0.15 V to 45m # RZ = 0.45
Thus the range of output voltage is 7.15 Volt to 7.45 Volt
4.49

Option (B) is correct.

If we assume C very large, then IB  0 and IE  IC ; VBE  0.7 V. We
assume that BJT is in active, so applying KVL in Base-emitter loop
IE  2  VBE  2  0.7  1.3 mA
RE
1k

V+ 

Now

10  10IC  VCE  IC  0
VCE  4.3 V
VBC  VBE  VCE

Since VBC
4.46

 0.7  ( 4.3)  5 V
 0.7 V, thus transistor in saturation.

Option (D) is correct.

Here the inverting terminal is at virtual ground and the current in
resistor and diode current is equal i.e.

or

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V0  1  sRC
Vi
1  sRC
4.50

Option (C) is correct.

V0  H (s)  1  sRC
Vi
1  sRC
1  jXRC
H (jX) 
1  jXRC

VD = 0  Vo1 = VT 1n 2
Is R
For the first condition
VD = 0  Vo1 = VT 1n 4
Is R

+H (jX)  G  tan - 1 XRC  tan - 1 XRC

Subtracting above equation

4.47

Vo1  Vo2 = VT 1n 4  VT 1n 2
Is R
Is R
4
Vo1  Vo2 = VT 1n = VT 1n2
2

Option (D) is correct.

We have
Vthp  Vthp  1 V
W
W
P
and
= N = 40NA/V2
LP
LN

Minimum value,
Maximum value,
4.51

4.52
4.53

From figure it may be easily seen that Vas for each NMOS and
PMOS is 2.5 V
NA
Thus
ID  K (Vas  VT ) 2  40 2 (2.5  1) 2  90 N A
V
4.48

1
V
1  sCR i

For the first condition

or

1
V
1  sCR i

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Vi  I eV /V
s
R
VD = VT 1n Vi
Is R
D

Vi 

Applying voltage division rule

(V  Vi)
V+  R1 (V0  Vi)  o
R1  R1
2
(V  Vi)
1
or
Vi  o
2
1  sCR
V
2
o
or
 1 
Vi
1  sRC

IR  ID
or

1
sC

R  sC1

V-  V+ 

Now

Since C is very large, we have IE  IC , thus

IC  1.3 mA
Now applying KVL in collector-emitter loop
or

Option (A) is correct.

The voltage at non-inverting terminal is

Gmin
Gmax

 2 tan - 2 XRC
=  Q (at X 3)
= 0( at X = 0)

Option (D) is correct.

In the transconductance amplifier it is desirable to have large input
impedance and large output impedance.
Option (C) is correct.
Option (D) is correct.
The voltage at inverting terminal is
V  V+  10 V
Here note that current through the capacitor is constant and that
is
I  V  10  10 mA
1k 1k

Option (C) is correct.

We have VZ  7 volt, VK  0, RZ  108
Circuit can be modeled as shown in fig below

Thus the voltage across capacitor at t  1 msec is

1m
1m
VC  1 Idt  1 10mdt
C
1
N
0
0
Im
 10 4 dt  10 V

4.54

Since Vi is lies between 10 to 16 V, the range of voltage across 200

k8
V200  Vi  VZ  3 to 9 volt

Option (A) is correct.

In forward bias Zener diode works as normal diode.
Thus for negative cycle of input Zener diode is forward biased and
it conducts giving VR  Vin .

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 92

Now
VCE  15  9  6 V
The power dissipated in transistor is

For positive cycle of input Zener diode is reversed biased

when 0  Vin  6 , Diode is OFF and VR  0
when Vin  6 Diode conducts and voltage across diode is 6 V. Thus
voltage across is resistor is
VR  Vin  6
Only option (B) satisfy this condition.
4.55

P  VCE IC  6 # 0.9  5.4 W

4.59

Option (C) is correct.

The circuit under DC condition is shown in fig below

Option (B) is correct.

If the unregulated voltage increase by 20%, them the unregulated
voltage is 18 V, but the VZ  Vin  6 remain same and hence Vout
and IC remain same. There will be change in VCE
Thus,
VCE  18  9  9 V
IC  0.9 A
Power dissipation
P  VCE IC  9 # 0.9  8.1 W
Thus % increase in power is
8.1  5.4 # 100  50%
5. 4

4.60

Applying KVL we have

VCC  RC (IC  IB)  VCE  0

...(1)

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and
VCC  RB IB  VBE  0
Substituting IC  CIB in (1) we have
VCC  RC (CIB  IB)  VCE  0
Solving (2) and (3) we get
VCE  VCC  VCC  VBE
RB
1
RC (1  C)
Now substituting values we get
12  0.7
 5.95 V
VCE  12 
53
1
1  (1  60)
4.56

4.61

where

Ri
Rif

...(2)
4.62

...(3)
...(4)

4.63

Rof  R0 (1  AC)
Input resistance without feedback
Input resistance with feedback.

Option (B) is correct.

The CE configuration has high voltage gain as well as high
current gain. It performs basic function of amplifications. The CB
configuration has lowest Ri and highest Ro . It is used as last step to
match a very low impedance source and to drain a high impedance
load
Thus cascade amplifier is a multistage configuration of CE-CB
Option (D) is correct.
Common mode gain
ACM  RC
2RE

C'  110 # 60  66
100

And differential mode gain

Substituting C'  66 with other values in (iv) in previous solutions

12  0.7
 5.29 V
VCE  12 
53
1
1  (1  66)
Thus change is

4.58

Option (D) is correct.

The effect of current shunt feedback in an amplifier is to decrease
the input resistance and increase the output resistance as :
Rif  Ri
1  AC

Option (B) is correct.

We have

4.57

Option (B) is correct.

Since the inverting terminal is at virtual ground, the current flowing
through the voltage source is
Is  Vs
10k
V
s
or
 10 k8  Rin
Is

ADM  gm RC

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 5.29  59.5 # 100  4.3%

5.95

Thus only common mode gain depends on RE and for large value
of RE it decreases.

Option (A) is correct.

Option (C) is correct.
The Zener diode is in breakdown region, thus
V+  VZ  6 V  Vin
R
We know that
Vo  Vin c1  f m
R1
or
Vout  Vo  6`1  12k j  9 V
24k
The current in 12 k8 branch is negligible as comparison to 10 8.
Thus Current
IC . IE .  Vout  9  0.9 A
RL
10

4.64

Option (C) is correct.

IE  Is `e nV  1j
VBE

 10
4.65

- 13

0.7

c e1 # 26 # 10

-3

 1m  49 mA

Option (C) is correct.

The circuit is as shown below

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 93

IL  24.2  0.5  23.7 mA

or
4.69
4.70

Option (D) is correct.

Option (B) is correct.
The small signal model is as shown below

Writing equation for I have

e 0  V  I
1M
e0  I (1M)  V
Writing equation for I+ we have
0  V+
 I+
1M

...(1)

or

...(2)

or

V+ = I+ (1M)
Since for ideal OPAMP V+  V- , from (1) and (2) we have

From the figure we have

Zin  2 M8

4.71

e0  I (1M)  I  (1M)
 (I  I) (1M) = IOS (1M)
Thus if e0 has been measured, we can calculate input offset current
IOS only.
4.66

4.67

Option (C) is correct.

At low frequency capacitor is open circuit and voltage acr s noninverting terminal is zero. At high frequency capacitor act as short
circuit and all input voltage appear at non-inverting terminal. Thus,
this is high pass circuit.
The frequency is given by
1
 1000
X  1 
RC
1 # 103 # 1 # 10 - 6
rad/sec

Z0  rd RD  20k 2k  20 k8
11

and

Option (A) is correct.

The circuit in DC condition is shown below

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Option (B) is correct.

The circuit under DC condition is shown in fig below

Since the FET has high input resistance, gate current can be neglect
and we get VGS  2 V
Since VP  VGS  0 , FET is operating in active region
2
( 2) 2
Now
ID  IDSS c1  VGS m  10 c1 
( 8) m
VP
 5.625 mA
Now

Applying KVL we have

VCC  RB IB  VBE  RE IE  0
or
VCC  RB IB  VBE  RE (C  1) IB  0
Since IE  IB  CIB
or
IB  VCC  VBE
RB  (C  1) RE
20  0.7

 40N A
430k + (50 + 1)1 k
Now
4.68

4.72

Option (B) is correct.

The transconductance is
gm 
or,
The gain is

IC  CIB  50 # 40N  2 mA
VC  VCC  RC IC = 20  2m # 2k = 16 V

Option (A) is correct.

The maximum load current will be at maximum input voltage i.e.
Vmax  30 V i.e.
Vmax  VZ  I  I
L
Z
1k
30  5.8  I  0.5 m
or
L
1k

VDS  VDD  ID RD  20  5.625 m # 2 k

 8.75 V

So,
4.73

VP

2
ID IDSS

 2 5.625mA # 10mA  1.875 mS

8
A  gm (rd RD)
= 1.875ms # 20 K  3.41
11

Option (B) is correct.

Only one diode will be in ON conditions
When lower diode is in ON condition, then
Vu  2k Vsat  2 10  8 V
2.5k
2.5
when upper diode is in ON condition

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 94

or
2V+  Vo  IL R2  0
Since V-  V+ , from (1) and (2) we have

Vu  2k Vsat  2 ( 10)  5 V
2.5k
4
4.74

4.75

Option (B) is correct.

An ideal OPAMP is an ideal voltage controlled voltage source.
Option (C) is correct.
In voltage series feed back amplifier, input impedance increases
by factor (1  AC) and output impedance decreases by the factor
(1  AC).

Vs  IL R2  0

4.77

IL  Vs
R2

or
4.80

Rif  Ri (1  AC)
Ro
Rof 
(1  AC)
4.76

...(2)

Option (D) is correct.

If IZ is negligible the load current is
12  Vz  I
L
R
as per given condition
100 mA # 12  VZ # 500 mA
R
12

5
At IL  100 mA
 100 mA
R

Option (A) is correct.

This is a Low pass filter, because
V0  0
At X  3
Vin
V0  1
and at X  0
Vin

R  708
12

5
At IL  500 mA
 500 mA
R

VZ  5 V

or

VZ  5 V

R  14 8
Thus taking minimum we get
or

Option (D) is correct.

When IC  ICO

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R  14 8
4.81
4.82

Option (B) is correct.

Option (C) is correct.
The Thevenin equivalent is shown below

IC
 1mA  0.04  40 mA/V
VT
25mV
C
rQ 
 100 - 3  2.5 k8
gm
40 # 10

gm 

4.78

4.79

Option (A) is correct.

The given circuit is wein bridge oscillator. The frequency of oscillation
is
2Qf  1
RC
1
or
 1 N
C  1 
2QRf
2Q
2Q # 103 # 103

VT 

R1 V  1
#5  1 V
R1  R2 C
41

Since C is large is large, IC . IE , IB . 0 and

IE  VT  VBE  1  0.7  3 mA
RE
300
VCE  5  2.2kIC  300IE
 5  2.2k # 1m  300 # 1m
 2.5 V

Now

Option (A) is correct.

The circuit is as shown below
4.83

Option (B) is correct.

For the different combinations the table is as follows

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CE

CE

We know that for ideal OPAMP

Ai

V-  V+
Applying KCL at inverting terminal
V-  Vs  V-  V0  0
R1
R1

Av

or
2V-  Vo  Vs
Applying KCL at non-inverting terminal
V+
V  Vo
 IL  +
0
R2
R2

...(1)

4.84

4.85

CC

CB

High

High

Unity

High

Unity

High

Ri

Medium

High

Low

Ro

Medium

Low

High

Option (D) is correct.

This circuit having two diode and capacitor pair in parallel, works
as voltage doubler.
Option (B) is correct.

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 95

If the input is sinusoidal signal of 8 V (peak to peak) then

or

Vi  4 sin Xt
The output of comparator will be high when input is higher than
Vref  2 V and will be low when input is lower than Vref  2 V.
Thus the waveform for input is shown below

In second case IB2

Thus

VCE2  VCC  IC2 R2  6  2m # 2 k8  2 V

4.90

4.91

From fig, first crossover is at Xt1 and second crossover is at Xt2

where
4 sin Xt1  2V
Xt1  sin - 1 1  Q
2
6
Xt2  Q  Q  5Q
6
6
5Q
Q
6  6
Duty Cycle 
1
2Q
3

Thus

4.86

Thus the output of comparators has a duty cycle of 1 .

3
Option (C) is correct.
CMMR  Ad
Ac

R2  2k8
IB1  IC1  1.5m  0.01 mA
150
C1
will we equal to IB1 as there is no in R1.
IC2  C2 IB2  200 # 0.01  2 mA

Option (A) is correct.

The given circuit is a R  C phase shift oscillator and frequency of
its oscillation is
1
f 
2Q 6 RC
Option (C) is correct.
If we see th figure we find that the voltage at non-inverting terminal
is 3 V by the zener diode and voltage at inverting terminal will be 3
V. Thus Vo can be get by applying voltage division rule, i.e.
20 V  3
20  40 o
V0  9 V

or

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4.92

Option (B) is correct.

The circuit is as shown below

20 log CMMR  20 log Ad  20 log Ac

 48  2  46 dB
Where Ad Differential Voltage Gain
and AC Common Mode Voltage Gain

or

4.87

Option (B) is correct.

The gain of amplifier is
Ai 

8 (3) = 8 k8
18
3
8
V+  V-  V
3

 gm
gb  jXC

V+ =

Thus the gain of a transistor amplifier falls at high frequencies

due to the internal capacitance that are diffusion capacitance and
transition capacitance.
4.88

4.89

Now applying KCL at inverting terminal we get

V-  2  V-  Vo  0
1
5

Option (A) is correct.

We have Ri = 1k8, C  0.2, A  50
Ri
Thus,
Rif 
= 1 k8
(1  AC)
11
Option (A) is correct.
The DC equivalent circuit is shown as below. This is fixed bias
circuit operating in active region.

4.93

Option (C) is correct.

The equivalent circuit of 3 cascade stage is as shown in fig.

VCC  IC1 R2  VCE1  0

6  1.5mR2  3  0

1k
50V1  40V1
1k  0.25k
1k
V3 
50V2  40V2
1k  0.25k
V2 

In first case
or

Vo  6V-  10
 6 # 8  10  6 V
3

or

Similarly

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

or
or
or
4.94

Page 96

V3  40 # 40V1
Vo  50V3  50 # 40 # 40V1
AV  Vo  50 # 40 # 40  8000
V1

Thus from above equation for sustained oscillation

6  1  R2
R1

20 log AV  20 log 8000  98 dB

Option (D) is correct.

If a constant current is made to flow in a capacitor, the output
voltage is integration of input current and that is sawtooth waveform
as below :
t
VC  1 idt
C 0
The time period of wave form is
T  1  1  2 m sec
f
500

or
or

Now
Slew Rate

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or

4.100

I
For satisfactory operations
Vin  V0
R
When Vin  30 V,
30  10
R
20
or
R

Option (B) is correct.

Let x be the gain and it is 20 db, therefore

Ln

2n  1

or
Thus R # 18188

$ 11 mA

R # 36368

Option (D) is correct.

We have

2 2  1  0.5 kHz

Option (A) is correct.

As per Barkhousen criterion for sustained oscillations AC $ 1 and
phase shift must be or 2Qn .

$ (10 + 1) mA

40 $ 11 # 10 - 3
R

4.101

fHn  fH

[IZ  IL  I]

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23  1

The higher cutoff frequency is

 IZ + IL

50  10 $ (10  1) mA
R

Option (A) is correct.

In multistage amplifier bandwidth decrease and overall gain increase.
From bandwidth point of view only options (A) may be correct
because lower cutoff frequency must be increases and higher must
be decreases. From following calculation we have
We have fL  20 Hz and fH  1 kHz
For n stage amplifier the lower cutoff frequency is
fL
20
f 

 39.2 . 40
Hz

 IZ  IL

R # 1818 8

or
when Vin  50 V

6
6
BW  10  10  105 Hz  100 kHz
Gain
10

4.98

Option (A) is correct.

The circuit is shown as below

Option (C) is correct.

In voltage-amplifier or voltage-series amplifier, the Ri increase and
Ro decrease because

20 log x  20
or
x  10
Since Gain band width product is 106 Hz, thus
So, bandwidth is

4.97

dVO
 AV Vm X  AV Vm 2Qf
c dt m
max
Vm  SR
AV V2Qf

1
10 - 6 # 100 # 2Q # 20 # 103
or
VM  79.5 mV


Rif  Ri (1  AC)
Ro
Rof 
(1  AC)
4.96

VO  VV Vi  Vm sin Xt
dVO  A V X cos Xt
V m
dt

-3

3

Thus the charging require 3 mA current source for 2 msec.

4.95

Option (C) is correct.

Let the gain of OPAMP be AV then we have
20 log AV  40 dB
or
AV  100
Let input be Vi  Vm sin Xt then we have

20 # 10
1
idt
6
2 # 10 0
i (2 # 10 - 3  0)  6 # 10 - 6
i  3 mA

R2  5R1

or
4.99

Thus

VO (f)
 1  R2
Vf (f)
R1
Vf (f)
1
C (f)  +0 
6
VO (f)
A

Now from circuit

Now
and
Thus

IDSS
VG
VS
VGS

 10 mA and VP  5 V
0
 ID RS  1 # 2.58  2.5 V
 VG  VS  0  2.5  2.5 V

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

gm  2IDSS 81  `  2.5 jB  2 mS
VP
5
V
0
 gm RD
AV 
Vi

Now

9
 1 # 10  50.3 MHz
2Q 10

Option (C) is correct.

The current gain of a BJT is
4.108

hfe  gm rQ
4.103

1
2Q LCeq
Ceq  C1 C2  2 # 2  1 pF
C1  C2
4
1
f 
-6
2Q 10 # 10 # 10 - 12
f 

 2ms # 3k  6

So,
4.102

Page 97

Option (D) is correct.

The circuit is as shown below

Option (A) is correct.

The ideal op-amp has following characteristic :
Ri 3
R0 0
and

4.104

4.105

4.106

Option (C) is correct.

Both statements are correct because
(1) A stable multivibrator can be used for generating square wave,
because of its characteristic
(2) Bi-stable multivibrator can store binary information, and this
multivibrator also give help in all digital kind of storing.
Option (B) is correct.
If fT is the frequency at which the short circuit common emitter gain
attains unity magnitude then
gm
38 # 10 - 3

fT 
2Q (CN  CQ)
2Q # (10 - 14  4 # 10 - 13)
10
or
 1.47 # 10 Hz
If fB is bandwidth then we have
10
f
fB  T  1.47 # 10  1.64 # 108 Hz
90
C

Let V- be the voltage of inverting terminal, since non inverting

terminal a at ground, the output voltage is

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Vo  AOL VNow applying KCL at inverting terminal we have
V-  Vs  V-  V0  0
R1
R2

Option (C) is correct.

If we neglect current through RB then it can be open circuit as
shown in fig.

4.109

Maximum power will dissipate in Zener diode when current through

it is maximum and it will occur at Vin  30 V
I  Vin  Vo  30  10  1 A
20
20

or

I IC  IZ  CIB  IZ
 CIZ  IZ  (C  1) IZ
IZ  I  1  0.01 A
C  1 99  1

...(1)
...(2)

From (1) and (2) we have

VO  A 
 R2
CL
Vs
R  R2  R1
ROL
Substituting the values we have
 10k
 1000 .  11
ACL 
89
1k  10k + 1k
100k
Option (A) is correct.
The first OPAMP stage is the differentiator and second OPAMP
stage is integrator. Thus if input is cosine term, output will be also
cosine term. Only option (A) is cosine term. Other are sine term.
However we can calculate as follows. The circuit is shown in fig

Since IC  CIB
since IB  IZ

Power dissipated in zener diode is

PZ  VZ IZ = 9.5 # 0.01 = 95 mW
IC  CIZ  99 # 0.1  0.99 A
VCE = Vo  10 V
Power dissipated in transistor is
PT  VC IC  10 # 0.99  9.9 W
4.107

Option (B) is correct.

From the it may be easily seen that the tank circuit is having
2-capacitors and one-inductor, so it is colpits oscillator and frequency
is

Applying KCL at inverting terminal of first OP AMP we have

V1   XjL   100 # 10 # 10 - 3   1
R
10
10
VS
 jVS
or
V1 
 j cos 100t
10
Applying KCL at inverting terminal of second OP AMP we have
VO   1/jXC
V1
100
1

 j10
j100 # 10 # 10 - 6 # 100

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

or
4.110

Page 98

V0  j10V2  j10 ( j cos 100t)

V0  10 cos 100t

Option (A) is correct.

Common mode gain is
AC  BRC
REE
Since source resistance of the current source is infinite REE  3 ,
common mode gain AC  0

4.111

4.112

Option (D) is correct.

In positive feed back it is working as OP-AMP in saturation region,
and the input applied voltage is +ve.
So,
V0  Vsat  15 V
Option (C) is correct.
With the addition of RE the DC abis currents and voltages remain
closer to the point where they were set by the circuit when the
outside condition such as temperature and transistor parameter C
change.

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4.113

R1 V  5
# 15  5 V
R1  R2 C
10  5
Since C is large is large, IC . IE , IB . 0 and
IE  VT  VBE
RE
4.3
 5  0.7 
 10 mA
0.430K8
0.430k8
VT 

4.119

Option (C) is correct.

The output voltage will be input offset voltage multiplied by open
by open loop gain. Thus
So
V0  5mV # 10, 000  50 V
But
V0  ! 15 V in saturation condition
So, it can never be exceeds ! 15 V
V0  ! Vset  ! 15V

So,
4.120
4.121

4.122

Option (A) is correct.

At high frequency

Option (A) is correct.

Option (A) is correct.
Negative feedback in amplifier reduces the gain of the system.
Option (A) is correct.
By drawing small signal equivalent circuit

gm
'
 jX (C)
gbc
1
Ai \
Capacitance
1
Ai B
frequency
Ai 

or,
and

Thus due to the transistor capacitance current gain of a bipolar

transistor drops.
4.114

4.115

4.116

4.117

4.118

by applying KCL at E2

Option (C) is correct.

As OP-AMP is ideal, the inverting terminal at virtual ground due
to ground at non-inverting terminal. Applying KCL at inverting
terminal
sC (v1 sin Xt  0)  sC (V2 sin Xt  0)  sC (Vo  0)  0
or
Vo  (V1  V2) sin Xt

gm1 VQ 
1

VQ
 gm2 VQ
rQ
2

at C2
from eq (1) and (2)

i 0  gm2 VQ

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Option (D) is correct.

There is R  C , series connection in parallel with parallel R  C
combination. So, it is a wein bridge oscillator because two resistors
R1 and R2 is also in parallel with them.

gm1 VQ 

Option (A) is correct.

The given circuit is a differentiator, so the output of triangular wave
will be square wave.

i 0  i
0
gm2 rQ
2

gm1 VQ  i 0 :1  1 D
gm2 rQ
1

Option (B) is correct.

In sampling and hold circuit the unity gain non-inverting amplifier
is used.

gm2 rQ  C > 1
so
gm1 VQ  i 0
i 0  g
m1
VQ
i0  g
a VQ  Vi
m1
Vi
Option (B) is correct.
Crossover behavior is characteristic of calss B output stage. Here 2
2

Option (D) is correct.

The Thevenin equivalent is shown below

4.123

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

transistor are operated one for amplifying +ve going portion and

Page 99

4.133

other for -ve going portion.

4.124

Option (C) is correct.

In Voltage series feedback mode input impedance is given by

and

So,
R in  1 # 103 (1  0.99 # 100)  100 k8
Similarly output impedance is given by
R0
ROUT 
R 0  output impedance
(1  Cv Av)
100
Thus
 18
ROUT 
(1  0.99 # 100)
4.125

4.127

4.128

4.134

4.135

Option (D) is correct.

In bridge rectifier we do not need central tap transformer, so its less
expensive and smaller in size and its PIV (Peak inverse voltage)
is also greater than the two diode circuit, so it is also suitable for
higher voltage application.
Option (C) is correct.
In the circuit we have
V2  IS # RD
2
V1  IS # RD
V2  1
2
V1

and

Option (B) is correct.

Regulation  Vno  load  Vfuel  load
Vfull  load
30

25 100  20%

25 #
Output resistance  25  25 8
1

4.126

In series voltage regulator the pass transistor is in common collector configuration having voltage gain close to unity.

R in  Ri (1  Cv Av)
Cv  feedback factor ,
Av  openloop gain
Ri  Input impedance

where

Option (C) is correct.

Option (D) is correct.

This is a voltage shunt feedback as the feedback samples a portion
of output voltage and convert it to current (shunt).
Option (A) is correct.
In a differential amplifier CMRR is given by
(1  C) IQ R 0
CMRR  1 ;1 
E
2
VT C
So where R 0 is the emitter resistance. So CMRR can be improved
by increasing emitter resistance.

V1  2V2
4.136

Option (C) is correct.

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4.137

Option (C) is correct.

The equivalent circuit of given amplifier circuit (when CE is
connected, RE is short-circuited)

Option (C) is correct.

We know that rise time (tr ) is
tr  0.35
fH
where fH is upper 3 dB frequency. Thus we can obtain upper 3 dB
frequency it rise time is known.

4.129

4.130

Ri  RB || r Q
Voltage gain
AV  gm RC
Now, if CE is disconnected, resistance RE appears in the circuit
Input impedance

Option (D) is correct.

In a BJT differential amplifier for a linear response Vid  VT .
Option (D) is correct.
In a shunt negative feedback amplifier.
Input impedance
Ri
R in 
(1  CA)
where

Ri = input impedance of basic amplifier

C = feedback factor
A = open loop gain

Input impedance
R in  RB || [rQ  (C  1)] RE
Input impedance increases
gm RC
Voltage gain
Voltage gain decreases.
AV 
1  gm R E

So, R in  Ri
Similarly
ROUT 

R0
(1  CA)

4.138

ROUT  R 0
Thus input & output impedances decreases.
4.139
4.131
4.132

Option (A) is correct.

Option (D) is correct.
Comparator will give an output either equal to  Vsupply or  Vsupply .
So output is a square wave.

Option (A) is correct.

In common emitter stage input impedance is high, so in cascaded
amplifier common emitter stage is followed by common base stage.
Option (C) is correct.
We know that collect-emitter break down voltage is less than
compare to collector base breakdown voltage.
BVCEO  BVCBO
both avalanche and zener break down. Voltage are higher than

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Page 100

2Va  4  Va  V0  0
V0  3Va  4
Va  V0  Va  0  0
100
10

BVCEO .So BVCEO limits the power supply.

4.140

Option (C) is correct.

If we assume consider the diode in reverse bias then Vn should be

greater than VP .

So

VP  Vn
by calculating
VP  10 # 4  5 Volt
44

V0  5.5 Volts
4.142

Vn  2 # 1  2 Volt
here VP  Vn (so diode cannot be in reverse bias mode).

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apply node equation at node a

Va  10  Va  Va  2
1
4
4

so current

4.141

6Va  10  8
Va  3 Volt
Ib  0  3  10  3
4
4
Ib  10  6  1 amp
4

Option (D) is correct.

By applying node equation at terminal (2) and (3) of OP -amp

Va  V0  10Va  0
11Va  V0
Va  V0
11
V0  3V0  4
11
8V0  4
11

Option (B) is correct.

Circuit with diode forward resistance looks

So the DC current will

IDC 
4.143

Vm
Q (R f  RL)

Option (D) is correct.

For the positive half cycle of input diode D1 will conduct & D2 will
be off. In negative half cycle of input D1 will be off & D2 conduct so
output voltage wave from across resistor (10 k8) is

Ammeter will read rms value of current

so
I rms  Vm (half wave rectifier)
QR
4

 0.4 mA
Q
(10 k8) Q
4.144

4.145

Option (D) is correct.

In given circuit positive feedback is applied in the op-amp., so it
works as a Schmitt trigger.
Option (D) is correct.

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Gain with out feedback factor is given by
V0  kVi
after connecting feedback impedance Z

Va  Q Va  V0
0

5
10

given input impedance is very large, so after connecting Z we have

Ii  Vi  V0
V0  kVi
Z

GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia

Ii  Vi  kVi
Z
V
i
Zin   Z
Ii
(1  k)

input impedance
4.146
4.147

Page 101

Option (A) is correct.

Option (A) is correct.
For the circuit, In balanced condition It will oscillated at a frequency
X
1
1


 105 rad/ sec
LC
10 # 103 # .01 # 106
In this condition
R1  R 3
R2
R4
5 R
100
1
R  20 k8  2 # 10 4 8

4.148

Option (C) is correct.

V0 kept constant at
so current in 50 8 resistor

V0  6 volt
I  96
50 8

I  60 m amp
Maximum allowed power dissipation in zener
PZ  300 mW
Maximum current allowed in zener
PZ  VZ (IZ ) max  300 # 103
&
 6 (IZ ) max  300 # 103
&
 (IZ ) max  50 m amp
Given knee current or minimum current in zener
In given circuit

(IZ ) min  5 m amp

I  IZ  I L
I L  I  IZ
(IL) min  I  (IZ ) max
 (60  50) m amp  10 m amp
(IL) max  I  (IZ ) min
 (60  5)  55 m amp

SPECIAL EDITION ( STUDY MATERIAL FORM )

At market Book is available in 3 volume i.e. in 3 book binding
form. But at NODIA Online Store book is available in 10 book
binding form. Each unit of Book is in separate binding.
Available Only at NODIA Online Store

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