Introduction to CAD

J.Raghavendra
13MVD1019
Contents
Introduction
VLSI Design Cycle
Y-Chart
Design Styles
Introduction
What is CAD?
Activity-> uses a computer -> to assist in the creation, Modification, and
analysis of the design
ECAD(Electronic CAD) or EDA(Electronic Design Automation)
Software tools-> designing electronic system-> PCB or IC
VLSI Design Cycle
System Specification [performance, functionality, Physical dimension,
Fabrication Technology, Design Techniques]
Architectural Design[The basic Architecture of the system]
Behavioral Design
Logic Design [RTL description -> simulation and Verification]
Circuit Design [Cells, Macros, Gates, Transistors ->To check the
Correctness and Timing of each component]
Physical Design[ Floor plan, Power planning, Clock distribution structure,
preliminary check, Place and Route, Parasitic extraction
and reduction, SDF generation etc..]
Fabrication [tape out]
Packaging, Testing and Debugging
CAD TOOL Classification
Front-end Tools :
Design Entry, Editors, Simulation, Synthesis, Timing Analysis, DFT Insertion,
Test Generation, . . .
Back-end Tools :
Floor Planning, Place-and-Route, Extraction, LVS (Layout vs. Schematic), LVL
(Layout vs. Logic), ERC, DRC, Pattern Generators, Format Converters, Mask
Graphics, . . .
Major Benefits of CAD
Improved performance and quality of product.
(better engineered products).
Higher productivity of designers.
More flexibility to react to market changes and product modifications.
Provide time to experiment and explore alternatives.
CAD Tool Components
Input Handler
Data structure + Algorithm
Output Handler
File Input / Output Handler
Y-Chart
Each axis represents a domain.
Introduced by Gajski in the year 1983.
The level of abstraction decreases from outside to the center.
Design styles
Full-custom Semi-custom
Full-custom Layout
Different blocks of a circuit can be placed at any location on a silicon wafer as long as all the blocks are
non-overlapping
Full-custom offers the highest performance and lowest part cost (smallest die size) with the
disadvantages of increased design time, complexity, design expense, and highest risk.
Microprocessors were exclusively full-custom, but designers are increasingly turning to semicustom
ASIC techniques in this area too.
Semi-custom Layout
Some parts of a circuit are predesigned and placed on some specific place on the silicon wafer
preferred to design an Application Specific Integrated Circuit
FULL-CUSTOM
The circuit partitioned into collection of sub-circuits
[Functionality]
have several levels of hierarchy
The chip clusters units functional blocks
Allows functional blocks of any size
Functional blocks can be placed at any location on the chip surface without any
restrictions
This style is characterized by the absence of any constraints on the physical design
process
Very compact design
Automating a full-custom design style has a much higher complexity than other
restricted models
Used only when final design must have minimum area and design time is less
Time consuming , inappropriate for very large circuits unless performance or chip size is
of utmost importance
Full-custom structure
I/O Pads
Used to complete the interconnection between different chips or the
interconnection between the chip and the board
Blocks
Placed within the chip area with the objective of minimizing the total area
Enough space should be left between the blocks and top of the blocks
Metal Layers
M1 width < M2 width
Metal Width and Via Sizes are larger for higher metal layers
Die Size
Interconnect area and the total transistor area
Standard Cell
Simpler than Full custom
consist of rectangular cells of the same height
circuit -> several small blocks-> equivalent to some predefined sub circuit(cell)
Collection of cells -> Cell library -> Usually consist of 500-1200 cells.
Cells are placed in rows-> Space between two rows -> channel
channels, space above and below of the cell -> Used for routing
Channel -> Used for interconnection if two cells are in same row or in adjacent
rows
Empty space -> used for interconnection if cells are non adjustment
Feed through -> Empty space between cells in a row
Interconnection steps : Feedthrough assignment followed by routing
Representation of a layout in the standard cell design style is greatly simplified
[not necessary to duplicate the cell information]
non-hierarchical
Well-suited for moderate size circuits and medium production volumes
Physical design- simpler compare to full-custom
Efficient [using modern design tools]
Each cell in the library -> requires highly skilled physical design specialists
Each Cell -> Created with several transistor size and tested
usually takes more than full custom[however it can be reduced if more metal
layers available and with tool optimization
Standard cell structure
Cell library
Gate Arrays
Simplification of standard cell design
All the cells in gate array are identical
Each chip -> An array of identical gates or cells
Cells -> separated by both horizontal and vertical spaces [ horizontal and vertical channels]
Gate array -> each cell may simply be a gate, such as three input NAND gate
Block to cell assignment
Each block in design is mapped or placed onto a prefabricated cell on the chip
during the partitioning/placement phase
Number of partitioned blocks must be less than or equal to the total number of
cells on the chip
After partition -> Interconnection done through channels
Number of tracks allowed for routing in each channel is fixed
Routing phase : complete the connection rather than minimizing the area
Cheaper and easier
non-hierarchical
Routability Simpler compared to standard cell and full-custom design styles
Conceptual Gate Array
FPGA: Field programmable Gate Array
Cells and Interconnect are prefabricated
Consist of horizontal rows of programmable logic blocks -> Interconnected by a
programmable routing network
Cells are more complex than standard cells but all the cells have the same layout
Logic Block
Memory Block [ Programmed to remember the logic table of a function]
Operation
For a given input, the logic block looks up the corresponding output from the logic
table and sets its output line accordingly
By loading different look-up tables, a logic block can be programmed to perform
different functions
K-bit Input, 2
K
bits are required in a logic block
Usually K= 5 or 6 bit is allowed for a logic block
Routing
Channel ->The rows of logic blocks are separated by horizontal routing which contains
predefined wiring segments
Antifuse: connection between horizontal segments
cross fuse: Connection between horizontal and vertical segments
Fuse based FPGAs are not re-programmable
re-programmable FPGAs uses pass transistors instead of fuses
Example:
Circuit partitioned into four sub circuits [P
1
, P
2
, P
3
, P
4
]
Each sub circuit have two inputs and one output
Truth Table for each logic block
P
1
,P
2
,P
3
and P
4
are mapped to logic blocks B
1
,B
4
,B
7
and B
10
respectively
Appropriate antifuses and cross fuses are programmed to implement the entire
circuit
Routing
Four rows of logic blocks
Circles Cross fuses
Rectangles - Antifuse
Sea of Gates
Improved Gate array
The master is filled completely with transistors
The master of the sea-of-gates has a much higher density of logic implemented
on the chip
Comparison between all the styles
Thank You