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Fmea Data&Plan

The document is a process FMEA (Failure Mode and Effects Analysis) for an electronics manufacturing process. It lists several process steps including plating, chemical polishing, photo resist coating, exposure, developing, back coating, and others. For each step it identifies potential defects, effects of defects, causes of defects, occurrence ratings, detection ratings, and risk priority numbers. It also includes an action plan table with process names, defect patterns, FMEA numbers, start and completion dates, and engineers responsible for controlling identified issues. The document provides a breakdown of key process steps in electronics manufacturing, potential failure modes, and plans for addressing higher risk issues.
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0% found this document useful (0 votes)
283 views5 pages

Fmea Data&Plan

The document is a process FMEA (Failure Mode and Effects Analysis) for an electronics manufacturing process. It lists several process steps including plating, chemical polishing, photo resist coating, exposure, developing, back coating, and others. For each step it identifies potential defects, effects of defects, causes of defects, occurrence ratings, detection ratings, and risk priority numbers. It also includes an action plan table with process names, defect patterns, FMEA numbers, start and completion dates, and engineers responsible for controlling identified issues. The document provides a breakdown of key process steps in electronics manufacturing, potential failure modes, and plans for addressing higher risk issues.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as XLS, PDF, TXT or read online on Scribd
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Process FMEA DATA LIST-UP

SP Production II Team
Process
Plating

Chemical polishing

2001-04-18 Rev.0
Function

Requirements

- Prevent Oxidation

- Meet plating thickness spec.

- Make Wire bonding easier

- No visual defect

- Removing anti-oxidation layer


- Decreasing roughness for better Solder
Ball Attaching

- Meet Cu polishing spec.

- Applying Photo resist for

- No uncoated area

circuit developing before exposure

- Meet PR Coating thickness spec.

- Applying UV on PR coated area

- No foreign material on the pattern


- Meet Alignment Spec

Pattern of Defect
- Discoloration

Effect of Defect
- 2nd W/B failed

- unpolished

- Bad Solder Ball Attaching

- overpolished

- Cu thickness too thin

- Uncoating

- Open/pit after etching

- Pattern dimension changed after etching - Spec out after etching


- Common defect(Short, Lead protusion, et - O/S
- Bad P/T Alignment(Overlap Spec out)

Cause of Defect

Effect

occurrence

Defect

RPN

- Moisture on plating bar

75

- Moisture absorbed at storage

50

- Contamination of bake oven

- Unsuitable process

50

18

conditions(Speed,temp,concentration)

18

- Unsuitable coating condition&raw meterial

20

- Unsuitable coating condition

12

- Bad Artwork and storage

20

- Bad Tool&Punching accuracy

16

- Unsatisfied Artwork&Alignment control

16

PR Coating

Exposure

for circuit developing

Developing

- Removing UV exposed area


using chemical for etching
- Applying PR on back side of tape

- Fail on Molding process

- Meet exposure intensity spec.

- Wrong pattern dimension

- Fail in dimension spec after etching

- Unsuitable exposure condition

12

- No undeveloped area

- Short, Lead protusion

- O/S

- Unsuitable developing condition/rincing water contaminated

20

- Meet dimension spec after developing

- Wrong pattern dimension

- Pattern dimension changed after etching

- Unsuitable exposure intensity/developing condition

24

- No bubble

- PI side Half etched after etching

- Half Eg on Ball Land

- Unsuitable BC thickness and dry condition

36

- Meet B/Cthickness Spec

- PI side etched

- Fail in molding process

- Unsuitable B/C condition(viscosity,speed)

24

- PI side foreign material/unstripped

- Solder Ball Attch FAIL(Miss Ball)

- Unsuitable B/C condition(viscosity,speed)

24

- No uncoated area

- PI side etched

- Fail in molding process

- Unsuitable B/C condition(viscosity,speed)

24

- No bleed to Bonding area

- SR bleed out

- W/B Fail

- Poor Screen Mask design/making

24

- Unsuitable printing condition(Alignment)

32

- Poor Screen Mask design/making

24

- Unsuitable printing condition(Alignment)

18

Back Coating
to protect from etching chemical

SR Printing

- Making dam to prevent epoxy bleed to


bonding area at die
attach process

- Meet Width/Thick Spec

- SR Spec out

- Die Attach/Wire Bonding Fail

- Strong adhesion between Ink and Tape

- Plating chemical permeated

- Delamiantion(SR and Tape)

- Unsuitable printing condition

24

Tape Aging

- Restoring Tape temp(room temp)

- No dew on Tape surface

- Bad adhesion

- Bubble at Cu Laminating

- absorbing moisture

45

Punching

- Punch function hole on PI film

- Accurate punching dimension

- Defect at Soler Ball Attaching

- Hole dimension error

- Poor die manufacturing

30

Vacuum dry

- Dry moisture on tape

- Minimize moisture in tape

- Bad adhesion

- Bubble at Cu Laminating

- Poor vacuum

45

Cu Lamination

- Laminating Cu foil on tape

- Meet Alignment spec

- Circuit open/short

- Cu foil slanting to one side

- Poor process control

12

- Visual control

- No transformation
Cure

- For strong adhesion strength between ta - Securing adhesion

- Bad adhesion

- Delamination

- Unsuitable Cure condition

20

Elastomer Attach

- Attach elastomer tape for chip attach

- No unattached area

- Unattached

Chip Crack

- wrong attach condition(Temp.,Pressure,time)

10

Slitting

- Slit multi rows to single row

- Maintain dimention of Cutting width

- Cutting width Over

- Wrong dimension control

- Error in Gang Tool manufacuring

18

Adhesive Lami'

Laminationg adhesive for Heat Sinker atta - Meet spec by Adhesive materials

- Error in laminating process

- Delamination between Heat Sink & Circuit film

- Error attach condition(temp,pressure,time)

50

Tape Lamination

- Attaching carrier Frame for

- Meet Alignment Spec

Circuit&Carrier Frame Misalignment

Chip attach Position Error

- Die Setting Miss

15

package assembly

- No transformation

Warpage

Chip Crack

- Error attach condition(temp,pressure,time)

15

Busbar Punching/Singulation

- Minimize Burr

Burr Spec Over

Wire Bonding Error

- Bad punch die

36

Debussing

Center Alignment

Remark

Process FMEA Action Plan


Team : SP Production II
NO

Precess

Recorder : H.I. Lee


Pattern of Defect

FMEA NO

Start date

Completion date

Engineer

Control or not

1 Precess

Discoloration

01-PLAT-001

01.01.25

01.04.20

Y. K. Cho

Controlled

2 Inspection

Discoloration

01-CUIN-001

01.01.25

01.04.20

Y. K. Cho

Controlled

3 Back coating

Half EG on Back side(tape)

01-BKNT-001

01.05.01

01.05.24

J. M. Shim

Controlled

4 Printing

SR Bleed out

01-PRNT-001

01.05.01

01.05.24

J. M. Shim

Controlled

Rev. 0
Remark

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