Real Time Embedded Systems

EE Department

COMSATS Institute of Information

Technology, Lahore.

Real Time Embedded Systems

(Lab 7 & 8)

Implement the SDRAM Chip with Nios II based system

&
Develop a Micro C/OS-II RTOS application

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Implement the SDRAM Chip with the Nios II based embedded system
&
Develop a Micro C/OS-II RTOS application

Objectives:

In this Lab you will be able to learn:

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The SDRAM Interface with NIOS II system

Timing issues with respect to the SDRAM on the DE2-70 board

The use of Clock Signals IP Core

The Implementation of Micro C/OS-II application using SBT

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Real Time Embedded Systems

Introduction
This document explains how the SDRAM chips on Alteras DE2-70 Development and Education
board can be used with a Nios II system implemented by using the Altera Qsys tool and
familiarizes you with the Nios II Software Build Tools (SBT) for Eclipse and the MicroC/OS-II
development flow. The Nios II SBT for Eclipse offers designers a rich development platform for
Nios II applications. The Nios II SBT for Eclipse enables you to integrate the MicroC/OS-II realtime operating system, giving you the ability to build MicroC/OS-II applications for the Nios II
processor quickly. In this lab we implement the built in MicroC/OS-II application on the NIOS II
based embedded system that uses the SDRAM.

The following contents are involved to perform this lab task.

Lab 6 Nios II based embedded system

The SDRAM Interface

Using the Clock Signals IP Core

Using the Qsys tool to Generate the Nios II System

Integration of the Nios II System into the Quartus II Project

Implement the MicroC/OS-II application using SBT

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Background
The lab 6 explains how the memory in the Cyclone II FPGA chip can be used in the context of a
simple Nios II system. For practical applications it is necessary to have a much larger memory.
The Altera DE2-70 board contains 2 SDRAM chips that can each store 32 Mbytes of data. Each
chip is organized as 4M x 16 bits x 4 banks. The SDRAM chips require careful timing control.
To provide access to the SDRAM chips, the Qsys tool implements an SDRAM Controller circuit.
This circuit generates the signals needed to deal with the SDRAM chips.
Doing this lab, the reader will learn about:
Using the Qsys tool to include an SDRAM interface for a Nios II-based system
Timing issues with respect to the SDRAM on the DE2-70 board
The SDRAM Interface
The two SDRAM chips on the DE2-70 board each have a capacity of 256Mbits (32Mbytes).
Each chip is organized as 4M x 16 bits x 4 banks. The signals needed to communicate with a
chip are shown in Figure 1. All of the signals, except the clock, can be provided by the SDRAM
Controller that can be generated by using the Qsys tool. The clock signal is provided separately.
It has to meet the clock-skew requirements as explained later in the section below. Note that
some signals are active low, which is denoted by the suffix N.

Figure 1. The SDRAM signals

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Using the Qsys tool to Generate the Nios II System

Our starting point will be the Nios II system discussed in the lab 6. We specified the system
shown in Figure 2.

Figure 2. The Nios II system defined in Lab 6

To add the SDRAM, in the window of Figure 2, select Memories and Memory Controllers >
External Memory Interfaces > SDRAM Interfaces > SDRAM Controller and click Add. A
window depicted in Figure 3 appears. Set the Data Width parameter to 16 bits, the Row Width to
13 bits, the Column Width to 9 bits, and leave the default values for the rest.

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Select the Timing tab to get to the window in Figure 4. Configure the SDRAM timing
parameters by setting the refresh command rate to once every 7.8125 microseconds and the delay
after power up to 200 microseconds. Click Finish. Now, in the window of Figure 2, there will be
a sdram module added to the design.

Figure 3. Add the SDRAM Controller

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Figure 4. SDRAM Timings

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Using the Clock Signals IP Core

If we use the 50-MHz system clock, CLOCK_50, as the clock signal for the SDRAM chips. This
approach leads to a potential timing problem caused by the clock skew on the DE2-70 board.
Due to the clock skew problem mentioned above, the Nios II processor may be unable to
properly access the SDRAM chip. The clock skew depends on physical characteristics of the
DE2-70 board. For proper operation of the SDRAM chip, it is necessary that its clock signal,
DRAM_CLK, leads the Nios II system clock, CLOCK_50, by 3 nanoseconds. This can be
accomplished by using a phase-locked loop (PLL) circuit which can be manually created using
the Mega Wizard plug-in. It can also be created automatically using the Clock Signals IP core
provided by the University Program. We will use the latter method in this lab.
To add the Clock Signals IP core, in the Qsys tool window of Figure 2, select University
Program > Clocks Signals for DE-Series Board Peripherals and click Add. A window
depicted in Figure 5 appears. Select DE2-70 from the DE Board drop-down list and uncheck
Video and Audio clocks as these peripherals are not used in this lab.

Figure 5. Clock Signals IP Core

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Click Finish to return to the window in Figure 2. Connect the clock and reset output of system
clock clk_0 to the clock and reset inputs of the Clock Signal IP core. All other IP cores
(including the SDRAM) should be adjusted to use the sys_clk output of the Clock Signal core
instead of the system clock. Rename the Clock Signal core to clocks and export the sdram_clk
signal under the name sdram_clk. The final system is shown in Figure 6.

Figure 6. The final Nios II system

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Select the command System > Assign Base Addresses to produce the assignment shown in
Figure 6. To make use of the SDRAM, we need to configure the reset vector and exception
vector of the Nios II processor. Right-click on the cpu and then select Edit to reach the window
in Figure 7. Select sdram to be the memory device for both reset vector and exception vector, as
shown in the figure 7. Click Finish to return to the System Contents tab and regenerate the
system.

Figure 7. Define the reset vector and the exception vector.

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Integration of the Nios II System into the Quartus II Project

After generating the Nios II system using Qsys, you integrate it into the Quartus II project. Using
the Quartus II software, you perform all tasks required to create the final FPGA hardware design.
In this section you perform the following steps to complete the hardware design:

Instantiate the Qsys system module in the Quartus II project.

Assign pin locations.

Compile the Quartus II project.

Pin assignments for the LEDs

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SDRAM pin assignments

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The complete board design file schematic is shown in the figure 8.

Figure 8: Completed board design file schematic

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Develop a Micro C/OS-II application Using the Nios II SBT for Eclipse
In this section, you use the Nios II SBT for Eclipse to compile a Hello Micro C/OS-II example
software program to run on the Nios II hardware system configured in the FPGA on your
development board. You create a new software project, build it, and run it on the target
hardware. This section presents the software development flow to demonstrate software running
on the hardware system you created in previous sections.
In this section, you perform the following actions:
Create a new Nios II Micro C/OS-II application and BSP project.
Compile the project.
Run the program on the target hardware.

When the target hardware starts running the program, the Nios II Console view
messages as shown in figure 9.

displays

Figure 9. Console view displaying Nios II hardware output

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Grading Lab(7 & 8)

Total Marks
Lab performance

Lab participation

Behavior in the Lab

Viva

Total

10

Date

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Obtained Marks

Instructor Signature

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