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Lect32 2state Minimization

The document discusses state minimization techniques for finite state machines (FSMs). It introduces the concept of state equivalence and describes a partitioning minimization procedure to determine which states are equivalent. The procedure works by iteratively splitting the states into partitions with subsets that are not equivalent. An example applies this procedure to a sample state table to arrive at a minimized representation with fewer states. The goal is to reduce the number of states, and thus complexity, of an FSM implementation.

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69 views6 pages

Lect32 2state Minimization

The document discusses state minimization techniques for finite state machines (FSMs). It introduces the concept of state equivalence and describes a partitioning minimization procedure to determine which states are equivalent. The procedure works by iteratively splitting the states into partitions with subsets that are not equivalent. An example applies this procedure to a sample state table to arrive at a minimized representation with fewer states. The goal is to reduce the number of states, and thus complexity, of an FSM implementation.

Uploaded by

purwant10168
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ECE380 Digital Logic

State Minimization

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 32-1

State minimization
• For simple FSMs, it is easy to see from the state
diagram that the number of states used is the
minimum possible
– FSMs for counters are good examples
• For more complex FSMs, it is likely that an initial
state diagram may have more states than are
necessary to perform a required function
• Minimizing states is of interest because fewer states
implies fewer flip-flops to implement the circuit
– Complexity of combinational logic may also be reduced
• Instead of trying to show which states are
equivalent, it is often easier to show which states are
definitely not equivalent
– This can be exploited to define a minimization procedure

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 32-2

1
State equivalence
• Definition: Two states Si and Sj are equivalent if
and only if for every possible input sequence, the
same output sequence will be produced regardless of
whether Si or Sj is the initial state
• If an input w=0 is applied to an FSM in state Si and
the FSM transitions to state Su, then Su is termed a
0-successor of Si
• Similarly, if w=1 and the FSM transitions to Sy, then
Sy is a 1-successor of Si
• The successors of Si are its k-successors
• With one input, k can only be 0 or 1, but if there are
multiple inputs then k represents all the valuations
of the inputs

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 32-3

Partitioning minimization
• From the equivalence definition, if Si and Sj are
equivalent then their corresponding k-successors
are also equivalent
• Using this, we can construct a minimization
procedure that involves considering the states of the
machine as a set and then breaking that set into
partitions that comprise subsets that are definitely
not equivalent
• Definition: A partition consists of one or more
blocks, where each block comprises a subset of
states that may be equivalent, but the states in one
block are definitely not equivalent to the states in
other blocks

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 32-4

2
Partition minimization example
• Consider the following state table

Present Next state Output


state w = 0 w = 1 z

A B C 1
B D F 1
C F E 0
D B G 1
E F C 0
F E D 0
G F G 0

An initial partition contains all the states in a single block


P1=(ABCDEFG)
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 32-5

Partition minimization example


• The next partition separates the states that
have different outputs
– P2=(ABD)(CEFG)
• Now consider all 0- and 1-successors of the
states in each block
– For (ABD), the 0-successors are (BDB)
• Since these are all in the same block we must still
consider A, B, and D equivalent
– The 1-successors of (ABD) are (CFG)
• We must still consider A, B, and D equivalent
– Now consider the (CEFG) block

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 32-6

3
Partition minimization example
• P2=(ABD)(CEFG)
• For (CEFG), the 0-successors are (FEFF) which are
all in the same block in P2
– C, E, F, and G must still be considered equivalent
• The 1-successors of (CEFG) are (ECDG)
– Since these are not in the same block in P2 then at least one
of the states in (CEFG) is not equivalent to the others
• State F must be different from C, E and G because its 1-
successor,D, is in a different block than E, C, and G
• Therefore, P3=(ABD)(CEG)(F)
• At this point, we know that state F is unique since it
is in a block by itself

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 32-7

Partition minimization example


• P3=(ABD)(CEG)(F)
• The process repeats yielding the following
– 0-successors of (ABD) are (BDB)
• A, B and D are still considered equivalent
– 1-successors of (ABD) are (CFG), which are not in
the same block
• B cannot be equivalent to A and D since F is in a different
block than C and G
– The 0- and 1-successors of (CEG) are (FFF) and
(ECG)
• C, E, and G must still be considered equivalent
• Thus, P4=(AD)(B)(CEG)(F)

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 32-8

4
Partition minimization example
• If we repeat the process to check the 0- and
1-successors of the blocks (AD) and (CEG),
we find that
– P5=(AD)(B)(CEG)(F)
• Since P5=P4 and no new blocks are
generated, it follows that states in each block
are equivalent
– A and D are equivalent
– C, E, and G are equivalent

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 32-9

Partition minimization example


• The state table can be rewritten, removing
the rows for D, E and G and replacing all
occurrences of D with A and all occurrences
of E or G with C
• The resulting state table is as follows

Present Nextstate Output


state w = 0 w = 1 z

A B C 1
B A F 1
C F C 0
F C A 0

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 32-10

5
Design Example
• Determine which states (if any) are equivalent in the
following Moore state diagram
reset

A/0
0 1
0 1
B/0 C/0
1 0
0 D/0 E/0 0
1 1
1 F/1 0

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 32-11

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