ECE380 Digital Logic

Combinatorial Circuit Building

Blocks:
Multiplexers

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-1

Multiplexers
• A multiplexer (MUX) circuit has
– A number of data inputs
– One (or more) select inputs
– One output
• It passes the signal value on one of its data inputs to
its output based on the value(s) of the select
signal(s)
s

s f(s,x1,x2)
x1 0 0 x1
f=x1s’+x2s 1 x2
x2 1

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-2

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Multiplexer implementations

y f

The preferred
implementation

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-3

4-input multiplexer
• A 4-input multiplexer ‘selects’ one of four data inputs
to be output based on the values of 2 select lines

s0
s1 s0 f
s1
0 0 w0
w0 00 0 1 w1
w1 01 1 0 w2
f
w2 10 1 1 w3
w3 11
f=s1’s0’w0+s1’s0w1+s1s0’w2+s1s0w3

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-4

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Building a 4-input MUX
• A 4-input multiplexer can be constructed using 2-
input multiplexers
s0

w0 0
s1

w1 1
0
f
1
w2 0

w3 1

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-5

MUX application (a 2x2 crossbar)

• A circuit with n inputs and k s
outputs whose function is to
provide a capability to x1 y1
connect any input to any x2 y2
output is called a nxk
crossbar switch
– With 2 inputs and 2 outputs, x1 0
it is called a 2x2 crossbar y1
– Useful in applications where 1
it is necessary to connect
one set of wires to another
s
set of wires, where the
connection pattern changes
from time to time x2 0
y2
– Telephone switching
networks are an example 1

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-6

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MUX application (prog. switch)
• In programmable devices (PLDs, CPLDs and FPGAs)
programmable switches connect wires inside the
device
– These can be implemented with multiplexers
storage
0/1 0/1
cell

i1 i1
f f
i2 i2

An FPGA logic block 0/1 0/1

with programmable inputs
MUX implementation
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-7

Logic functions using MUXs

• MUXs can be used to synthesize logic functions
– The LUT implementations use MUXs to select a (constant)
value from a look-up table
• Consider the XOR function

a
a b f b

0 0 0 0 00
0 1 1 1 01
f
1 0 1 1 10
1 1 0 0 11

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-8

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Logic functions using MUXs
• The previous XOR solution is not particularly efficient

a b f
0 0 0 a f
when a=0, f=b
0 1 1 0 b
1 0 1 1 b’
when a=1, f=b’
1 1 0
a

b 0
f
1

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-9

Logic functions using MUXs

• Implement the following with a 2-input MUX
and any additional logic gates

a b f
0 0 1
0 1 1
1 0 0
1 1 1

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-10

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Logic functions using MUXs
• A 3-input XOR can be implemented with two 2-input
MUXs
x y z f
0 0 0 0
0 0 1 1 y
y⊕z x
0 1 0 1
0 1 1 0 z 0
1 0 0 1 0
1 f
1 0 1 0 1
(y⊕z)’
1 1 0 0
1 1 1 1

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-11

Logic functions using MUXs

• Implement the following with 2-input MUXs
and any additional logic gates
x y z f
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-12

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Shannon’s expansion theorem
• Any Boolean function f(w1,…,wn) can be
written in the form
f(w1,…,wn)=(w1)’ ⋅ f(0,w2,…,wn)+(w1) ⋅ f(1,w2,…,wn)
• The expansion can be done using any of the
n variables
• If f(w1,w2,w3)= w1w2+w1w3+w2w3
– Expanding this in terms of w1 gives
f(w1,w2,w3)= w1(w2+w3)+(w1)’(w2w3)

f when w1=1 f when w1=0

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-13

Shannon’s expansion example

w w w f
1 2 3
0 0 0 0 w f
1
0 0 1 0 w w
0 2 3
0 1 0 0 w +w
1 2 3
0 1 1 1
1 0 0 0
1 0 1 1 w
w 1
1 1 0 1 w2
3
1 1 1 1 f

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-14

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Shannon’s expansion example

x y z f f=x’y’z’+x’y’z+x’yz+xy’z’+xy’z
0 0 0 1
0 0 1 1 choose x as the expansion variable
0 1 0 0
0 1 1 1 f=x’(y’z’+y’z+yz)+x(y’z’+y’z)
1 0 0 1 f=x’(y’+z)+x(y’)
1 0 1 1
1 1 0 0 z x
1 1 1 0
y f

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-15

Shannon’s expansion example

x y z f f=x’y’z’+x’y’z+x’yz+xy’z’+xy’z
0 0 0 1
0 0 1 1 choose z as the expansion variable
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 21-16