Digital Logic Design
Practice Homework-2
1.
Given is a Boolean function F(A,B,C,D) = (0, 1, 2, 5, 6, 7, 8, 9, 10)
a. Draw the K-map for this function F.
i. List the prime implicants
ii. List the essential prime implicants
iii. Derive the reduced SOP expression for F from the K-map
iv. Draw the AND-OR gate-level schematic for the reduced SOP expression.
v. Draw the NAND-NAND gate-level schematic for the reduced SOP expression. (Apply the bubble
method)
vi. Draw the NOR-NOR gate-level schematic for the reduced SOP expression. (Apply the bubble method)
b. Draw the K-map for the function F
i. List the prime implicants
ii. List the essential prime implicants
iii. Derive the reduced SOP expression for F from the K-map
iv. Derive the reduced POS expression for F, from the answer to the above question (Question-1(b)(iii))
c. Using Quine-McCluskey tabular method find the reduced SOP expression for function F. Show your steps,
including the appropriate tables (combination table, prime implicants table, reduced prime implicants table, etc).
Also mention the essential prime implicants, etc.
2.
Given is a Boolean function F(A,B,C,D,E) = (0, 2, 4, 6, 7, 8, 10, 16, 18, 23, 24, 26)
a. Draw the K-map for this function F.
i. List the prime implicants
ii. List the essential prime implicants
iii. Derive the reduced SOP expression for F from the K-map
iv. Draw the AND-OR gate-level schematic for the reduced SOP expression.
v. Draw the NAND-NAND gate-level schematic for the reduced SOP expression. (Apply the bubble
method)
vi. Draw the NOR-NOR gate-level schematic for the reduced SOP expression. (Apply the bubble method)
b. Draw the K-map for the function F
i. List the prime implicants
ii. List the essential prime implicants
iii. Derive the reduced SOP expression for F from the K-map
iv. Derive the reduced POS expression for F, from the answer to the above question (Question-2(b)(iii))
c. Using Quine-McCluskey tabular method find the reduced SOP expression for function F. Show your steps,
including the appropriate tables (combination table, prime implicants table, reduced prime implicants table, etc).
Also mention the essential prime implicants, etc.
Digital Logic Design
3.
Given is a multi-stage gate-level schematic in Fig.1
Fig. 1
a.
b.
c.
Redraw this schematic with only NAND gates, i.e. a NAND-NAND-NAND- implementation. (Apply the
bubble method) (You may include/delete inverters if necessary)
Redraw this schematic with only NOR gates, i.e. a NOR-NOR-NOR- implementation. (Apply the bubble
method) (You may include/delete inverters if necessary)
From Fig.1, obtain/write the Boolean expression for function F. (Do not reduce the expression)
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Following questions are from the Book (Digital Design, by M. Mano and M. Ciletti, 4th Edition)
Digital Logic Design
Digital Logic Design
