2014 IEEE Compound Semiconductor Integrated Circuit Symposium

2014 IEEE CSIC Symposium

SPONSORED BY:

The IEEE Electron Devices Society

TECHNICALLY CO-SPONSORED BY:

The IEEE Solid State Circuits Society

The IEEE Microwave Theory & Techniques Society

INTEGRATED CIRCUITS IN GaAs, InP,

SiGe, GaN and OTHER COMPOUND
SEMICONDUCTORS

TECHNICAL
DIGEST
2014
La Jolla, CA, USA
1922 October 2014
ISBN: 978-1-4799-3622-9

2014 IEEE

Catalogue: CFP14GAA-ART

2014 IEEE Compound Semiconductor Integrated Circuit Symposium

(CSICS)
Copyright 2014 by the Institute of Electrical and Electronic Engineers, Inc.
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CHAIRS MESSAGE

It is with great pleasure that I invite you to be a part of the 2014 IEEE Compound Semiconductor IC Symposium
(CSICS). Thanks to the efforts of the many dedicated volunteers on the organizing committee and the generous
support of the IEEE Electron Devices, Microwave Theory and Techniques, and Solid-State Circuits Societies,
CSICS is proud to offer a world class technical program. For this 36th edition, CSICS will be held on October 19-22
in La Jolla, San Diego, California.
From its origins in 1978 as an international gathering for distinguished experts to present their latest results in GaAs
IC technology and Monolithic Microwave Integrated Circuit design, the symposium has become much more and
now embraces GaN, InP, SiGe, nanoscale CMOS, and many other emerging technologies. This convergence allows
CSICS to offer a perfect blend of state of the art IC performance, innovative design techniques, and advanced device
technologies. There are no other events in the world where you can see GaN HPAs, InP THz PAs, 100 Gb/s
CMOS/SiGe transceivers, GaN HEMT power devices, and advances in compact modeling all presented alongside
each other.
Following its tradition, CSICS will include presentations from worldwide submissions on all aspects of the
technology, from materials and device fabrication and modeling to IC design and testing, high-volume
manufacturing, and system applications. It will also feature the very latest results in RF/microwave, millimeterwave, THz, analog mixed signal, and optoelectronic integrated circuits.
On Sunday prior to the symposium opening, CSICS will offer two topical short courses: GaN HEMT Device
Modeling and Fundamentals of Power Conversion and Envelope Tracking. Taught by leading experts, they are
intended for both technologists and IC designers who seek a comprehensive understanding of the latest trends and
techniques in GaN technology and circuit design. CSICS is also very proud to present two Primer courses this year
instead of the customary single course: Fundamentals of A/D Converters and Introduction to Si RFIC design.
Both tutorials introduce the key concepts, techniques and practices for Si mixed signal and RF circuit design and are
guaranteed to provide valuable insight for designers of all backgrounds.
As a complement to the technical program, the symposium includes numerous social events that allow participants
to interact and network in a relaxed setting. These include the Sunday Evening Opening Reception, the Monday
Evening Exhibition Opening Reception, and the Technology Exhibition Luncheon on Tuesday. CSICS also offers a
daily breakfast and AM/PM coffee breaks on Monday through to Wednesday.
Please join us at the Compound Semiconductor IC Symposium in beautiful La Jolla, California.
Douglas S. McPherson
2014 IEEE CSICS Chair

iii

CORPORATE BENEFACTORS
This year, we are pleased to continue with the IEEE Compound Semiconductor IC Symposium Corporate Benefactors Program.
This program allows companies interested in compound semiconductors to show their support of the Symposium by making
contributions towards the cost of some of our social events.
These additional resources enable the Symposium to increase the quality of our event, as well as allowing companies an
opportunity for some tasteful promotional activities. To discuss any of the benefactor opportunities in more depth, please contact:
Douglas S. McPherson
Tel: +1-613-670-3371
E-mail: dmcphers@ciena.com
As of this printing, the Corporate Benefactors for the 2014 Compound Semiconductor IC Symposium are as follows.

Gold Level Benefactor

RF Micro Devices, Inc.

Silver Level Benefactors

Keysight Technologies

TriQuint

OMMIC

The Symposium Web Site www.csics.org has become a critical tool for the dissemination of information to prospective attendees,
committee members, sponsors of the Symposium, and technical exhibitors. Every year, the web site must be updated and
maintained to effectively serve this purpose. We would like to acknowledge the following benefactor for providing the
Symposium web site support for the 2014 CSIC Symposium:

Comments regarding the web site or any publicity materials should be directed to the Publicity Chair, Brian Moser
(bmoser@rfmd.com). Links to our corporate benefactors appear on our symposium website.

iv

2014 IEEE CSICS SYMPOSIUM ORGANIZERS

EXECUTIVE COMMITTEE
Douglas S. McPherson
Symposium General Chair
Ciena Corporation
Ottawa, ON, Canada

Charles Campbell
Technical Program Chair
TriQuint Semiconductor
Richardson, TX

Harris Moyer
Technical Program Vice Chair
HRL Laboratories, LLC
Malibu, CA

Jim Carroll
Local Arrangements Chair
NI-AWR GROUP
Dallas, TX

Douglas S. McPherson
Symposium Treasurer
Ciena Corporation
Ottawa, ON, Canada

Brian Moser
Symposium Publicity Chair
RFMD
Greensboro, NC

Peter Zampardi
Exhibit Chair
RFMD
Westlake Village, CA

Bruce Green
Publications Chair
Freescale Semiconductor
Tempe, AZ

Francois Colomb
Chair, Emeritus
Raytheon
Andover, MA

David Osika
Webmaster
Anadigics, Inc.
Warren, NJ

OVERSEAS ADVISORS
Marc Rocchi
OMMIC
Limeil Brevannes, France

Kazuya Yamamoto
Mitsubishi Electric Corporation
Hyogo, Japan

Tomoya Kaneko
NEC Corporation
Kawasaki, Japan

TECHNICAL PROGRAM COMMITTEE

Avram Bar-Cohen

University of Maryland/DARPA-MT0

Douglas McPherson

Ciena

James Buckwalter

University of California San Diego

Brian Moser

RFMD

Charles Campbell

TriQuint Semiconductor

Harris Moyer

HRL Laboratories

Jim Carroll

NI-AWR GROUP

Munehiko Nagatani

NTT Corporation

Shuoqi Chen

TriQuint Semiconductor

Arun Natarajan

Oregon State University

Myung-Jun Choe

Teledyne Scientific Company

Th Linh Nguyen

Finisar Corporation

Kenneth Chu

BAE Systems

Sean Nicolson

Broadcom

Gilberto De la Rosa

Anadigics Incorporated

Marc Rocchi

OMMIC

Bruce Green

Freescale Semiconductor

Mark Rodwell

University of California Santa Barbara

Yuriy Greshishchev

Ciena Corporation

Paul Rosenthal

Boeing Satellite Development Center

Zachary Griffith

Teledyne Scientific Company

Dave Runton

Nitronex LLC

Hossein Hashemi

University of Southern California

Michael Schroeter

University of California San Diego

Steve Huettner

Nuvotronics LLC

Shahriar Shahramian

Alcatel-Lucent

Kazutaka Inoue

Sumitomo

Craig Steinbeiser

TriQuint Semiconductor

Rob Jones

Raytheon Company

Paul Tasker

Cardiff University

Rik Jos

NXP Semiconductors

Han Wui Then

Intel Corporation

Tomoya Kaneko

NEC Corporation

Frank Traut

Hittite Microwave Corporation

Hooman Kazemi

Nuvotronics LLC

Frank van Vliet

TNO

Waleed Khalil

The Ohio State University

Noriyuki Watanabe

NTT Photonics Labs

Faramarz Kharabi

RFMD

Simon Wood

Cree

Donald Kimball

MaXentric Technologies

Barry Wu

Agilent Technologies

Kazuaki Kunihiro

NEC Corporation

Kazuya Yamamoto

Mitsubishi Electric Corporation

Kumar Lakshmikumar

Cisco Systems

Peter Zampardi

RFMD

Simon Mahon

MA/Com Technology Solutions

Qi Zhang

Hittite Microwave Corporation

Joseph Maurer

Booz Allen Hamilton

IEEE ADVISORS
Shana Ramandi
IEEE Meeting & Conference Management
Piscataway, NJ

Sherry Russ Sills

Director, Event Management Services
IEEE Meeting & Conference Management
Piscataway, NJ

Jean Bae
EDS Conference Administrator
IEEE Electron Devices Society
Piscataway, NJ

Chris Jannuzzi
EDS Exective Director
IEEE Electron Devices Society
Piscataway, NJ

CONFERENCE MANAGEMENT
Shana Ramandi
IEEE Meeting & Conference Management
445 Hoes Lane, Piscataway, NJ 08854 USA
Phone: + 1-732-465-5809
Email: s.ramandi@ieee.org

vi

Table of Contents
SESSION A: Plenary Session
Chairpersons: Harris Moyer, HRL Laboratories, LLC
Jim Carroll, NI-AWR Group
A.1

Evolution of Multi-Gigabit Wireline Transceivers in CMOS ......................................................................................... 1

Ichiro Fujimori

A.2

FD-SOI Technology Development and Key Devices Characteristics for Fast,

Power Efficient, Low Voltage SoCs ................................................................................................................................... 5
Joel Hartmann

A.3

Materials and Integration Strategies for Modern RF Integrated Circuits ..................................................................... 9

Daniel S. Green, Carl L. Dohrman, Avinash S. Kane and Tsu-Hsi Chang

A.4

Future of GaN RF Technology in Europe ....................................................................................................................... 13

H. Blanck, J. Splettster and D. Floriot

A.5

GaN for Next Generation Electronics ............................................................................................................................. 17

Paul Saunier

SESSION B: Advanced Low Noise and Mixer Technology

Chairpersons: Gilberto A. De la Rosa, Anadigics
Tomoya Kaneko, NEC
B.1

An InP MMIC Process Optimized for Low Noise at Cryo ............................................................................................ 21

P. . Nilsson, J. Schleeh, N. Wadefalk, J. P. Starski, H. Rodilla,
G. Alestig, J. Halonen, B. Nilsson, H. Zirath and J. Grahn

B.2

Single Chip RF Variable Gain Low Noise Amplifier ..................................................................................................... 25

Bin Hou, Yibing Zhao, Eric Newman and Shuyun Zhang

B.3

A 0.05-26 GHz Direct Conversion I/Q Modulator MMIC............................................................................................. 29

Eric W. Iverson and Milton Feng

B.4

A up to 100 GHz Broadband Mixer with Cascaded Distributed Amplifier ................................................................. 33

Yihu Li, Goh Wang Ling and Yong-Zhong Xiong

SESSION C: Thermal Management of GaN Devices

Chairpersons: Hooman Kazemi, Nuvotronics
Avinash Kane, Booz Allen Hamilton
C.1

Optimizing GaN-on-Diamond Transistor Geometry for Maximum Output Power ................................................... 37

J. W. Pomeroy and M. Kuball

C.2

Progress on Phase Separation Microfluidics .................................................................................................................. 41

Damena D. Agonafer, James Palko, Yoonjin Won, Ken Lopez, Tom Dusseault,
Julie Gires, Mehdi Asheghi, Juan G. Santiago and Kenneth E. Goodson

vii

C.3

High Resolution Thermal Characterization and Simulation of Power AlGaN/GaN HEMTs Using
Micro-Raman Thermography and 800 Picosecond Transient Thermoreflectance Imaging ...................................... 45
Kerry Maize, Georges Pavlidis, Eric Heller, Luke Yates, Dustin Kendig,
Samual Graham and Ali Shakouri

C.4

Thermal Interface Resistance Measurements for GaN-on-Diamond Composite Substrates ..................................... 53

Jungwan Cho, Yoonjin Won, Daniel Francis, Mehdi Asheghi and Kenneth E. Goodson

C.5

Microfluidic Heat Exchangers for High Power Density GaN on SiC ........................................................................... 57
Yoonjin Won, Farzad Houshmand, Damena Agonafer, Mehdi Asheghi and Kenneth E. Goodson

SESSION D: mm-Wave & THz Amplifiers

Chairpersons: Arun Natarajan, Oregon State University
Hooman Kazemi, Nuvotronics LLC
D.1

A 23.2dBm at 210GHz to 21.0dBm at 235GHz 16-Way PA-Cell Combined InP HBT SSPA MMIC........................ 62
Zach Griffith, Miguel Urteaga, Petra Rowell and Richard Pierson

D.2

Backside Process Free Broadband Amplifier MMICs at D-Band and H-Band

in 20 nm mHEMT Technology......................................................................................................................................... 66
Thomas Merkle, Arnulf Leuther, Stefan Koch, Ingmar Kallfass, Axel Tessmann,
Sandrine Wagner, Hermann Massler, Michael Schlechtweg and Oliver Ambacher

D.3

A Broadband 220-320 GHz Medium Power Amplifier Module .................................................................................... 70

A. Tessmann, A. Leuther, V. Hurm, H. Massler, S. Wagner, M. Kuri,
M. Zink, M. Riessle, H.-P. Stulz, M. Schlechtweg and O. Ambacher

D.4

A >200mW SSPA from 76-94GHz, with Peak 28.9% PAE at 86GHz .......................................................................... 74
Zach Griffith, Miguel Urteaga, Petra Rowell and Richard Pierson

SESSION E: Advanced Optical Modulators

Chairpersons: Craig Steinbeiser, TriQuint Semiconductor
Munehiko Nagatani, NTT Photonics Laboratories
E.1

Linear Optical Modulator for DAC-Based Coherent Fiber Communications Systems .............................................. 78
Hiroshi Yamazaki

E.2

A Compact Low-Power 224-Gb/s DP-16QAM Modulator Module with InP-Based

Modulator and Linear Driver ICs ................................................................................................................................... 82
Naoki Itabashi, Taizo Tatsumi, Tomoko Ikagawa, Naoya Kono, Morihiro Seki, Keiji Tanaka,
Kazuhiro Yamaji, Yasushi Fujimura, Katsumi Uesaka, Takashi Nakabayashi,
Hajime Shoji and Shoichi Ogita

E.3

Silicon Photonic Modulator Based on a MOS-Capacitor and a CMOS Driver ........................................................... 86

M. Webster, C. Appel, P. Gothoskar, S. Sunder, B. Dama and K. Shastri

E.4

Gallium Arsenide Electro-Optic Modulators ................................................................................................................. 90

R. G. Walker, M. F. O'Keefe, N. Cameron, H. Ereifej and T. Brast

viii

SESSION F: mm-Wave & THz Arrays

Chairpersons: Shahriar Shahramian, Bell Laboratories
Kazuya Yamamoto, Mitsubishi Electric
F.1

Wafer-Scale Millimeter-Wave Phased-Array RFICs .................................................................................................... 94

Gabriel M. Rebeiz, Woorim Shin, Faith Golcuk, Ozgur Inac,
Samet Zihir, Ozan Gurbuz, Jennifer Edwards and Tumay Kanar

F.2

245 GHz SiGe Transmitter Array for Gas Spectroscopy .............................................................................................. 98

Klaus Schmalz, Johannes Borngrber, Wojciech Debski, Mohamed Elkhouly,
Ruoyu Wang, Philipp Neumaier and Heinz-Wilhelm Hbers

F.3

A Compact 340 GHz 2x4 Patch Array with Integrated Subharmonic Gilber
Core Mixer as a Building Block for Multi-Pixel Imaging Frontends ......................................................................... 102
Yogesh Karandikar, Herbert Zirath, Yu Yan and Vessen Vassilev

SESSION G: Emerging Technologies and Devices

Chairpersons: Paul Rosenthal, Boeing
Han Wui Then, Intel Corp
G.1

Diverse Accessible Heterogeneous Integration (DAHI) at Northrop Grumman

Aerospace Systems (NGAS) ........................................................................................................................................... 106
Augusto Gutierrez-Aitken, Kelly Hennig, Dennis Scott, Ken Sato, Wesley Chan, Benjamin Poust,
Xiang Zeng, Khanh Thai, Eric Nakamura, Eric Kaneshiro, Nancy Lin, Cedric Monier,
Ioulia Smorchkova, Bert Oyama, Aaron Oki, Reynold Kagiwada and Greg Chao

G.2

Enabling Power-Efficient Designs with III-V Tunnel FETs ........................................................................................ 110

Moon Seok Kim, Huichu Liu, Karthik Swaminathan, Xueqing Li, Suman Datta
and Vijaykrishnan Narayanan

G.3

Device Perspective on 2D Materials .............................................................................................................................. 114

Peide D. Ye

SESSION H: High-Speed Optical Communication Components

Chairpersons: TheLinh Nguyen, Finisar
Yuriy Greshishchev, Ciena Corporation
H.1

Advances on III-V on Silicon DBR and DFB Lasers for WDM Optical Interconnects
and Associated Heterogeneous Integration 200mm-Wafer-Scale Technology .......................................................... 118
S. Menezo, H. Duprez, A. Descos, D. Bordel, L. Sanchez, P. Brianceau, L. Fulbert,
V. Carron and B. Ben Bakir

H.2

Optical Phase-Locking and Wavelength Synthesis ...................................................................................................... 124

M. J. W. Rodwell, H. C. Park, M. Piels, M. Lu, A. Sivananthan, E. Bloch, Z. Griffith,
M. Uteaga, L. Johansson, J. E. Bowers and L. A. Coldren

H.3

InP DHBT Mux-Drivers for Very High Symbol Rate Optical Communications ...................................................... 128
J. Godin, J.-Y. Dupuy, F. Jorge, F. Blache, M. Riet, V. Nodjiadjim, P. Berdaguer
B. Duval and A. Konczykowska

H.4

A 25Gb/S Common-Cathode VCSEL Driver ............................................................................................................... 132

Kwan Ting Ng, Yeung Bun Choi and Keh Chung Wang

ix

SESSION I: High Efficiency Power Amplifier Architectures

Chairpersons: David W. Runton, M/A-COM Tech. Solutions Inc.
Rik Jos, NXP Semiconductors
I.1

Power Amplifier Design Optimized for Envelope Tracking ....................................................................................... 136

Gayle Fran Collins, Jeremy Fisher, Fabian Radulescu, Jeff Barner,
Scott Sheppard, Rick Worley and Don Kimball

I.2

GaN Technology in Base Stations - Why and When? .................................................................................................. 140

Eric Higham

I.3

Development of High-Efficiency X-Band Outphasing Transmitter............................................................................ 145

Chenggang Xie, David Cripe, John Reyland, Don Landt and Anders Walker

I.4

Broadband Doherty Alternative with Filter Design Considerations .......................................................................... 149

Jeff Jones, Basim Noori, Jeff Frei and Enver Krvavac

SESSION J: GaN Modeling

Chairpersons: Faramarz Kharabi, RFMD
Kenneth K. Chu, BAE Systems
J.1

Status of the GaN HEMT Standardization Effort at the Compact Model Coalition ................................................ 153
Samuel D. Mertens

J.2

Symmetrical Modeling of GaN HEMTS ....................................................................................................................... 157

Ankur Prasad, Christian Fager, Mattias Thorsell, Christer M. Andersson and Klas Yhland

J.3

First Pass Multi Cell Modeling Strategy for GaN Package Devices ........................................................................... 161
Subrata Halder, John McMacken and Joseph Gering

J.4

Model Development for Monolithically-Integrated E/D-Mode Millimeter-Wave

InAlN/AlN/GaN HEMTs ................................................................................................................................................ 165
Jun Ren, Bo Song, Huili Grace Xing, Shuoqi Chen, Andrew Ketterson, Edward Beam,
Tso-Min Chou, Manyam Pilla, Hua-Quen Tserng, Xiang Gao, Paul Saunier and Patrick Fay

SESSION K: mm-Wave & THz Subsystems

Chairpersons: Frank E. van Vliet, TNO
Marc Rocchi, OMMIC
K.1

SiGe Transmitter and Receiver Circuits for Emerging Terahertz Applications ....................................................... 169
U. R. Pfeiffer, J. Grzyb, R. Al Hadi, N. Sarmah, K. Statnikov, S. Malz and B. Heinemann

K.2

Silicon Wireless Systems for 60-GHz Consumer and Infrastructure Applications ................................................... 173
Alex Tomkins, Alan Poon, Eric Juntunen, Ahmed El-Gabaly, Grigori Temkine, Yat-Loong To,
Craig Farnsworth, Arash Tabibiazar, Mohammad Fakharzadeh, Saman Jafarlou,
Hatem Tawfik, Brad Lynch, Mihai Tazlauanu and Ronald Glibbery

K.3

An Active Double-Balanced Down-Conversion Mixer in InP/Si BICMOS

Operating from 70-110 GHz .......................................................................................................................................... 177
Jamin J. McCue, Matthew Casto, James C. Li, Paul Watson and Waleed Khalil

K.4

GaN Technology for E, W and G-Band Applications .................................................................................................. 181

A. Margomenos, A. Kurdoghlian, M. Micovic, K. Shinohara, D. F. Brown, A. L. Corrion,
H. P. Moyer, S. Burnham, D. C. Regan, R. M. Grabar, C. McGuire, M. D. Wetzel,
R. Bowen, P. S. Chen, H. Y. Tai, A. Schmitz, H. Fung, A. Fung and D. H. Chow

SESSION L: Evaluation and Modeling of High-Power and High-Speed Devices

Chairpersons: Michael Schroter, UCSD/TUD
Rob Jones, Raytheon
L.1

An Evaluation of Extraction Methods for the Emitter Resistance for InP DHBTs................................................... 185
T. Nardmann, J. Krause and M. Schroter

L.2

The Impact of Electro-Thermal Coupling on HBT Power Amplifiers ....................................................................... 189

Matthew T. Ozalas

L.3

Analysis of the Influence of Layout and Technology Parameters on the Thermal

Impedance of GaAs HBT/BiFET Using a Highly-Efficient Tool ................................................................................ 193
A. Magnani, V. d'Alessandro, L. Codecasa, P. J. Zampardi, B. Moser and N. Rinaldi

L.4

Evaluation and Modeling of Voltage Stress-Induced Hot Carrier Effects in High-Speed SiGe HBTs .................... 197
Grazia Sasso, Cristell Maneux, Josef Boeck, Vincenzo d'Alessandro, Klaus Aufinger,
Thomas Zimmer and Niccol Rinaldi

SESSION M: High Frequency Power Amplifiers

Chairpersons: Simon Wood, Cree
Frank van Vliet, TNO
M.1

Miniaturization of Ka-Band High Power Amplifier by 0.15 m GaN MMIC Technology ...................................... 201
Kris Kong, Ming-Yih Kao and Sabyasachi Nayak

M.2

X-Ku Wide-Bandwidth GaN HEMT MMIC Amplifier with Small Deviation of Output Power and PAE............. 205
Yoshitaka Niida, Yoichi Kamada, Toshihiro Ohki, Shiro Ozaki, Kozo Makiyama,
Naoya Okamoto, Masaru Sato, Satoshi Masuda and Keiji Watanabe

M.3

A 6-12 GHz Push-Pull GaN Amplifier for Low Harmonic Drive Applications ......................................................... 209
Michael Roberg and Bumjin Kim

M.4

Investigation of Various Envelope Complexity Linearity under Modulated Stimulus Using

a New Envelope Formulation Approach ....................................................................................................................... 213
F. L. Ogboi, P. J. Tasker, M. Akmal, J. Lees, J. Benedikt, S. Bensmida, K. Morris,
M. Beach and J. McGeehan

SESSION N: Application of Next Generation Technologies

Chairpersons: Steve Huettner, Nuvotronics LLC
Jim Carroll, NI-AWR Group
N.1

W-Band GaN Receiver Components Utilizing Highly Scaled, Next Generation GaN Device Technology.............. 217
A. Margomenos, A. Kurdoghlian, M. Micovic, K. Shinohara, H. Moyer, D. C. Regan,
R. M. Grabar, C. McGuire, M. D. Wetzel and D. H. Chow

N.2

Ka Band Chip-Set for Electronically Steerable Antennas ........................................................................................... 221

Rmy Leblanc, Noelia Santos Ibeas, Ahmed Gasmi and Jol Moron

xi

N.3

12.5 THz Fco GeTe Inline Phase-Change Switch Technology for Reconfigurable RF
and Switching Applications ............................................................................................................................................ 225
Nabil El-Hinnawy, Pavel Borodulin, Evan B. Jones, Brian P. Wagner, Matthew R. King,
John S. Mason Jr., James Bain, Jeyanandh Paramesh, T. E. Schlesinger, Robert S. Howell,
Michael J. Lee and Robert M. Young

N.4

Low Loss, High Performance 1-18 GHz SPDT Based on the Novel Super-Lattice Castellated
Field Effect Transistor (SLCFET)................................................................................................................................. 228
Robert S. Howell, Eric J. Stewart, Ron Freitag, Justin Parke, Bettina Nechay, Harlan Cramer,
Matthew King, Shalini Gupta, Jeff Hartman, Pavel Borodulin, Megan Snook, Ishan Wathuthanthri,
Parrish Ralston, Karen Renaldo and H. George Henry

SESSION O: Mixed Signal Circuits

Chairpersons: James Buckwalter, UC San Diego
Hui Pan, Broadcom, Irvine
O.1

1700 Pixels Per Inch (PPI) Passive-Matrix Micro-LED Display Powered by ASIC.................................................. 232
Wing Cheung Chong, Wai Keung Cho, Zhao Jun Liu, Chu Hong Wang and Kei May Lau

O.2

Programmable Active Clock Spine for 100Gb/200Gb Coherent Optical Receiver Chip in 32nm CMOS .............. 236
Naim Ben-Hamida, Christopher Kurowski, Robert Gibbins, Junxian Weng, Ted Wong,
John Lindsay, Harvey Mah, Sadok Aouini and Andrew McCarthy

O.3

A 7-8 GHz Serrodyne Modulator in SiGe for MIMO Signal Generation .................................................................. 240
Johan C. J. G. Withagen, A. J. Annema, B. Nauta and F. E. van Vliet

SESSION P: Breaking News Papers

Chairpersons: Douglas S. McPherson, Ciena
Charles F. Campbell, TriQuint Semiconductor
P.1

A Highly Integrated Chipset for 40 Gbps Wireless D-Band Communication Based

on a 250 nm InP DHBT Technology.............................................................................................................................. 244
Sona Carpenter, Zhongxia He, Mingquan Bao and Herbert Zirath

P.2

Characterization of the High Frequency Performance of 28-nm UTBB FDSOI MOSFETs

as a Function of Backgate Bias ...................................................................................................................................... 248
Stefan Shopov and Sorin P. Voinigescu

P.3

An 8-Bit 140-GHz Power-DAC Cell for IQ Transmitter Arrays with Antenna Segmentation ................................ 252
Stefan Shopov and Sorin P. Voinigescu

P.4

Advanced Process and Modeling on 600+ GHz Emitter Ledge Type-II GaAsSb/InP DHBT .................................. 256
Huiming Xu, Barry Wu, Ardy Winoto and Milton Feng

P.5

170 GHz SiGe-BiCMOS Loss-Compensated Distributed Amplifier .......................................................................... 261

Paolo Valerio Testa, Guido Belfiore, David Fritsche, Corrado Carta and Frank Ellinger

P.6

Direct Down-Conversion 38 GHz GaAs and SiGe Receivers ...................................................................................... 265

Ryan M. Clement, Leigh E. Milner, Emmanuelle R. Convert, Leonard Hall, Michael Parker,
MacCrae G. McCulloch, Anna Dadello, Benny Wu, James T. Harvey
Anthony E. Parker and Simon J. Mahon

Author Index ............................................................................................................................................................ 269

xii

Table of Contents

Evolution of Multi-Gigabit Wireline Transceivers in CMOS

Ichiro Fujimori
Broadcom Corporation, Irvine, CA 92617, USA, 949-338-2087, ichiro@broadcom.com
which reduces deterministic jitter introduced by environmental
noise. Shunt peaking was extensively used in the OC-192 receiver
10Gbps path including CML latches and combinational logic in
the linear phase detector [3]. Further bandwidth extensions can be
made with a T-coil structure shown in Fig. 1 (a). The bridge
capacitor CB enhances peaking and enables use of a smaller
inductor, resulting in reduced parasitic capacitance. The T-coil
combines both shunt and series peaking to effectively tune out
parasitic capacitance, but trades off delay. The technique is useful
for cases with large loads such as limiting amplifiers driving
multiple slicers in an OC-768 receiver [4]. A T-coil can provide
2.8x improvement over no peaking. By adjusting the mutual
inductance K between the inductors L1 and L2, the peaking
characteristics can be optimized for flat frequency response and
good group delay characteristics to realize low ISI. The technique
also helps reduce effect of ESD protection capacitance in a
transmit driver [5]. Complex inductive peaking schemes like this
can be implemented with small area penalty. As shown in Fig. 1
(b), the bridge cap, and the two coils can be stacked on top of each
other because of the multiple metal layers.

Abstract Since the first OC-192 transceiver in CMOS was

introduced in 2000, architecture and technology advancements
have pushed wireline transceivers in CMOS to mainstream,
even for OC-768 data rates. A diverse portfolio of multigigabit SerDes I/Os is now essential for large scale SOCs, not
only for Networking but also Consumer applications. DSPbased transceivers with ADC frontends have forced a
paradigm shift in how wireline transceivers are architected.
This paper covers the evolution of CMOS wireline
transceivers at Broadcom.
Index Terms Wireline Transceivers, SerDes, ADC, CMOS,
CML, Inductive Peaking, CDR
I. INTRODUCTION: 10G IS IMPOSSIBLE IN CMOS
In the late 1990s when the first OC-48 transceiver in CMOS
was developed [1], III-V technology such as InP HBT was
common for commercial wireline transceivers with data rates
above 10Gbps. At that time, the newly introduced SiGe Bi-CMOS
was an increasingly popular option for new developments, because
of the availability of bipolar devices at the cost of mature CMOS
lithography. Plain vanilla CMOS was not considered a viable
option for 10Gbps due to drawbacks such as transistor mismatch,
noise, lower trans-conductance per current, and larger swing
requirements for Current-Mode-Logic (CML). Despite the fact
that the device FT of 45GHz for 0.18um CMOS was comparable to
FT of 47GHz for a common Bi-CMOS technology (IBM 6HP), it
was often considered impossible to use CMOS for commercial
manufacturing [2]. The use of standard CMOS has a number of
advantages such as reduction of power and cost, scaling with
technology, and integration with other digital functions on the
same die. In 2000, the first commercial OC-192 transceiver in
CMOS was introduced overcoming the challenges [3]. Over the
past 15 years, thanks to advanced technology and design
innovation, multi-gigabit wireline transceivers in CMOS have now
become mainstream, enabling the incredible scaling of computer
and networking systems, ranging from handheld electronics,
servers/switches in data centers, to supercomputers. This paper is
an overview of the key advancements and innovations that pushed
the CMOS evolution, and the challenges moving forward.

Fig. 1. (a) CML with T-coil, (b) T-coil and bridge capacitor
B.

The key architecture level advancement for CMOS wireline

transceivers is the transition to digital. This often denotes rich
content of standard cell logic with full swing CMOS digital
circuits used instead of CML even in the high frequency path. One
essential feature in a digital transceiver is the use of a digital clock
and data recovery (CDR), where a Bang-Bang phase-detector
(PD), in conjunction with a fully digital loop filter, controlling the
phase-interpolator (PI). This is in contrary with the analog CDR
where a linear PD, linear filter, and a VCO forms the CDR loop.
The merits of the digital CDR include the reduced PVT variations,
and support of multi-lane configuration with one PLL avoiding
any interaction between multiple VCOs. However, the early
applications have been limited to systems with forwarded clocks
or small frequency offset, because of the finite frequency and jitter
tracking capability due to latency in the digital filter. Technology
advancement helped lower latency in the digital filter, as well as
reduce metastability in the Bang-Bang PD that improves jitter
performance, making the digital CDR a viable choice for
mainstream applications. A 8Gbps digital CDR achieves a
frequency tracking range of 15.6Kppm, and a tracking bandwidth
of 10MHz in 40nm [6], sufficient to support 5Kppm for

II. PUSHING THE SPEED BARRIER IN CMOS

A.

Mastery of Spiral Inductors

The most significant circuit level advancement for transition to

CMOS is the mastery of spiral inductors. Modern day CMOS
technology has multiple metal layers (10+ layers!), allowing many
variations to the inductor geometries. One of the most effective
techniques is inductive peaking in CML. In CML, the gain
bandwidth product can be optimized by the load resistance and the
tail current. Higher current density in the CMOS transistor
improves speed, but the size constraints due to reliability
guidelines limit the upper bandwidth. Inductive shunt peaking can
be employed by connecting an on-chip spiral inductor in series
with the load resistor, inserting a zero in the transfer function,
which extends the bandwidth. Also, it enhances the slew rate,

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Digital Wireline Transceivers

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which also owes to the improved PLL jitter performance [10]. The
eye height at 45Gbps is larger for more margin. For transmitters in
the fastest optical transceivers, CML drivers are commonly used
instead of CMOS inverter stages because of the reduced
sensitivity to power supply noise. The consistent eye shapes at
faster rates are results of advancements in the CML drivers
including: use of inductance without degrading return loss
characteristics, pre-emphasis to tune out package parasitics, and

frequency offset, 3Kppm for input sinusoidal jitter, and

5Kppm for Spread-Spectrum Clocking (SSC). This allows one
SerDes to support various Standards and coexist on the same SOC
even with limited reference clocks. Once digital, many functions
can be realized at low cost. Features such as SATA host tracking
and xPON loop timing can be supported by feeding the digital PI
control signal from the CDR to the TX side PI through an IIR
filter without the need for a costly analog clean-up PLL. In an OC768 transceiver, the latency of the digital filter limits the RX jitter
tolerance. A 45Gbps digital CDR in 40nm uses only the rising
edge data transitions to provide phase error information [4]. As a
result, early/late signals can be coded using twos complement,
allowing insertion of phase detection into the de-multiplexing
pipeline. The loop latency is reduced by 32 Unit Intervals (UIs),
resulting in 0.05 UI RX jitter tolerance improvement. Another
aspect of digital on the TX side is the driver using CMOS
inverter stages with sources series termination instead of CML. In
advanced technology, CMOS stages are fast enough to meet the
eye template requirements, while allowing easier implementation
of features such as TX pre-emphasis [7].
C.

Evolution of 10G binary transceivers

Fig. 2 shows the evolution of the 10G binary transceivers.

Plotted along with the area reduction trend is the digital scaling
trend line of -40% per node for comparison. In 180nm technology,
the Transmitter and Receiver were separate chips [3]. In 130nm,
inductive peaking is still extensively used. In 65nm [8], a
significant part of area reduction comes from use of more CMOS
logic instead of CML at high speed stages, and less use of
inductors due to the faster technology. In 40nm, the transition to a
digital transceiver architecture result in a significant reduction that
exceed the digital scaling trend. One notable is the increased
channel loss equalization capability for each generation. In 130nm
and 65nm, the technology supports adequate bandwidth for a
linear (peaking) equalizer prior to the CDR. In 40nm and 28nm, a
digital transceiver allows low cost implementation of a decisionfeedback equalizer (DFE) [7]. Overall, the area reduction from
180nm to 28nm is 96%.

Fig. 3. Evolution of Transmit Eye for Optical Transceivers

advancement in ESD protection with less parasitic effects [5].
III. LARGE SCALE SOCS WITH WIRELINE TRANSCEIVERS
A.

Evolution of Networking SOCs

Fig. 4 shows an IEEE 802.3ae 10GE LAN PHY introduced

in 2001. The SOC integrates both the 10.3Gbps Transceiver
(PMA) and the 3.125Gbps x 4 sub-layer system SerDes (XAUI),
2
with half a million gates of digital logic. The chip is 8.5 x 6.0mm
in 0.18um CMOS, with power dissipation of 2.5W at 1.8V supply.
To the authors knowledge, this was the first SOC where a 10Gbps
serial transceiver and multiple SerDes standards were integrated
with sizeable logic functions. The digital functions include the
PCS layers for both XAUI and PMA, an elastic FIFO to
synchronize the 4 clock domains: PMA RX and TX on the line
interface, and XAUI RX and TX on the system interface, and
Built-in Self-Test. This opened the door to wireline SOCs where
multiple SerDes are integrated on the same die. The integration
advanced rapidly over the years to keep up with the data
throughput requirement of Networking SOCs. The latest state of
the art is a Ethernet Switch SOC integrating 128 ports of 10Gbps

10G PMA
Receive

XAUI
Receive

Fig. 2. Evolution of 10G Transceivers

Digital

D. BEYOND 10GBPS
Fig. 3 shows the evolution of the transmit eye for the most
advanced Optical transceivers at the given times [1][3][4][9]. The
vertical and horizontal scale is matched for comparison. The eye
shape remains roughly the same for 2.5Gbps and 45Gbps, since
the eye template for newer Standards remain consistent in terms of
UIs. Mandating improved rise/fall time and jitter for faster rates.
The rise/fall time is 35ps at 10Gbps, while 8ps at 45Gbps. The
random jitter is 600fsrms at 10Gbps, while 200fsrms at 45Gbps,

XAUI
Transmit

10G PMA
Transmit

Fig. 4. IEEE 802.3 ae 10GE LAN PHY

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transceivers together with 4 billion transistors [11]. Industry

forecasts suggest such Ethernet Switch SOC will need to support
5Tbps throughput by 2017 to meet demands for data centers.
B.

fine phase adjustment for channel phase mismatch. Timeinterleaved structures suffer from mismatches between the
separate channels such as sub-ADC gain, PGA bandwidth,
comparator offset, and interleaved clock phases. Therefore, timeinterleaved ADC extensively employs digital assisted calibration
to correct these errors. In a flash ADC, comparators need to be
aggressively undersized to save dynamic power. A combination of
minimal comparator redundancy in addition to individual
calibration achieve this without effecting ADC yield. Specifically,
dynamic reconfiguration of the comparator order can reduce the
required comparator offset adjustment range [13]. Simply using a
Wallace-Tree adder as the thermometer-to-binary decoder
provides that flexibility, since its operation is independent of
comparator switching order. Numerical simulation results predict
that the effective comparator standard deviation can be reduced by
a factor of two with optimal comparator reordering, resulting in 4x
power and area savings.

SerDes for Communication SOCs

The wide spread adoption of CMOS wireline transcievers in

SOCs have resulted in a rapid diversification of transceivers
supporting various standards and applications for communication
SOCs. Fig. 5 shows the SerDes IP portfolio required for such
SOCs. In addition to the transceivers for the conventional areas
such as Optical Transport and Networking, there is an extensive
portfolio in the Consumer space. This includes standards such and
DigRF, Mipi-MPHY and USB required for Mobile handsets, as
well as SATA, DisplayPort, and HDMI for home entertainment
applications. One notable is the increase of EPON and GPON
transceiver usage due to the rapid increase of Fiber-to-the-Home
applications. The diversification of SerDes usages brings many
new design challenges in transceiver design. For example, in the
mobile space, the bit-error-rate requirement is relaxed compared to
Networking applications, but low stand-by power becomes critical
because of the battery operation.

Fig. 6. Evolution of ADC frontends for 10G-LRM/10G-KR

B.

Fig. 5. SerDes Portfolio for SOCs

Fig. 6 shows the evolution of 10GS/s 6-bit ADC frontends. The

90nm generation consists of eight flash ADCs operating in parallel
at 1.25Gs/s. The 65nm generation has four flash ADCs running at
2.5GS/s due to faster technology [12]. The 40nm is roughly half of
65nm because of the use of the rectified flash ADC architecture,
where the number of comparators can be reduced to half [14].
Overall, shows a 90% area reduction compared to the 90nm
generation. One key observation is that the scaling for each
technology nodes are significantly better than digital scaling trend.
This is due to the extensive use of calibration and architecture
innovations, in addition to technology advancement. This trend
will continue, and DSP-based transceivers with ADC frontends
will become a viable option for a wider range of applications.

IV. THE PARADIGM SHIFT: DSP-BASED TRANSCEIVERS

A.

Evolution of ADC Frontends for 10Gbps DSP Receivers

Time-Interleaved ADC Frontends

A significant paradigm shift in the recent years is DSP-based

transceivers with ADC frontends. Once the input is digitized by
the ADC, the DSP can carry out powerful equalization functions
such as Feed-Forward Equalization (FFE) and DFE at low cost.
Timing recovery can be done by phase detection in digital,
controlling the PIs for ADC sampling. The commercial adoption
of DSP-based transceivers started in niche applications such as
10G-LRM for multi-mode fiber and 10G-KR signaling over
legacy backplanes, where conventional analog equalization does
not meet the required performance, and a cost premium can be
commanded. For Networking applications, the ADC frontend is
required to have very high resolution bandwidth of 5 GHz and
-15
very low bit error rate of 10 , which puts an extremely high
requirement on the bandwidth of the entire data and clock paths if
a single ADC is used. By contrast, in a time-interleaved ADC, the
sub-ADC in each channel operates at a reduced sampling rate. The
interleaving factor is determined by the time-period to ensure low
meta-stability that meets the BER requirement, which becomes
shorter with advanced technology, hence, less parallel ADCs. In
65 nm, a 4-way interleaved flash ADC is employed to reduce the
power/area of each sub-ADC while keeping the load from the
separated sample and holds low [12]. Four clock phases are 100ps
apart generated by 4 independent 2.5GHz PIs which also provide

C.

Beyond NRZ: Multi-level coding

Use of multi-level coding in DSP-based transceivers have been

accelerated by the adoption of 4-level Pulse Amplitude
Modulation (PAM-4) in the IEEE 802.3bj 100GBase KP4
Standards to support 25Gbps data-rate over legacy 10G-KR
channels. In PAM-4, the Nyquist frequency becomes half
compared to conventional NRZ. Lower Nyquist reduces the return
loss and insertion loss, which relaxes the equalization
requirements, while a lower baud rate simplifies implementation
and lowers cost. For legacy link situations, this is especially
beneficial, since secondary impairments other than copper loss
becomes more significant at higher frequency. The drawback is
the degraded SNR due to the reduced eye height, increasing

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sensitivity to crosstalk. Most importantly, multi-level coding is

inherently compatible with ADC frontends. The PAM level is just
one system parameter that affects the required ENOB, contrary to
binary receivers where the PAM level drastically changes the
architecture. Conventional wisdom suggests that a higher PAM
level should be used for every 10dB increase in insertion loss.
Although, it is less straightforward for DSP-based receivers.
Equalization effectively reduces the steepness of the loss curve,
but also multiplies the quantization noise of the ADC. To analyze
the optimal cost, Fig. 7 shows the receiver complexity vs. datarate for various PAM levels using a 12-inch 10G-KR compliant
backplane. The complexity is normalized to NRZ at 10Gbps. The
ADC complexity is computed based on the required quantization
noise with a flash architecture, and the DSP equalizer is
implemented with actual DFE/FFE taps with finite bit-width. The
NRZ shows the lowest cost at lower rates but has a steeper
increase. PAM coding shows higher cost at lower rates but show a
flatter increase. The curves basically follow the inverse of the
insertion loss. Increases linearly at low frequency and becomes
exponential at higher frequency. The curves for different PAM
levels will intersect and gradually flatten out. At 25Gbps, PAM4 is
the best choice with a complexity index of 3.3. At 50Gbps, PAM8
is the best with normalized complexity of 13, roughly 4x of PAM4
at 25Gbps. This suggest that combined with the cost reduction
trend over time according to Moores law, employing more
sophisticated DSP with higher level coding will stay more
economical than upgrading the backplane media. Therefore, the
trend of DSP-based receivers supporting legacy backplanes will
continue. Multi-level coding is also a very interesting area for
future research. Approaches like adaptive PAM levels may be
explored to deal with crosstalk. Perhaps, more creativity in the TX
DAC designs such as pre-cancellation of near-end crosstalk can

chromatic dispersion. The ADC oversamples by 2X at 56GS/s,

due to the asynchronous nature [15]. In optical communications, a
-3
relaxed BER of 10 is tolerable due to the FEC. Circuit metastability becomes less critical at high BER, which makes low
power architectures such as SAR a viable choice [16]. A SAR
ADC is more susceptible to meta-stability, because the comparator
is making successive decisions that can cause an error as large as
half the full scale, but has lower power since it only has one
comparator. Further exploitation for SAR architectures for high
speed ADC frontends will continue. Combining coherent detection
with DWDM, more than 1Tbps communication over 1000 km is
possible using one fiber.
B.

The latest FinFET technology promises tremendous speed

improvement and power reduction in logic gates due to lower
threshold voltage and larger Idsat. The same is not true for mixedsignal circuits, which are often operated at different bias
conditions. A better measure of performance will be the device FT,
which have decreased from 20nm planar CMOS to FinFET,
because of the increased parasitic gate capacitance due to the 3D
nature [17]. It presents an additional challenge to take advantage
of improved drive current but depend less on FT. The slow-down
of Moores law will accelerate architecture innovations that take
advantage of DSP to reduce the area and power. Most importantly,
with all of these architecture options, there has never been a more
interesting time for wireline transceiver designers.
REFERENCES
[1] A. Momtaz, et al., Fully-integrated SONET OC-48 Transceiver in
standard CMOS, IEEE JSSC, vol. 36, no. 12, pp. 1964-1973, Dec. 2001.
[2] Details of 10Gbps LSI Technology, Nikkei Microdevices, pp. 123131, June 2002.
[3] J. Cao, et. al, OC-192 Transmitter and Receiver in Standard 0.18u
CMOS, IEEE JSSC, vol. 37, no. 12, pp. 1768-1780, Dec. 2002.
[4] B. Raghavan, et al., A Sub-2W 39.8-to-44.6Gb/s Transmitter and
Receiver Chipset with SFI-5.2 Interface in 40nm CMOS, IEEE JSSC,
vol. 48, no. 12, pp. 3219-3228, Dec. 2013.
[5] S. Galal, et. Al., Broadband ESD protection circuits in CMOS
technology, IEEE JSSC, vol. 38, no. 12, pp. 2334---2340, Dec. 2003.
[6] H. Pan, et al., A Digital Wideband CDR with +/-15.6kppm
Frequency Tracking at 8Gb/s in 40nm CMOS, IEEE ISSCC 2011, pp.
442-443, Feb 2011.
[7] A. Nazemi, et al., A 2.8 mW/Gb/s quad-channel 8.511.4 Gb/s
quasi-digital transceiver in 28 nm CMOS, IEEE VLSI Circuits Symp.
2013, pp. 276-277, June 2013.
[8] N. Kocaman, et al., 11.3 Gb/s CMOS SONET Compliant
Transceiver for Both RZ and NRZ Applications, IEEE JSSC, vol. 46, no.
12, pp. 3089-3100, Dec. 2011.
[9] D. Cui, et al., A Dual-Channel 23Gb/s CMOS Transmitter/Receiver
Chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK Optical
Transmission, IEEE JSSC, vol. 47, no. 12, pp. 3249-3260 , Dec. 2012.
[10] M. Ahmadi, et al., A 288fs RMS Jitter Versatile 8-12.4GHz WideBand Fractional-N Synthesizer for SONET and SerDes Communication
Standards in 40nm CMOS, IEEE VLSI Circuits Symp. 2013, June 2013.
[11] N. Ilyadis, Plenary: The Evolution of Next Generation Data Center
Networks for High Capacity Computing, IEEE VLSI Circuits Symp. 2012.
[12] J. Cao, et al., A 500mW Digitally Calibrated AFE in 65nm CMOS
for 10Gb/s Serial Links over Backplane and Multimode Fiber, IEEE
JSSC, vol. 45, pp 1172-1185, Jun. 2010.
[13] S. Verma, et al., A 10.3-GS/s, 6-b Flash ADC for 10G Ethernet
Applications, IEEE JSSC, vol. 48, no. 12, pp. 3038-3047, Dec. 2013.
[14] B. Zhang, et al., A 195mW / 55mW Dual-Path Receiver AFE for
Multi-standard 8.5-to-11.5 Gb/s Serial Links in 40nm CMOS, IEEE
ISSCC 2013, Feb. 2013.
[15] I. Dedic, 56GS/s ADC, enabling 100GbE, OFC 2010
[16] I. Fujimori, Short course: Advanced Wireline Transceivers in the
Era of Disruptive Changes, IEEE VLSI Circuits Symp. 2013, June 2013.
[17] M. Wakayama, Nanometer CMOS from a Mixed-Signal/RF
Perspective, IEEE IEDM 2013, Dec 2013

Fig. 7. Normalized complexity of DSP-based Receiver with

multi-level coding vs. Data rate
further alleviate channel impairments.
V. MOVING FORWARD
A.

FinFET and End of Moores Law

Towards Terabit Communication: Coherent Detection

Coherent detection is an optical communication system using

DSP-based EDC with high-level modulation of DP-QPSK. Two
optical QPSK traveling at different polarization, will result in two
pairs of I/Q at 28Gbps for 100Gbps data rate with FEC overhead.
Coherent detection offers access to amplitude and phase of the
optical electric field in electronic domain. The major enabler is the
ADC, which allows complex functions previously implemented in
optical domain now be performed by the DSP. Simple digital
filters can compensate for the linear channel transfer functions,
allowing nearly perfect compensation of polarization mode and

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FD-SOI technology development and key devices characteristics for

fast, power efficient, low voltage SoCs
Joel Hartmann
STMicroelectronics, Crolles, 38926, France, +33 4 7652 6000, joel.hartmann@st.com
Abstract Electronics is more and more pervasive in
everyday life: smartphones, connected cars, Internet of
Things All this is not only about mobile energy efficient
technologies: it is wireless and wireline connectivity, sensors.
UTBB FD-SOI (Ultra Thin Body and Buried-oxide Fully
Depleted Silicon On Insulator) is a planar semiconductor
technology that introduced the advantages of fully depleted
transistors from the 28nm technology node, which is cost
optimal, allowing joining the advantages of a general
purpose high speed technology with the ones of a low power
one. The paper describes the development of the FD-SOI
technology, the choice of devices centering, and their main
characteristics, especially suited for high speed energy
efficient operation, even in low voltage conditions, thanks to
the their intrinsic characteristics offered by being fully
depleted. Those, are not limited to digital logic devices, but
extend to memory bit-cells (fast, low leakage, and operating
at low voltage) and the exceptional analog characteristics of
devices.
Index Terms UTBB FD-SOI, ARM Cortex A9, forward
body-bias

electrostatics of UTBB FDSOI is no longer related to

doping, the additional advantage of the structure resides in
undoped channel with all its benefits to variability and
mobility. Finally it is to be noted that the conventional FD
SOI (thin Silicon on thick buried oxide) does not possess
the advantages since here the thick buried oxide
contributes to the depletion depth thus spoiling the
scalability, and also rendering body-bias inefficient [4].
II. LOGICAL DEVICES
As illustrated in Figure 1, FD-SOI transistor
electrostatic is not only controlled by the Silicon film
thickness but also strongly depends on buried oxide
thickness [4].
A key metric usable for optimizing devices is VGT = Vdd
VT: the higher it is, the higher is the transistor
performance at low voltage. On top of the already
excellent behavior, UTTB FD-SOI offers a further
leverage of control through body biasing, extremely
efficient in this technology (at the 28nm node, we
measured a VT of 80mV/V). Thanks to buried oxide
isolation, the body bias amplitude can go well above the
diode on-set voltage (0.3V) that is the limiter in bulk
technologies. Body biasing is exploitable in designs in
many ways, from temporary speed boosting for mobile
applications to process compensation techniques, to
decreasing the devices process spread thus allowing
reducing design margins.

I. INTRODUCTION
Transistor scaling theory [1] is dated since quite a long
time and has regulated the whole semiconductor industry
for almost 4 decades. Nevertheless, it is not accounting for
some parameters and effects like the invariability of the
subthreshold slope (responsible for the Ioff/Ion conflict),
nor the SCE and DIBL parameters that play a key role in
the behavior of a transistor. When applying correctly the
voltage-doping transformation [2], [3], we end up
realizing that SCE and DIBL depend on ratio of
parameters rather than on absolute values of the
parameters (such as junction depth, gate oxide thickness
and depletion depth) . This implies that planar bulk
transistors cannot be any longer shrunk and that new
devices are required to continue the path on the Moores
law. UTTB (ultra-thin body and buried oxide) FD-SOI
(fully depleted SOI) is one of those [4]. It owes its
superior scalability to the fact that in this structure both
the junction depth and the depletion depth do not result
from ion implantation and thermal diffusion like in Bulk
but are determined by the thicknesses of the Silicon film
and that of buried oxide, respectively. Making the latter
two extremely thin, i.e much thinner than conventional
Bulk junction depth and depletion depth, you can achieve
an excellent electrostatics and thus scalability. As the

978-1-4799-3622-9/14/$31.00 2014 IEEE

III. MEMORIES
The excellent electrostatic behavior and mismatch
control of FD-SOI transistors reflects also in better
performing and dense memory bitcells, which are
fundamental in today SoC designs. Thanks to the
mismatch parameter reduced by 40% in FD-SOI
(compared to a bulk planar technology), bitcells already
exhibits a 100mV reduction in the operating Vmin (fig. 2),
on top of offering 30 to 50% read current increase for the
same leakage [5].
Design techniques are applicable to UTBB FD-SOI
bitcells, allowing mixing RVT nFETs with LVT pFET in
a so called single-well architecture (lets remember, this

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technology does not use doping to control the VT of

devices. In contrast, VT is adjusted by using the doping
type in the wells (and the gate type), as well as by
applying body biasing. The end result is bitcells with good
read and write margins, capable of further reducing their
operating voltage of an additional 70mV (fig. 3).
The great flexibility of UTBB FD-SOI can be also
exploited for implementing original solutions to further
shrink bitcell sizes. An example is given by the feasibility
of a 4T bitcell studied in [6]. A 4T bitcell consists of a
pull-down nMOS driver and a pMOS access transistor,
where the leakage of the access transistor holds the 1. In
such bitcells it is critical retaining the data stored during
read operation and when in stand-by. Thanks to the unique
capability of UTBB FD-SOI to allow easily mixing
transistors VT also in bitcells, it is possible to use a leakier
low-VT pMOS access transistor (thanks to a single-well
configuration), thus improving the stability of the bitcell
during read operations.

core, thanks to its ultra-wide DVFS capability, can also

reach 2.6GHz when operated at 1.3Va.
UTBB FD-SOI is also well suited for AMS designs. An
example is given by the implementation of a 20GHz 6b
10GS/s Time-Interleaved ADC done in 28nm UTBB FDSOI [9] (fig. 8) that, thanks to fast operating nMOS
devices and forward body-bias usage, allowed doubling
the sampling rate of an equivalent implementation done
with a 28LP HKMG bulk planar technology, reaching
state of the art power consumption and active area, and
not needing any gain/skew calibration process, necessary
in all other implementations to reach comparable speeds
(table. 1).
V. CONCLUSION
Planar UTBB FD-SOI technology has been proven
working on silicon and is today an industrial reality,
allowing taking the benefits of a fully-depleted technology
from the 28nm node. Real designs have shown on silicon
the great advantages both in terms of speed and power
efficiency, for digital design but also for analog/mixedsignal IPs, demonstrating it is a real general purpose
technology, suitable for a wide range of applications.

IV. DESIGN EXAMPLES

Thanks to its intrinsic device characteristics, UTBB FDSOI is an excellent technology for building general
purpose SoCs, offering high speed operation at
exceptional energy efficiency levels, but also at low
operating voltages.
A dual Cortex A9 subsystem for mobile applications has
been demonstrated in 28nm FD-SOI [7], showing an ultrawide DVFS capability ranging from 0.52V to 1.37V,
operating between 3GHz and 300MHz, with an
improvement up to +544% at 0.61V/1.3V FBB vs. an
equivalent implementation (same floorplan) in 28LP
HKMG bulk planar technology. A specific architecture
has been developed to allow a fine grained control over
activation of cores (through power switches), a versatile
dedicated PLL, and an embedded body bias generator
(driven by the power controller) to generate the reference
voltages for forward body biasing the cores, thus allowing
higher speeds and energy efficiency. FBB can be used
here for offering on-demand speed boost (+20% in
overdrive conditions, >3x at underdrive), for optimizing
the core energy efficiency (at ambient temperature, for a
given speed applying 600mV FBB we measured up to
15% total power saving, fig.4), but also for process
compensating the slow parts and operate them as typical
to fast parts (fig. 5).
A second example is about a ultra-low voltage capable
32bit VLIW DSP, recently demonstrated on silicon [8],
operating in the range 0.397-1.3V, and capable of
reaching 460MHz at 0.397V for a mere 62pK/cycle (fig.
6), more than 10x faster for the same voltage than state of
the art WVRs published in the literature (fig. 7). The same

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[1] R.H. Denard et al., IEEE J. SSC, pp. 256-268, Sept. 1974.
[2] T. Skotnicki, et al., Electron Device Letters, Vol 9, N 3,
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[3] T. Skotnicki, invited paper ESSDERC 2000, pp. 19-33, edit.
Frontier Group
[4] T. Skotnicki et al., Innovative Materials, Devices, and
CMOS Technologies for Low-Power Mobile Multimedia,
pp. 96-130, vol 55 IEEE TED, January 2008.
[5] R. Ranica et al. FD-SOI Process/design full solutions for
Ultra Low Leakage, High Speed and Low Voltage SRAMs,
Simposia on VLSI Technology and Circuits 2013
[6] V. Asthana et al., Circuit Optimization of 4T, 6T, 8T, 10T
SRAM Bitcells in 28nm UTBB FD-SOI Technology using
Back-Gate Bias Control, ESSCIRC 2013
[7] D. Jaquet et al., A 3GHz Dual Core Processor ARM
CortexTM-A9 in 28nm UTBB FD-SOI CMOS With UltraWide Voltage Range and Energy Efficiency Optimization,
IEEE Jurnal of Solid-State Circuits, Vol. 49, No. 4, Apr
2014
[8] R. Wilson at al., A 460MHz @ 397mV 2.6GHz @ 1.3V
32bit VLIW DSP Embedding Fmax Tracking, ISSCC 2014
[9] S. Le Tual et al., A 20GHz-BW 6b 10GS/s 32mW TimeInterleaved SAR ADC with Master T&H in 28nm UTBB
FD-SOI Technology, ISSCC 2014

Table of Contents

Fig. 4. Comparative silicon measures off total power consumption

for two similar dual Cortex A9 implementations (same
get), one done with 28LP
floorplan/area, same max leakage targ
HHMK technology and the other with
w
28nm FD-SOI. The
comparison shows up to >50% power saving thanks to FD-SOI
(and FBB) vs. 28LP HKMG

Fig. 1. The strong improvement in DIBL and SS sets off at thin

buried oxide (UTBB FD SOI) whereas at thhick Buried oxide
(conventional FD SOI), DIBL and SS are almoost independent on
buried oxide thickness.

SOI technology vs.

Fig. 2. a) Mismatch is greatly reduced in FD-S
bulk planar; b) Vmin improvement in a hiigh density bitcell
thanks to the reduced mismatch offered by FD-SOI technology

c
lot of the dual
Fig. 5. a) Vmin search test result for a corner/skew
Cortex A9 for both the 28LP HKMG and FD-SOI
implementation

Fig. 3, a) the single well architecture possiible with FD-SOI,

allowing mixing in the same bitcell a RVT nnFET with a LVT
pFET. b) the consequence of the mix is an impproved Vmin of the
bitcells, allowing to gain an extra 70mV vvs. a non flip-well
implementation

Fig. 5 b) Vmin search result when

w
applying process
compensation through FBB (600mV applied here) to slow
parts. Slow parts are totally recovered th
hanks to FBB.

Table of Contents

Fig. 6 a) Fmax silicon measures of a 332bit VLIW DSP

implemented with 28nm FD-SOI technology. 460MHz Fmax @
397mV are possible thanks to 2V FBB

Fig. 8 a) A 20GHz 6b 10GS/s Time-In

nterleaved ADC core
layout in 28nm FD-SOI. b) The silicon die mounted for testing
Fig. 9. 10GS/s ADC Output Spectrum

Fig. 6 b) Energy efficiency silicon measuress of a 32bit VLIW

DSP implemented with 28nm FD-SOI technoology. Best energy
efficiency of 62pJ/cycle is reached @ 460MH
Hz

Fig. 7 Comparison of speeds of different 32bit VLIW DSP

available in the literature. FD-SOI offers best--in-class speeds on
the overall Vdd range.

v other work
Table 1. ADC performances summary vs.

Table of Contents

Materials and Integration Strategies for Modern RF Integrated

Circuits
Daniel S. Green1, Carl L. Dohrman2, Avinash S. Kane2, Tsu-Hsi Chang3
1

U.S. Defense Advanced Research Projects Agency (DARPA), Arlington, VA 22203

2
Booz Allen Hamilton, Inc., Arlington, VA 22203
3
HetInTec Corp.; Rockville, MD 20850
with fmax above 1THz [1] as well as ultra-high-speed
mixed-signal circuits (see, for example, [2]). The wide
energy bandgap of GaN has enabled large voltage
swings as well as high breakdown voltage RF power
devices [3]. Excellent thermal conductivity of SiC also
makes tens of kilowatt-level power switches possible
[4].
Additionally,
on-chip
high-Q
microelectromechanical resonators and switches in various
materials, such as AlN, have been demonstrated that
potentially can be used for clock references and
frequency selective filters [5].
The advantages of CS materials are illustrated in
Table 1 below. As indicated by Table 1, compound
semiconductors exhibit many superior materials
properties relative to silicon technology. However, the
modest complexity of CS circuits relative to silicon
circuits has limited their deployment in many
applications. In particular, GaN is a material system
with an unparalleled combination of high breakdown
field, band gap, and thermal conductivity, but with
limited integration complexity to date. Overall, it is
clear that no materials system excels for all metrics
highlighting the benefit to integration.

Abstract The DARPA Microsystems Technology

Office is developing revolutionary materials, devices, and
integration techniques for meeting the RF integrated
circuit performance requirements for advanced modern
RF systems. DARPA is enabling these systems through
systematic development of materials and devices, circuits,
and
integration
technologies
for
compound
semiconductors. The DARPA Nitride Electronic NextGeneration Technology (NEXT) program is developing
high performance nitride transistors for high-speed RF,
analog and mixed signal electronics, thus overcoming the
Johnson figure of merit limits to achieving simultaneous
high-speed operation and high breakdown voltage. The
DARPA Microscale Power Conversion (MPC) program is
developing nitride-based technology to enable dynamic
envelope-tracking power conversion embedded in RF
radiating elements. The DARPA Diverse Accessible
Heterogeneous Integration (DAHI) program is developing
transistor-scale heterogeneous integration processes to
intimately combine advanced compound semiconductor
(CS) devices, as well as other emerging materials and
devices, with high-density silicon CMOS technology. Taken
together, these programs are addressing many of the
critical challenges for next-generation RF modules and
seek to revolutionize DoD capabilities in this area.

Modern RF systems are under consistent pressure to

make use of the RF spectrum in increasing sophisticated
ways. As the RF spectrum becomes increasingly
congested, RF systems must contend with increased
interference while achieving frequency agility and
spectral efficiency and simultaneously achieving
increased data rates. Additionally, as mobile technology
becomes more pervasive in both commercial and DoD
technology, novel RF systems must work within
increasingly limited power budgets. Furthermore, there
is a constant push to achieve reduced size and weight
for RF systems of all size scales.
Such system requirements create concomitant
challenges for RF integrated circuits for which
compound semiconductors provide a potential solution.
The compound semiconductor (CS) electronics industry
has a long history of driving advancements in RF/mixed
signal systems. The success of CS materials in these
systems is due in large part to the many superior
properties of these materials relative to silicon. For
example, high electron mobility and peak velocity of
InP-based material systems have resulted in transistors

U.S. Government work not protected by U.S. copyright

Table 1. Material properties and circuit maturity of various

semiconductor technologies. Footnotes: 1 InAs channel, 2
InGaAs channel, 3 SiC substrate.

In order to address the challenges of next-generation

RF system requirements, substantial innovation in
compound semiconductor materials, devices, circuits,
and integration technologies is required. The DARPA
Microsystems Technology Office has invested in a
number of programs which seek to provide this
innovation. The DARPA Nitride Electronic NextGeneration Technology (NEXT) program [6] is

Table of Contents

developing high performance nitride transistors for

high-speed RF, analog and mixed signal electronics,
thus overcoming the Johnson figure of merit limit to
achieving simultaneous high-speed operation and high
breakdown voltage. The DARPA Microscale Power
Conversion (MPC) program [7] is developing nitridebased technology to enable dynamic envelope-tracking
power conversion embedded in RF radiating elements.
The DARPA Diverse Accessible Heterogeneous
Integration (DAHI) program [8] is developing
transistor-scale heterogeneous integration processes to
intimately combine advanced compound semiconductor
(CS) devices, as well as other emerging materials and
devices, with high-density silicon CMOS technology.
This paper reviews the latest technical progress of these
three DARPA programs.

NEXT has aggressively improved device yield and

circuit complexity, achieving a 501-stage ring oscillator
using both enhancement-mode and depletion-mode
HEMTs on a single substrate.

II. DARPA NEXT PROGRAM

The DARPA NEXT program has made significant
strides in enhancing the capabilities of GaN transistor
technology to more fully realize GaNs potential for
high speed-high breakdown devices, as indicated by its
superior Johnson figure of merit [10]. As reported
previously [6], NEXT has aggressively pushed the
operating speed of GaN HEMTs by simultaneously
minimizing carrier transit time, maximizing electron
density, reducing access resistances, and optimizing
parasitic capacitances with novel device structures.
The DARPA NEXT program goals focus on GaN
enhancement-mode and depletion-mode HEMT
performance, yield, uniformity, and reliability. These
are shown in Figure 1, with the check marks indicating
metrics that have been met by the program. This table
indicates the considerable success that the DARPA
NEXT performers have achieved in relation to the
program goals.

Figure 2. Plot of fmax versus fT for GaN HEMTs

developed in the DARPA NEXT program. State-of-theart GaN HEMTs developed before NEXT shown for
comparison.
III. DARPA MPC PROGRAM
The DARPA MPC program has focused on
leveraging recent progress in GaN transistor technology
to develop GaN MMIC-based RF power amplifiers
which utilize envelope-tracking to achieve very high
efficiency at X-band frequencies. As reported
previously [7], the program envisions co-designing a
MMIC power amplifier with a dynamic voltage power
supply modulator consisting of a very fast GaN power
switch.
MPC program participants have made substantial
progress in advancing the state-of-the-art in envelopetracking power supply technology. Figure 3 plots
power-added efficiency versus operating frequency for
state-of-the-art power amplifiers. Results from the MPC
program show the efficiency increase from 20% to over
50% at 10GHz. Similarly, Figure 4, which plots
efficiency versus envelope bandwidth, shows that the
MPC program achieved a 500MHz RF envelope
bandwidth with an efficiency of 40% or greater, which
is more than an order of magnitude increase over the
state of the art (20MHz).

Figure 1. DARPA NEXT program goals. Check marks

indicate goals which have been met.
The current status of HEMT operating speed in the
DARPA NEXT program is shown in Figure 2.
Aggressive device scaling has resulted in enhancementand depletion-mode GaN HEMTs with dramatically
improved unity-gain cutoff frequency (fT) and
maximum oscillation frequency (fmax) as compared to
the state-of-the-art prior to the program. Additionally,

10

Table of Contents

mixed-signal electronics lies in the integration of CS

materials with silicon technology in a way that will
allow the advantages of the two technology types to be
optimally combined.
Figure 5 illustrates the potential impact of
heterogeneous integration in RF/mixed signal systems,
using a representative transceiver as an example.
Essentially all major components in a typical transceiver
can potentially benefit from the reduced parasitics of
heterogeneous integration, utilizing the benefits of highperformance CS materials with the control and
calibration capabilities of Si CMOS.
Figure 3. Plot of power-added efficiency versus output
frequency for state-of-the-art power amplifiers.

Figure 5. Diagram of a representative transceiver illustrating

the preferred set of device technologies for optimal
performance of each transceiver component.

To that end, the DARPA DAHI program is

developing transistor-scale heterogeneous integration
processes to intimately combine advanced compound
semiconductor (CS) devices, as well as other emerging
materials and devices, with high-density silicon CMOS
technology. The ultimate goal of DAHI is to establish a
manufacturable, accessible foundry technology for the
monolithic heterogeneous co-integration of diverse
(e.g., electronic, photonic, MEMS) devices, and
complex silicon-enabled architectures, on a common
substrate platform for defense and commercial users.
This capability will not only have significant impacts on
the performance of both military and commercial
microsystems, but it also represents a new paradigm for
the CS electronics community.
One element of DAHI, the Compound
Semiconductor Materials on Silicon (COSMOS) thrust,
has demonstrated three different approaches (shown in
Figure 3) to achieving InP BiCMOS integrated circuit
technology featuring InP HBTs and deep submicron Si
CMOS [12][13][14] for RF and mixed signal circuits.
DAHI/COSMOS performers have demonstrated
complex heterogeneously integrated mixed-signal
circuit designs, including digital-to-analog converters
(DACs) with unprecedented SFDR performance in the
GHz output frequency regime [15] as well as
revolutionary ultra-wide band ADCs. The ADC design
employs a time-interleaved architecture utilizing InP

Figure 4. Plot of power-added efficiency versus RF

envelope bandwidth for state-of-the-art envelopetracking power amplifiers.
IV. DARPA DAHI PROGRAM
The preceding sections have highlighted many of the
advantages of CS materials for RF modules. However,
despite the advantages of CS materials, Si CMOS-based
technologies have increasingly been employed in highperformance RF/mixed signal systems. These
technologies have leveraged the enormous investments
in digital CMOS device scaling and process
development to achieve tremendous levels of
complexity and integration, while also demonstrating
far higher levels of yield and manufacturability than any
CS technology. The integration density of Si-based
technologies has enabled novel on-chip digital
correction and linearization techniques (for example,
[9]), producing excellent RF and mixed-signal circuit
performance despite the limitations of silicons material
properties.
Such correction techniques have the potential to
produce dramatic RF and mixed-signal performance
improvements in CS electronics as well; however, CS
technologies lack the integration density and yield to
implement these circuit concepts. Given these trends, it
is our view that the future of high-performance RF and

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11

Table of Contents

HBTs for track-and-hold circuitry and 130nm Si CMOS

to provide the sub-ADCs and the circuitry required for
complex time-interleaving. This ADC represents the
most complex heterogeneously integrated circuit to
date, with ~1000 InP HBTs, ~16,000 Si HBTs, and
2500 Si MOSFETs, with more than 1800 heterogeneous
interconnects between the InP HBT chiplet and the Si
base chip. This approach has resulted in an ultra-wide
band ADC with state-of-the-art signal-to-noise-anddistortion ratio (SINAD) of over 30dB across frequency
ranges of 2.75-8.75GHz and 14.25-20.25GHz. This
performance level is on par with the most advanced
ADCs currently demonstrated [16], which required the
use of 32nm CMOS technology (as compared to the
130nm CMOS used by the DAHI/COSMOS ADC). It is
expected that the combination of InP HBTs
heterogeneously integrated with an advanced CMOS
node would enable dramatically improved SINAD at
higher frequencies, far in excess of the current state-ofthe-art. DAHI performers have also demonstrated the
worlds first GaN + CMOS RF amplifier using
monolithic heterogeneous integration of GaN HEMTs
with Si pMOS gate bias control [17].
Recently, a new DAHI Foundry Technology thrust
was initiated [18] to advance the diversity of
heterogeneous device and materials available in a
silicon-based platform. This foundry will seek to
include a wider array of materials and devices
(including, GaN and MEMS technologies) with
complex silicon-enabled (e.g. CMOS) architectures and
thermal management structures on a common silicon
substrate platform. The goal of the DAHI Foundry
Technology thrust is to develop a mature, reliable
heterogeneous integration technology in a cost-effective
foundry.

REFERENCES
[1] R. Lai, et al, Fabrication of InP HEMT Devices with
Extremely High Fmax, 2008 International Conference
on InP and Related Materials, Versailles, France.
[2] S.E. Turner, D.E. Kotecki, Direct Digital Synthesizer
With Sine-Weighted DAC at 32-GHz Clock Frequency
in InP DHBT Technology, IEEE J. Solid-State Circuits,
Vol. 41, No. 10, 2006, pp. 2284-90.
[3] Y.F. Wu; M. Moore, A. Saxler, T. Wisler, P. Parikh,
40W/mm Double Field Plated GaN HEMTs, 64th
Device Research Conference, 2006, pp. 151-152.
[4] Crees SiC Schottky Diode Chip CPW2-1200-S050B.
[5] Crespin, E. R., et al., "Fully integrated switchable filter
banks," 2012 IEEE MTT-S, pp.1-3, 17-22 June 2012.
[6] Albrecht, J.D.; Tsu-Hsi Chang; Kane, AS.; Rosker, M.J.,
"DARPA's Nitride Electronic NeXt Generation
Technology Program," 2010 IEEE C.S. Integrated Circuit
Sym. (CSICS), pp.1-4, 3-6 Oct. 2010.
[7] Albrecht, J.D.; Kane, A; Tsu-Hsi Chang, "DARPA's
Microscale Power Conversion Program," 2012 IEEE
Compound Semiconductor Integrated Circuit Symposium
(CSICS), pp.1-4, 14-17 Oct. 2012.
[8] Green, D. S., Dohrman, C. L., & Chang, T. H., The
DARPA Diverse Accessible Heterogeneous Integration
(DAHI) Program: Status and Future Directions. 2014
Compound Semiconductor Manufacturing Technology
conference (CS MANTECH), 2014.
[9] Adrian Tang, et al. , A Low Overhead Self-Healing
Embedded System for Ensuring High Performance Yield
and Long- Term Sustainability of a 60GHz 4Gbps Radioon-a-Chip, 2012 ISSCC Digest, 2012.
[10] E.O. Johnson, "Physical limitations on frequency and
power parameters of transistors", RCA Review, vol. 26,
pp. 163-177, 1965.
[11] Fang, S. F.; Adomi, K.; Iyer, S.; Morko, H.; Zabel, H.;
Choi, C.; Otsuka, N., Gallium arsenide and other
compound semiconductors on silicon J. Appl. Phys., 68,
R31-R58 (1990).
[12] A. Gutierrez-Aitken, et al., Advanced heterogeneous
integration of InP HBT and CMOS Si technologies for
high performance mixed signal applications, IEEE
Microwave Symposium Tech. Dig., pp. 1109-1112, 2009.
[13] T.E. Kazior, et al., A high performance differential
amplifier through the direct monolithic integration of InP
HBTs and Si CMOS on silicon substrates, IEEE
Microwave Symposium Tech. Dig., pp. 1113-1116, 2009.
[14] J.C. Li, et al., Heterogeneous wafer-scale integration of
250nm, 300GHz InP DHBTs with a 130nm RF-CMOS
technology, IEDM Tech. Dig., pp. 944-946, 2008.
[15] Oyama, B., et al. "InP HBT/Si CMOS-Based 13-Bit
1.33Gsps Digital-to-Analog Converter with >70 dB
SFDR," 2012 CSICS Tech. Dig., pp.1-4, 2012.
[16] Kull, L., et al., "A 90GS/s 8b 667mW 64 interleaved
SAR ADC in 32nm digital SOI CMOS," 2014 ISSCC
Proc., pp.378-9, 2014.
[17] W. E. Hoke, et al. Monolithic integration of silicon
CMOS and GaN transistors in a current mirror circuit, J.
Vac. Sci. Tech. B 30(2), pp. 02B101-1-6, 2012.
[18] http://www.darpa.mil/Our_Work/MTO/Programs/DAHI/
DAHI_Foundry_Technology.asp.

ACKNOWLEDGEMENT
The authors would like to thank the program
participants in the DARPA NEXT, MPC, and DAHI
program. The authors also thank the NEXT, MPC, and
DAHI government team members for their support.
Finally, the authors thank the original DARPA program
managers: John Albrecht (NEXT and MPC), Sanjay
Raman (DAHI), and Mark Rosker (COSMOS).
The views, opinions, and/or finding contained in this
article/presentation are those of the author(s)/
presenter(s) and should not be interpreted as
representing the official views or policies, either
expressed or implied, of the Defense Advanced
Research Project Agency or the Department of Defense.

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Future of GaN RF Technology in Europe

H. Blanck, J. Splettster, D. Floriot
United Monolithic Semiconductors GmbH
Ulm, Germany
herve.blanck@ums-ulm.de
Abstract In the last years GaN has remained a key
technology in Europe in particular, but not only, for RF
Applications. After an intensive period of research and
development the scope has shifted towards industrialization
and product development. This is especially true for the
applications up to around 20GHz where systems are now
being built using European GaN-based components. At the
same time, an increasing part of the research activity has
moved toward higher frequencies beyond 20GHz.
Index Terms Gallium Niride, MMICs, Microwave
device, millimeter wave devices.

TABLE I.
GAN PLAYERS IN EUROPE
Topic
Substrate
Epitaxy
Device &
Process

I. INTRODUCTION
The interest for GaN technologies and components in
Europe remains at a very high level. They are viewed as a
strategic part of future systems. The performances
achieved with GaN components will be essential to
guaranty the availability of competitive systems in the
future. This is visible through the number of players
involved in this field starting from the substrate material
up to the final systems (Table I.). Through the very strong
worldwide competition some players have unfortunately
disappeared of stopped their activity on GaN but has been
compensated by the entrance of new players, for instance
spin-offs from research institutes. It is not possible to
present all work and results obtained recently in the frame
of this paper but some of the key elements have been
picked out and are being summarized below.

Circuit design
Module &
Systems
Characterisatio
n

Players
(non exhaustive)

Amonnoa, SiCrystala, Norstela

Epigana, IQEa, CLASSICa, ATL III-V Lab,
IMEC, IAF, FBH, Ulm Uni., Linkeping Uni.,
CRHEA, etc
UMSa, IAF, FBH, ATL III-V Lab, Ulm Uni.,
RWTH Aachen, NXPa, IMEC, IEMN, Selexa,
OMMICa etc
IAF, FBH, Airbus Defence and Spacea,
Thalesa, UMSa, TESATa, Alcatel-Lucenta,
SAABa, Ericssona, Selexa, AMSa, TNOa, ATL
III-V Lab, IEMN, etc...
Thalesa, Airbus Defence and Spacea, IAF,
NXPa, TNOa, Selexa, Alcatel-Lucenta, Tesata,
Astriuma, etc...
Bristol Uni., UMSa, IAF, ATL III-V Lab, FBH,
IEMN, Padova Uni., Tor Vargata Uni., IRCOM,
XLIM, ISOM, etc...

A. INDUSTRIAL OR COMMERCIAL ACTIVITY

II. MATERIAL
Getting the appropriate Material is a prerequisite for
achieving sufficient performance. For some applications it
is also essential to have access to material that is not bond
to export limitations. Several projects (MODs, European
Union, Space agencies) have been dedicated to developing
the corresponding supply chain in order to allow full
independence for European products. The feasibility and
performances have been largely demonstrated up to
100mm. The industrialization and qualification of this
material at foundry level remains to be done and will be
the objective of the next projects.

978-1-4799-3622-9/14/$31.00 2014 IEEE

Fig. 1: Mapping of the sheet resistance of a HEMT structure

grown on a 100 (MANGA project [1]).

13

Table of Contents

IV. CIRCUITS AND APPLICATIONS

II. TECHNOLOGY AND DEVICES

A. Foundries

Many functions can benefit from the intrinsic

advantages of GaN. Table II shows the possible evolution
for radar applications for instance.

Commercial foundries have been very active since

several years and the first technologies have been
successfully qualified [2]. Fig. 2 shows an example of the
reliability results during the qualification of 3GH50-10 at
UMS. Based on these technologies European GaN
components are being integrated in today on new systems.
The substrate of choice remains in almost all cases SiC,
thanks to its exceptional RF and thermal properties, but
some players also focus on Si, with its inherent substrate
dimension and cost advantage [3].

TABLE II.

HPA

S-band

short-term solution
Si BJT -> GaAs HBT

mid-term solution
GaN HEMT

X-band

GaAs HBT, P-HEMT

GaN HEMT

C-Ku band

GaAs P-HEMT

GaN HEMT

Core-chip

all bands

GaAs P-HEMT

SiGe

LNA

all bands

GaAs P-HEMT

GaN HEMT

T/R Switch

all bands

Circulator

Power MEMS

(Courtesy of Thales)
A. Power bars
Many products have been put on the market since 2012.
Fig. 4 shows the performance of a 50-Watt power bar

commercialized by NXP.
A major advantage of GaN component is to allow
operation modi that are normally difficult, if at all, to
achieve with LDMOS devices. For instance digital
transmitters
have
been
successfully
fabricated
demonstrating a world record drain efficiency of 85%.

Fig. 2: MTF versus 1/kT Vds=50V - 106 hours @ 200C [2].

B. Devices
So far, most of the work has been done devices based
AlGaN/GaN hetero-structures, in particular for
applications up to 20GHz where the current products are
being fabricated. For higher frequencies, on which most of
the research and development is now focused, the
situation is still quite open. A few alternatives are
competing including conventional AlGaN, InAlN or AlN
based hetero-structures [4]-[10] (see Fig. 3.
AlN/GaN-on-Si DHFET

35

Lg = 120 nm

30

20 dB/dec

VDS = 20 V

Gain (dB)

25
U
MSG
H21

20
15
10

ft = 75 GHz

Fig. 4: Typical power bar performance inside a demo-board.

(Courtesy of NXP).

fmax (U) = 202 GHz

5
1

10
100
Frequency [GHz]

Fig. 3: Typical power bar performance inside a demo-board.

(Courtesy

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Fig. 6: Schematic and picture of the X-Band transmitter with a

GaN MMIC power amplifier. (Courtesy of ESA, Syrlink,
TESAT and Fraunhofer IAF).

Fig. 5: Performance a digital Power amplifier combining a

CMOS driver with a GaN chips as last stage. (Courtesy of NXP
and Fraunhofer IAF).

B. Applications and circuits

In the frame of a project (GREAT2 [11]) supported by
the European Space Agency (ESA) a first GaN MMIC has
been sent to Orbit in 2013 as a part of an X-Band
transmitter inside a satellite dedicated to the Earth
observation (PROBA V, see Fig. 6). The transmission link
is operating since one year in space without incident.
Radar systems can especially benefit from the use of
GaN circuits and many designs have been fabricating
reaching the state-of-the art. Fig. 7 and Fig. 8 show some
results on an X-Band HPA and a robust LNA respectively.
The HPA reaches an extremely high efficiency of 50%
across a wide band-width close to 2GHz. The LNA
reaches good low noise figures and is able to sustain an
input power of 10W without any damage.
Looking at higher frequencies Fig. 9 shows an example
of the results obtained on a two-stage power amplifier
30GHz based on a 100-nm gate length technology on
AlGaN/GaN.

978-1-4799-3622-9/14/$31.00 2014 IEEE

Fig. 7: X-band high efficiency power amplifier. (Courtesy of

Thales).

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Table of Contents

and technical support from: EDA, EC, ESA, BMBF, DLR,

BWB, DGA, CNES, WTD81, FMV, MDE, Difesa, dstl,
Defensie, ANR, MiUR EPSRC..
REFERENCES
[1] M. Mikulla, M-A. Poisson, S. Storm, E. Zanoni, N.
Henelius, M. Kuball, Manga: Manufacturable GaN,
EUMW 2011.
[2] D. Floriot, H. Blanck, D. Bouw, F. Bourgeois, M. Camiade,
L. Favde, M. Hosch, H. Jung, B. Lambert, A. Nguyen2,K.
Riepe, J. Splettster, H. Stieglauer, J. Thorpe, and U.
Meiners, New Qualified Industrial AlGaN/GaN HEMT
Process: Power Performances & Reliability figures of
merit, EUMW 2012, Amsterdam.
[3] M. Rocchi, 100nm GaN/Si mmW foundry service and
MMICs, CS international 2014.
[4] O. Jardel, J.-C. Jacquet, L. Baczkowski, D. Carisetti, D.
Lancereau, M. Olivier, R. Aubry, M.-A. di Forte Poisson,
C. Dua, S. Piotrowicz and S. L. Delage. InAlN/GaN
HEMTs based L-band high-power packaged amplifiers,
International Journal of Microwave and Wireless
Technologies,
available
on
CJO2014.
doi:10.1017/S175907871400004X.
[5] I. Rossetto, F. Rampazzo, R. Silvestri, A. Zanandrea, C.
Dua, S. Delage, M. Oualli, M. Meneghini, E. Zanoni, G.
Meneghesso Comparison of the performances of an
InAlN/GaN HEMT with a Mo/Au gate or a Ni/Pt/Au gate,
European Symposium on Reliability of Electron Devices,
Failure Physics and Analysis, Volume 53, Issues 911,
SeptemberNovember 2013, Pages 14761480.
[6] O Jardel, G Callet, D Lancereau, J-C Jacquet, T Reveyrand,
N Sarazin, R Aubry, S Leger, E Chartier, M Oualli, C Dua,
S Piotrowicz, E Morvan, M A Di Forte Poisson, S L
Delage, First demonstration of AlInN/GaN HEMTs
amplifiers at K band, 2012 IEEE/MTT-S International
Microwave Symposium Digest.
[7] A. Malmros, P. Gamarra, M. Thorsell, M.-A. di FortePoisson, C. Lacam, M. Tordjman, R. Aubry, H. Zirath, N.
Rorsman, Evaluation of an InAlN/AlN/GaN HEMT with
Ta-based ohmic contacts and PECVD SiN passivation,
physica status solidi (c), 11, 3-4, 1610-1642.
[8] F. Medjdoub, Y. Tagro, B. Grimbert, D. Ducatteau, N.
Rolland, toward highly scaled AlN/GaN-on-Silicon
devices for millimeter wave applications, International
Journal of Microwave and Wireless Technologies, 2013,
5(3), pp. 335-340
[9] M. Mikulla, A. Leuther, P. Brckner, D. Schwantuschke, A.
Tessmann, M. Schlechtweg, O. Ambacher, M. Caris,
European Microwave Week 2013, Nuremberg, Germany.
[10] http://www.alinwon-fp7.eu/fp7/
[11] http://www.great2-project.com/index.html
[12] J. Chron, M Campovecchio, R. Qur, D. Schwantuschke,
R. Quay, O. Ambacher, High-Efficiency Power Amplifier
MMICs in 100 nm GaN Technology at Ka-Band
frequencies, European Microwave Week, 6-8Oct 2013,
Nuremberg, Germany.

Fig. 8: Noise figure of a robust LNA able to sustain 10W input

power without damage. (Courtesy of Airbus DS).

Fig. 9: Measurement results of the two-stage MMIC from 28

GHz to 32 GHz at 26.3 dBm of available input power. (Courtesy
of Fraunhofer IAF).

VII. CONCLUSION
A very significant activity on the development and
production of GaN-related devices and circuits is on-going
in Europe. All domains are involved covering material to
system applications. A complete industrial supply chain is
being put in place and the first products are currently
being integrated in new systems and have been sent to
Space already. For the future, the focus is shifting towards
higher frequencies and some of the best results have been
obtained in this area on conventional AlGaN-based
hetero-structures as well as InAlN or AlN-based ones.
ACKNOWLEDGMENT
The authors would like to thank all the European GaN
community for their support and contribution to this work.
The authors would also like to acknowledge the financial

978-1-4799-3622-9/14/$31.00 2014 IEEE

16

Table of Contents

GaN for Next Generation Electronics

Paul Saunier
TriQuint Semiconductor, Inc.
Richardson, TX, 75080
Abstract We report the development of a new generation
of GaN devices and their performance. This new E/D
technology based on Si-like processes will offer the
possibility of competing with Si-Ge and C-MOS devices for
mixed-mode circuits and mm-Wave array applications. The
advantage comes from their superior breakdown voltages
and ft/fmax while using processes and geometries only known
so far by the Si industry. We are reviewing the performances
of these devices developed under the DARPA NEXT
program at TriQuint and other companies (HRL). At
TriQuint, 30nm self-aligned gate InAlN/AlN/GaN devices
achieved simultaneous fT/fmax of 359/347GHz. Thanks to
their reduced geometry, these devices make excellent lowvoltage RF devices. We published excellent performances at
10GHz with up to 67-69% PAE at 6V bias and 30GHz with
up to 14.4dB associated gain and 2.6W/mm, 39.6% PAE at
8V bias. The Noise Figure of these devices at 10GHz was
~0.25dB with 3V drain bias. HRL has demonstrated fT/fmax
as high as 454/444GHz at Vd=3V with a 20nm gate selfaligned device.

continuous scaling of GaN HEMTs towards THz operation.

We speculate on what such a GaN-on-Si technology could
bring to the field by allowing Si-like integration level.
II. E/D APPROACH AND MATERIAL GROWTH
Our group at TriQuint first reported monolithic
integration of enhancement- and depletion-mode (E/D)
InAlN/AlN/GaN HEMTs using a low-cost E-mode gate
recess approach with the advantage of low-resistance
access regions even for the E-mode device [2]-[3].
Sets D-mode pinch-off voltage
Sets E-mode pinch-off voltage

100-mm SiC
**Compatible with
TriQuints 100-mm
GaAs/GaN
production line

It is tempting to envision a GaN-on-Si technology based on

such devices where a fabrication process fully compatible
with a Si foundry would allow the use of 8 wafers but more
importantly the use of a large number of interconnect layers
with micron and sub-micron geometries, both unknown to
the III-V world. Preliminary work has been reported by
Raytheon with GaN transistors on a 200 mm GaN-on-Si
wafer (grown by MBE) fabricated with Au free metallurgy.

AlN

In0.18Al0.82N

GaN

E-mode device is an AlN/GaN HEMT

InAlN provides low-resistance access regions

Selective plasma
recess to AlN

Fig. 1. Sketch of TriQuint InAlN/AlN/GaN material- and device

structure for E/D GaN based technology.

Index Terms InAlN, E/D-mode, AlGaN/GaN HEMT,

scaling, self-aligned gate

The vertically-scaled HEMT structure depicted in the

inset of Figure 1 is grown on 6H-SiC in a high throughput
GaN MOCVD production tool. Following a nucleation
layer, a GaN buffer is grown. The vertically scaled
barrier layer consisted of an AlN transition layer followed
by a thin In0.18Al0.82N layer lattice matched to GaN.
Lehighton measurements gives a sheet resistivity of 220
/ 1.2%.

I.INTRODUCTION
Group III-nitride material system offers unique
combination of high breakdown voltage field, high electron
velocity and large sheet electron density. It has enabled
HEMTs devices and PAs with significantly higher (~10 X)
output power than other systems as GaAs and InP and
operating at much higher voltage (~20- to >40V). Over the
last few years it has been possible to drastically increase the
ft/fmax in the range of 350- to 450GHz reaching that of Si
deep submicron technology, while keeping breakdown
voltage in the 7V >10V range. This is accomplished by
borrowing Si-like fabrication concepts such as self-aligned
gates (SAG), CMP, material regrowth (here, of n+ ohmic
contacts), use of ALD for dielectric and metal deposition.
Monolithic integration of E/D mode GaN HEMT in 501stage ring oscillators have been demonstrated. This paper
reviews recent progress of high frequency GaN HEMT
performances and discusses key technologies that enable

978-1-4799-3622-9/14/$31.00 2014 IEEE

E-mode

D-mode

Another approach pioneered by HRL [1] is shown in

Figure 2 where the E- and D-mode epitaxial layers are
integrated using selective area regrowth by MBE. The
process starts with E-mode epi growth followed by
patterning of a SiO2 growth mask on E-mode device area,
dry etching of exposed E-mode area and D-mode epi
regrowth.
III. REQUIREMENTS FOR FT ~300-450GHZ
Simple simulations allow an understanding of the

17

Table of Contents

contribution of different device parameters on ft.

define and etch

the area to be re-grown for contacts. The MBE re-growth
step follows. The process leaves Poly-GaN on these
dummy gates. A planarization step including dielectric
deposition followed by CMP removes the Poly-GaN (on
top of the gates) and reveals these gates. The dummy gate
material is etched and the resulting gate trunk is ready for
gate-shrink (as described earlier). Following this step, Emode devices are recessed (while the D-mode are masked
by a simple lithography level).

dummy gate

Recess S/D

n+ ohmic regrowth

Ohmic metal

Planarization

DG Formation Ohmic recessOhmic regrowth Metallization

Fig. 2. HRL vertically scaled DH-HEMT epitaxial structures

with (a) GaN (2.5nm)/AlN (3.5nm) top barrier for D-mode
and (b) thinner Al0.5Ga0.5N (2.5nm) /GaN (2.0nm) top
barrier for E-mode

CMP

With a ~5 passivation, conventional alloyed contact

(Rc~0.3Ohm.mm), a small ~0.1m (T-) gate length
only brings ft to ~120GHz. Etched passivation, reduced
gate length of ~80nm allows ft ~ 150-180GHz. Further
gate length reduction will not result in substantial ft
improvement. The next limitation is source resistance
including ohmic contact- and access resistance. With regrown ohmic contact Rc ~ 0.1-Ohm.mm, ~1m sourcedrain spacing ft can reach 200GHz-250GHz. Decreasing
the gate length to less than ~50nm does not bring forth
drastic improvement. Further ft increase comes from
reducing Source-Drain spacing in conjunction with further
reduction of the gate length. For gate length <<0.1m the
e-beam direct write process is not reliable/reproducible and
too slow (due to the lower dose needed) and a side-wall /
gate-shrink process is very advantageous. At TriQuint we
have achieved ft of ~ 300GHz with source-drain spacing of
~ 0.15m Source-Drain spacing and gate length ~ 35nm
using a re-aligned e-beam written shrink gate process. As
the gate length is reduced, it becomes impossible to use
conventional metal evaporation for the gate trunk. ALD
metal deposition allows T-gate with foot print of 20-30nm
and trunk height 1000A to 1500A. We have done so and at
TriQuint we have achieved ft / fmax of 334GHz/446GHz.
Further improvement call for a Self-Aligned Gate (SAG)
process as described next.

DG removal Sidewall shrink

Recess

ALD

ALD Gate Metal

Channel etchback

Fig. 3. Flow diagram of TriQuint Self-Aligned Gate (SAG)

process.

ALD metal deposition is next followed by gate T-cap

formation. The gate-cap is used as a mask for etching the
ALD metal in unwanted areas. The rest of the front-side
fabrication is fairly conventional.

Mo/Au

n+GaN

B. Ohmic contact re-growth

Non-alloyed
Metal
InAlN/AlN
GaN

Regrowth Recess
regrowth n+ GaN
metallization

(InAlN/AlN)

GaN

Carrier concentration = 3.3x1020 cm-3

Contact
of n+ regrowth
to InAlN
Contact
of n+ regrowth
to InAlN (2DEG)

Metal-to-regrowth:
0.01 -mm, 25 /sq
Effective metal-to-2DEG:
0.04 -mm, 250 /sq

IV. SELF-ALIGNED GATE AND KEY PROCESS

DEVELOPMENTS

Fig. 4. MBE re-grown ohmic contacts: sketch of completed

channel, TEM of contact showing re-grown GaN overlapping
the InAlN barrier and SEM of the source-drain area.

A. Self-Aligned Gate (SAG)

Figure 3 shows the flow diagram of TriQuint process.
First dummy gates are fabricated by substitution i.e.
etching through dielectric, refill and etching of the
surrounding dielectric. These gates are used as mask to

We have developed a reproducible process where the

GaN based material is first recessed a few ten nanometers
followed by MBE GaN n+ re-growth [4]. The

18

Table of Contents

corresponding layer has a sheet resistivity of 25- to 40Ohm/sq. The non-alloyed contact resistance to this layer
is 0.01-Ohm.mm and the effective metal to 2-DEG
contact resistance is typically < 0.1Ohm.mm. Figure 4
summarizes the results, showing a sketch of the structure,
a SEM view of the channel and a TEM cross-section
showing the n+ contacting the InAlN/GaN layers.

~10V.

C. Gate-Shrink process and recess

Base opening

88 nm

0.0

2.0
ID (A/mm)

1.0
0.5

In this (well-known) process a <0.1m gate-trunk pattern

is first defined in PMMA and etched in the dielectric layer
by RIE. ALD isotropic dielectric deposition followed by
anisotropic RIE etching gives the side-wall shrink. Deep
submicron gate footprints are reproducibly achieved
giving controlled ~30nm gate opening, an example is
shown on Figure 5.

(a)

1.5
Ron = 0.
25 -mm

ID (A/mm)

2.0

2.5

E-mode
-1<=VG<= 2 V

0 mS/mm
gds = 15

2
VDS (V)

gds = 226

mS/mm

(b)

1.5
1.0
0.5

D-mode
-3<=VG<=2 V

0.0

Ron = 0.2
6 -mm

2.5

2
3
VDS (V)

Fig. 6. DC characteristics of TriQuint E- and D-mode devices.

Gm max are 1.4- and 1,1S/mm respectively, threshold voltages are
Vt = +0.3V and -1.14V

HRL results are a benchmark for the GaN technology;

by reducing the Source-Gate and Gate-Drain spacing to
~40nm or less they have shown that the critical Source
Starvation can be suppressed; this results in a very
desirable flat Gm as a function of Vg as shown in Figure 6.
For the D-mode device, Gm is larger than 1S/mm from
Vg=0.25V to +2V. For the E-mode, Gm is larger than
1S/mm from ~+.25v to + 1.75V reaching 2S/mm at
~+1.3V.

Sidewall shrink

24 nm

Figure 5. Side-wall shrink process for deep sub-0.1m gate.

The next step was the selective gate recess: the D-mode
devices were masked and the E-mode devices recessed.
The recess process was performed by ICP based on BCl3.
The developed recess process stops at the AlN spacer
layer. The resulting threshold uniformity measured over
4 wafers is 150mV or less. Reproducibility wafer to
wafer and run to run is less than 100mV.

Fig. 7. DC characteristics of HRL self-aligned D- and E-mode

device with 60nm Gate Length and 40nm S-G and G-D spacing.

D. ALD gate metal

Ft as a function of Vd on highly scaled devices:

The impact of lateral S-D scaling on ft is discussed.
Typically, with an unscaled S-D spacing (Lgs = Lgd >
500nm) ft is maximum at low drain voltage (1- to 2V)
then decreases with Vd. Both TriQuint and HRL observed
that for aggressive scaling of S-D spacing (Lgs = Lgd ~
40nm) ft shows a continuous increase with Vd above the
saturation voltage (~0.5V). Using Molls method to
extract the drain delay, one can show that this drain delay
shows a monotonic decreasing transit time with
increasing voltage. More importantly, the observed
decrease in transit time indicates an increase in average
electron velocity reaching 1.5 x107 cm/s at ~ 5V
compared to 1.1 x107 cm/s at lower drain voltage (~1V).
Figure 8-a shows the ft function of drain voltage for 2

As gate length are shrunk below 50nm it becomes

impossible to adequately deposit gate metal by
conventional evaporation and insure metal continuity
from trunk to gate-cap. ALD is the perfect tool to
isotropically deposit metals for deep sub-0.1m gates.
V.DC AND RF CHARACTERIZATION
The low ohmic contact resistance resulting from n+ GaN
in direct contact with the channel, combined with low
resistance <50 nm long 220 /sq source and drain access
regions, results in sub-0.3 -mm on-resistance.
Transconductance and drain current are in excess of 1
S/mm and 2 A/mm. Off-state breakdown voltage BVDS
measured using the drain current injection method is

19

Table of Contents

TriQuint devices with respectively S-D=360nm and

101nm. Figure 8-b shows HRL Peak ft for Gen.I
(unscaled and Gen.II (scaled) devices

sd

performance of 2 x 50m non-scaled devices with a

tuning for a compromise between high associated gain
and good PAE. Fig. 8 shows that at 8V bias 2.6W/mm is
obtained with 13.1dB associated gain and 45.7% PAE. By
tuning a device further for higher gain while sacrificing
some efficiency we achieve 2.6W/mm with 14.1dB gain
and close to ~40% PAE.

sd

Full microwave and mm-Wave performance evaluation of

deeply-scaled devices is still to be performed. We
anticipate that the increasing ft as a function of drain
voltage and the elimination of source starvation will offer
a tremendous advantage in performance.
VI.OPPORTUNITY FOR GAN-ON-SI
Fig. 8-a. ft function of Vd for TriQuint un-scaled and scaled
devices.

It is tempting to envision a GaN-on-Si technology based on

such devices where a fabrication process fully compatible
with a Si foundry would allow the use of 8 wafers but
more importantly the use of a large number of interconnect
layers with micron and sub-micron geometries, both
unknown to the III-V world. Preliminary work has been
reported by Raytheon with GaN transistors on a 200 mm
GaN-on-Si wafer (grown by MBE) fabricated with Au free
metallurgy.
Acknowledgements
We would like to thank Dr. Keisuke Shinohara (HRL) for
providing the author with (already published) detailed
charts on their E/D device performances and Dr. Tom
Kazior for sending some information and charts on
Raytheons Si CMOS Compatible GaN Growth and
Fabrication.

Fig. 8-b. HRL Gen I (un-scaled) and Gen II (scaled) device ft

dependence on Drain Voltage.

At 5V and 400mA/mm the best TriQuint Enhancementmode devices had ft/fmax =334GHz/446GHz. Best HRL
devices have ft/fmax =444GHz/454GHz at Vds=3V.
30

1.09W/mm
16.4dB
25.2%

[1] K. Shinohara, D. C. Regan, Y. Tang, A. L. Corrion, D. F.

Brown, J. C. Wong, J.F. Robinson, H. H. Fung, A.
Schmitz, T. C. Oh, S. J. Kim, P. S. Chen, R. G. Nagele, A.
D. Margomenos, and M. Micovic, Scaling of GaN HEMT
and
Schottky
Diodes
for
Submillimeter-Wave
Applications, IEEE Transactions on Electron Devices, vol.
60, pp. 2982-2996 Oct. 2013.
[2] M. Schuette, A. Ketterson, E. Beam, T. Chou, M. Pilla, H.
Q. Tserng, B. Song, P. Fay, H. Xing, X. Gao S. Guo, and
P. Saunier, State-of-the-Art E/D InAlN/AlN/GaN HEMTs
Technology, GOMACTech 2013 March 11-14 2013, Las
Vegas.
[3] Y. Tang, P. Saunier, R. Want, A. Ketterson, X. Gao, S.
Guo, G. Snider, D. Jena, H. Xing, and P. Fay Highperformance monolithically-integrated E/D mode
InAlN/AlN/GaN HEMTs for mixed-signal applications,
in Proc. IEEE Intl. Electron Dev. Mtg., San Fransisco,
CA, 2010, pp. 30.4.1-30.4.4.

60
50

20

40

15

30

10

20

10

PAE (%)

Pout (dBm) and Gain (dB)

25

2.6W/mm
14.1dB
39.16%

References

0
0

10

15

20

Input Power (dBm)

Fig. 9. 30GHz and 8V bias: 2 X 50m device tuned for high

gain. At lower input power, as much as 16.4dB associated
gain is reached with 1W/mm and 25% PAE

[4]

RF Power performance on NON-SCALED devices: at

TriQuint, we have evaluated the 30GHz load-pull

20

J. Guo et Al. , MBE-regrown ohmics in InAlN HEMTs

with a regrowth interface resistance of 0.05 Ohm-mm,
IEEE Electron Dev. Lett., vol. 33, pp. 525-527, April 2012

Table of Contents

An InP MMIC Process Optimized for Low Noise at Cryo.

P. . Nilsson1, J. Schleeh2, N. Wadefalk2, J. P. Starski1,H. Rodilla1, G. Alestig1, J. Halonen1, B.
1
1
1
Nilsson , H. Zirath , and J. Grahn .
1

Department of Microtechnology and Nanoscience (MC2), Chalmers University of Technology, 412 96

Gteborg, Sweden. per-ake.nilsson@chalmers.se.
2
LowNoiseFactory AB, Frlundagatan 37, 431 44 Mlndal, Sweden

Abstract An InP MMIC process was developed and

optimized for ultra-low noise amplifiers (LNAs) operating at
cryogenic temperature. The amplifiers from the process are
working up to 100 GHz. The processed wafers are 4 and
can carry more than 4000 3-stage units. For a significant
number of 6-20 GHz 3-stage LNAs we have measured an
average noise temperature of 5.8 K at ambient temperature
of 10 K, state of the art in this frequency range, and 66.3 K at
300K. Associated gain was 35.9 dB (10K) and 33.2 dB (300
K). The standard deviation at room temperature for 47
LNAs was 1.5 K for the noise and 0.3 dB for the gain.
Index Terms Cryogenic, InP HEMT, low noise
amplifier (LNA), MMIC.

TiPtAu gate
n-doped
In0.65Ga0.35As cap

In0.65Ga0.35As channel

NiGeAu contact

In0.40Al0.60As barrier

I. INTRODUCTION
Cryogenically cooled extremely low noise amplifiers
are required in many areas of radio astronomy and
advanced physics research to obtain demanded sensitivity.
The lowest noise achieved so far, at microwave
frequencies, is in amplifiers based on indium phosphide
high electron mobility transistors (InP HEMTs), cooled to
cryogenic temperatures. Noise temperatures as low as 1.2
K has been reached in a 4 GHz 8 GHz amplifier cooled
to 10 K [1].
Many of the largest present and future telescopes
combine arrays of small antennas to increase the
collecting area, even up to 1 km2 [2-4]. Each antenna in
the telescopes covers decades of bandwidth with several
cryogenically cooled receivers. The large number of
antennas as well as the large bandwidths makes a low
noise MMIC process the natural choice for this
technology.
Wideband cryogenic LNAs have previously been
published for both lower [5-7] and higher frequency bands
[8-9]. We have developed an InP MMIC process that has
been optimized for low noise at cryogenic temperatures
with excellent noise properties [7]. The process uses 4
InP wafers and is capable of producing a large number of
LNAs with a small deviation in performance.

978-1-4799-3622-9/14/$31.00 2014 IEEE

Fig. 1. STEM cross section of the 130 nm InP HEMT

optimized for low noise at cryogenic temperatures.

II. MMIC PROCESS

The MMIC process is based on a 130 nm InP HEMT,
with a Tg of 1 K at 6 GHz and 10 K [1]. The HEMT uses
a gate length of 130 nm placed on a barrier 14 nm from a
15 nm InGaAs channel, Fig.1. The ohmic contacts are
annealed and made from a NiGeAu stack. The entire
device is passivated by a SiN layer. The epi structure is
grown on an InP substrate. The channel mobility is
2
12000 cm /Vs at room temperature, but increases to over
2
60000 cm /Vs when the device is cooled to 10 K. The high
mobility at cryo shows the very low level of interface
scattering in this hetero structure. The annealed ohmic
contact resistance is 50 mmm at room temperature.
When the devices are cooled, there is a slight (20%)
increase in the ohmic contact resistance. Ft and fmax for the
HEMT are 210 GHz and 380 GHz respectively. The gate
leakage is below 1 A/mm. The extremely low noise is
due to an optimized quality of pinch off [1,10] at
cryogenic temperature and the simultaneously low gate
leakage current.

21

Table of Contents

Fig. 3. Schematic of the 3-stage 6-20 GHz

G MMIC LNAs

Fig. 2. InP MMIC wafer with 4 wafer ddiameter

and 75 m thickness. The wafer contains 44000 LNAs.
Fig. 4. Photograph of the 3-stage 6-20 GHz MMIC LNA. Chip
dimensions are 2 mm x 0.75 mm.

The HEMT is included in a full MMIC

C process that is
run on 4 InP wafers, Fig. 2. The wafers aare thinned down
to 75 m and the circuits are groundeed to a backside
metallization through 45 m diameter via holes. NiCr
resistors, 50 /square (temperature inndependent) are
added. The 150 nm thick SiN passivationn layer is used as
the dielectric layer for capacitors. T
The process is
optimized for wideband LNAs, and desiggns can be made
in a frequency range from around 1 GHzz to 100 GHz. A
0.5 13 GHz LNA had a lowest noise tem
mperature of 3 K
and a 24-40 GHz LNA a minimum noisse temperature of
10 K, both measured at 15 K [7]. The chiip size is 2 mm x
0.75 mm, and on a 4 wafer there is room for 4000 LNAs.

nsions, excluding connectors,

Fig. 5. 6-20 GHz LNA module. Dimen
are 22 mm 19.6 mm 7.8 mm.

III. PROCESS STABILITY.

stability and decrease the magnittude of S11, a source

inductance was connected to the first transistor using a
high impedance microstrip line.
ure is almost linearly
The minimum noise temperatu
varying with frequency [1]. The besst trade-off, concerning
wide band noise performance, is th
hus to noise match the
first transistor at the upper frequency limit and accept
some mismatch at the lower frequeencies. In this way, the
noise temperature of the LNA was
w held constant with
frequency. The second and third sttages were matched for
flat gain, stability and output match.
Network matching was performed using MIM
capacitors, TFRs, via-holes and microstrip lines. All
designs had common bias networkss for all three stages. A
schematic of the 3-stage LNA is shown in Fig. 3.

In this work, we looked at the proceess uniformity in

addition to a new LNA design. A numbber of 6-20 GHz
LNAs were designed and measured. Thee gain and noise
were measured on 47 LNAs in order too investigate the
process uniformity.
A. Amplifier design
A suitable gate width for impedance m
matching in the 620 GHz frequency range is 200 m. W
When aiming for
lowest noise performance, the matchingg network of the
first stage ultimately sets the noise perforrmance. To avoid
substrate losses, and consequently degraded noise
performance, an external input matching nnetwork on a low
loss RT Duroid 6002 substrate was ussed. To improve

22

35

175

30

150

25

125

20

100

15

75

10

50

25

0
5

11

(dB)

200

10

11

&S

22

40

15
20

S22

25

0
3

11

13

15

17

19

30

0
23

21

Frequency (GHz)

35

35

30

30

25

25

20

20

15

15

10

10

0
7

11

13

15

17

13

15

17

19

19

21

40

21

23

400

Gain

35

Gain (dB)

40

Noise Temperature (K)

Gain (dB)

40

11

Fig. 8. Input and output return loss for MMIC based 3-stage 620 GHz LNAs at room temperature.

Fig. 6. Noise temperature (dashed) and gain (solid) for MMIC

based 3-stage 6-20 GHz LNAs at 300 K.

Frequency (GHz)

350

30

300

25

250

20

200

15

150

Noise

10

100

50

0
23

11

13

15

17

19

21

Noise Temperature (K)

Gain (dB)

Table of Contents

0
23

Frequency (GHz)

Frequency (GHz)
Fig.7. Noise temperature (dashed) and gain (solid) for MMIC
based 3-stage 6-20 GHz LNAs at 10 K.

Fig.9. Noise temperature and gain for 47 3-stage 6-20 GHz

MMIC LNAs at room temperature.

Photographs of the 2 mm 0.75 mm chip can be seen in

Fig. 4.
To finalize the LNAs, the MMICs were mounted,
together with the external input matching network, in
modules with SMA connectors, Fig. 5. To avoid
oscillation problems, the microstrip and MMIC cavities
were dimensioned to have cut-off frequencies far above
the highest MMIC gain frequency.

When cooled to 10 K, Fig.7, the average noise

temperature was reduced to 5.8 K. The gain increased to
35.9 dB. The optimum bias changed to Vd = 1.1 V, and Id
= 12 mA. The resulting DC power consumption reduced
to 13 mW.
Small signal measurements of the mounted LNA
modules were done at room temperature with an Agilent
E8361A Network Analyzer. Input return loss, measured at
300 K, was better than 7.5 dB. Output return loss was
better than 11 dB. (Fig. 8.)
To highlight the repeatability of the achieved noise
temperature and gain, 47 LNAs have been measured at
room temperature. Noise temperature and gain of all
LNAs are plotted in Fig. 9. The average in-band noise
temperature and gain of the 47 LNAs was 66.8 K and 33.2
dB, respectively. The standard deviations from these
averages were 1.5 K and 0.3 dB.

B. Measurements and Characterization

At room temperature, the optimum drain voltages with
respect to noise temperature were Vd = 1.7 V. Optimum
Id was 50 mA. The resulting DC power consumption was
85 mW and 100 mW, respectively.
Noise measurements were performed both at 300 K and
15 K using Agilent N8975A noise figure analyzer. At
room temperature, Fig. 6, the average in-band noise
temperature was 66.3 K. The average in-band gain, was
33.2 dB.

23

Table of Contents

Noise Temperature (K)

REFERENCES
[11]

[1]

J. Schleeh, G. Alestig, J. Halonen, A. Malmros, B. Nilsson, P.A.

Nilsson, J.P. Starski, N. Wadefalk, H. Zirath, J. Grahn, UltralowPower Cryogenic InP HEMT With Minimum Noise Temperature of
1 K at 6 GHz, IEEE Electron Device Letters, 33, n 5, 664, 2012.
[2] SETI Institute. Available: http://www.seti.org/ata
[3] ALMA. Available: http://www.almaobservatory.org/
[4] SKA. Available: http://www.skatelescope.org/
[5] J. Pandian, L. Baker, G. Cortes, P. Goldsmith, A. Deshpande, R.
Ganesan, J. Hagen, L. Locke, N. Wadefalk, and S. Weinreb, "Lownoise 6-8 GHz receiver," IEEE Microw. Mag., vol. 7, pp. 74-84,
Dec. 2006.
[6] J. Randa, E. Gerecht, D. Z. Gu, and R. L. Billinger, "Precision
measurement method for cryogenic amplifier noise temperatures
below 5 K," IEEE Transactions on Microwave Theory and
Techniques, vol. 54, pp. 1180-1189, Mar 2006.
[7] J. Schleeh, N. Wadefalk, P. A. Nilsson, J. P. Starski, and J. Grahn,
"Cryogenic Broadband Ultra-Low-Noise MMIC LNAs for Radio
Astronomy Applications," IEEE Transactions on Microwave
Theory and Techniques, vol. 61, pp. 871-877, 2013.
[8] M. W. Pospieszalski, "Cryogenic Amplifiers for Jansky Very Large
Array Receivers," in 19th International Conference on Microwaves,
Radar and Wireless Communications (MIKON), May 2012.
[9] T. Yu-Lung, N. Wadefalk, M. A. Morgan, and S. Weinreb, "Full
Ka-band High Performance InP MMIC LNA Module," in IEEE
MTT-S International Microwave Symposium Digest, June 2006,
pp. 81-84.M.W. Pospieszalski , Extremely low-noise amplification
with cryogenic FETs and HFETs: 1970-2004, IEEE Microwave
Magazine, v 6, 3, 62-75, 2005.
[10] M.W. Pospieszalski , Extremely low-noise amplification with
cryogenic FETs and HFETs: 1970-2004, IEEE Microwave
Magazine, v 6, 3, 62-75, 2005.
[11] L. Samoska, M. Varonen, R. Reeves, K. Cleary, R. Gawande, P.
Kangaslahti, T. Gaier, R. Lai, S. Sarkozy, W-Band Cryogenic InP
MMIC LNAs with Noise Below 30 K, Microwave Symposium
Digest (MTT), 2012 IEEE MTT-S International. 1-3, 2012.

[7]

10

This Work
[5]
[1]
1

10

F (GHz)

100

Fig. 10. Noise temperatures for selected state of the

art cryogenic wide band low noise amplifiers.

IV. CONCLUSION
A low noise InP MMIC process, on 4 wafers, has been
developed for cryogenic operation. The process makes it
possible to produce LNAs with extremely low noise for
frequencies below 100 GHz. The process can produce a
large number of LNAs with good repeatability and state of
the art noise results at cryogenic temperatures, Fig. 10.
ACKNOWLEDGMENT
This work was carried out in the Gigahertz Centre in a
joint research project financed by the Swedish
Governmental Agency for Innovation Systems
(VINNOVA), Chalmers University of Technology,
Omnisys Instruments AB, Wasa Millimeter Wave AB,
Low-Noise Factory AB and SP Technical Research
Institute of Sweden. Parts of the work was financed by the
European Space Agency, ESA.

24

Table of Contents

Single Chip RF Variable Gain Low Noise Amplifier

Bin Hou, Yibing Zhao, Eric Newman, Shuyun Zhang
Analog Devices Inc., Wilmington, MA, 01887, U.S.A.
Abstract
A monolithic integrated single chip RF
variable gain low noise amplifier (VGLNA) based on GaAs
BiFET technology is demonstrated in this work. The LNA
could be operated from 700MHz to 3GHz. The measured NF
is 1dB at both 975MHz and 1.75GHz. The gain of the
VGLNA can be varied from a maximum of 36dB down to a
minimum of -13dB at 1.75GHz. Measured Output IP3 is
38.4dBm and measured Output 1dB compression is greater
than 27dBm at 1.75GHz at maximum gain. The measured
input return loss is better than 14dB across the full gain
range. The single die VGLNA is implemented in a 5x5mm
LFCSP package. It draws 265mA on a 5V supply.
Index Terms GaAs, BiFET, variable gain low noise
amplifier.

II. DESIGN OF RF VGLNA

A. Design of Low Noise Amplifier (LNA)
The challenge of the LNA design in the BiFET process
is to optimize the amplifier noise and S-parameter
performances with an accurate pHEMT device noise
model. A simple device noise model based on van der
Ziels model [3], [4] is extracted from device noise
parameters. A MATLAB code based on device impedance
matrices and noise correlation matrices were applied to
find the optimum bias point and deivce geometry for input
impedance matching and minimum noise figure
performance. The sub-circuit block of LNA is designed by
source inductive degenerated E-mode pHEMT which
achieves low noise figure, descent gain and input and
output impedance match. The simplified schematic of the
open-drain LNA design with By-pass switch is shown in
Figure 2. The RC shunt-shunt feedback (Rf-Cf) helps
maintain good impedance match and stabilize the LNA at
low frequency range where the gain of the LNA is high.
The feedback resistor Rf is chosen so that its thermal noise
is not going to significantly affect the overall LNA Noise
Figure performance at RF frequency. The on chip bias cell
helps stabilize the LNA performance over supply and
temperature variations. The by-pass switch is designed by
D-mode pHEMT with low RONCOFF which achieves high
linearity, low insertion loss.

I. INTRODUCTION

VPOS2

18

RFIN3

16

VPOS1

13

VGAIN2

RFOUT2

15

VSW1

VGAIN1

30

VSW1

RFIN2

The rapid development of modern telecommunication

systems requires highly integrated high performance
RFICs. GaAs BiFET process which integrates E/D mode
pHEMT and HBT process enable the monolithic
integration of high performance LNA, VVA, switches and
power amplifier into one module [1] [2]. A single chip RF
VGLNA based on GaAs BiFET technology suitable for
base-station, point-to-point radio and instrumental
applications is introduced in this work.

21

11

28

RFOUT1 32

AMP3

AMP1

VVA1
2

ADL5246

AMP2
4

12 14 17 19 22

NIC

RFOUT3

EP

10 20 23 24 25 27 29 31

GND

12233-001

RFIN1

26

VVA2

Figure 1. Block diagram of the RF VGLNA

Figure 1 illustrates the block diagram of the single chip

VGLNA. It consists of five sub-circuit blocks: the first
stage is a low noise amplifier which achieves low noise
figure with good input and output impedance match; the
second stage is a voltage controlled variable attenuator
(VVA); the third stage is a LNA same as the first stage
design but with an additional by-pass switch; the fourth
stage is a VVA same as the second stage; The last stage is
a highly linear driver amplifier.

978-1-4799-3622-9/14/$31.00 2014 IEEE

Figure 2. Schematic of LNA with By-Pass switch

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Table of Contents

The LNA achieved 12dB gain, 0.9dB Noise Figure,

22dBm Output 1dB compression point and 36dBm Output
third-order intercept point at 1.75GHz with 60mA bias
current on 5V supply.
B. Design of Voltage-Controlled Attenuator (VVA)
The VVA is also designed by D-mode pHEMT which
achieves low insertion loss, wide attenuation range, high
linearity, descent impedance match. As shown in Figure 3,
the VVA is composed of shunt and series connected
multi-gate D-mode pHEMT transistors in a pi-shape
network. A voltage control circuit generates bias voltages
to the gates and channels of the series and shunt connected
D-mode pHEMTs. As the control voltages varies, the
channel resistances of D-mode pHEMTs varies, hence the
attenuation between RFin and RFout varies accordingly. The
attenuation of the VVA is controlled by a single external
control voltage varied from 0V to 3.3V and it achieved
about 24dB attenuation range at 2GHz on a 5V supply.

Figure 4. Schematic of Driver Amplifier

A picture of the VGLNA die is illustrated in Figure 5.

The dies size is 2.44mm2.44mm. The broadband design
of the LNA and VVA inter-stage impedance matching is
achieved on the die. The driver amplifier impedance
matching to a specific frequency band is achieved by offchip tuning components. The VGLNA is mounted in a
32L 5mm5mm LFCSP package. Extensive EM
simulations were performed for on-chip inductors and for
the package parasitics to ensure the isolation between subblocks so that the Full-chain VGLNA is un-conditional
stable.

Figure 3. Schematic of VVA

C. Design of Driver Amplifier

The last stage driver amplifier is designed by high
performance HBT which achieves high gain, high linearity
performances with off-chip impedance matching to 50
ohms. Figure 4 presents a simplified schematic of the
driver amplifier design. The main amplifier is designed in
open collector common-emitter configuration with emitter
thermal ballasting resistors to protect the transistor from
thermal run-away. The shunt-shunt RC feedback network
also improves frequency stability. The on-chip active bias
circuit helps stabilize the performance of the driver
amplifier over supply and temperature variations.
At 2GHz, the driver amplifier achieved 13dB gain,
27.2dBm Output 1dB compression point and 41dBm
Output third-order intercept point with 140mA bias
current on a 5V supply.

Figure 5. Photograph of the VGLNA die.

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Table of Contents

III. MEASUREMENT RESULTS

within 100MHz bandwidth of 1.75GHz. As shown in the

figure the colored lines represent S11 data measured at
frequencies from 1.70GHz to 1.80GHz.

Figure 6 shows the VGLNA mounted on a FR-4 PCB

evaluation board. Figure 7 shows the measured full-chain
VGLNA gain range at 1.75GHz band. The Max. Gain is
35.6dB at 1.75GHz while the Min. gain is -13.5dB. The
gain curve vs. the control voltage is monotonic. The
achieved gain range is more than 48dB at this frequency.
The gain variation over 100MHz bandwidth is less than
1dB across the full vctrl range.

S11 (dB)

-5
-10
-15
-20
-25
0

2
Vctrl (V)

Figure 8. S11 vs. Vctrl at 1.75GHz

In Figure 9 the measured full-chain VGLNA noise

figure vs. the full-chain VGLNA gain at 1.75GHz is
illustrated. The minimum noise figure measured is less
than 1dB at maximum gain at room temperature. When
the Control voltage increases from 0V to 3.3V, the fullchain VGLNA gain reduced according to the curve shown
in figure 7 and the Noise Figure of the VGLNA increases
according to figure 9.
Figure 6. VGLNA Evaluation board

20
15
NF (dB)

40

S21 (dB)

30
20

10
5

10

-10
-20

10

20
Gain (dB)

30

40

Figure 9. VGLNA NF vs. gain at 1.75GHz

2
Vctrl (V)

4
The Input referred IP3 and P1dB performances of the
VGLNA across the gain range are shown in Figure 10.
The input referred 1dB compression point is at -8dBm and
the input referred IP3 is at 2dBm at Max. gain. The input
referred 1dB compression point and input referred IP3
increase as shown in figure 10 as the gain reduced
according to figure 7. High linear operation of the
VGLNA over the gain variation ranges is demonstrated.

Figure 7. VGLNA gain vs. contrl voltage at 1.75GHz

The input return loss (S11) of the full-chain VGLNA

measured at the input port of the first stage LNA is
illustrated in Figure 8. Across the full control voltage
range descent input impedance matching is achieved

27

Table of Contents

TABLE I

ACKNOWLEDGEMENT

SUMMARY OF MEASUREMENT AT 1.75GHZ

The authors wish to thank Steven Bonadio, Jim

Bedrosian of the RF Group in Analog Devices Inc. for
their work on the production and application support of
the RF VGLNA.

Measurement data
Parameters

IcP1dB and IIP3 (dBm)

Max. Gain
Min. Gain
Input RL
Output RL
NF
Output IP3
Output P1dB

Data
Unit
Notes
35.6
dB High Gain mode
-13.46
dB High Gain mode
14.27 22.08 dB High Gain mode
11.53 21.14 dB High Gain mode
0.978
dB
At Max. gain
38.37
dBm At Max. gain
27.39
dBm At Max. gain

REFERENCES
[1] Lin, C.K.; Li, S.J.; Tsai, S.H.; Wang, C.W.; Wang, Y.C.;
Wu, P.H.; Li, J.Y., The monolithic integration of InGaAs
pHEMT and InGaP HBT technology for single-chip
WiMAX RF front-end module, Circuits and Systems
th
(MWSCAS), 2011 IEEE 54 International Midwest
Symposium on.
[2] Yibing Zhao, Bin Hou, Shuyun Zhang, Monolithically
integrated high performance digital variable gain
amplifiers, IEEE RFIC Symp. Dig., pp. 159-162, June
2012.
[3] T. H. Lee, The Design of CMOS Radio-Frequency
Integrated Circuitss, Cambridge University Press, New
st
York, NY, 1 Edition, 1998.
[4] A. van der Ziel, Noise in Solid State Devices and Circuits,
John Wiley & Sons, New York, NY, 1986.

25
20
15
10

P1dB

IIP3

0
-5

-10
0

10

20
Gain (dB)

30

40

Figure 10. VGLNA IP3 and P1dB vs. gain at 1.75GHz.

Table I summarizes the measured full-chain RFVGA

performances at 1.75GHz. The RFVGA is unconditional
stable over the full gain range. Performances at other
frequency band such as 850MHz, 975MHz, 1.5GHz, and
2.6GHz are also evaluated for the VGLNA with similar
results as shown in this paper.

IV. CONCLUSION
A monolithic integrated single die RF VGLNA achieves
wide gain range, low noise figure, high linearity is
demonstrated in this work. The measured results show the
VGLNA is suitable for modern telecommunication system
applications.

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Table of Contents

A 0.05-26 GHz Direct Conversion I/Q Modulator MMIC

Eric W. Iverson, Milton Feng
University of Illinois at Urbana-Champaign, Urbana, IL, 61801, USA, iverson2@illinois.edu
Abstract An integrated I/Q modulator is presented,
implementing a static frequency divider for local oscillator
(LO) quadrature phase splitting, Gilbert cell switching
mixers for direct upconversion, and fabricated in a high
speed Indium-Phosphide HBT process. LO quadrature is
fine-tuned by a control voltage with 0.18 degrees/mV for 2.14
GHz operation. Single-sideband conversion gain ranges from
-14 to -23 dB across the LO frequency range of 50 MHz to 26
GHz. Single-carrier W-CDMA ACPR ranges from -64 dBc to
-53 dBc for approximately -20 dBm output power. Output
intercept point (OIP3) ranges from +14 dBm at 50 MHz to
+4.6 dBm at 26 GHz.
Index Terms I/Q Modulator, Quadrature Modulator,
Indium Phosphide, DHBT

I. INTRODUCTION
A broadband direct conversion I/Q modulator must
maintain sideband suppression and low distortion across
its full frequency range. There are two primary causes of
poor sideband suppression in I/Q modulators: conversion
gain imbalance between the I and Q mixers (GQI =
GCQ/GCI) and local oscillator quadrature error (LO = Q
I + 90o). During device operation, the sideband
suppression can be optimized by adjusting voltage
amplitude imbalance of the I and Q baseband signals (AQI
= AQ/AI) and phase offset between the baseband signals
(QI = Q I + 90o). If a net voltage amplitude
, then the sideband
imbalance is defined as
suppression ratio (i.e. the ratio of lower sideband power to
upper sideband power during upper sideband modulation)
can ideally be formulated as:
1
1

2 cos
2 cos

Fig. 1. IQ Modulator with static divider quadrature

generation and Gilbert cell mixers.
processes are labor-intensive, so it is desirable to keep the
amplifier gains as balanced as possible. One SiGe radio
frequency broadband modulator shows sideband
suppression of <-50 dBc for fLO = 0.05 6 GHz [1]. To
achieve this performance, the modulator requires the
baseband amplitude imbalance AQI to be calibrated for best
sideband suppression.
This work presents a broadband I/Q modulator that uses
a static divider to generate the quadrature LO signals,
which are then supplied to two Gilbert cell switching
mixers, as shown in the block diagram of Figure 1. This
work discusses the design constraints associated with
static divider quadrature generation, as well as
experimental results of the I/Q modulator.

(1)

II. QUADRATURE BY STATIC DIVIDER

The only solution to drive sideband suppression to zero

requires A = 1 and LO = QI. In practice, it is difficult
to generate a broadband IF phase delay , so it is
desirable to drive the on-chip LO phase error LO to zero.
Gain imbalance, however, can be corrected using variable
attenuation on the baseband I and Q signals, or by lasertrimming on-chip gain control resistors. Both of these

978-1-4799-3622-9/14/$31.00 2014 IEEE

The output signals of an ideal master-slave static

frequency divider are square waves at half the input
frequency. It was shown that the output of the static
frequency divider can be used to generate quadrature
square waves [2].

29

Table of Contents

Fig. 2. Timing diagram showing the relationship

between input duty cycle and output phase error when
generating quadrature by static divider.
The relative phase between master and slave outputs are
related to the duty cycle of the input signal. Because the
master latch reverses state with every rising clock edge
and the slave latch reverses state with every falling edge,
the output signals have a 50% duty cycle but a relative
phase defined by the amount of time the clock spends in
the high state, TH. This is shown in Fig. 2.
When the duty cycle of the clock is 50%, the relative
o
phase of the output I and Q signals is 90 , but when there
is some duty cycle error, the output signals are imparted
with a phase error LO. Duty cycle error on the signal into
the divider can be caused by any frequency spurs that are
not at the fundamental frequency or its odd harmonics.
Spurs with relative voltage amplitude Aspur (normalized to
the fundamental tone) will, in the worst case, cause a
-1
phase error LO sin (Aspur). If the sideband suppression
/4.
is limited by phase error, this results in PLSB/PUSB
Thus, a -40 dBc spur on the clock can cause the sideband
suppression ratio to be -46 dBc.
In order to meet the stringent requirement on clock duty
cycle while relaxing harmonic requirements of the LO
source, a duty cycle controller could be implemented. As
seen in Figure 1, the limiting amplifier is designed
differentially, with the 2xLO signal on the positive input
and a DC-driven control voltage VF on the negative input.
For small duty cycle errors, the duty cycle and phase error
are linearly related to the control voltage VF. In this
configuration, the clock signal can be driven to 50% duty
cycle even in the presence of relatively large evenharmonic distortion on the 2xLO input.

Fig. 3. Static divider schematic used to generate

quadrature local oscillator signals from the input
signal at double the local oscillator frequency.
which causes the I and Q LO signals to have peak-to-peak
voltage of 0.47 V. The common-collector helper on the
latches act as a low impedance output buffer to the mixers
and shift the DC voltage of the LO signals to be -1.1 V,
which allows the switching transistors of the mixer to
operate in forward active mode. The 2xLO signal is
generated off-chip and provided to a limiting amplifier
which drives the static divider. The divider was designed
to be as symmetric as possible, to reduce the quadrature
error between I and Q signals.
In order to automatically drive the duty cycle to 50%,
the feedback voltages VFBP and VFBN were designed to
generate a DC voltage proportional to the duty cycle error.
The clock signal that is input to the static divider is also
low-pass filtered through a single-pole RC filter with f3dB
= 15 MHz and sent to the VFBP and VFBN outputs. Thus,
VFBP-VFBN can be treated as an error voltage for an
automatic controller that controls VF to drive the duty
cycle to 50%.
As seen in Fig. 1, the design uses two Gilbert cell
mixers [3]. The differential baseband I and Q signals are
input to a common-collector stage with 50-ohm input
impedance and driving the transconductance stage of the
mixers. Each mixer was designed to have 18 mA tail
current and 55-ohm degeneration resistors on the
transconductance stage, and the two mixers share 50-ohm
load resistors to ground. The upconverted signal is then
sent directly off-chip through GSG RF pads. The output

III. CIRCUIT DESIGN

The quadrature local oscillator signals are generated by
an ECL static divider shown in Figure 3. The static divider
has tail currents of 5.3 mA and 90-ohm load resistors,

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Table of Contents

Fig. 4. Chip photo of the IQ modulator

could be taken differentially or single-ended. In this case,
for ease of measurement, the output is taken single-ended.
This design uses the ground voltage as VCC, with a
supply voltage VEE = -4.5V. In simulation, the circuit
consumed 110 mA and had OIP3 of +17 dBm during
single-sideband operation. The IC was designed in a high
frequency InP DHBT process at Keysight Technologies
High Frequency Technology Center (HFTC) in Santa
Rosa, CA.

Fig. 6. Output spectrum around 2.14 GHz under

single-carrier W-CDMA modulation.
elements in addition to the desired upper and lower
sidebands and the expected 3rd order distortion. At the
center is the LO feedthrough at the carrier frequency. This
spur can be fully suppressed by applying a small DC
voltage offset to the baseband differential input, which is
not currently available in the measurement system.
Several other spurs appear as random glitches during the
course of the spectrum analyzer sweep. The power
spectral density of the noise skirt around the upper
sideband signal is consistent with the phase noise of the
PNA-X source, and the phase noise added by the
modulator appears to be small. The modulator was also
measured under single-carrier W-CDMA modulation
across the frequency range. The output spectrum is shown
in Figure 6 for a 2.14 GHz carrier frequency, showing -19
dBm output power and -63 dBc ACPR.
The conversion gain, sideband suppression, OIP3, and
ACPR were recorded from 50 MHz to 26 GHz, with
results shown in Table 1. The data shown in Table 1 and
Figures 5 and 6 used optimization of the baseband
amplitude, and the phase control voltage VF was left open.

IV. MEASUREMENT
The chip was measured at the University of Illinois at
Urbana-Champaign. The chip photo with pinout is shown
in Figure 4. The 2xLO signal was provided by a Keysight
N5247A PNA-X, VEE was provided by a Keysight
E3615A DC power supply, and the baseband inputs
(IP,IN,QP,QN) were generated by an Keysight 81150A
Arbitrary waveform generator. The RF output was
measured using a Keysight E4448A spectrum analyzer.
Two-tone single sideband modulation measurements
were performed at frequencies from 50 MHz to 26 GHz
with IF frequency of 2 MHz and PIF = 1.9 dBm. The
output spectrum for a 2.14 GHz carrier frequency is
shown in Figure 5. The spectrum shows several spurious

TABLE I
SUMMARY OF MEASURED BENCHMARKS
W-CDMA
Conversion Sideband
OIP3
ACPR
Gain
Suppression
(GHz)
(dB)
(dBc)
(dBm) (dBc)
0.05
-16
65.2
14.1
-2.14
-17
65.4
13.3
-63
5
-17.6
64.4
13.0
-63
10
-17.8
64.5
12.2
-58
20
-21.7
65.1
6.0
-55
26
-22.5
61.8
4.6
-53
f0

Fig. 5. Output spectrum around 2.14 GHz for twotone single-sideband modulation

31

Table of Contents

Fig. 8. Quadrature error as a function of tuning

voltage VF as calculated using Equation 1.

Fig. 7. Sideband suppression as a function of tuning

voltage VF.

<-60 dBc sideband suppression after optimization of the

two-tone baseband signal. The output intercept point and
ACPR indicate that the mixers have an excess of
distortion compared to state-of-the-art I/Q modulators.
After improvement of the distortion characteristics, this
I/Q modulator design could be readily used in broadband
applications such as multiband radios and vector signal
generator test equipment.

For further improvement of the sideband suppression, it

is possible to use the control voltage VF and optimize the
sideband suppression. To test this, an HP 4142B DC
source was used as a voltage source to vary the control
voltage VF, and the two-tone baseband signals were
optimized for maximum sideband suppression. It was
found that the tuning voltage could drive the sideband
suppression to <-85 dBc. The relationship between
sideband suppression and tuning voltage is shown in
Figure 7. Using Equation 1, the sideband suppression
numbers from Figure 7 can be related back to the phase
error (assuming no amplitude imbalance) using Equation
1. As shown in Figure 8, there is an approximately linear
relationship between the control voltage and the
quadrature error, with a tuning factor of about 0.18
degrees/mV. Due to constraints in the measurement setup,
the I/Q modulator has not yet been operated using the
VFBP and VFBN and VF in an automatic control loop.
However, simulations have shown that the automatic
control loop could drive the sideband suppression to <-80
dBc in the presence of up -20 dBc of even-order
harmonics on the 2xLO input signal.

ACKNOWLEDGMENT
The authors thank Keysight Technologies for their
support on this project. The authors would also like to
thank Don DAvanzo, Robert Shimon, Tim Shirley, Craig
Hutchinson, Masaya Iwamoto, and Robert Uang for their
generous and helpful insights on this work.
REFERENCES
[1] Texas Instruments, 50-MHz to 6-GHz Quadrature
Modulator, TRF370417 datasheet, January 2010.
[2] Negus, K.J., Wholey, J.N. Multifunction Silicon
MMICs for Frequency Conversion Applications,
IEEE Trans. On Microwave Theory and Techniques,
vol. 38, no. 9, pp. 1191-1198. 1990.

V. CONCLUSION
In this work, the static divider method of quadrature
generation was investigated, with emphasis on
maximizing sideband suppression. Without using the
control voltage, the I/Q modulator was able to achieve

[3] Gilbert, B. A precise four-quadrant multiplier with

subnanosecond response, IEEE J. Solid-State
Circuits, vol. SC-3, pp. 365-373, Dec. 1968.

32

Table of Contents

A up to 100 GHz Broadband Mixer with Cascaded Distributed

Amplifier
Yihu Li1,2, Goh Wang Ling1, Yong-Zhong Xiong2
1

School of Electrical and Electronic Engineering, Nanyang Technological University, 639798, Singapore
Semiconductor Device Research Laboratory, Terahertz Research CenterCAEP, Chengdu, 611731, China

Abstract An ultra-broadband mixer with cascaded

distributed amplifier is proposed and analyzed in this paper.
The input and output capacitors of the mixer are absorbed
in the artificial transmission lines (ATL) of the distributed
amplifier. 0.13-m SiGe BiCMOS process is used to
fabricate the proposed design. The distributed amplifier is
designed with cascode amplification cells to have an average
gain of 12.5 dB gain with the operating frequency range of 1
to 110 GHz. The whole design achieves an ultra broad
frequency range up to 97 GHz. An average conversion gain
of 14 dB is measured on chip with the input Lo power equals
to 1 dBm. The Lo to RF and Lo to IF rejection are better
than 50 dB and 30 dB, respectively. Good input and output
return losses are obtained, that are below -10 dB from 5 to
90 GHz. Including the testing pads, the total chip area
occupied is 1.80.7 mm2, and the DC power consumption is
105 mW including the output IF buffer.
Index Terms Ultra-broad band mixer, distributed
amplifier, cascode, SiGe:BiCMOS.

Fig. 1. Basic concept of distributed amplifier.

Distributed mixer is another application of this

distributed technology. Some researchers have recently
published DMs based on Gilbert cells [6-8]. The Gilbert
cell based DMs have the advantages of high conversion
gain and relatively wide bandwidth. But the need of one
more TL to carry the out-of-phase Lo signal further
complicates the circuit layout. Passive DMs [9, 10] have
been designed for broad bandwidth operation. This is
attributed to its circuit simplicity, but its low conversion
gain still leads to severe drawbacks.
In this paper, an ultra-broadband mixer with cascaded
distributed amplifier is proposed and analyzed in this
paper. The input and output capacitors of the mixer are
absorbed in the artificial transmission lines of the
distributed amplifier. 0.13-m SiGe BiCMOS process is
used to fabricate the proposed design. The distributed
amplifier is designed with cascode amplification cells to
have an average gain of 12.5 dB gain with the operating
frequency range of 1 to 110 GHz.

I. INTRODUCTION
With the improvements of silicon based technologies,
more millimeter-wave integrated circuits and systems are
realized
based on complementary metal-oxide
semiconductor (CMOS) or Silicon-Germanium (SiGe)
BiCMOS technologies. Comparing with MOSFETs, SiGe
HBTs offer both higher cutoff frequency and power gain.
Thus, SiGe HBTs are preferred when the operating
frequency is shifting to higher band. [1, 2].
Distributed technology is widely used to design ultrabroad band amplifiers in multi-band systems. The basic
idea of distributed configuration is to use the artificial
transmission line (ATL) to absorb the input and output
capacitance of each amplifying stage cell. An illustration
of a basic DA is shown in Fig. 1. The distributed
inductors labeled as L and the input/output capacitance of
the transistors form artificial transmission lines. The
overall bandwidth is defined by the cutoff frequency of
the artificial transmission line, ideally, which may go
beyond the cutoff frequency of the transistors. Some high
quality distributed amplifiers (DA) fabricated by CMOS
are reported recently [3-5]. But due to the non-ideality of
the transmission line, the number of amplification cells is
normally limited to six or seven, and this actually restricts
the overall performance of the DAs. Cascade DA is an
effective solution to raise the gain with the bandwidth
unchanged.

978-1-4799-3622-9/14/$31.00 2014 IEEE

II. CIRCUIT DESIGN

This 0.13-m SiGe:BiCMOS process involves seven
metal layers, which include two top thick metal layers. A
~12-m silicon dioxide layer provides better electrical
performance for passive components. Fig. 2 shows the
complete schematic of the proposed ultra-broad band
mixer. The whole structure is composed by a two-stage
cascaded DA and a mixing cell. Three artificial
transmission lines are involved. All the capacitors labeled
as Cbp are bypass capacitors, to block the DC voltage; the

33

Table of Contents

Fig. 2 Schematic of the proposed broad band mixer.

capacitance of Cbp is designed to be 3 pF by considering

the low frequency return loss and the layout area. The
inductors named LDCF, serve as RF choke to feed the DC
supplies realized through spiral on-chip inductors with a
value of 1 nH. Vcc1 and Vcc2 are designed as 2.5 V and 3
V, respectively. The resistors marked as RL are the
dummy loads for matching the transmission lines.
The amplification cell is based on cascode
configuration. The impedance Ze added between the
emitter of the transistor and the ground is composed by a
resistor and a capacitor in parallel to raise the high
frequency gain. Cb is the base RF grounding capacitor.
The physical sizes of the HBTs are 0.848 m and the
cutoff frequency is 240 GHz. The first and second stage
of the DA contains 4 and 2 amplification cells,
respectively. The simulation results of the S-parameters
for the cascaded DA is given in Fig. 3. The solid line
depicts the S21 of the DA, an average gain of 12.5 dB is
obtained from 5 to 110 GHz. Dashed and dotted lines
demonstrate the S11 and S22, respectively. Lower than 10 dB return losses are observed in the frequency range of
10 to 100 GHz and hence, a broad band impedance
matching is achieved for both input and output ports.
Higher return loss for the output port is seen at lower
frequencies, this is due to the use of non-ideal RF chokes
and DC blocks. The RF choke are realized via on chip
spiral inductors with the value of 1 nH. 3pF capacitors
serve as the DC blocks by considering the layout area.

A mixing cell is added in cascade with the DA. The

main challenge is to realize a broadband mixer without
shrinking the DA's bandwidth. The mixing cell is
designed with the similar structure of the amplification
cell, except for a IF load resistor Rm (see Fig. 2) added at
the collector of the HBT. The input capacitor is absorbed
by the artificial transmission line (labeled in Fig. 2). The
transistors used are with the same dimensions as the ones
in amplification cell, so that discontinuities can be
avoided.

S-parameters(dB)

20
10
S11
S21
S22

0
-10
-20
-30
-40

20

40

60

80

100 120

Freq (GHz)
Fig. 3 Simulated S-parameters of the cascade DA.

34

Table of Contents

Return Loss (dB)

In the whole structure, three artificcial transmission

lines are involved. Refer to Fig. 2, ATL11 is the RF input
transmission line. ATL2 serves as the RF ooutput as well as
the Lo input transmission line; the RF and Lo signals
meet up at the input point of the mixing ccell. ATL3 is the
intermediate transmission line cascadingg two stages of
DA. The distributed inductors are maade up through
hollow ground micro strips. The illuustration of the
physical structure of an ATL is shown in Fig. 2 at the left
upper corner. The quality of the transmisssion lines indeed
defines the bandwidth of the mixer. The simulated return
losses of the three transmission lines are shhown in Fig. 4.
All the transmission lines provide ggood impedance
matching to 50 Ohm from the plots in Figg. 4. This ensures
a broadband operation for the proposed str
tructure. Because

RF measured
Lo measured

60

80

100

10

0
40

80

15

CG (m
measured)
CG (simulated)

ATL1
ATL2
ATL3

20

60

20

-20

40

Fig. 6. Measured return losses of the prop

posed DM

-10

-40

20

Freq (GH
Hz)

CG/NF (dB)

Return Loss (dB)

-20

-30

-30

-10

20

40

60
0

80

100

RF_Freq (GHz)
(

100

Freq (GHz)
Fig.7. Measured conversion gains versus RF
R frequencies.
Fig. 4 Return losses of the artificial transmission linnes.

the Lo signal injects to the collectors of thhe cascode HBTs,

good Lo to RF and IF rejections can be achieved. The
chip photo is shown in Fig. 5 and the aarea occupied is

III. MEASUREMENT RESULTS

The on wafer test system wiith broadband network

analyzer was used for this measurem
ment, and the IF output
power was measured with the specttrum analyzer.
Fig. 6 demonstrates the S-parameters measured
m
The triangle and
results of the proposed broadband mixer.
circle sampled lines represent the measured RF and Lo
B
impedance
return losses, respectively. Broadband
matching for both ports is verified
d. The conversion gains
of the proposed design are show
wn in Fig. 7. The IF
frequency remains at 3 GHz and Lo
o signal sweeps from 6
to 100 GHz at the power level of 1 dBm. The simulated
and measured conversion gains match well along the
f
47 to 59 GHz are
operation frequencies. The results from
missing due to the instrument lim
mitations. An average
conversion gain of 14 dB is obtained through the
operation band. Fig. 8 depicts the Lo to RF and Lo to IF
rejections. Over 50 dB rejection iss realized for Lo to RF
leakage throughout the band and Lo to IF rejection is
o frequency is higher
greater than 30 dB when the Lo

1.80.7 mm2.

Fig.5. Chip photo of the proposed design.

35

Table of Contents

TABLE I
Recently Published Broadband Mixers
Ref

Technology

Unit Cell

Frequency
(GHz)

Conversion
Gain (dB)

Lo to RF
Rejection (dB)

Power Dissipation
(mW)

Chip Size
(mmmm)

[6]

0.18m CMOS

Gilbert

2-30

12.5

45

40

0.870.82

[7]

90nm CMOS

Gilbert

25-75

93

0.550.55

[8]

0.15m GaAs

Gilbert

4-41

3.51

19

100

21

[9]

0.13m CMOS

Drain Mixer

0.8-77.5

-5.5

20

0.670.58

[10]

0.18m CMOS

Cascode

4-45

-12

40

1.4

0.920.72

this work

0.13 m SiGe HBT

Cascode

3-97

14

50

105*

1.80.7

than10 GHz. The total DC power consumption of this

chip is 105 mW.

measurement data and assistance in the research work

presented.
REFERENCES

Lo Rejction (dB)

[1]

Y.S. Noh, M.S. Uhm, and I.B. Yom, "A Compact Ku-Band SiGe
Power Amplifier MMIC With On-Chip Active Biasing," IEEE
Microw. Wireless Compon. Lett., vol.20, no.6, pp.349-351, Jun.
2010.
[2] B. Zhang, Y.-Z. Xiong, L.Wang, S. Hu, T.G. Lim, Y.Q. Zhuang,
L.W. Li, and X. Yuan, "130-GHz gain-enhanced SiGe low noise
amplifier," in Proc. IEEE ASSCC Dig. Tech. Papers, pp. 14, Nov.
2010.
[3] R.-C. Liu, T.-P. Wang, L.-H. Lu, H. Wang, S.-H. Wang and C.-P.
Chao, An 80Ghz traveling-wave amplifier in a 90nm CMOS
technology, IEEE. ISSCC Dig. Tech. Papers, pp. 154-155, Feb,
2005.
[4] J. Kim, J. Plouchart, N. Zamdmer, R. Trzcenski, R. Groves, M.
Sherony, Y. Tan, M. Talbi, J. Safran, and L, Wagner. A 12dBm
320GHz GBW distributed amplifier in a 0.12m SOI CMOS,
ISSCC Dig Tech. papers, pp. 478-479, Feb. 2004.
[5] B. Ballweber, R. Gupta, and D. J. Allstot, A Fully Integrated 0.55.5-GHz CMOS Distributed Amplifier, IEEE J. Solid-State
Circuits,, vol. 35, no. 2, Feb. 2000.
[6] C.-R. Wu, H.-H. Hsieh, and L.-H. Lu, An Ultra-Wideband
Distributed Active Mixer MMIC in 0.18-m CMOS Technology,
IEEE Trans. Microw. Theory Tech., vol. 55, no. 4, Apr. 2007.
[7] J.-H. Tsai, P.-S, Wu, C.-S. Lin, T.-W. Huang, J G. J. Chern, and
W.-C. Huang, A 25-75 GHz Broadband Gilbert-Cell Mixer Using
90-nm CMOS Technology, IEEE Microw. Wireless Comon. Lett.,
vol. 17, no. 4, Apr. 2007.
[8] F.-C. Chang, P.-S. Wu, M.-F. Lei, and H. Wang, A 4-41GHz
Singly Balanced Distributed Mixer Using GaAs pHEMT
Technology, IEEE Microw. Wireless Comon. Lett., vol. 17, no. 2,
Feb. 2007.
[9] H.-Y. Yang, J.-H. Tsai, C.-H. Wang, C.-S. Lin, W.-H. Lin, K.-Y.
Lin, T.-W. Huang, and H. Wang, Design and Analysis of a 0.877.5-GHz Ultra-Broadband Distributed Drain Mixer Using 0.13m CMOS Technology, IEEE Trans. Microw. Theory Tech., vol.
57, no. 3, Mar. 2009.
[10] Y.-S. Lin, C.-L. Lu, and Y. H. Wang, A 5 to 45 GHz Distributed
Mixer with Cascoded Complementary Switching Pairs, IEEE
Microw. Wireless Comon. Lett., vol. 23, no. 9, Sep. 2013.

60
40
20
Lo to IF
Lo to RF

0
0

10

20

30

40

RF_Freq (GHz)
Fig. 8 Measured Lo to RF and Lo to IF rejections.

IV. CONCLUSION
An ultra-broadband mixer with cascaded distributed amplifier
is proposed and analyzed in this paper. 0.13-m SiGe BiCMOS
process is used to fabricate the proposed design. The distributed
amplifier is designed with cascode amplification cells to have an
average gain of 12.5 dB gain with the operating frequency range
of 1 to 110 GHz. The whole design achieves an ultra broad
frequency band up to 97 GHz. An average conversion gain of 14
dB is measured on chip with the input Lo power equals to 1
dBm. Good input and output return losses are obtained, that are
below -10 dB from 5 to 90 GHz. Including the testing pads, the
2
total chip area occupied is 1.80.7 mm , and the DC power
consumption is 105 mW including the output IF buffer. A
comparison of the proposed design with recently published
broadband mixers is shown in Table I. The proposed design

gains better conversion gain and bandwidth among them.

ACKNOWLEDGEMENT
The authors would like to thank the staff of the
National Institute of Metrology, China, for providing the

36

Table of Contents

Optimizing GaN-on-diamond Transistor Geometry for Maximum

Output Power
J.W. Pomeroy and M. Kuball
H.H. Wills Physics Laboratory, University of Bristol, Bristol, BS8 1TL, UK
Email: James.Pomeroy@bristol.ac.uk, Tel: +44 117 3318110
Abstract Recent thermography measurements have
demonstrated the potential of GaN-on-diamond transistors
to offer significantly reduced thermal resistance with respect
to equivalent GaN-on-SiC devices. However, measurements
performed to date have focused on smaller transistors which
are not representative of larger power devices and do not
take full advantage of the superior heat spreading provided
by high thermal conductivity diamond substrates. In order to
explore the possible gain in output power for AlGaN/GaN
HEMTs on diamond substrates we have developed a
parametric thermal model for optimizing the geometry of a
GaN-on-diamond transistor cell. We use simulation input
parameters that have been experimentally validated against
measurements, giving a high confidence in the modelling
results. We demonstrate that by optimizing the geometry of
GaN-on-diamond transistors, combined which additional
diamond heat spreading layers, a ~3 increase in total output
power can be gained with respect to GaN-on-SiC.
Index Terms Gallium nitride, HEMTs, thermal
analysis, thermal resistance, simulation.

TABLE I
THERMAL MODEL INPUT PARAMETERS
Material
GaN
Diamond
substrate
(effective value)
SiC
AuSn
CuW
Diamond
heat spreader
Interface
GaN/SiC
GaN/diamond
a
e

I. INTRODUCTION
Commercial GaN-based RF power amplifiers already
offer greatly increased output power densities with respect
to GaAs technology, reducing die size and circuit
complexity [1]. Further increasing the power density of
GaN transistors will ultimately require new thermal
management approaches in order to efficiently spread 10s
of Watts of waste heat and ensure that channel
temperatures are kept within safe operating limits. Since
GaN devices are fabricated on foreign substrates, the close
proximity of the substrate to the transistor channel (12 m) offers the potential for a high thermal conductivity
substrate to efficiently spread heat. For this reason, SiC is
currently the most commonly used substrate material for
high power GaN devices, having a relatively high thermal
conductivity thermal conductivity ( ) of ~420 W/mK in
comparison alternative substrate materials used in low
cost applications, e.g. silicon ( Si= 130 W/mK). However,
at higher power dissipations (Pdiss) the SiC substrate
becomes a thermal bottleneck. Replacing the SiC with
diamond, the highest thermal conductivity material
available (bulk CVD diamond of up to 2000 W/mK), is a
highly attractive option for reducing the thermal resistance
of GaN transistors potentially increasing their power

978-1-4799-3622-9/14/$31.00 2014 IEEE

Thermal conductivity [W/mK]

(Temperature dependence)
a
-1.5 b
160 (T )
a
-1 c
1200 (T )

-1.4 e

420 (T )
d
57
d
200
f
-1 c
2000 (T )

-8

TBReff [10 m K/W]

g

2.5
a
2.7

Ref. [4]; b Ref. [5]; c Ref. [6]; d Manufacturers data;

Ref. [7]; f Element Six TM200 product; g Ref. [8].

handling capability by several times. The integration of

GaN devices with polycrystalline CVD diamond
substrates up to 4 inches in diameter has been
demonstrated [2]. The fabrication process starts with GaN
layers grown on a silicon substrate, from which the silicon
is removed and CVD diamond is grown on the back side
of the GaN layer, after deposition of a thin layer of
dielectric. Excellent RF performance has been
demonstrated for the resulting GaN-on-diamond
transistors [3]. GaN-on-diamond is however not a
homogenous material, including interfaces and crystal
grain structure close to the GaN layer that can affect heat
transport. It is therefore important to use a combination
thermal simulation and experimental temperature
measurement to assess device thermal resistance and
validate the thermal simulation parameters, rather than
relying on estimations based on only bulk material
parameters, which may be misleading. Raman
thermography has been used to measure the temperature
distribution
in
and
around
GaN-on-diamond
transistors [4]. Combined with thermal modelling, key
parameters, namely the effective GaN/diamond thermal

37

Table of Contents

120

SiC

100

62.5m
AuSn

80

GaN-on-SiC/CuW
GaN-on-diamond/CuW

140

60

120

TBR

150m

140

160

GaN-on-SiC
GaN-on-di

100

Die attach

80

TBR

GaN

Temperature [deg. C]

Temperature rise [Deg. C]

160

60
40

Tambient

20

40

GaN

Substrate

Base

0
20
0

100

200

300

0.01

400

Lateral position [microns]

0.1

1
10
Depth [m]

100

1000

Figure 2: Modeled temperature profile beneath the central

(hottest) gate finger in a GaN-on-diamond and GaN-on-SiC
transistor with the same geometry: 12 125 m (27 m gate
pitch). In each case the die is attached with a AuSn solder
layer to a CuW package. The power dissipation density is
5 W/mm (7.5 W total power dissipation).

Figure 1: Modeled temperature rise at the upper GaN surface

of 12 finger, 125 m-wide, 27 m gate pitch GaN HEMT,
plotted laterally across the center of the gate fingers,
comparing GaN-on-diamond and GaN-on-SiC. In both cases
the die is mounted on a a CuW package with AuSn dia attach.
Power dissipation is 5 W/mm (7.5 W total) and the ambient
temperature is 25C. AS INSET: 3D thermal simulation result
showing the surface temperature of the GaN-on-SiC transistor
(a symmetric 1/4 portion of the model is shown).

including an additional diamond heat spreading layer or a

thicker diamond substrate.
II. THERMAL MODEL
A 3D finite element (FE) thermal model of a multifinger
transistor cell with a fairly typical foot print of
125300m (125 m finger width) was constructed. The
die size is 33 mm. The number of gate fingers is
parameterized in the model, enabling the total number of
gate fingers to be changed while maintaining a uniform
finger-to-finger spacing and a fixed 5 W/mm power
density; thereby the total Pdiss of the cell is proportional to
the number of gate fingers. Power is dissipated in a
0.5 m-long region at the drain edge of the gate foot in
each finger, representing the high-field region where Joule
heating occurs [10]. A 100 nm mesh size was used in the
vicinity of each gate in order to accurately model the high
temperature gradient in this region. For the GaN-ondiamond transistor a GaN thickness of 1 m is used,
similar to reported structures [3], while a typical 1.8 m
GaN layer thickness was used for the GaN-on-SiC device.
In each case the substrate thickness is 100 m. A 25 mthick eutectic AuSn solder layer is used to attach the die a
1 mm-thick 1010 mm CuW carrier. The modelled device
layout and layer structure is illustrated in the inset of
Fig. 1. A fixed 25C boundary temperature is applied to
the carrier back side.
Two alternative schemes were investigated to address
the limited heat spreading capacity of the CuW package,
by further spreading and reducing the heat flux before the
CuW base: Either placing a commercially available CVD

boundary resistance (TBReff) and effective diamond

substrate thermal conductivity have been determined. The
1200 W/mK effective diamond substrate thermal
conductivity includes contributions from grain boundaries
within the first 10s of micrometers close to the diamond
nucleation surface, near the GaN buffer layer [4].
Although this is lower than the bulk (average) thermal
conductivity of ~1550 W/mK determined for this material
by the laser flash measurements [9], the effective diamond
substrate thermal conductivity still offers an impressive 3
increase over SiC. The agreement between transistor
temperature measurements and thermal modeling results
gives a high confidence in the material thermal parameters
used in the modeling [4]. Subsequently, we can use these
experimentally validated thermal model parameters to
optimize the design of GaN-on-diamond transistors
through simulation, which is the aim of this work.
In previous measurements we have demonstrated a 40%
improvement in the thermal resistance of GaN-ondiamond transistors versus GaN-on-SiC transistors with
the same geometry [4]. However, the 2 finger transistors
measured are not necessarily optimized to take the fullest
advantage of GaN-on-diamond, having a relatively low
Pdiss. In this work we use thermal modelling to investigate
the high-power potential of a GaN-on-diamond transistor
cell by optimizing the gate finger spacing. Schemes to
further improved heat spreading are also investigated,

38

10

25

30
150

GaN-on-SiC/CuW
GaN-on-di/CuW
GaN-on-di/di/CuW
GaN-on-(thick)di/CuW

200

150

Power dissipation [W]

15
20

Temperature rise [Deg. C]

Peak Channel Temperature Rise [Deg.C]

Table of Contents

Tmax

100

10

20
30
Number of Gate Fingers

40

GaN
TBReff
Di substrate

AuSn Solder
Di heat spreader
CuW

100

50

0
Gan-on-di
/ CuW

Figure 3: Modeled peak temperature rise in a GaN HEMT

versus number of gate fingers (lower axis), having a constant
device footprint of 300125 m. A fixed power density of
5 W/mm is used and the total power dissipation is indicated on
the upper axis. GaN-on-SiC is compared to three different heat
spreading schemes for GaN-on-diamond, in each case
mounted on a CuW base with AuSn solder layers.

Gan-on-di / Gan-on-(thick)di /
di / CuW
CuW

Figure 4: Modeled temperature rise for a 32125 m, 10 m

gate pitch, GaN-on-diamond transistor with a 20 W power
dissipation. The temperature rise across each layer beneath the
device is shown, comparing three heat spreading schemes:
Mounted directly on CuW, with an additional diamond heat
spreader or with a thicker (300 m) diamond substrate.

diamond heat spreader (Element Six, 2000W/mK,

10100.3 mm) between the die and CuW base or
increasing the diamond substrate thickness from 100 m
to 300 m, assuming that the additional diamond layer has
a similar grain size and thermal conductivity as bulk CVD
diamond (2000 W/mK). The thermal model input
parameters summarized in Table I have been
experimentally verified, based on GaN-on-diamond and
GaN-on-SiC transistor temperature measurements [4]. A
-1
conservative T temperature dependence is assumed for
the diamond thermal conductivity, whereas polycrystalline
diamond exhibits a weaker temperature dependence [6].
The variation in thermal conductivity of metals is
negligible in the temperature range investigated. We note
that the TBReff of commercially available GaN-on-SiC
-8
2
wafers can range from 2-510 m K/W [5]; here we have
-8
2
chosen a conservative value of 2.510 m K/W which is
similar to the measured GaN/diamond TBReff. A typical
epitaxial GaN thermal conductivity value of 160 W/mK
[11] is used for both the GaN-on-diamond and GaN-onSiC, which has been shown to be consistent with transistor
temperature measurements [4]. Manufacturers data sheet
thermal conductivities were used for the AuSn, CuW and
diamond heat spreader materials.

finger spacing. A temperature profile plot across the gate

fingers is also illustrated in Fig. 1, clearly showing the
increased temperature of the central gate fingers with
respect to the outer gate fingers for the GaN-on-SiC
device. In comparison, the plot overlaid for a GaN-ondiamond transistor with the same geometry exhibits
negligible thermal cross talk due to the improved heat
extraction through the diamond substrate. Figure 2 shows
a comparison of the simulated temperature depth profile
beneath the central (hottest) gate finger in a 12 finger
transistor, for GaN-on-diamond and GaN-on-SiC. We note
that in each case the temperature rise across the GaN and
GaN/substrate interface is similar and is proportional to
the local power density (W/mm). The SiC substrate
thermal resistance has a large contribution, whereas the
temperature rise across the diamond substrate is
negligible, highlighting the greater heat handling
capability of the diamond substrate.
By decreasing the gate pitch, the total Pdiss of the
transistor cell can be scaled with the number of gate
fingers, while maintaining the same power dissipation per
finger (W/mm). A plot of peak channel temperature versus
number of gate fingers is shown in Fig. 3. For comparison,
the same result is plotted for a GaN-on-SiC and GaN-ondiamond device. At 16 fingers (20 m gate pitch) and a
total power dissipation of 10 W, the GaN-on-SiC device
temperature rise reaches 150 C, which is a conservative
junction temperature limit for device operation [12]. To
reach the same temperature rise in the GaN-on-diamond
device, the total number of gate fingers can be increased
to 32, attaining a 2 increase in Pdiss (20 W). At this high

III. RESULTS AND DISCUSSION

The inset of Fig. 1 shows the modeled surface temperature
for a 12 finger (27 m gate pitch) GaN-on-SiC device,
having a total power dissipation of 7.5 W. Thermal cross
talk is clearly evident and limits the minimum possible

39

Table of Contents

power dissipation the limited heat spreading capacity of

the CuW package contributes significantly to the total
thermal resistance of modeled GaN-on-diamond device, as
demonstrated in Fig. 4.
A further reduction in thermal resistance can be
achieved by increasing heat spreading before the CuW
layer. This can be addressed by either including an
additional diamond heat spreading layer before the CuW
base or increasing the diamond substrate thickness:
Figure 4 illustrates that both schemes offer a similar
further improvement in thermal resistance for the
transistor and die geometry considered. With an additional
diamond heat spreader, heat is spread over a larger area,
reducing the temperature rise across the CuW base.
However, a larger T is generated across the solder layer
between the diamond substrate and diamond heat
spreading layer. Reducing the thermal resistance of the die
attach is beneficial in this scenario, e.g., by reducing the
solder thickness enabled by the low thermal expansion
coefficient of the adjacent diamond layers. The thermal
resistance of the solder layer between the diamond heat
spreader and CuW base is a negligible due to the larger
contact area. Increasing the GaN-on-diamond substrate
thickness from 100 m to 300 m spreads heat more
evenly across the die, reducing heat flux through the
solder layer beneath the active device, reducing the solder
layer thermal resistance contribution. The temperature rise
across the CuW base is reduced, although to a lesser
extent than for the separate diamond heat spreader.
Figure 4 illustrates that with either an additional
diamond heat spreader or thicker diamond substrate, the
number of gate fingers can be further increased to 44 for
GaN-on-diamond (27 W), achieving a 2.7 increase in
total power dissipation for GaN-on-diamond with respect
to an equivalent GaN-on-SiC device, while keeping the
peak junction temperature below 175 C.

ACKNOWLEDGEMENT
We appreciate helpful discussions with Daniel Twitchen
and Daniel Francis of Element Six in addition to diamond
and GaN/diamond samples.
REFERENCES
[1] U. K. Mishra, P. Primit, and W. Yi-Feng, "AlGaN/GaN
HEMTs-an overview of device operation and applications."
Proceedings-IEEE, vol. 90, no. 6, pp. 1022-103, June 2002.
[2] D. Francis, F. Faili, D. Babi , F. Ejeckam, A. Nurmikko,
and H. Maris, "Formation and characterization of 4-inch
GaN-on-diamond substrates." Diamond and Related
Materials, vol. 19, no. 2, pp. 229-233, Feb. 2010.
[3] D. C. Dumka, T. M. Chou, F. Faili, D. Francis, and
F. Ejeckam, "AlGaN/GaN HEMTs on diamond substrate
with over 7 W/mm output power density at 10 GHz."
Electronics Letters, vol. 49, no. 20, pp. 1298-1299, Sep.
2013.
[4] J. W. Pomeroy, M. Bernardoni, D. C. Dumka, D. M.
Fanning, and M. Kuball, "Low thermal resistance GaN-ondiamond transistors characterized by three-dimensional
Raman thermography mapping." Applied Physics Letters,
vol. 104, no. 8, pp. 083513-1-5, Feb. 2014.
[5] C. Mion, J. F. Muth, E. A. Preble, and D. Hanser, "Accurate
dependence of gallium nitride thermal conductivity on
dislocation density," Applied Physics Letters, vol. 89, no. 9,
pp. 092123-1-3, Sep. 2006.
[6] E. Wrner, J. Wagner, W. MllerSebert, C. Wild, and P.
Koidl, Infrared Raman scattering as a sensitive probe for
the thermal conductivity of chemical vapor deposited
diamond films, Applied Physics Letters, vol. 68, no. 11,
pp. 1482-1484, March 1998.
[7] E. A. Burgemeister, W. von Muench and E. Pettenpaul,
Thermal conductivity and electrical properties of 6H
silicon carbide Journal of Applied Physics, vol. 50, no. 9,
pp. 5790-5794, Sep. 1979.
[8] A. Manoi, J. W. Pomeroy, N. Killat, and M. Kuball,
"Benchmarking of thermal boundary resistance in
AlGaN/GaN HEMTs on SiC substrates: Implications of the
nucleation layer microstructure." Electron Device Letters,
IEEE, vol. 31, no. 12, pp. 1395-1397, October 2010.
[9] D. Twitchen (Element Six), private communication, May
2014.
[10] S. Rajasingam, J. W. Pomeroy, M. Kuball, M. J. Uren, T.
Martin, D. C. Herbert et al., "Micro-Raman temperature
measurements for electric field assessment in active
AlGaN-GaN HFETs." Electron Device Letters, IEEE, vol.
25, no. 7 pp. 456-458, July 2004.
[11] J. Zou, D. Kotchetkov, A. A. Balandin, D. I. Florescu, and
F. H. Pollak, "Thermal conductivity of GaN films: Effects
of impurities and dislocations." Journal of Applied Physics,
vol. 92, no. 5, pp. 2534-2539, August 2002.
[12] L. Sangmin, R. Vetury, J. D. Brown, S. R. Gibb, W. Z. Cai,
J. Sun et al., "Reliability assessment of AlGaN/GaN HEMT
technology on SiC for 48V applications." In 46th Annual
International Reliability Physics Symposium, pp. 446-449,
April 2008.

IV. CONCLUSION
Using experimentally verified thermal models and input
parameters, we have explored the possible power gains
which could be achieved using existing GaN-on-diamond
material with respect to equivalent devices fabricated
using GaN-on-SiC. The superior heat spreading capacity
provided by high thermal conductivity diamond substrates
reduces thermal cross talk, enabling a smaller gate pitch
and increased number of gate fingers per transistor cell.
With additional diamond heat spreading layers, a possible
~3 increase in total output power dissipation can be
achieved for GaN-diamond transistors with respect to
GaN-on-SiC for the same peak junction temperature rise.

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Progress on Phase Separation Microfluidics

Damena D. Agonafer, James Palko, Yoonjin Won, Ken Lopez, Tom Dusseault, Julie Gires, Mehdi
Asheghi, Juan G. Santiago, Kenneth E. Goodson
Mechanical Engineering Department, Stanford University, Stanford, CA 94305
Abstract High power density GaN HEMT technology
can increase the capability of defense electronics systems
with the reduction of CSWaP. However, thermal limitations
have currently limited the inherent capabilities of this
technology where transistor-level power densities that exceed
10 kW/cm2 are electrically feasible. This paper introduces the
concept of an evaporative microcooling device utilizing some
of the current two-phase vapor separation technologies
currently being developed for water and dielectric liquids.
Index Terms GaN, HEMT, Electronics Cooling.

properties but major integration challenges. Chemical and

geometric surface engineering is being applied for robust
and finely controlled phase separation including advances
in fundamental understanding of effects of geometrically
optimized surfaces for retaining completely wetting
liquids,

I. INTRODUCTION
Dimensional scaling and corresponding exponential
increase in transistor density has been accompanied by a
significant increase in power density in microchips and the
heat flux for high performance chips in the 14 nm
2
generation is projected to be greater than 100 W/cm with
a junction-to-ambient thermal resistance <0.2C/W [1].
High power density GaN high-electron-mobility transistor
(HEMT) technology can increase the capability of defense
electronics systems however, thermal challenges arise due
to transistor-level power densities that can exceed 10
kW/cm2. This has motivated research on liquid cooling,
both direct [2] and indirect [3], have been well with an
emphasis on addressing challenges for high power
electronics and reducing cost related to the system level
integration.
In this work, we focus on developing vapor phase
separation technology designed for an evaporative
microheat exchanger, designed to target heat fluxes
2
exceeding 5 kW/cm with a temperature rise of less than
5K. To achieve these aggressive targets, three essential
goals must be met: 1.) Obtaining a stable, ultra-thin
evaporating liquid film at the walls of the microcooling
device that remains wetted even at extreme heat fluxes
and does not flood at low heat fluxes. 2.) Providing
adequate liquid delivery and vapor extraction while
maintaining small pressure drops (to minimize elevation
of saturation temperature and required pumping power).
3.) Ensuring the lowest possible thermal conduction and
convection resistances from heat generation volumes to
the phase change surface including conduction along
extended surfaces. We address these issues with a tightly
integrated combination of porous material design, surface
engineering, intricate microfluidic phase management, and
application of available materials with exceptional thermal

978-1-4799-3622-9/14/$31.00 2014 IEEE

Fig. 1. Schematic of our microcooling heat exchanger device

2
used to remove heat fluxes exceeding 5 kW/cm . The
microcooling technology includes diamond fin channels for heat
spreading integrated with and a thin microporous copper layer
and bilayer for evaporative cooling and phase separation.

such as dielectric refrigerants. Finally, all these elements

are being integrated with high thermal conductivity
substrates including diamond. Figure 1 shows a schematic
of our microcooling heat exchange device. Heat is spread
from the hot spot to the diamond fins, where liquid is
delivered through a thin microporous copper liquid
delivery layer that allows evaporative cooling at the top of
the nanoporous capping layer. Phase separation occurs by
integration of a nanoporous cap layer (bilayer) that
extracts vapor and retains liquid by maintaining a capillary
pressure that exceeds the viscous pressure loss across the
microporous copper layer.
Evaporative cooling is
maintained at the top of the liquid delivery layer while
boiling is suppressed by maintaining a liquid pressure
greater than the saturation pressure.

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drop of ~60 kPa across the microporous layer, which

requires the bilayer to have a pore size ~1 m in order to
yield a burst pressure that matches the viscous pressure
drop.

II. VAPOR PHASE SEPARATION TECHNOLOGY

A. Study of Key Parameters for Microporous Copper
Liquid Delivery Layer and Bilayer
As previously discussed, it is critical to design a phase
separation device that maintains capillary pressures
exceeding the viscous pressure drop across the
microporous layer in order to mitigate flooding at the
bilayers top surface and suppress boiling. We therefore,
simulate the key parameters for minimizing both the
thermal and hydrodynamic resistances.
The bilayer and liquid delivery layer is integrated on a
diamond fin of 5000 m x 500 m. The working fluid used
in these studies is R1234ze. The viscous pressure drop
across the microporous layer is calculated based on a 2D
Darcy Model using COMSOL Multiphysics as a function
of pore diameter, porosity, and tortuosity. The
permeability constants are calculated using the KozenyCarman equation, where porosity ( )=0.7, grain size
(d)=1-20 m, and tortuosity ()=1.1. The boundary
conditions

B. Vapor Pressure Drop Analysis across Bilayer

Small pore sizes for the bilayer is advantageous because
it increases the bursting pressure, thus allowing the
capabilities of liquid to be delivered at higher pressure
through the microporous layer, while mitigating flooding
at the top of the bilayer. However, reducing the pore size
decreases the capability of the membrane to transport
vapor. The hydrophobic capping layers are dry, with the
evaporating surface maintained below them. Therefore,
the bilayer must allow the passage of large volumetric
flow rates of vapor.

Fig. 3. Pressure drop across a hydrophobic nanoporous capping

layer for an applied heat flux

We have modeled the ability of a nanoporous layer to

transport vapor from the evaporating surface due to
diffusive and pressure driven transport [4]. These two
fluxes have different dependencies with pore radius.
Figure 3 shows the mass flux and its contributions due to
pressure driven flow and diffusion as a function of pore
size across a 10 m thick membrane with a driving
pressure difference of 10 kPa for water at 393K. The
evaporative surface is assumed to be at saturated
conditions. Porosity and tortuosity of the membrane are
0.75 and 2 respectively. Horizontal lines indicate mass
fluxes required to support heat fluxes of 200 W/cm2 (0.9
kg/s/m2) and 500 W/cm2 (2.3 kg/s/m2). We can see that
the mass flux sustained by the membrane is sufficient to
support extreme evaporative cooling applications.

Fig. 2. Pressure drops for various pore diameters are calculated

using COMSOL Multiphysics simulation. This figure shows
burst pressure limits with various capping layer pore diameters
from 1 m to 10 m. Thermal resistance (R=1/h) has been
scaled as 1/h=d/k where k and d are the effective thermal
conductivity and pore diameter, respectively.

include a pressure inlet and evaporative mass generation

out of plane, where mass flux is calculated based as the
heat flux and latent heat of the working fluid. All other
sides of the microporous layer are considered adiabatic.
The viscous pressure across the microporous copper
layer drop is plotted as a function of pore diameter as
shown in Fig. 2. The plot shows smaller pore sizes yield
smaller convective resistances (i.e. larger surface to area
to volume ratio) but at the expense of higher viscous
pressure drops. A pore size of 1 m leads to a pressure

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C. Optimized Pore Geometry for Dielectric Liquids

III. MATERIAL FABRICATION FOR BILAYER

A. Fabrication of Microporous Copper Layer

Dielectric fluids exhibit wetting properties that do not

allow for feasible chemical surface modifications for
producing non-wetting surfaces, such as with hydrophobic
surfaces used with water. Hence, this leaves the design of
a phase separation membrane to rely solely on geometric
considerations. In order to successfully produce the
necessary capillary burst pressures for phase-separation,
the pore-level geometries must exhibit a sudden sharp
discontinuity in their shapes [5].
Figure 4 shows burst pressure experiments performed
using microglass capillaries. Initially flow encounters
minimal viscous effects as the flow rate is maintained well

Resistance to heat conduction across thin liquid films

has posed a classic problem for liquid cooling
technologies. Liquid film thickness on the order of
microns is required for management of next-generation
2
heat fluxes on the order of 10 kW/cm with feasible
pumping requirements. To address this issue, we are
developing thin porous copper films to deliver fluid to
hotspots.
We fabricate thin porous copper films using the colloidal
template method described in previous work [6]. Figure 5
summarizes the steps involved for fabrication of the
copper microporous liquid delivery layer. The first step
includes synthesizing monodisperse polystyrene spheres
with diameters on the order of 1 m using dispersion
polymerization. The template is fabricated for the porous
material by drop casting a suspension of spheres in
ethanol on silicon wafers with Ti/Au seed layers deposited
1. Drop cast spheres

2. Electrodeposited Copper

3. Dissolve spheres

Fig. 4. Glass capillary bursting pressure experimental results for

FC-40.

5m

below the regime where viscous effects are significant

(Ca<10-5), and consequently, the pressure remains
constant (point A in Fig. 4.). During this period, the
pressure in the liquid is lower than that in the gas above by
an amount determined by the curvature of the meniscus as
it climbs up the capillary. At this point, the pressure in the
liquid begins to rise as the meniscus becomes less concave
(point B, Fig.4.). Eventually, the meniscus becomes
planar, and the pressure between the liquid and gas phases
is equal as shown at point C in Fig. 4. The meniscus runs
off to the outer diameter edge of the microglass capillary,
where it pins and begins to grow in curvature. The
meniscus is able to reach the surface of the outer diameter
where it reaches its minimum radius of curvature and
maximum burst pressure, which is indicated at point D in
Fig. 4. After the burst pressure is reached, viscous and
evaporative effects balance the capillary flow forces which
gives a constant pressure plateau as seen at point E in Fig.
4. These results show proof that a microfabricated
structure can be engineered to pin dielectric liquids
based on optimization of pore geometry.

Fig. 5. Fabrication steps for porous copper films using the

colloidal crystal template method (left) and top view SEM image
of porous copper (right).

by physical vapor deposition (PVD). Following

metallization of the silicon substrate, copper is
electrodeposited through the bed of packed spheres. The
polymer spheres are then dissolved using in
tetrahydrofuran (THF) in order to attain the microporous
copper structure. This method allows the growth of porous
thin films of thickness on the order of 10 microns. We
characterize the porosity of the porous copper films by
analyzing cross-sectional scanning electron micrographs
as described in previous work [6]. Our samples typically
have porosities in the range of 60-90%.

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B. Fabrication of a Hydrophobic Capping Layer

V. CONCLUSION

For water, the key element in producing capping layers

with high burst pressures that impose a specific phase
boundary is achieving strongly hydrophobic surface
chemistries along with fine pore sizes. We have developed
monolithic porous layers of hydrophobic material to
accomplish these goals. Monolithic layers allow ease of
localization and independent control of pore size and
porosity, since they are deposited as a separate layer on
top of the microporous layer. Monolithic phase separation
layers, however, also pose challenges. Bonding is less
robust, as the burst pressure is supported by a sharp
interface at the top of the microporous layer, and thickness
of the layer must be tightly controlled so as not to
excessively impede the escape of vapor.
We use phase separation to produce monolithic
hydrophobic
capping
layers
composed
of
polyvinylidenefluoride (PVDF) based on their successful
application in microfluidic gas/liquid contactors [7].
Figure 6 shows an example of the layers produced. The
fabrication process consist of: 1.) dissolution of PVDF (20
wt%) in dimethylacetamide (DMAc) 2.) casting of films
from the PVDF/DMAc solution 3.) rapid immersion of the
cast films in a second liquid which is miscible with DMAc
but does not dissolve PVDF (e.g. 1:1 ethanol:water).

We have developed phase separation technologies in

order to mitigate the challenges with pressure drops
associated with two-phase liquid cooling. We are applying
these advances to next generation power devices such as
microwave high-electron mobility transistors (HEMT) and
ultra-high density chip scale integrated (stacked chip)
digital devices such as microprocessors. By attacking the
fundamental limitations to electronics cooling, we have
the opportunity to deliver orders-of-magnitude gains in
heat flux removal and open up dramatic avenues of
advance for application of electronic devices.
ACKNOWLEDGMENT
The authors would like to acknowledge financial
support from DARPA (agreement # HR0011-13-2-0011,
titled: Phase Separation Diamond Microfluidics for
HEMT Cooling) monitored by Dr. Avi Bar Cohen, Dr. Joe
Maurer, and Dr. Matin Kaiser.
REFERENCES
[1] H. Graeb, "ITRS 2011 analog EDA challenges and
approaches," in Design, Automation & Test in Europe
Conference & Exhibition (DATE), 2012, 2012, pp. 11501155.
[2] M. Arik and A. Bar-Cohen, "Immersion cooling of high
heat flux microelectronics with dielectric liquids," in
Advanced Packaging Materials, 1998. Proceedings. 1998
4th International Symposium on, 1998, pp. 229-247.
[3] R. C. Chu, U. P. Hwang, and R. E. Simons, "Conduction
Cooling for an LSI Package: A One-Dimensional
Approach," IBM Journal of Research and Development,
vol. 26, pp. 45-54, 1982.
[4] R. Schofield, A. Fane, and C. Fell, "Heat and mass transfer
in membrane distillation," Journal of membrane Science,
vol. 33, pp. 299-313, 1987.
[5] D. D. Agonafer, Lopez, K., Palko, J., Won, Y., Asheghi,
M., Santiago, J.G., Goodson, K.E., "Phase-Separation of
Wetting Fluids Using Nanoporous Alumina Membranes and
Micro-GLASS Capillaries," in IEEE Intersociety
Conference on Thermal and Thermomechanical Phenomena
in Electronic Systems (ITHERM), Orlando, Fl, 2014.
[6] T. J. Dusseault, Gires, J., Barako, M.T., Won, Y., Agonafer,
D.D., Asheghi, M., Santiago, J.G., Goodson, K.E., "Inverse
Opals for Fluid Delivery in Electronics Cooling Systems,"
in IEEE Intersociety Conference on Thermal and
Thermomechanical Phenomena in Electronic Systems
(ITHERM) Orlando, Fl, 2014.
[7] E. Karatay and R. G. Lammertink, "Oxygenation by a
superhydrophobic slip G/L contactor," Lab on a Chip, vol.
12, pp. 2922-2929, 2012.

Fig. 6. Nano-porous PVDF produced by phase separation from

solution.

Spin coating or doctor blading can be used to deposit the

PVDF solution. Thicknesses of ~10 m have been
achieved with targeted thicknesses as small as 1 m.
Immersion of the film results in rapid removal of DMAc
from the PVDF solution and the formation of porous, solid
PVDF, with submicron pore sizes.

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High Resolution Thermal Characterization and Simulation of Power

AlGaN/GaN HEMTs Using Micro-Raman Thermography and 800
Picosecond Transient Thermoreflectance Imaging
Kerry Maize1, Georges Pavlidis2, Eric Heller3, Luke Yates2, Dustin Kendig4, Samuel Graham2, and Ali
Shakouri1
1

Birck Nanotechnology Center, Purdue University, West Lafayette, IN, 47907, USA, e-mail:
2
kmaize@purdue.edu; Woodruff School of Mechanical Engineering, Georgia Institute of Technology,
Atlanta, GA, 30332 USA; 3Materials and Manufacturing Directorate, Air Force Research Laboratory,
Wright-Patterson Air Force Base, OH, 45433, USA; 4Microsanj Inc., San Jose, CA, 95051, USA
Abstract Self-heating in gallium nitride based high
frequency, high electron mobility power transistors (GaN
HEMTs) is inspected using micro-Raman thermography and
800 picosecond transient thermoreflectance imaging. The
two methods provide complementary temperature
information inside the semiconductor and on top metal
layers of the GaN HEMT. Self heating is measured under
both steady-state and ultra-fast pulsed transient operation
with submicron spatial resolution, 50 milliKelvin
temperature resolution, and nanosecond time resolution.
Fine grain electro-thermal modeling of the HEMT steady
state and transient self-heating are presented alongside
measurements. Large spatial and temporal temperature
gradients are quantified. Deviations due to unknown
parameters are discussed.
Index Terms Gallium nitride, HEMTs, MODFETs,
power transistor, Raman thermography, thermoreflectance
imaging.

allowing for spatial resolution close to 0.5 m and the

identification of temperature specifically in the GaN layer
or the GaN and SiC substrate simultaneously. It is
possible to perform Raman in both steady state and
transient modes with time resolutions on the order of 10
ns. [1]-[6] Transient thermoreflectance imaging [7]-[9],
offers submicron spatial resolution and 50 milliKelvin
temperature resolution. A camera acquires full field
thermal images quickly with no scanning required of the
measurement probe or sample. Recent enhancements
using pulsed laser illumination have demonstrated
transient thermoreflectance imaging with sub-nanosecond
time resolution.
Combining micro-Raman and thermoreflectance
imaging
provides
complementary
measurement
information particularly advantageous in thermal
characterization of high frequency power semiconductor
integrated electronics, such as GaN HEMTs. Raman can
measure average temperature a few microns below the
semiconductor surface. Thermoreflectance imaging
measures temperature optimally on the device surface.
Raman has been used extensively to measure temperature
and stress in semiconductors whereas thermoreflectance
excels at measuring temperature of metals (e.g. contacts.)
By combining these techniques, it is possible to measure
the transient temperature response, thermal resistances,
phonon lifetimes, and thermal stresses that exist in
AlGaN/GaN HEMTs with accuracy. Such parameters are
necessary for the thermal analysis of these devices,
providing a more complete picture of their thermal
response and factors that can impact device reliability.

I. INTRODUCTION
Gallium nitride material systems have gained attention
in the power electronics community due to their high
breakdown voltage and high temperature tolerance. High
electron mobility transistors based on gallium nitride
(AlGaN/GaN HEMTs) demonstrate robust performance
under both steady state and high frequency switching
operation. Despite these promising characteristics,
insufficient understanding of thermal behavior and
reliability has limited applicability of GaN HEMTs,
especially at high power densities. Knowledge of steady
state and transient temperature effects at the fail site can
lead to improved designs and expanded range of
application.
Multiple techniques have been proposed to measure
temperature in GaN HEMTs with the required high spatial
and time resolution. Raman spectroscopy has been
demonstrated as a powerful technique for the
quantification of temperature in AlGaN/GaN HEMTs,

978-1-4799-3622-9/14/$31.00 2014 IEEE

II. DEVICE DESCRIPTION

Self-heating was studied in the high speed, gallium
nitride high electron mobility transistor shown in Fig. 1.
The structure consists of two 150 m wide conducting

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Fig. 1. (a) Optical CCD image of two finger AlGaN/GaN high electron mobility RF power transistor. Gate width ~ 150 m.
Channel length ~ 5 m. Enlarged image shows location of thermoreflectance sampling boxes for HEMT drain metal, GaN channel,
and gate metal. (b) AlGaN/GaN HEMT cross section (not to scale).

channels. Channel length of each finger is approximately

5 m. The channels are AlGaN/GaN stacks, controlled by
field effect through metal gate atop the stack. MicroRaman and thermoreflectance measurement was
performed for identical AlGaN/GaN HEMT devices.
Micro-Raman spectroscopy was applied directly to the
channel of the devices to measure both the average
temperature rise and thermal stresses in the GaN layer.
Thermoreflectance imaging analyzed temperature
gradients in the HEMT gate metal, drain contact metal,
and GaN channel. All Raman measurements were
performed under steady state conditions while
thermoreflectance was performed under pulsed operation
over a range of frequencies to include both fast transient
and quasi steady state operating conditions.
III. Experiment Methods

was made at all power conditions in order to estimate the

uncertainty of the temperature measurement (95%
confidence intervals).
All power sourcing and electrical measurements were
conducted with a Keithley 2410 SMU for biasing the gate
and a 2425 SMU for biasing the drain where high current
and high voltage are needed. Ground-singal-ground
probes connected to bias tees with 50 Ohm terminations
were used to make electrical contact with the devices.
Both the calibration and measurement steps for microRaman thermal metrology were done with a temperature
controlled stage set at 298 K. (Instec HCP302). Thermal
grease (~ 35 m thick) was used between the backside of
the wafer and the thermal stage to reduce interface
thermal resistance. The resulting Raman spectrum was
analyzed with a Gaussian-Lorentzian (Voigt) fit to find
peak parameters of the Stokes peaks of GaN.
The temperature and the stress in the devices were
estimated using the two peak fit method according to [7]:

A. Micro-Raman Thermography
Micro-Raman spectroscopy was performed using a
Renishaw InVia Raman microscope with a 0.25 m focal
length spectrometer and a 488 nm laser with a laser beam
diameter 0.8 m as the excitation source. Sub-band gap
laser wavelengths were used for Raman measurements to
prevent localized heating of GaN by laser light absorption.
The collected Raman signals were imaged on a charge
coupled device (CCD) camera. Experiments were carried
out with the laser light perpendicular to the basal plane of
GaN in a 180 backscattering configuration and unpolarized detection with a 50X objective. For the
experiments, a 3000 l/mm grating was used with a slit
width of 65 m. An average of at least 20 measurements

E 2(High) = AE 2(High) T + K E 2(High)

(1)

A1(LO) = AA1(LO)T + K A1(LO) .

(2)

and

KE2(High) and KA1(LO) are linear coefficients for the stressphonon frequency relations, obtained by X-ray diffraction
and Raman measurements on high-quality GaN templates
(KE2(High) = -3.09 0.41 cm-1/GPa and KA1(LO) = -2.14 0.28
AE2(High) and AA1(LO) describe the linear
cm-1/GPa).
temperature-phonon frequency relations, derived by

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performing Raman measurements on a high quality HVPE

GaN sample subject to known temperatures from room
temperature up to 673 K (AE2(High) = -0.0150 0.0001 cm1
/K and AA1(LO) = -0.0281 0.0001 cm-1/K). The residual
stress was calculated using the strain-free E2 (high) mode
frequency 0 = 568.15 0.13 cm-1 and the Raman biaxial
conversion factor, KE2(High).

Lock-in voltage pulses during thermoreflectance

imaging were applied to the HEMT drain-source with gate
held constant and fully open with VGATE = +2 V for all
measurements. Gate leakage was negligible. Drain voltage
pulse duty cycle was 15%. Pulse width and pulse
amplitude are presented with results. Drain voltage pulses
were supplied by a Berkeley Nucleonics voltage pulser
with 3 ns rise time and 10 ns fall time. Constant gate
voltage was supplied by a DC source. No bias tees were
required for pulsed excitation of the HEMT. VDRAIN pulse
waveforms were monitored using a LeCroy high
bandwidth 3.5 GHz digital oscilloscope. Current through
the HEMT was measured from the pulsed voltage drop
across a 50 resistor in series with the HEMT drain. The
HEMT was probed on wafer using Cascade Microtech
ACP-40L ground-signal-ground high speed coplanar
probes. Custom low profile Cascade Microtech DCQ
coplanar probes were used for high magnification probing
configurations. The bottom of the sample wafer was fixed
by thermal paste to a two-inch thick copper heat sink
maintained at room temperature.

B. Transient Thermoreflectance Imaging

Thermoreflectance imaging microscopy measures the
small change in material surface reflectance for a change
in temperature. Thermoreflectance imaging of the GaN
HEMT was performed by electrically probing the sample
under a reflectance microscope using narrow bandwidth
visible wavelength illumination. Pulsed laser illumination
(440 nm) was used for 800 ps time resolution and pulsed
light emitting diode illumination (530 nm) was used for
50 ns time resolution. The HEMT was electrically excited
with periodic, low duty-cycle square voltage pulses at a
lock-in
signal
frequency
ranging
between
approximately one kHz to one MHz, depending on the
temporal resolution desired. The voltage pulses produce
self-heating in the HEMT at the lock-in frequency and
corresponding reflectance change signal on the surface of
the device active area. HEMT surface reflectance was
recorded by an Andor 512 x 512 pixel high dynamic range
electron multiplying charge coupled device camera
(EMCCD) synchronized to the device lock-in excitation
signal. By using pulsed illumination synchronized to the
lock-in frequency, separate images of HEMT surface
reflectance are recorded corresponding to the hot (on) and
cold (off) time segment of the excitation cycle. Amplitude
of thermoreflectance change between the hot and cold
images were extracted by averaging over many HEMT
excitation cycles. Thermoreflectance images with signal
to noise ratios greater than five were achieved for HEMT
metal regions in less than five minutes of averaging.
Thermoreflectance amplitude images are converted to full
field maps of temperature change across the HEMT
surface by scaling with experimentally extracted material
Material
thermoreflectance
coefficients,
CTH.
thermoreflectance varies with wavelength of source
illumination. For 530 nm LED illumination, the HEMT
drain contact metal thermoreflectance coefficient was
experimentally found to be CTH-contact metal = 1.6 0.23 x 10-4
K-1. Thermoreflectance coefficients for the HEMT gate
metal and GaN channel were estimated indirectly based
on drain contact metal coefficient using an isothermal
approximation during the cooling transient for the HEMT.
Estimates of thermoreflectance temperature resolution are
given with each result presented in this report.

C. Electrothermal Modeling
Transient and steady-state modeling was performed for
this device using ISE Sentaurus Device [10] and based on
nominal dimensions (design rules) for the device. The
steady state simulation domain was about 10 m away
from the heat generating region as done in [11], with a
temperature dependent thermal boundary condition linked
to a large-scale 3-D finite-element thermal model built in
ANSYS [12] of the device, substrate, 35 m thermal
grease (0.57 W/m/K assumed as per data sheet) and
copper block held fixed at 298 K. The unusual thermal
boundary in this model A in Fig. 2 was chosen to
approximate the location of an isotherm and simplify
representation of this thermal boundary layer. Model A
is useful at very short time scales (before the heat
propagates to the end of the simulation domain), and at
steady state, but in between will not be accurate. A
simulation B with a very different thermal boundary
condition was used to test the region of validity of this
model and disagreement of 1 K was reached at 0.3 s. To
improve this, the electro-thermal model was expanded,
with an adiabatic thermal boundary condition midway
between the two fingers and a 78 m by 62 m simulation
domain containing one finger (representing twice this
width and the two fingers of the actual device). Again, a
simulation with a very different thermal boundary
condition C was used to test the region of validity of
this model and disagreement of 1 K was reached at 10 s.
Fig. 2 shows this process, and the level of agreement.
While this complication could be eliminated with a full

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Table of Contents

Fig. 3. Data showing the temperature rise between the gate

and drain in the AlGaN/GaN HEMT under DC bias conditions,
with modeled data (high thermal resistance is the solid line,
lower thermal resistance is the dashed line). The laser location
is represented by the red circle. A maximum temperature rise of
135 K is observed at 14 W/mm power dissipation.

Fig. 2. Different small scale simulation domains illustrating

temporal regions of validity. Drain bias is ramped up linearly
over the first 1 ns of the simulation (not shown), while gate
voltage was held at 0 V.

3D electro-thermal simulation down to the thermal sink,

the process described is far more computationally
efficient. In all cases, meshing was fine in regions of high
gradients (electrical/thermal) such as drain corner of the
gate and perpendicular to the channel and coarser away
from high gradients, with verification that additional
refinement did not significantly impact thermal or
electrical results (~0.1%).
From this point on in the text and after Fig. 2, only
simulation data in the known region of validity (prior to
0.3 s, prior to 10 s, or steady state depending on
domain) are shown.
Fig. 4. Data showing the thermoelastic stress induced in the
channel during DC operation. A maximum compressive stress
of 260 MPa is observed at 14 W/mm power dissipation.

IV. RESULTS
A. Results: Micro-Raman Thermography

in this estimation and is expected to induce a residual

tensile stress in the AlGaN layer which is still detrimental
to the reliability of the device. In addition, the thermal
expansion mismatch between the gate metallization and
the AlGaN layer has also been shown to induce additional
tensile stresses in the AlGaN region near the gate which
must also be considered in the overall picture of
operational induced stresses in AlGaN/GaN HEMTs.

Steady-state Raman measurements of the temperature

rise between the gate and the drain are shown in Fig. 3.
The data shows the maximum temperature rises 135 K
above equilibrium at a power of 14 W/mm. Measurements
over multiple devices on the same wafer showed
repeatable results. Also, the data show a thermal
resistance of 9.6 mmK/W for the devices, considering a
linear power density. Fig. 4 shows the corresponding
thermoelastic stress in the channel. It is shown that the
induced stress is compressive and reaches a maximum
near -260 MPa at a power of 14 W/mm. With a residual
stress of 284 18 MPa, the induced compressive stress at
the highest powers reduces the average stress in the GaN
layer to close to zero. However, it should be noted that
inverse piezoelectric stresses has not been accounted for

B. Results: Transient Thermoreflectance Imaging

Pulsed illumination in thermoreflectance imaging
permits capture of the time evolution of the self-heating
signal within devices. The camera records reflectance data
only when the light pulse is on, serving effectively as an
exposure shutter to inspect selected time windows in the
device excitation cycle. Temporal resolution is equivalent

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to the minimum width of the light pulse. For pulsed

LEDs, this is in the range of 50 ns. Transient
thermoreflectance imaging using a pulsed 800 picosecond
440 nm laser has been demonstrated with subnanosecond
time resolution. By controlling the delay between the
phase synchronized device pulse and light pulse,
individual thermoreflectance images can reconstruct the
thermal transient of the device over the full excitation
cycle. Fig. 5 shows the transient thermoreflectance images
of the GaN HEMT using 800 picosecond pulsed
illumination at 100X magnification. Images of the HEMT
gate metal and drain metal thermal transient in response to
a 300 ns square voltage pulse were acquired with five ns
time resolution. Drain-source voltage pulse amplitude was
15 V, producing drain current of 280 mA and power of
14.3 W/mm. Fig. 5a shows the CCD image of the top
HEMT channel and four false color transient
thermoreflectance images of the same region at 15, 25, 50,
and 100 ns after the rising edge of the excitation pulse.
Images were averaged 10 minutes each. Minimum
temperature resolution The plot of Fig. 5b compares the
transient thermal response of the gate metal and drain
metal for time = 0-50 ns. Each data point represents the
mean temperature of all pixels in a sampling rectangle of
width equal to the full channel width visible in the thermal
image and length indicated for each region in Fig. 1a. One
standard deviation for the sampled pixels was 1 K for the
drain metal and 6 K for the gate metal. Ultra-fast transient
thermal characterization reveal self-heating in the first 50
ns is prominent in the active channel and gate regions,
indicating the occurrence of significant thermal gradients
between active GaN channel and adjoining metal gate and
contact regions under fast switching conditions.
The full-field view of spatial temperature distribution in
the HEMT demonstrates how thermoreflectance imaging
can complement micro-Raman measurement. Raman
provided precise measurement of the GaN layer channel
temperature at a tight spot location. Thermoreflectance
imaging simultaneously provides an overview of HEMT
self-heating in several adjoining regions, including the
gate metal and contacts, with submicron spatial resolution.
HEMT transient self-heating was also measured beyond
the first 50 ns of excitation. The full rising thermal
transient from 50 ns out to quasi-steady state at 100 s
was
measured
using
LED
based
transient
thermoreflectance imaging and 50X magnification. Fig. 6
plots temperature change versus logarithmic time for three
critical HEMT features: GaN channel, gate metal, and
drain contact. HEMT pulsed drain voltage was 20.1 V,
producing drain current of 280 mA. Power was 19 W/mm.
Duty cycle was 15%. The full rising transient was
assembled piecewise from three separate transient

Fig. 5. Eight hundred picosecond pulsed laser transient

thermoreflectance imaging of the GaN HEMT. (a) Enlarged
EMCCD image of one finger in the GaN HEMT with gate metal
and drain contact metal indicated. Corresponding
thermoreflectance images show self-heating at 15, 25, 50, 100
ns after the rising edge of a 300 ns, 15 V excitation pulse
applied to drain. (b) HEMT transient self-heating compared for
the gate metal and drain metal with 5 ns time resolution. Pixel
sampling region indicated in Fig. 1a. One standard deviation is
1 K for drain metal and 6 K for gate metal. Pulsed laser
wavelength is 440 nm. Magnification is 50X.

imaging sweeps. HEMT temperature change within time

windows one, 10, and 100 s after the pulse rising edge
were acquired using temporal resolution steps of 50 ns,
500 ns, and 5 s respectively. One standard deviation for

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Table of Contents

Fig. 7. Illustrates the location of data extraction, with green

to represent the Thermoreflectance gate temperature
measurement, the large red dot the thermoreflectance channel
temperature measurement (and neighboring dots to show lateral
variation), and the large blue dot the thermoreflectance ohmic
temperature measurement (and again neighboring dots to show
lateral variation). S, G, D show location of Source, Gate,
and Drain. Last, the brown rectangle shows the location of the
temperature data extraction to compare to Raman. Because the
Raman laser is sub-bandgap, the data will represent an average
through the thickness of the GaN and therefore model data was
integrated over this region.

at very different regions and time scales, data is modeled

and presented differently but the same underlying model
parameters were used for all models. Where simulation
domain and boundary conditions were varied (A, B,
C), it was verified they agree at very short times where
these differences will not matter.
Fig. 8 and Fig. 9 show the modeled temperature at very
short time scales, and Fig. 8 shows the transient electrical
response of the modeled device. In this case, current

Fig. 6. AlGaN/GaN HEMT temperature rise versus

logarithmic time for time = 50 ns to 100 s after rising edge of
the excitation pulse, measured with transient thermoreflectance
imaging. Rising thermal transients compared for HEMT
channel, gate metal, and drain contact metal regions. One
standard deviation is 1, 8, and 13 K for drain metal, gate metal,
and GaN channel respectively.

pixels sampled was 1 K for the drain metal, 8 K for the

gate metal, and 13 K for the GaN channel.
Comparing thermal rise times for the three HEMT
features we see the GaN channel displays the fastest selfheating transient. The small gate metal heats nearly as fast
as the channel. The comparatively slow thermal rise time
of the drain contact metal suggests the speed at which heat
from the active channel diffuses into the adjoining
contacts. HEMT drain metal temperature change does not
rise significantly above ~ 65 K between time = 40-100 s,
indicating the HEMT fast thermal transients have
stabilized (quasi-steady state) for pulse durations greater
than 100 s. Consequently, it is possible to estimate the
HEMT thermal rise time (1-1/e) to be in the range of ~ 10
s. The smaller and much slower background thermal
transients in the full chip and heat sink are expected to be
-1
1
on the order of 10 -10 seconds.
From Fig. 6, thermoreflectance estimates GaN channel
temperature rise of ~ 140 K at quasi steady state under
applied bias of 19 W/mm. Using the linear thermal
resistance extracted from Fig. 3, Raman measurement
extrapolates GaN channel temperature rise of 182 K for
the same power.

Fig. 8. Modeling results at short time scales, for the data

extraction points shown in Fig. 7 (small and large red dots map
to thin and thick red lines, blue to blue, green to green), and for
drain current (black lines), at set bias of VD = 20.5 V and VG = 0
V. Because there is substantial variation for published high and
low bounds to thermal resistance for the GaN epilayer and the
GaN/SiC interface from ref [4], the error this can introduce in
models must be understood. Double ended arrows represent the
level of disagreement between modeling using optimistic or
pessimistic input parameters in reported temperature at one
location and effectively represent an error bar for modeling in
the face of these unknowns.

C. Results: Electrothermal Modeling

Modeling was done to compare to both the Raman and
Thermoreflectance measurements, with locations of data
extraction shown in Fig. 7. Because the techniques look

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Table of Contents

Fig. 10. Modeling results at selected times and for the

high/low thermal resistance bounds. The thermal bottleneck at
the GaN/SiC interface is apparent in the top row after 100 ns
and 10 s of applied power.

V. CONCLUSION
We have presented transient thermoreflectance imaging
temperature data together with the results obtained from
Raman for the GaN HEMT. Temperature gradients near
the interface between the gate metal and GaN channel
were inspected, as temperature related stresses here may
be important in device reliability at high power density.
The experimental results are compared with Sentaurus
Device and finite element electrothermal modeling. From
fast transient experimental and model data, we have data
sufficient to begin to extract metal/semiconductor thermal
interface resistances in as-fabricated devices. While the
trends are consistent, some deviations are observed due to
the unknown thin film thermal conductivity as well as
GaN/substrate and the metal/semiconductor thermal
interface resistances. As metallic layers play a key role in
in-plane heat spreading, future work will use the
temperature profile on the top surface at different times in
order to extract key parasitic parameters and cross validate
with thermal models.

Fig. 9. Modeling results at very short time scales comparing

gate, channel, and ohmic data extraction points.
Zero
temperature rise is at 25C = 298.15 K at the bottom of each
scale. Data extraction points are shown by the large dots in Fig.
7 (large red dots map to red lines, blue to blue, green to green).
It is critical to note that the model assumed there was no
thermal boundary resistance between gate and channel, so the
gate heat-up in the model will be much faster than with a
boundary layer in place. In fact, thermoreflectance data is seen
as a way to characterize this type of unknown in the model.

droops with increasing time mostly because the electrical

characteristics of the channel such as mobility and
saturation velocity worsen with increasing temperature as
the channel heats up. In Fig. 9, the ohmic reproduced the
expected thermoreflectance data reasonably well. The
gate is seen to heat up much faster than the experiment
however. It is critical to note that the model assumed
there was no thermal boundary resistance between gate
and channel, so the gate heat-up in the model will be
much faster than with a boundary layer in place. In fact,
thermoreflectance data is seen as a way to characterize
this type of unknown in the model.
Modeling data with respect to Raman is shown in Fig. 3
for high thermal resistance (top solid line) and low
thermal resistance (bottom dotted line) at the VD = 20.5 V
and VG = 0 V bias selected for modeling to be consistent
with bias conditions and baseplate temperature selected
for the Raman measurement. Other than altering AlGaN
barrier thickness and composition, dimensions within the
channel and epi stack, substrate mounting details and
electrical properties to properly reflect the electrical
properties of the devices employed in this study, the
modeling methodology was entirely consistent with [1].

REFERENCES
[1] E. Heller, S. Choi, D. Dorsey, R. Vetury, and S. Graham,
Electrical and structural dependence of operating
temperature of AlGaN/GaN HEMTs, Microelectronics
Reliability, vol. 53, no. 6, pp. 872877, 2013.
[2] R. Simms, J. Pomeroy, M. Uren, T. Martin, and M. Kuball,
Current collapse in AlGaN/GaN transistors studied using
time-resolved Raman thermography. Applied Physics
Letters, 93, 203510, 2008.
[3] A. Manoi, J. W. Pomeroy, R. Lossy, R. Pazirandeh, J.
Wrfl, M. J. Uren, T. Martin, and M. Kuball, Timedependent thermal crosstalk in multifinger AlGaN/GaN
HEMTs and implications on their electrical performance,
Solid-State Electronics, vol. 57, no. 1, pp. 1418, March
2011.
[4] S. Choi, E. Heller, D. Dorsey, R. Vetury, and S. Graham,
Thermometry of AlGaN/GaN HEMTs using multispectral

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[5]
[6]

[7]

[8]

Raman features, IEEE Transactions on Electron Devices,

vol. 60, no. 6, pp. 1898-1904, June 2013.
T. Beechem and S. Graham, Temperature and doping
dependence of phonon lifetimes and decay pathways in
GaN, Journal of Applied Physics, vol. 103, 093507, 2008.
T. Beechem, S. Graham, S. Kearney, L. Phinney, and J.
Serrano, Invited Article: Simultaneous mapping of
temperature and stress in microdevices using micro-Raman
spectroscopy, Review of Scientific Instruments, vol. 78,
no.6, 2007.
S. Ju, O. Kading, Y. Leung, S. Wong, & K. GooDon,
Short-timescale thermal mapping of semiconductor
devices, IEEE Electron Device Letters, vol. 18, no. 5, pp.
169-171, May 1997.
G. Tessier, S. Hol, and D. Fournier, Quantitative thermal
imaging by synchronous thermoreflectance with optimized

[9]

[10]
[11]

[12]

52

illumination wavelengths, Applied Physics Letters, 78, pp.

2267-2269, 2001.
M. Burzo, P. Komarov, and P. Raad, Noncontact transient
temperature mapping of active electronic devices using the
thermoreflectance method, IEEE Transactions on
Components and Packaging Technologies, vol. 28, no. 4,
pp. 637-643, December 2005.
Sentaurus Device User Manual, Ver. A-2007.12, Synopsys,
Inc., Mountain View, CA, December. 2007.
E. Heller, R. Vetury, and D. Green, Development of a
versatile physics-based finite-element model of an
AlGaN/GaN HEMT capable of accommodating process and
epitaxy variations and calibrated using multiple DC
parameters, IEEE Transactions on Electron Devices,
vol.58, no.4, pp.1091-1095, April 2011.
ANSYS/Mechanical Software Suite, ANSYS, Inc.,
Canonsburg, PA.

Table of Contents

Thermal Interface Resistance Measurements for

GaN-on-Diamond Composite Substrates
Jungwan Cho,1 Yoonjin Won,1 Daniel Francis,2 Mehdi Asheghi,1 and Kenneth E. Goodson1
1

Mechanical Engineering Department, Stanford University, Stanford, CA 94305, USA

2

Element Six Technologies, 3901 Burton, Santa Clara, CA 95054, USA

Abstract The performance of high-power gallium

nitride (GaN) high-electron-mobility transistors (HEMTs) is
limited by self-heating effects. High thermal resistances
within micrometers of the active device junction often
dominate the junction temperature rise and fundamentally
limit the device power handling capability. The use of highthermal-conductivity diamond in close proximity to the
transistor junction can mitigate this thermal constraint, but
careful attention is required to the quality of the thermal
interface between the GaN and diamond. Here we apply
time-domain thermoreflectance (TDTR) to two GaN-ondiamond composite substrates with varying GaN thicknesses
to measure the thermal interface resistance between the GaN
and diamond (29 m2 K GW1) as well as the thermal
conductivity of the GaN buffer layer (112 W m1 K1) at
room temperature. Informed by these data, we perform
finite-element analysis to quantify the relative impact of the
GaN-diamond thermal interface resistance, diamond
substrate thermal conductivity, and a convective cooling
solution on the device channel temperature rise.

contribution to the overall thermal resistance of the

devices, the selection of a suitable substrate material is
crucial [7].
SiC has been a common choice as a substrate material
due to its higher thermal conductivity (~400 W m1 K1)
than that of Si (~142 W m1 K1) and sapphire (~35 W m
1
K1) [7]. But the near-junction thermal resistance of
GaN-on-SiC devices still restricts efficient heat spreading
away from the active device regions and therefore limits
the device performance and reliability [4], [8]. The
integration of chemical-vapor-deposited (CVD) diamond
substrate in close proximity to the transistor junction
holds promise in improving the near-junction cooling of
GaN HEMT devices mainly due to its excellent heat
spreading capability. A typical value for the roomtemperature thermal conductivity of high-quality
polycrystalline CVD diamond is near 1500 W m1 K1 [9],
which is higher by a factor of nearly 5 than that of SiC.
However, the large mismatch of key crystalline properties
(i.e., lattice constants and coefficients of thermal
expansion) of GaN and diamond compared to the
mismatch of these properties of GaN and SiC creates a
challenge for the fabrication of high-quality GaN on
diamond substrate [10], [11].
Current GaN-on-diamond fabrication technologies can
be grouped broadly into two categories: i) direct GaN
heteroepitaxy on single crystalline diamond [11]-[13] and
ii) GaN epilayer transfer to polycrystalline CVD diamond
[8], [14]-[16]. The former method involves approximately
1-m-thick transition layers between the GaN and single
crystal diamond for strain compensation. Such relatively
thick transition layers often contain high densities of
defects, and exhibit high thermal resistance [15]. The
second method, used in this work, involves the transfer of
pre-grown AlGaN/GaN heterostructures to polycrystalline
CVD diamond using a thin intermediate adhesion layer
(~50 nm). This approach is beneficial in that the thermal
resistance of the intermediate material between the GaN
and diamond is much lower than that of the first approach.
But this approach still requires reduction in the thermal
interface resistance between the GaN and diamond.

Keywords

High-Electron-Mobility Transistors
(HEMT), Gallium Nitride (GaN), Diamond, Thermal
Boundary Resistance (TBR), Thermal Interface Resistance,
Thermal Conductivity, Time-Domain Thermoreflectance
(TDTR), Electronics Cooling

I. INTRODUCTION
Gallium nitride (GaN)-based high-electron-mobility
transistors (HEMTs) are promising for high-power
electronic applications such as a radar amplifier [1]. High
electrical breakdown fields of GaN and high electron
charge densities at the AlGaN/GaN heterojunction enable
higher-power and higher-frequency operation of GaNbased transistors than GaAs- and Si-based transistors
allow [2], [3]. However, device-level self-heating and
associated thermal management challenges at this higher
power density severely limit the peak power density and
impair the device reliability [4], [5]. High thermal
resistances in the near-junction region (i.e., a region
within micrometers of the heated electronic junction)
often hinder efficient heat transport from the active device
regions to the heat sink components [4], [6], [7]. Since the
spreading resistance of the substrate makes a key

978-1-4799-3622-9/14/$31.00 2014 IEEE

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In this paper, we use time-domain thhermoreflectance

(TDTR) to extract the thermal conductivvity of the GaN
buffer layer as well as the GaN-diamond tthermal interface
resistance for two GaN-on-diamond compposite substrates
with varying GaN thicknesses. Our data suggest that the
GaN/diamond thermal interface resistancee is near 30 m2 K
GW1 at room temperature for the ccurrent GaN-ondiamond composite substrates. Informed by our data and
m finite element
other available literature data, we perform
thermal analysis to quantify the relativee impact of the
GaN-diamond thermal interface resistannce as well as
other resistance components on the device channel
temperature rise (see Appendix).
Fig. 1. Cross-sectional schematiic drawing of the GaNon-diamond composite substratess used in this study with
a representative cross-sectional transmission electron
micrograph near the GaN-diamon
nd interface.

II. SAMPLES AND EXPERIMENTAL METHODS

Figure 1 shows the two GaN-on-diam
mond composite
substrates used in this study, with twoo different GaN
thicknesses (0.85 m and 0.37 m). T
The AlGaN/GaN
heteroepitaxial layers are first grown on a Si substrate by
metal-organic chemical vapor deposition (MOCVD). The
material stack consists of an ~25-nm-thiick GaN/AlGaN
device layer, an ~0.8-m-thick GaN bufffer layer, and an
~1-m-thick AlN and AlGaN transition layer on top of
the Si substrate. The 1-m-thick transitionn layer serves to
reduce lattice mismatch stresses during grrowth. Because it
is highly resistive [15], we etch it as well as the Si
substrate away. Then, an ~30-nm-thhick disordered
adhesion layer is deposited on the back-side of the GaN
buffer layer, and CVD diamond with a thickness of
approximately 100 m is grown on top of the adhesion
layer. Two composite substrates with thiis final structure
are fabricated; one remains as it is and the other is etched
The two samples
to a different GaN thickness of 0.37 m. T
are coated with a thin Al film of ~47 nm
m that acts as the
temperature transducer for TDTR measureements.
Cross-plane thermal conductivity of the GaN buffer
layer and thermal interface resistance beetween the GaN
and the diamond are measured by TDTR. TDTR is a wellestablished technique used to measure thhin film thermal
conductivities and thermal interface resisstances in multilayer stacks [17]-[22]. Details of our T
TDTR setup are
described in [21] and [22]. We fit the T
TDTR data with
three parameters: the Al/GaN therrmal boundary
resistances (TBRs) Rb, Al -GaN , the thermal conductivity of
the GaN buffer layer kGaN , and thee GaN-diamond
thermal interface resistance, Rb , GaN - Diaam . The GaNdiamond thermal interface resistance is not the discrete
boundary resistance but rather invvolves multiple
resistance contributions: i) the thermal reesistance of lowquality GaN regions near the adhesion/diaamond interface,
ii) the two discrete boundary resistances at the adhesion

layer interfaces with the GaN and

d the diamond, iii) the
intrinsic thermal resistance of the adhesion
a
layer, and iv)
the thermal resistance of the near-in
nterfacial diamond (i.e.,
the nucleation/coalescence region
ns). These resistance
contributions are lumped and reepresented as a single
effective interface resistance. We use
u literature values for
the heat capacities of the constituen
nt layers [9], [23], [24],
and we assume a range of thermal conductivity from 400
W m1 K1 to 2000 W m1 K1 for the thermal
conductivity of the diamond substtrate [9]. The diamond
thermal conductivity within the assumed range has a
minimal impact on the fitted values of kGaN and
Rb , GaN - Diam [25].
III. RESULTS AND DISSCUSSION
Figure 2a shows representativee TDTR data with the
best analytical fits at room temperaature for the two GaNon-diamond composite substrates. We simultaneously fit
o samples under the
the TDTR data from the two
assumption that kGaN and Rb , GaN
G - Diam do not vary
strongly between the two sampless [22], [26]. Using this
approach, we find kGaN = 112 15 W m1 K1 and
Rb , GaN - Diam = 29 2 m2 K GW1 at room temperature.
The uncertainty in the values is due
d to variations in the
thickness of the Al transducer film (47 2 nm). The
room-temperature Al/GaN thermal boundary resistance is
determined to be 13 m2 K GW1 for the thicker GaN
sample and 10 m2 K GW1 for the thinner GaN sample.
Our approach takes advantage off different measurement
sensitivities to these two properrties at different GaN
thicknesses [22]. We define a TDTR sensitivity
coefficient as the logarithmicc derivative of the
thermoreflectance signal R with respect to the thermal

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We extract the GaN-diamon

nd thermal interface
resistance as well as the thermal co
onductivity of the GaN
buffer layer using TDTR on two GaN
G thicknesses. Recent
simulation [7] has shown thatt a GaN-on-diamond
configuration with an interface resiistance of below 30 m2
K GW1 can outperform a GaN
N-on-SiC configuration
even with zero interface resistancee in terms of the device
channel temperature rise. The inteerface resistance of the
current GaN-on-diamond composiite substrates seems to
reach this target. With an anticip
pated reduction in the
interface resistance, the GaN-o
on-diamond composite
substrates should enhance the neear-junction cooling of
HEMT devices.
ACKNOWLEDGM
MENT
The authors acknowledge supp
port from AFOSR and
DARPA MTO under NJTT and ICECool programs, as
well as collaboration and direct sponsorship from RFMD
and Element Six.
M NITRIDE-DIAMOND
APPENDIX: IMPACT OF GALLIUM
INTERFACE RESISTANCE ON THE CHANNEL
H
TEMPERATURE

We perform finite-element anaalysis using COMSOL

Multiphysics to investigate the rolle played by the GaNdiamond thermal interface resisstance in the device
channel temperature rise of the ov
verall HEMT package,
including the AlGaN/GaN epilayer, diamond substrate,
vice schematic for the
and diamond microchannel. A dev
simulation considers two thermal resistance
r
mechanisms:
i) conduction/spreading in GaN-o
on-diamond composite
substrates (near-junction thermal trransport, NJTT) and ii)
fluidic convection in diamond microchannels
m
(thermal
transport in advanced heat sinks).
s
The assumed
microchannel features have a <1
100 m width and an

Fig. 2. (a) Representative TDTR data (bblack solid lines)

with best analytical fits (red dashed lline) for the two
GaN-on-diamond composite substratess. (b) Sensitivity
coefficients for the GaN thermal conducctivity (red lines)
and the GaN-diamond thermal interfacee resistance (blue
lines) for the two samples as a functioon of the pumpprobe delay time.

parameter of interest : S = ln( R ) / ln( ) . Figure

2b illustrates the sensitivity coefficientts for kGaN and
Rb , GaN - Diam for the two different thickneess samples and
as a function of the probe delay time. T
The thicker GaN
sample primarily affects the value of kGGaN whereas the
thinner GaN sample mostly determinees the value of
Rb , GaN - Diam .
The GaN thermal conductivity determinned here is lower
than the values found previously [7], [22],, [26], which can
be attributed to the size effect as well as the effect of
phonon scattering on material defects. Thhe GaN-diamond
thermal interface resistance determined heere is also lower
than what we measured previously [15] m
mainly due to the
absence of the highly resistive transittion layer. Our
measured interface resistance is comparabble to the recent
Raman-measured value of 27 m2 K GW1 at
approximately 400 K [16].

Fig. 3. Device channel temperaature rise due to GaNdiamond thermal interface resistan
nce, diamond substrate
thermal conductivity, and convective resistance of
cooling solution.

V. CONCLUSIONS

55

Table of Contents

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aspect ratio of 10:1. The 3-D conduction simulation

dissipates a 5 kW cm2 in a device-level hot spot (200 m
x 200 m) and 1 kW cm2 in the background (5 mm x 5
mm). Figure 3 depicts the results of the channel
temperature rise for different diamond thermal
conductivities and different values of the channel wall
heat transfer coefficient. For example, a simulation result
indicates that the hot spot temperature rise is 4.5 C for a
heat transfer coefficient of 101 kW cm2 K1 and a
diamond thermal conductivity of 2000 W m1 K1. The
temperature rise due to the GaN-diamond thermal
interface resistance is particularly important, as clearly
indicated by red bars in Fig. 3. The large interface
resistance of 100 m2 K GW1 can account for more than
50% of the overall channel temperature rise when the
diamond thermal conductivity is 2000 W m1 K1. The
accurate determination of the GaN-diamond thermal
interface resistance is therefore important for accurate
prediction of the channel temperature rise.
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Table of Contents

Microfluidic Heat Exchangers

for High Power Density GaN on SiC
Yoonjin Won, Farzad Houshmand, Damena Agonafer, Mehdi Asheghi, Kenneth E. Goodson
Mechanical Engineering Department, Stanford University, Stanford, CA 94305

Abstract The high power densities targeted for GaN

HEMT on SiC technology can dramatically increase the
performance of radar systems. The increasing power will
require improved heat removal technologies associated with
conduction and convection. Here we explore combined
cooling technologies based on SiC substrate and SiC or Cu
microstructures, which improve the thermal performance of
high power devices.
Index Terms GaN, HEMT, SiC, Electronics Cooling.

for realistic drain efficiency, preventing extreme hotspot

temperatures. Additionally, we introduce the separated
hotspot designs to prevent the extreme hotspot
temperature rises of compact design due to self-heating.
The combined techniques of two-phase cooling, SiC
etching, and separated hotspots can extend the cooling
limitation of GaN HEMT devices.
II. CONVECTIVE COOLING

I. INTRODUCTION

The heat transfer coefficient of flow boiling is strongly

influenced by the boiling regime as well as parameters
including the heat flux, mass flux, and vapor quality. Heat
transfer coefficients can be increased by increasing heat
flux in nucleate boiling dominant regimes, whereas in
annular flow regime heat transfer can be increased by
increasing the mass flux [10]. However, based on the
studies on transition between different flow regimes,
transition to annular flow occurs at smaller qualities at
high mass fluxes [11]. Several studies demonstrated the
enhancement in two-phase heat transfer using extended
surfaces (e.g., [5], [9], [12], [13]). The extended surfaces
increase the area in contact with flowby the factor of fin
effectiveness ( )and increase the effective heat transfer
coefficient (heff = hW ). This approach may also expedite
the onset of nucleate boiling by increasing the nucleation
cites at the corners. The other important issue in flow
boiling is the critical heat flux (CHF) associated with dry
out conditions, which can lead to device failure. Total heat
flux ( "
) can be increased by proper heat spreading
while maintaining the wall heat flux below the CHF
values [14].
Researchers have been studying the CHF in flow boiling
in channels for many years [15-17] and developed various
correlations for a wide range of dimensions and fluids.
Kaya et al. [18] reported a correlation for CHF at high
2
heat fluxes approaching 30 kW/cm based on their study
2
using water at high mass fluxes (~40000 kg/m -s) using
microchannel geometries, Meyer et al. [19] suggested a
semi empirical correlation for CHF in the impinging jet
configuration. Ohadi et al. [20] reported values of CHF
2
for a range of mass fluxes (up to 1400 kg/m -s) using 3-D
manifolding structures.

Gallium nitride high electron mobility transistors (GaN

HEMT) target extreme power densities approaching 100
2
kW/cm . Much attention has been given to thermal
management to develop advanced heat sinks using micro
and nanofabrication technology. In this work, we aim to
minimize the thermal resistances by using highly
conductive materials to spread heat over larger areas and
transmit heat to a phase change interface. Two-phase
cooling helps to achieve large convective heat transfer
coefficients and remove large heat fluxes exceeding ~30
2
kW/cm .
Two-phase flow heat transfer at micro/mini scales and
particularly flow boiling has been studied extensively in
past years [1-4] due to high heat transfer coefficients and
reduced pumping power. However, convection boiling can
lead to higher pressure drops [5] and instability issues [6],
[7] that should be considered in the design of the microheat exchanger and in the system level to achieve a robust
cooling system [8], [9].
Gallium nitride HEMT power transistor and integrated
circuit technologies are typically manufactured on silicon
carbide (SiC) substrates, which have relatively high
conductivities near 400 W/m-K at room temperature.
However, the thermal conductivity of SiC rapidly
decreases with high temperature, which is often close to
the junction temperature of devices. This has motivated
the etching of SiC substrates to define cooling channels or
thinning SiC substrates to utilize the extended surfaces or
decrease the overall thermal resistance of SiC substrates.
Thus, the micromachining of SiC substrates allows high
power densities of GaN HEMT to be efficiently dissipated

978-1-4799-3622-9/14/$31.00 2014 IEEE

57

Table of Contents

TABLE I
SUMMARY OF PROPOSED ARCHITECTURES
DESIGN 1

DESIGN 2
Thin SiC,
Cu Fin

DESIGN 3
Thin SiC,
CIOs

2 m x 340 m x 40
m
1.5
m
20
m
80
m
m
m
10

1.5
20
5
100
10

1.5
20
5
100
10

C
C

240
210

140
134

SiC Fin only

GEOMETRY PARAMETERS
Gate
GaN
SiC Base Thickness
SiC Fin Thickness
TIM Thickness
Cu Fin/Mesh Thickness
Fin Width/Pore size
2

RESULT (h= 300 kW/m -K)

T max, Compact Heater
T max, Separated Heater

287
240

III. PROPOSED ARCHITECTURES AND FABRICATION

METHODS

In order to predict the performance of heat exchangers,

it is crucial to estimate the two-phase heat transfer
coefficients. Several groups worked on developing
correlation for prediction of two-phase heat coefficient in
microchannels [10, 22]. For instance, Szczukiewicz et al.
[23] obtained a fine-resolution time-averaged two-phase
flow heat transfer coefficients in an array of
microchannels and compared their results with the
previously developed correlations. Recently, Kaya et al.
[18] reported very high values for local heat transfer
2
coefficients (> 400 kW/m -K) for boiling in microtubes at
high flow rates. However, the heat transfer coefficient data
2
collected at high mass fluxes and heat fluxes (> 1kW/cm )
are still limited.
The effect of geometry (especially in non-microcahnnel
configurations) should also be considered to design the
heat exchangers. To mention a few experimental studies
for geometries close to the proposed design in the next
section, Sung et al. [21] reported heat transfer data for
hybrid jet impingement geometry with an array of
microchannels and presented a correlation for two-phase
heat transfer coefficient as a function of heat flux and
subcooling. The maximum heat transfer coefficient of 45
2
kW/m -K was reported at wall heat fluxes of qw <0.2
2
kW/cm . Ohadi et al. [20] utilized an array of
microchannels with 3-D manifolding using and reported
2
heat transfer coefficients up to ~37 kW/m -K for qw ~ 0.2
2
kW/cm .

The peak power densities of GaN HEMT technology

are limited by the hierarchy of thermal resistances from
the junction to the cooling fluid. The goal is to dissipate
large heat fluxes with minimum temperature rise. First, we
micromachine SiC substrates to spread heat over larger
area and transmit heat to the phase-change interface. Then,
we use the small hydraulic diameter of microchannels or
porous structures to improve the convective heat transfer.
Gallium nitride HEMT circuits are typically grown on
SiC substrates. The conductivity of the SiC substrate is
high at room temperature (400 W/m-K), but it decreases
significantly with increasing temperature (e.g., kSiC~120
W/m-K at 200C). We minimize the effect of the
temperature dependence by micromachining SiC channels
or thinning the SiC substrate. The micromachining has
been demonstrated by numerous groups, resulting in
controlled transfer of complex, micro-scale geometries to
both SiC thin films and substrates [23], [24]. These studies
have leveraged semiconductor manufacturing techniques
to create vias and trenches in SiC using plasma etching
with SF6 and O2 source gases as well as HBr and Cl2
source gases. These processes have been developed and
demonstrated to create microscale features with
approximately 5:1 aspect ratios and etching depths as deep
as 200 m (NASA).
The micromachining of SiC channels (design 1 SiC
fins) allows the use of extended surfaces, which decrease
the wall heat flux by spreading the dissipated heat to the
flow over a larger area. The SiC fin configuration is
associated with the capability for deep etching of SiC to

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Table of Contents

Fig. 1. Temperature rises along the y-direction below the compact hotspot (dashed line) or separated hotspot (solid line) designs of 92.4W
(Design 2).

hotspot are shown in inset of Fig. 1. Here, the compact

hotspot shows 40 gates of 1 m 400 m. The separated
hotspot also has 40 gates of 1 m 400 m where 10
gates are separated with a large gap of 220 m. The larger
gaps enlarge the footprint width from 1000 m to 1600 m
and increase the number of fins from 50 to 80.

create microscale features with approximately 10 mwidth and 8:1 aspect ratios. Therefore, we have the 20 mthick SiC spreading layer with 80 m-deep SiC channels.
Because of the strong temperature dependence of the
SiC substrate, design 2 includes the thinning process of
SiC substrate to minimize the thermal resistance of SiC
and Cu fin fabrication (design 2 Cu fins only on thin SiC
substrate). In order to minimize the gate temperature, it is
important to achieve high heat transfer coefficients to
dramatically decrease the overall thermal resistance. Since
it is challenging to etch micron level channels with higher
aspect ratios >10, we introduce copper porous structures
by using the electrodeposited template method [25].
Design 3 has the technology of thinning SiC substrates
and copper inverse opals (CIOs) fabrication (design 3
CIOs on thin SiC substrate). CIOs are used to by means to
deliver liquid coolant. This process can help minimize the
thermal resistance by promoting the development of ultrathin liquid films. Small hydraulic diameters of CIOs can
increase effective heat transfer coefficient. State of the art
manufacturing
technology
using
a
template
electrodeposition can produce structures with tightly
controlled pore size (from < 1 m to 30 m) and thickness
as well as extreme ordering in pore placement. Also, this
template method can integrate porous liquid transport
layers on the interior surfaces of microchannels.
Additionally, we introduce the concept of a separated
hotspot to avoid the extreme hotspot temperature rise due
to self-heating. The details of the separated and compact

IV. CONDUCTION SIMULATIONS AND DISCUSSION

A simulation was performed using COMSOL
Multiphysics to account for the thermal resistances
associated with the GaN and transition layer and
conduction within the SiC substrates and various channels.
The proposed designs are described in section III, and the
details are indicated in Table 1. The top layer is 1.5 mthick GaN; the following layer is SiC base and/or fins.
Thicker base thickness increases thermal resistances but
improves the spreading. Thus, in this modeling, the
optimized SiC base thickness is suggested as 20 m while
the channel depth is 80 m (design 1). Design 2 and 3 has
SiC substrates of 20 m only after the thinning process;
additional 5 m-thick thermal interface materials (TIM)
and 10 m Fins/CIOs are followed. For the conduction
simulation, we have included the material properties for
each layer. The simulations account for the thermal
conductivity of GaN and SiC as a function of temperature.

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Table of Contents

Fig. 2. Conduction part has been simulated using COMOSL Multiphysics. The simulations account for the temperature dependency
2
using kSiC(T) and kGaN(T). Gate temperatures as a function of h from 100-500 kW/m -K using design 1-3 proposed are shown. Heat
flux is given to the gates (hotspot) with a power of 92.4. The fluid inlet temperature is assumed as Tfluid = 25C.

method can push the limit of hotspot temperature and help

to improve the device performance. This approach needs
more careful design to minimize the pressure drop across
the small feature sizes and maximize the CoP (coefficient
of performance).

For the boundary conditions, the heat flux of 330

2
kW/cm is given to the gates (2 m x 340 m x 40), which
gives the total power of 92.4 W to the system. The heat
2
transfer coefficients with a range of 200-500 kW/m K are
imposed to the fin walls. The other surfaces are adiabatic
conditions.
We perform the simulations starting with design 1 and
extend to designs 2 to 3. The simulations provide us the
temperature distributions in the fin structures. The
example results (Top view) are shown in Fig. 1. The
calculations of temperature distributions of various
components to the total temperature rise using the
separated (dashed) and compact (solid) hotspot
distributions with copper fins (design 2) are plotted in Fig.
1. This particular case shows the 30C improvement with
the separated hotspot while other contribution ratios are
similar. Therefore, the separated hotspot design
significantly decreases the gate temperature.
Our solution features SiC fins, Cu fins, or CIOs for heat
exchange with two-phase flow. The results for hotspot
temperature as a function of heat transfer coefficient, h,
are shown in Fig. 2. Design 2 using Cu fins with a
separated hotspot, Tmax is decreased from 350C to 200C
2
2
when h is increased from 300 kW/m -K to 500 kW/m -K.
This design improves dT of 50-70C for various values of
the heat transfer coefficient, h despite of using additional
interface layer. With design 3, we introduce porous
conductive, CIO structures. As discussed earlier, the small
hydraulic diameter enhances the heat transfer coefficients
as well as increases the surface area. Therefore,
fabrication techniques such as a template electrodeposition
[1]

V. CONCLUDING REMARKS
The theoretical modeline and literature review presented
here suggest strongly that the combination of two-phase
cooling, SiC etching, and separated hotspots to extend the
cooling limitation of GaN HEMT devices. For future
work, it is important to understand the physics behind the
etched channels and porous structures produced and their
performance in devices by characterizing the effective
thermal conductivity and convective heat transfer.

ACKNOWLEDGEMENTS
The authors would like to acknowledge financial
support from DARPA (agreement # HR0011-13-2-0011,
titled: Phase Separation Diamond Microfluidics for
HEMT Cooling) and AFRL (contract # FA8650-14-C7464, titled: ICECool Applications) monitored by Dr. Avi
Bar Cohen, Dr. Joe Maurer, and Dr. Kaiser Matin.
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IEEE Sensors J., vol. 7, no. 4, pp. 568576.
T.J. Dusseault, J. Gires, M.T. Barako, Y. Won, D.D.
Agonafer, M. Asheghi, J.G. Santiago, K.E. Goodson,
"Inverse Opals for Fluid Delivery in Electronics Cooling
Systems," IEEE Intersociety Conference on Thermal
and Thermomechanical Phenomena in Electronic
Systems (ITHERM) 2014, May 27 - 30, Orlando, FL,
USA.

Table of Contents

A 23.2dBm at 210GHz to 21.0dBm at 235GHz

16-way PA-cell combined InP HBT SSPA MMIC
Zach Griffith, Miguel Urteaga, Petra Rowell, Richard Pierson
Teledyne Scientific Company, 1049 Camino Dos Rios, Thousand Oaks, CA 91360
zachary.griffith@teledyne.com, 805-453-8011

Abstract A 3-stage, 16-way PA-cell combined InP HBT solidstate power amplifier MMIC is presented demonstrating
23.2dBm (208.7mW) Pout at 210GHz to 21.0dBm (126.0mW) at
235GHz for 10dBm Pin this represents 13.2-11.0dB large-signal
gain. The total high-power bandwidth of this SSPA is between
190.8-237GHz. The amplifier has 24.3-26.7dB S21 gain from 206243GHz. The total PDC is 5.81W. A power-cascode cell topology is
used for the PA unit cell, which is used to generate a 3-Stage, 4Cell output combined SSPA then four of these 4-Cell SSPAs are
combined using low insertion loss Wilkinson dividers and
combiners to realize the overall 16-way PA cell combined MMIC.
This is the first reported SSPA MMIC demonstrating > 200mW
Pout above 200GHz operation. The output powers from this work
across 190.8-237GHz are the highest values reported from an
SSPA MMIC and improves upon state-of-the-art by 1.16-1.6
from 190.8-225GHz and by 1.6 from 230-235GHz. This result
closely meets or exceeds across the same frequency operation the
highest Pout reported from a solid-state based PA, a four-chip
waveguide-block combined module.

I. INTRODUCTION

Fig. 1 IC Micrograph of the 3-Stage, 16-Cell InP HBT SSPA MMIC.

Dimensions: 1.95mm 1.90mm.

Synthetic aperture radars and high resolution imaging

systems operating at G-band frequencies and higher will
continue to benefit from the development of solid-state power
amplifiers (SSPA). These solid-state sources are typically used
to drive diode multiplier chains for THz applications or to
drive power vacuum tube amplifiers at the same frequency.
Design fundamentals for solid-state power amplifiers
includes identifying the appropriate transistor geometry and
layout for single PA-cell, as well as being able to power
combine these cells for a given output power objective. For 2n
corporate power combining, the losses from the combiner and
path length between PA cells degrade combining efficiency
once these overall losses reach 1.5-2dB, spatial power
combining (as a more efficient combining method) must be
considered if higher Pout is required from an amplifier module.
At high-mm-wave and sub-millimeter wave frequencies, there
are a number of challenges associated with spatial power
combining of multiple SSPA MMICs they include
identifying PAs having similar gain and phase characteristics,
low RF isolation between PA chips and waveguide blocks,
build-to-build variations generating chip-to-chip phase
mismatch, and increased DC bias complexity. For these
reasons, increasing the RF power from a single-chip MMIC
will always be pursued as it is a less complex and much lower
cost approach to high-power 0.25-1W SSPA modules
operating at G-band frequencies and higher.
We present a 3-stage, 16-way PA-cell combined InP HBT
SSPA MMIC demonstrating 23.2dBm (208.7mW) Pout at
210GHz to 21.0dBm (126.0mW) at 235GHz for 10dBm Pin.
978-1-4799-3622-9/14/$31.00 2014 IEEE

The total high-power bandwidth is between 190.8-237GHz.

The amplifier has 24.3-26.7dB S21 gain from 206-243GHz.
This is the first reported SSPA MMIC demonstrating
> 200mW Pout above 200GHz operation. The output powers
from this work across 190.8-237GHz are the highest values
reported from an SSPA MMIC and improves upon state-ofthe-art [1-3] by 1.16-1.6 from 190.8-225GHz and by 1.6
from 230-235GHz. This result closely meets or exceeds across
the same frequency operation the highest Pout reported from a
solid-state based PA, a four-chip waveguide-block combined
module [4].
II. MMIC POWER AMPLIFIER DESIGN
A single power amplifier (PA) cell was designed having a
cascode topology using a 20um emitter length (Le) commonemitter (CE) HBT and 24um Le common-base (CB) HBT. A
detailed description of the device topology, DC performance,
and RF performance (gain and stability) of these 250nm InP
HBT cells have been reported in [5]. Each cascode PA cell has
its input matched to 50-Ohm Zo for highest small- and largesignal RF gain. The PA cell output is matched so the CB HBT
collector voltage and current traverse a class-A load-line,
coincident with the high performance operating area of the
HBT for 200-240GHz large-signal operation.

62

Table of Contents

30

DC Block

PA Cell

PA Cell

Amplifier gains (dB)

PA Cell

1:4 Splitter

DC Block

1:2 Splitter

PA Cell

PA Cell

4:1 Combiner

PA Cell

2:1 Combiner

DC Block

PA Cell

2:1 Combiner

1:2 Splitter

4-Cell PA

DC Block

4-Cll PA
4-Cell
PA

4-Cell PA
PA Cell

Upper 8-cell PA

VC1
(V)
1.89
1.71

IC1
(mA)
453
459
912

VE2
(V)
-1.59
-1.20

IE2
(mA)
630
640
1270

0
-10

~ 26.3dB

22

11

-20
210

220

230

240

250

frequency (GHz)

260
P

DC

= 5.81W

Fig. 3 S-parameters of the 3-Stage, 16-Cell SSPA MMIC.

30

Lower 8-cell PA

VC2
(V)
1.96
1.98

21,mid-band

3-stage, 16-Cell SSPA

Fig. 2 Circuit block diagrams of the 4-Cell SSPA (top) and how
it is configured as a 16-Cell SSPA MMIC (bottom) using 2-way
Wilkinson dividers and combiners.

16-Cell
SSPA
Stgs-1, 2
Stage-3
Totals

10

Amplifier gains (dB)

1:2 Splitter

4-Cell PA
PA Cell

2:1 Combiner

1:2 Splitter

4-Cll PA
4-Cell
PA

2:1 Combiner

2:1 Combiner

16-cell SSPA

1:2 Splitter

PA Cell

20

IC2
(mA)
603
610
1213

PDC
(W)
3.04
2.76
5.81

25

21

20
15

S , upper 8-cells
21

S , lower 8-cells
21

10
5
0

A)

Table-1 DC summary for the 16-Cell SSPA MMIC.

S , 16-cells

Unthinned 25-mil InP wafer measurements

210

220

230

240

250

frequency (GHz)

15

2.5

1.0

S
B)

10
5

1.5
S gain difference
21

21

gain (dB)

Phase difference

2.0

phase (degrees)

The amplifier components were simulated in Agilent

ADS, using an Agilent-HBT model for the 250nm HBT
technology. Interconnects, transmission lines, MIM
capacitors, probe pads, and power splitter/combiner structures
were designed using ADS Momentum. Thin-film microstrip
transmission lines are formed using the lowest metal
interconnect layer as DC and RF ground potential, and the
upper three metal interconnect layers for signal routing.
Additional details associated with the use of this wiring
scheme for WR04 frequency operation can be found in [5, 6]
Figure-2 shows circuit block-diagrams of the SSPA. The
objectives were to generate an SSPA MMIC design
demonstrating 200mW Pout at 220GHz and 140mW Pout at
235GHz operation while having > 14dB large-signal gain. To
satisfy these objectives, a three-stage SSPA having four output
cascode power cells combined (4-Cell SSPA) was first
generated, expecting 50-Ohm impedance to be presented to
the input and output nodes of this amplifier. Then by using 2way Wilkinson dividers and combiners, four of these 4-Cell
SSPAs are combined to generate the 3-Stage, 16-Cell SSPA
MMIC. The DC bus design employs shunt R-C bypass
networks (series 600fF + 15Ohm) along the bus lines to
provide RF isolation from the DC bias pads and between PA
stages. The insertion loss of the 2-way and 4-way
divider/combiner structures used in the SSPA is 0.45dB and
0.5dB, respectively (reported in detail in [6]).

0.5

-5

0.0

-10
210 220 230 240 250 260 270 280
Frequency (GHz)

Fig. 4 S21 gain measurements (plot-A) of the 16-Cell SSPA and

of the upper and lower 8-Cell SSPAs when separately DC biased,
as well as the S21 gain and phase difference (plot-B) between the
upper and lower 8-Cell PAs comprising the 16-Cell SSPA
MMIC. Note: all MMIC measurements reported here are from
the same amplifier; however, the measurements from these
figures were collected from the MMIC prior to wafer thinning.

III. EXPERIMENTAL RESULTS

VNA measurements were performed using 206-325GHz
OML T/R frequency extender modules (controlled by an
Agilent 8510C) with GGB WR03 waveguide coupled wafer
probes. LRRM probe-tip VNA calibration was used. The InP
chip thickness is 3-mil and it is mounted to a heatsink (unless
63

Table of Contents

220

25

216GHz

20

225GHz (triangles)

160

(dBm)

180
220GHz

out

206GHz

140

out

210GHz

120

DC

4
6
P , mW

A)

in

231.5GHz (hallow-circles)

(dBm)

237GHz

244GHz

DC

3
4
P , mW

3dB

10

DC

20

235GHz

= 5.81W

Gain
P

20

208.7mW
out

10

210GHz operation

-10

-5

PAE

0
P (dBm)

= 5.81W

15

~ 182mW

3.40%

10

B)

in

Fig. 5 16-Cell SSPA MMIC Pout for swept Pin. Plot-A contains
frequency sweeps from 206-225GHz and plot-B from 230-244GHz.

185.3mW

out

3dB

10

25

15

DC

10

216GHz operation

-10

-5

= 5.81W

PAE

0
P (dBm)

3.03%

5
0
10

in

30

(dBm)
out

155.1mW

15

out

10

20

Gain

3dB

15

~ 108mW

225GHz operation

10
PAE

2.53%

-5
C)

-10
P

DC

-5

0
P (dBm)

= 5.81W

DC

(dBm)
out

Gain
3dB

-5

15

~ 96mW

10

235GHz operation

= 5.81W

25
20

out

10

-10

PAE

0
P (dBm)

2.02%

10

Gain (dB), PAE

0
D)

126.0mW

15

10

in

25
20

25

Gain (dB), PAE

20

20
15

Gain

~ 152mW

25

otherwise noted in the figures). The amplifier S-parameters

are shown in figure 3, evaluated at the DC bias summarized in
table-1. The 16-Cell SSPA MMIC demonstrates 24.3-26.7dB
S21 gain from 206-243GHz. Because of the high isolation
associated with the Wilkinson structures, the S21 gain and
phase of the upper and lower 8-Cell amplifiers, when
separately biased, could be evaluated to verify that they have
similar gain and phase characteristics as a means of
confirming that a 16-Cell MMIC with highest performance
has been generated these measurements are shown in figure
4, where only 0.5-1.1dB S21 gain variation and 5-11 degrees
S21 phase variation is observed between the two 3-Stage, 8Cell PAs.
For large-signal measurements, a VDI amplifier
multiplier chain (AMC, 16 multiplier) is used for power
sweep testing of the SSPA from 190.8-244GHz. An Erickson
PM4 power sensor measured the output power, and
appropriate deembedding of the RF wafer probes and
waveguide transitions have been considered.
Figure-5 summarizes the 16-Cell SSPA MMIC Pout for
swept Pin for frequency sweeps from 206-244GHz at
200GHz, only a single power level of 4.65mW Pin is available
from the source. Small increases to the DC currents of ~ 1.5%
were observed during high RF power operation these
corresponding increases to PDC are considered in the
calculation of PAE. This SSPA demonstrates peak 220.8mW
Pout at 200GHz and 208.7mW Pout at 210GHz. At 235GHz
operation, peak Pout remains high and is 126.0mW.

in

25

230GHz

233.25GHz (hallow-squares)

15

10

out

140
130
120
110
100
90
80
70
60

= 5.81W

out

P
B)

out,sat

100
0

= 221mW (Pin = 4.65mW)

Gain (dB), PAE

, mW

A)

200GHz P

25
Gain (dB), PAE

, mW

200

in

Fig. 6 16-Cell SSPA MMIC Pout, Gain, and PAE for swept Pin at
210GHz (plot-A), 216GHz (plot-B), 225GHz (plot-C) and 235GHz
(plot-D).
64

20
P

DC

P = 2.5mW
in

200

= 5.81W

PAE
210

220

(mW)
out

200
P

out

200

= 5.81W

210

PAE
220

230

220

Teledyne Monolithic 16-PA cell combined

InP HBT SSPA, Pin ~ 6-12mW

200
180
160
140

NGAS 32-InP HEMT cell, 4-way WG-block

combined SSPA module, Pin ~ 30mW

120
200

205

210

215

220

225

230

235

frequency (GHz)
16

P = 6.0mW
in

120

DC

240

12

160

4
0

Fig. 8 Comparison of the maximum Pout achieved at a given

frequency for the 16-way PA cell combined InP HBT MMIC
(reported here) to the 32-way (8 PA cells per InP HEMT SSPA
MMIC) PA cell combined module using 4-way WG-block
combining [4].

Gain (dB), % PAE

Gain

190

B)

230

frequency (GHz)

240

80

15
10

190

A)

Gain

out

RF output power (mW)

out

220
200
180
160
140
120
100
80
60

Gain (dB), % PAE

(mW)

Table of Contents

the Pout achievable for the amplifier by 5-10%, as well as

increase the amplifier large-signal bandwidth from 235GHz to
245-250GHz.
ACKNOWLEDGEMENT
This work was supported jointly by Teledyne Scientific,
as well as DARPA under contract HR0011-13-C-0013. The
views, opinions, and/or findings contained in this article are
those of the authors and should not be interpreted as
representing the official views or polices, either expressed or
implied, of the Defense Advanced Research Projects Agency
or the Department of Defense.

240

frequency (GHz)

Fig. 7 Pout, Gain, and PAE for swept frequency at fixed input
power Pin = 2.5mW (plot-A) and Pin = 6.0mW (plot-B) for the 16Cell SSPA MMIC.

Approved for Public Release, Distribution Unlimited

Figures-6 shows the Pout, Gain, and PAE with swept input
power at 210GHz, 216GHz, 225GHz, and 235GHz. The plots
show well behaved amplifier characteristics. The 16-Cell
SSPA MMIC 3dB gain compression output power P3dB is
182mW at 210GHz (208.7mW Psat), 152mW at 216GHz
(185.3mW Psat), 108mW at 225GHz (155.1mW Psat), and is
96mW at 235GHz (126.0mW Psat).
Gain flatness of the SSPAs under large signal operation
was examined. Figure-7 shows Pout, Gain, and PAE for the 16Cell SSPA MMIC at fixed 2.5mW and 6.0mW Pin. At 2.5mW
Pin, the SSPA demonstrates 109.0-186.2mW between 190.8237GHz; the associated gain is 16.4-18.7dB. At 6.0mW Pin,
the SSPA demonstrates 124.7-220.8mW between 200235GHz; the associated gain is 13.2-15.6dB. It is unclear why
the Pout is measured lower at 205GHz because the WR03
probes are operating below the WR03 band, the authors
speculate that an impedance is presented to the amplifier
output that shifts the HBT RF load-line trajectory to one
having lower Pout. This issue does not modify the S-parameter
measurements due to VNA calibration.
Lastly, figure-8 is a comparison of the maximum Pout
achieved at a given frequency for the 16-way PA cell
combined InP HBT MMIC (reported here) to the 32-way (8
PA cells per InP HEMT SSPA MMIC) PA cell combined
module using 4-way WG-block combining reported in [4].
With continued decreases to the physical layout height, the
shorter combining interconnect will improve the combining
efficiency of the 16-Cell InP HBT SSPA this will increase

The authors thank Dr. Bobby Brar of Teledyne Scientific,

Dr. Bruce Wallace of DARPA, and Dr. Alfred Hung of ARL
for their support of this work. The authors also acknowledge
and thank the Teledyne Scientific Fabrication Operations team
for fabrication of this MMIC.
IV. REFERENCES
[1] Z. Griffith et al., A 50-80mW SSPA from 190.8-244GHz at
0.5mW Pin, IEEE MTT Int. Microwave Symposium, Tampa, FL,
June 1-6, 2014.
[2] V. Radisic et al., 50mW 220GHz InP HBT Power Amplifier
MMIC, IEEE MTT Int. Microwave Symposium, Tampa, FL,
June 1-6, 2014.
[3] T. Reed et al., A 180mW InP HBT Power Amplifier MMIC at
214GHz, Proc. IEEE Compound Semiconductor IC
Symposium, Monterey, CA, Oct. 13-16, 2013.
[4] V. Radisic, et al., 220-GHz Solid-State Power Amplifier
Modules, IEEE Journal of Solid-State Circuits, Vol. 47, No.
10, October 2012.
[5] Z. Griffith et al., Multi-finger 250nm InP HBTs for 220GHz
mm-Wave Power, Proc. Indium Phosphide and Related
Materials Conference, Santa Barbara, CA Aug. 26-30, 2012.
[6] Z. Griffith el at., A 227.5GHz InP HBT SSPA with 101mW
Pout at 14dB Compressed Gain and 4.04%, Proc. IEEE
Compound Semiconductor IC Symposium, Monterey, CA, Oct.
13-16, 2013.

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Table of Contents

Backside Process Free Broadband Amplifier MMICs at D-Band and

H-Band in 20 nm mHEMT Technology
Thomas Merkle1, Arnulf Leuther1, Stefan Koch, Ingmar Kallfass2, Axel Tessmann1, Sandrine Wagner1,
Hermann Massler1, Michael Schlechtweg1, and Oliver Ambacher1
1

Fraunhofer Institute for Applied Solid State Physics (IAF), Tullastr. 72, 79108 Freiburg, Germany,
phone: +49-761-5159-555, email: thomas.merkle@iaf.fraunhofer.de

University of Stuttgart, Institute of Robust Power Semiconductor Systems, Pfaffenwaldring. 47, 70569
Stuttgart, Germany

Abstract High gain amplifier MMICs (monolithic

microwave integrated circuits) addressing broadband radar
and communication applications at the waveguide bands
WR-6 (110 - 170 GHz) and WR-3 (220 - 325 GHz) are
presented. All circuits are manufactured in the next
generation metamorphic high electron mobility transistor
(mHEMT) technology featuring 20 nm gate length and a
strained 100% InAs channel. The transistors are
encapsulated by 0.3 m and 1.4 m thick layers of
benzocyclobutene (BCB). The 1.4 m thick BCB layer is used
to form shielded thin-film microstrip (TFMS) lines confined
at the front-side of the wafer for implementing matching
networks. Substrate thinning and backside processing is not
required for the function of the amplifiers. The amplifier for
WR-6 operates over the whole waveguide band with an
average gain of 28 dB. A gain of more than 24 dB was
measured for the MMIC from 215 290 GHz. All presented
MMICs exceed 30% of gain defined bandwidth.
Index Terms Metamorphic high electron mobility
transistor (mHEMT), monolithic microwave integrated
circuit (MMIC), broadband amplifier, millimeter-wave, thinfilm microstrip (TFMS), benzocyclobutene (BCB).

waveguide bands WR-1.5 (500 750 GHz) and WR-1.2

(600 900 GHz). The down-scaling of the wafer thickness
has mechanical limitations and effects yield. Thin-film
transmission lines at the front-side of the wafer is one
possible solution for this dilemma. Backside processing
can be omitted.
[3] used for the first time front-side thin-film microstrip
lines (TFMS) for the design of a 35 nm mHEMT based
3-stage amplifier at H-band having a gain of 11 16 dB
from 206 to 294 GHz. Previously this transmission line
implementation was reserved to InP HBT based amplifier
designs [4]. Inverted front-side thin-film microstrip lines
(I-TFMS) were tested in [5], also with an InP HBT
process. All results were demonstrated at H-band. Inverted
grounded CPW thin-film transmission lines were
employed in [6] for the design of amplifiers up to
670 GHz with a small signal gain of 24 dB.
This work introduces front-side thin-film transmission
lines for the design of broadband D-band and H-band
amplifiers. A new 20 nm mHEMT technology is used with
a 100% InAs channel.

I. INTRODUCTION
High resolution radar systems and high data rate
communication systems greatly benefit from increased
absolute bandwidths available at millimeter-wave and submillimeter-wave frequencies. Multi-channel and multipixel applications with beam-forming features require
very compact integrated MMIC building blocks. For a
pixel pitch of half of the free-space wavelength, the
maximum dimensions at 170 GHz are less than 0.89 mm,
and at 325 GHz less than 0.46 mm respectively. Increased
bandwidth, high gain and compact circuit size are at first
opposing requirements.
Amplifiers at frequencies up to 600 GHz having more
than 20 dB gain were demonstrated since the first
introduction of 35 nm mHEMTs [1][2]. Those designs use
coplanar waveguide (CPW) transmission lines of groundto-ground spacing less than 10 m. While wafer thinning
to 50 m was used, a thickness of 25 m is preferred at

978-1-4799-3622-9/14/$31.00 2014 IEEE

II. TECHNOLOGY
The two presented amplifiers were fabricated using the
latest metamorphic HEMT technology with a gate length
of 20 nm. The heterostructure layer sequence of the
transistor device is grown by molecular beam epitaxy
(MBE) on 100 mm semi-insulating GaAs wafers
according to Fig. 1. On the bottom of the sequence, a
quartenary InxAl04.8Ga0.52-xAs (x=00.52) buffer of 1 m
thickness matches the lattice constant of the GaAs wafer
to that of InP. The transistor channel has a 100% InAs
content in contrast to work in [7]. Excessive charges are
provided by -doping above and below the channel. The
++
n -doped cap layer is mesa etched to isolate the devices.
The T-gate is defined by two different photoresist layers
patterned by e-beam direct writing. The first layer is used
to dry etch a 20 nm wide opening in a thin SiN layer. This

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Fig. 3. SEM cross section of a manu

ufactured shielded TFMS
line. The galvanic metal is omitted in th
his example.

Fig. 1. Layer sequence of the heterostruccture used for the

20 nm metamorphic HEMT.

A schematic cross section of the TF

FMS implementation is
shown in Fig. 2. The actual dimen
nsions indicated in the
schematic are motivated by the desiign of sub-THz MMICs
up to WR-1.0 (750 - 1100 GHz).
The first metallization layer (MET1) realizes a
continuous ground plane in betweeen the 0.3 m thick and
1.4 m thick BCB device encapsulations. The second
metallization layer (MET2) im
mplements the signal
conductor of a microstrip line. The
T third metallization
layer (METG), a galvanically dep
posited metal, enforces
the signal conductor where impo
ortant and reduces the
transmission line losses. In addiition, the thin ohmic
metallization layer (OHM) is used
d to distribute the gate
bias conveniently underneath the ground
g
plane, separated
from the high frequency signals.
Fig. 3 provides a SEM crosss section image of a
manufactured TFMS. The first metal (MET1) was opened
underneath the signal conductor and
a the galvanic metal
(METG) was omitted. Fig. 4 compaares simulated coplanar
waveguide (CPW) transmission liines on thinned GaAs
wafers (h = 50 m) and the TFMS transmission
t
lines. Two
different CPW lines of ground-to--ground spacing 50 m
and 20 m are added to the graph.
g
The losses are
normalized to the effective quarterr wavelength /4 of the

defines the foot of the T-gate with a lateral recess of

Next, a second
40 nm underneath the SiN layer. N
photoresist layer on top of the SiN laayer is stair-case
patterned to realize the 100 nm wide heaad of the T-gate.
Finally, a Pt/Ti/Pt/Au metal sequence iss evaporated into
the patterned preform composed of the sm
mall 20 nm wide
foot and the wider 100 nm head of the T-ggate.
The T-gate module is encapsulated byy a 0.3 m thick
layer of benzocyclobutene (BCB), an 80 nnm thick layer of
SiN and another 1.4 m thick layer of BCB
B.
An extrinsic current gain cut-off ffrequency fT of
660 GHz was extrapolated for a 2-fingeer device of gate
width 2 x 10 m. The maximum frequenncy of oscillation
fmax was estimated to be more than 1000 G
GHz. The key DC
parameters were an extrinsic transconnductance gm of
2500 mS/mm, a maximum current Id,max of 1400 mA/mm
mm, all extracted
and an output conductance gds of 200 mS/m
at a drain voltage Vds of 1 V.
III. SHIELDED THIN-FILM MICROSTR
RIP LINES
Backside processing, including wafeer thinning and
through substrate via etching, was omittted in this work.
All amplifier results were measured oon 625 m thick
wafers. This was possible thanks to thee introduction of
shielded thin-film microstrip (TFMS) traansmission lines.

Fig. 4. Estimation of transmission line

l
losses normalized to
the effective quarter wavelength off the propagation mode
(simulations only).

Fig. 2. Layer sequence of front-side sshielded thin-film

microstrip line. The first metal MET1 forms a continuous ground
plane. Second metal MET2 implements the siggnal conductor.

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Table of Contents

Fig. 5. Extracted attenuation constant of copplanar transmission

lines on GaAs and shielded TFMS linne from TRL-M
measurements up to 110 GHz.

fundamental propagating mode. Fig. 4 shows that the

wider the ground-to-ground spacing of thee CPW the lower
the losses per quarter wavelength. On thhe downside the
precision of reference planes and the exccitation of higher
order modes limits the upper operating freequencies.
The measured attenuation of the three ttransmission line
types is compared to 110 GHz in Fig. 55. The multi-line
thru-reflect-line (M-TRL) calibration methhod was used for
the parameter extraction.

Fig. 7. Chip photograph of the manufactured

2
5 x 0.9 mm .
amplifier. Size outline photograph: 1.65

D-band

Fig. 8. Chip photograph of the manufactured

2
5 x 0.5 mm .
amplifier. Size outline photograph: 1.65

H-band

t the same value of

enhancement. They were fixed to
around 10 and their individual efffect was controlled by
the length of the parallel stubs.
m
amplifier
Chip photographs of both manufactured
MMICs are shown in Fig. 7 and Fiig. 8. The circuits were
matched to the reference planes IN
N-OUT indicated in the
photograph by the arrows. An auxiiliary transmission line
section of 260 m length was ad
dded at the input and
output for measurement purposes only.
o
These access lines
are not part of the matching nettworks and they were
calibrated out by an on-wafer TRL
T
calibration in the
S-parameter measurements presenteed.
The occupied functional area of the amplifiers is
indicated by the dashed rectangularr box. The D-band and
2
H-band amplifier consume an areea of around 0.43 mm
2
respectively 0.27 mm . For the D-b
band amplifier, this is a
significant size reduction comparred to the first CPW
2
design in [7] that occupied an area of nearly 1.7 mm . The
d
from around
effective dielectric constant r,eff decreases
5.1 to 2.1 when replacing the CPW
W lines by the TFMS
approach, which in fact increases the matching networks
required line lengths. This can be compensated
c
by heavier
meandering, which is possible since the TFMS confines
t a small area. Cross
the modal electromagnetic field to
coupling to neighboring networks can
c be neglected to first
order for that reason during the eq
quivalent circuit design
phase. At H-band, meandering of matching networks is
not possible anymore except at thee input and output and

IV. CIRCUIT DESIGN AND MEASUREMEN

NT RESULTS
The circuit topology of Fig. 6 was sselected for both
amplifiers in this work. All transistors haave a gate width
of 2 x 15 m, for the D-band as well as the H-band
version. Four amplification stages weree used and their
gate and drain DC bias were provided frrom a single I/O
pad. The major matching elements are capacitively
shorted parallel stubs. R1 - R4 on the draain side introduce
losses for stabilization, gain equalizationn and bandwidth

Fig. 6. Schematic circuit diagram of lossy matching topology

used for both amplifiers at D-band and H-bannd. R1-R4 are used
for broadband matching and stabilization.

68

Table of Contents

bandwidth of 30%. The 10 dB matching bandwidth is

slightly lower at 26%.

40

S-Parameters (dB)

30
S21

20

min: 26.3 dB

V. CONCLUSION
A next generation 20 nm metamorphic HEMT
technology with a 100% InAs channel was used in
combination with thin-film microstrip lines located at the
front-side of the wafer. Four-stage amplifiers at D-band
and H-band were designed on this new technology
platform for the first time. The achieved S-parameter
results set a benchmark performance for the trade-off in
bandwidth, gain and circuit size. Further designs were
realized at WR-2.2 (330 - 500 GHz) and WR-1.5
(500 - 750 GHz) in this work and will be presented in
extended publishing formats when results are confirmed.

10
0
-10
S11

-20

S22

-30
105

115

125 135 145 155

Frequency (GHz)

165

175

Fig. 9. Measured S-parameters of the D-band amplifier. The

calibration reference plane is at the probe tips (results are not deembedded to the amplifier reference plane (in-out).

ACKNOWLEDGMENT
The presented work was conducted while the main
author was at the Stuttgart Technology Center of Sony
Deutschland GmbH. All authors would like to thank the
colleagues at Sony for their support and encouragement.

40

S-Parameters (dB)

30

S21

20

min: 24.1 dB

REFERENCES
10

[1] A. Leuther, A. Tessmann, H. Massler, R. Lsch, M.

Schlechtweg, M. Mikulla, O. Ambacher, 35 nm
Metamorphic HEMT MMIC Technology,, in 20th
International Conference on Indium Phosphide and Related
Materials (IPRM), pp. 1-4, May 2008.
[2] A. Tessmann, A. Leuther, H. Massler, M. SeelmannEggebert, A high gain 600 GHz amplifier TMIC using
35 nm metamorphic HEMT technology, in IEEE CSIC
Symposium Digest, pp. 1-4, Oct. 2012.
[3] W. Ha, Z. Griffith, D.-H. Kim, P. Chen, M. Urteaga, and B.
Brar, High Performance InP mHEMTs on GaAs Substrate
with Multiple Interconnect Layers, in 22nd International
Conference on Indium Phosphide and Related Materials,
pp. 1-4, May 2010.
[4] J. Hacker, M. Seo, A. Young, Z. Griffith, M. Urteaga, T.
Reed, and M. Rodwell, THz MMICs based on InP HBT
technology, in IEEE MTT-S Int. Microwave Symposium
Digest, pp. 11261129, May 2010.
[5] Vesna Radisic, Dennis Scott, Sujane Wang, Abdullah
Cavus, Augusto Gutierrez-Aitken, and William R. Deal,
235 GHz Amplifier Using 150 nm InP HBT High Power
Density Transistor, IEEE Microwave and Wireless
Component Letters, vol. 21, no. 6, pp. 335-337, June 2011.
[6] J. Hacker, M. Urteaga, M. Seo, A. Skalare, R. Lin, InP
HBT amplifier MMICs operating to 0.67 THz, in IEEE
MTT-S Int. Microwave Symposium Digest, pp. 1-3, June
2013.
[7] A. Leuther, S. Koch, A. Tessmann, I. Kallfass, T. Merkle,
H. Massler, R. Loesch, M. Schlechtweg, S. Saito, O.
Ambacher,
20 nm metamorphic HEMT with 660 GHz fT,
rd
in 23 International Conference on Indium Phosphide and
Related Materials (IPRM), pp. 1-4, May 2011.

0
-10

S22

-20

S11

-30
200

215

230 245 260 275

Frequency (GHz)

290

305

Fig. 10. Measured S-parameters of the H-band amplifier. The

calibration reference plane is at the amplifier reference plane (inout).

the size reduction compared to a CPW design is not

significant anymore.
The manufactured amplifiers were characterized using
on-wafer measurement probes with a pitch of 75 m at
D-band and 60 m at H-band. Both circuits were operated
at a drain voltage of Vd = 1 V and the drain current
Id = 500 mA/mm, which totals to a current of 60 mA.
At D-band, Fig. 9, an average gain of 28 dB from 115 to
175 GHz has been achieved. The minimum in-band gain is
26.3 dB. The relative bandwidth defined by a matching of
better than 10 dB and 3dB gain roll-off exceeds 40%.
At H-band, Fig. 10, a gain of better than 24 dB has been
achieved from 215 to 290 GHz corresponding to a

69

Table of Contents

A Broadband 220-320 GHz Medium Power Amplifier Module

A. Tessmann, A. Leuther, V. Hurm, H. Massler, S. Wagner, M. Kuri, M. Zink, M. Riessle, H.-P. Stulz,
M. Schlechtweg, O. Ambacher
Fraunhofer Institute for Applied Solid State Physics (IAF),
Tullastr. 72, 79108 Freiburg, Germany, axel.tessmann@iaf.fraunhofer.de
Abstract In this paper, we present the development of
an ultra-broadband H-band (220 325 GHz) submillimeterwave monolithic integrated circuit (S-MMIC) medium power
amplifier (MPA) module for use in next generation highresolution imaging systems and communication links
operating around 300 GHz. Therefore, a variety of compact
amplifier circuits has been developed by using an advanced
35 nm InAlAs/InGaAs based depletion-type metamorphic
high electron mobility transistor (mHEMT) technology in
combination with grounded coplanar waveguide (GCPW)
circuit topology. A three-stage amplifier S-MMIC based on
compact cascode devices was realized, demonstrating a
maximum gain of 22.2 dB at 294 GHz and a small-signal gain
of more than 16 dB over the frequency range from 184 to
312 GHz. Finally, mounting and packaging of the monolithic
amplifier chip into a WR-3.4 waveguide module was
accomplished with only minor reduction in circuit
performance.

active and passive imaging systems, high data rate

wireless communication links as well as ultra-wideband
transmitter and receiver components, e. g. for use in
explosive detection spectroscopy or measurement
instrumentation, can be successfully realized [1]. Several
MMICs and modules, based on InGaAs/InAlAs HEMT
technology and InP/InGaAs HBT devices have recently
been reported with operating frequencies up to 670 GHz
and even beyond [2-6].
In this paper, we report on the development of a
coplanar three-stage H-band (220-325 GHz) cascode
medium power amplifier circuit, using an advanced 35 nm
gate length metamorphic HEMT technology. The utilized
grounded coplanar waveguide technology is very
attractive at millimeter-wave and submillimeter-wave
frequencies, due to the high isolation between adjacent
lines, the low source inductance of the active devices, and
the suppression of unwanted substrate modes. For lowloss packaging of the amplifier circuits, a set of
waveguide-to-microstrip transitions has been realized on
50 m thick quartz substrates, covering the entire H-band
frequency range from 220 to 325 GHz.

Index Terms H-band, medium power amplifier (MPA),

metamorphic high electron mobility transistor (mHEMT),
microstrip-to-waveguide
transition,
packaging,
submillimeter-wave monolithic integrated circuit (S-MMIC).

I. INTRODUCTION
The millimeter-wave and submillimeter-wave frequency
range of the electro-magnetic spectrum is increasingly
addressed by safety, security, and communication
technologies. In comparison to visible and infrared
radiation, a particular benefit of millimeter- and
submillimeter-waves for imaging and sensing applications
is the penetration of dust, fog, rain, snow or even clothes.
Operating distances up to a few hundred meters are
feasible. The usable frequencies are around 94, 140, 220,
340, 670, and 850 GHz, where the transmission of the
atmosphere exhibits local maxima. The higher operating
frequency allows for precise geometrical resolution due to
high absolute bandwidth and small wavelength.
Furthermore, it reduces the size of components and
antennas, making them especially suitable for airborne
systems, such as unmanned aerial vehicles (UAVs).
Modern high electron mobility transistor (HEMT) and
heterojunction bipolar transistor (HBT) technologies have
enabled frequency conversion and even amplification up
to the submillimeter-wave frequency regime between
300 GHz and 3 THz. Based on these advanced
semiconductor devices, new types of high-resolution

978-1-4799-3622-9/14/$31.00 2014 IEEE

II. METAMORPHIC HEMT TECHNOLOGY

For the fabrication of the 35 nm gate length H-band
medium power amplifier S-MMICs, we used an
In0.52Al0.48As/In0.80Ga0.20As single channel technology.
The metamorphic HEMT structure was grown by
molecular beam epitaxy (MBE) on 100 mm semiinsulating GaAs wafers. To adapt the lattice constant, a
metamorphic buffer was grown with a linear
(x = 0 0.52)
transition
in
InxAl0.48Ga0.52-xAs
composition. The active devices consist of T-shaped
35 nm Pt-Ti-Pt-Au gates, which were defined by 100 kV
e-beam lithography and passivated with 250 nm chemical
vapor deposited (CVD) silicon nitride. The parasitic gate
capacitance was minimized by encapsulating the T-gates
with BCB offering a dielectric constant of only r = 2.65.
The measured maximum channel current Id,max is
1600 mA/mm. At Vd = 1 V, a peak transconductance of
more than 2500 mS/mm was measured. By using a high
channel indium content of 80 % an extrinsic transit
frequency of fT = 515 GHz was extrapolated from the on-

70

Table of Contents

wafer measured current gain for a 2 10 m common

source HEMT. For the same device size,, we calculated a
maximum oscillation frequency fmax oof approximately
1 THz from both, the measured Masons unilateral gain
MSG). A detailed
(MUG) and the maximum stable gain (M
description of the 35 nm mHEMT tecchnology can be
found in [7]. Due to the very compacct design of the
submillimeter-wave amplifier circuits, w
we also had to
adjust our grounded coplanar waveguuide technology.
Thus, the GCPW transmission lines w
were realized by
using the first evaporated metal only annd the ground-toground spacing was reduced to 14 m. After front side
processing, the GaAs substrates were thhinned to a final
thickness of 50 m. The via-hole diameteer at the etch stop
layer on the front side of the wafer was reeduced to 20 m,
enabling successful suppression of paarasitic substrate
modes. Furthermore, a capacitor on via-hhole process was
developed, allowing the distribution of nuumerous through
substrate vias over the entire chip area.

Fig. 2. Chip photograph of the threee-stage H-band cascode

medium power amplifier S-MMIC
C. The chip size is
2
0.5 1.35 mm .

Fig. 3. Block diagram of the three-stage H-band medium

power amplifier S-MMIC.

III. CIRCUIT DESIGN AND EXPERIMENTTAL RESULTS

ments were performed

On-wafer S-parameter measurem
using an Agilent 8510C VNA sy
ystem with an 85105A
submillimeter controller, two Oleso
on WR-3 T/R frequency
extension modules and two Picoprobe
P
Model 325
microwave probes. For an LRL-ttype calibration at the
probe tip, a modified CS-15 calibration substrate was
chosen. The on-wafer measured S-parameters of the
35 nm three-stage MPA circuit aree depicted in Fig. 4, in
the frequency range from 180 to 320
3 GHz. A maximum
gain of 22.2 dB was achieved at 294 GHz, by applying a
drain voltage of Vds = 1.8 V, a seecond gate voltage of
Vg2 = 1.05 V and a gate voltage off Vg = 0.15 V. The total
drain current at this bias point was Id = 72 mA. Between
184 and 312 GHz, we measured a small-signal gain of
more than 16 dB.

Based on the high performance 35 nm gate length

mHEMT technology, a coplanar three-stage cascode MPA
circuit was developed meeting the requireements of H-band
communication links as well as high-ressolution imaging
applications for high output power, broadband gain
characteristic and moderate consumptiion power. The
schematic diagram of a single cascode aamplifier stage is
shown in Fig. 1. The utilized transistors hhave a gate width
of 4 9 m, each.

S-Parameters [dB]

30

Fig. 1. Schematic diagram of a single 3300 GHz cascode

amplifier stage (GCPW: grounded coplanar waaveguide).

Fig. 2 shows a chip photograph of the realized H-band

medium power amplifier S-MMIC. Thhe use of space
saving grounded coplanar waveguide technology resulted
in an over-all die size of only 0.5 1.35 mm2. The block
diagram of the three-stage H-band MPA circuit is shown
in Fig. 3. In the final amplifier stagee, two compact
tandem-x couplers have been integratedd to combine the
which have been
output power of two cascode devices w
placed in parallel.

20

S21

10
0S
11
-10
-20

S22

-30
180 200 220 240 26
60 280 300 320

Frequency [GHz]

Fig. 4. On-wafer measured S-param

meters of the three-stage
cascode MPA S-MMIC [Vds = 1.8 V, Vg2 = 1.05 V, Vg = 0.15 V,
Id = 72 mA].

71

Table of Contents

S-Parameters [dB]

IV. MEDIUM POWER AMPLIFIER MODULE

For future use in high-performannce radar and

communication systems, the medium ppower amplifier
circuit was packaged in a WR-3.4 wavveguide module.
Thus, a set of H-band waveguide-to-micrrostrip transitions
has been realized on 50 m thick qquartz substrates
ensuring thickness compatibility with the S-MMIC. Fig. 5
shows a Computer-Aided Design (CAD)) drawing of the
waveguide-to-microstrip transition, whichh was optimized
to cover the entire frequency range from 220 to 325 GHz.
To couple the signal to and from thee waveguide, an
E-plane probe was realized on the quartz substrate, and
aligned to the waveguide in longitudinnal manner, i. e.
along the direction of propagation. The backside
metallization is removed on the part of thee substrate which
protrudes into the waveguide. To simulatte the transitions,
the high-frequency structure simulator H
HFSS of Ansoft
was used. The measured S-parameterrs of a quartz
transition in back-to-back configurationn are shown in
Fig. 6. We obtained an insertion loss S21 oof approximately
2.5 dB for two quartz transitions iin back-to-back
configuration, leading to an insertion looss of less than
1.2 dB for a single transition. The returrn loss S11 of the
test structure stays below 15 dB in th
the characterized
waveguide band from 220 to 320 GHz.
A close-up view of the open S-MMIC aamplifier module
is shown in Fig. 7. The gold plated brrass module was
realized in split-block configuration. The ddissection plane

0
-5
-10

S21

-15

S11

-20
-25
-30
220

240

260
280
2
300
Frequency [GHz]

320

Fig. 6. Measured insertion loss (S21) and return loss (S11) of a

50 m thick quartz H-band waveguide-to-microstrip transition in
back-to-back configuration. The lengtth of the microstrip line
between the two quartz transitions is 2 mm.
m

divides the input and output rectangular WR-3.4

o the longer side. The
waveguides along the middle line of
bond-wires for the DC and RF interconnection were
chosen as short as possible, using wedge-bonded 17 m
gold wires. The total module sizee is 30 30 20 mm3.
The measured S-parameters of th
he three-stage medium
power amplifier module are shown in Fig. 8. The WR-3.4
waveguide module achieved a smaall-signal gain of more
than 15 dB from 220 to 320 GHz and
a a maximum gain of
21.7 dB at 305 GHz.
Fig. 9 and Fig. 10 show the measured power
w
module. A
performance of the H-band waveguide
saturated output power of 4.8 dBm
d
was achieved at
300 GHz for an input power of -10
- dBm. At the same
input power, an output power of more
m
than 2.7 dBm was
obtained between 275 and 320 GHzz.
The presented results dem
monstrate that current
state-of-the-art InGaAs-based 35 nm
m metamorphic HEMT
technology enables the fabricatio
on of ultra-broadband
medium power amplifier MMIC
Cs and modules with
operational frequencies well into the submillimeter-wave
regime.

Fig. 7. Close-up view of the threee-stage H-band medium

power amplifier module.

Fig. 5. EM model of an H-band quarrtz waveguide-tomicrostrip transition (h = 50 m) including wire bond interconnection and RF signal pad.

72

Table of Contents

V. CONCLUSIONS

S-Parameters [dB]

30

S21

20

A medium power S-MMIC amplifier based on

metamorphic HEMT technology has been developed for
operation in the submillimeter-wave frequency regime
around 300 GHz. The three-stage 35 nm gate length
amplifier circuit demonstrated a small-signal gain of more
than 16 dB between 184 and 312 GHz and a maximum
gain of 22.2 dB at 294 GHz. Furthermore, packaging
solutions with excellent submillimeter-wave performance
were developed resulting in a WR-3.4 medium power
amplifier module with a small-signal of more than 15 dB
from 220 to 320 GHz and a saturated output power of
4.8 dBm at 300 GHz.

10
0
-10

S11

-20
-30
220

S22
240

260

280

300

320

Frequency [GHz]
Fig. 8. Measured S-parameters of the three-stage H-band
medium power amplifier module.

ACKNOWLEDGMENT

25
Pout

Ouput Power [dBm]

Gain [dB]

Gain
20

15

10

-5
Frequency = 300 GHz

5
-22

The authors would like to thank their colleagues from

the Fraunhofer IAF epitaxy and technology department for
excellent wafer growth and processing. This work was
funded by the German Federal Ministry of Defence
(BMVg) and the Bundeswehr Technical Center for
Information Technology and Electronics (WTD81) in the
framework of the TERATEC program.

10

-20

-18

-16

-14

-12

REFERENCES

-10
-10

[1]

Input Power [dBm]

Fig. 9. Measured gain and output power of the H-Band MPA
module as a function of input power. Measurement frequency
is 300 GHz.

[2]

[3]

Gain [dB], Pout [dBm]

20
15

Pin = -10 dBm

Gain

[4]

10

[5]

Pout

5
0

[6]

280

290

300

310

320

Frequency [GHz]

[7]

Fig. 10. Measured gain and output power of the H-Band MPA
module as a function of frequency. The input power is -10 dBm.

73

S. Sarkozy, J. Drewes, K. M. K. H. Leong, R. Lai, X. B. Mei, W.

Yoshida, M. D. Lange, J. Lee, W. R. Deal, Amplifier based
broadband pixel for sub-millimeter wave imaging, Opt. Eng.
51(9), 091602 (May 22, 2012).
http://dx.doi.org/10.1117/1.OE.51.9.091602 .
W. R. Deal, K. Leong, A. Zamora, V. Radisic, and X. B. Mei,
Recent Progress in Scaling InP HEMT TMIC Technology to
850 GHz, in IEEE MTT-S Int. Microwave Symp. Dig., June 2014.
V. Radisic, W. R. Deal, K. M. K. H. Leong, X. B. Mei,
W. Yoshida, P.-H. Liu, J. Uyeda, A. Fung, L. Samoska, T. Gaier,
and R. Lai, A 10-mW Submillimeter-Wave Solid-State PowerAmplifier Module, 2010 IEEE Transactions on Microwave Theory
and Techniques, vol. 58, no. 7, pp. 1903-1909, July 2010.
Z. Griffith, M. Urteaga, P. Rowell, R. Pierson, A 50-80 mW SSPA
from 190.8-244 GHz at 0.5 mW Pin, in IEEE MTT-S Int.
Microwave Symp. Dig., June 2014.
J. Hacker, M. Urteaga, M. Seo, A. Skalare, R. Lin, InP HBT
Amplifier MMICs Operating to 0.67 THz, in IEEE MTT-S Int.
Microwave Symp. Dig., June 2013.
A. Tessmann, A. Leuther, H. Massler, M. Seelmann-Eggebert, A
high gain 600 GHz amplifier TMIC using 35 nm metamorphic
HEMT technology, IEEE Compound Semicond. Integrated
Circuits Symp., Dig., pp. 1-4, Oct. 2012.
A. Leuther, A. Tessmann, H. Massler, R. Lsch, M. Schlechtweg,
M. Mikulla, O. Ambacher, 35 nm Metamorphic HEMT MMIC
Technology, 20th International Conference on Indium Phosphide
and Related Materials, MoA3.3, May 2008.

Table of Contents

A >200mW SSPA from 76-94GHz, with peak 28.9% PAE at 86GHz

Zach Griffith, Miguel Urteaga, Petra Rowell, Richard Pierson
Teledyne Scientific Company, 1049 Camino Dos Rios, Thousand Oaks, CA 91360
zachary.griffith@teledyne.com, 805-453-8011
Abstract A 69.5-94.0GHz solid-state power amplifier MMIC
is presented in 250nm InP HBT, where from 76-94GHz it
demonstrates >200mW Pout with simultaneous >23.5% PAE,
11dB compressed gain and 694mW PDC. At 86GHz operation,
232mW Pout with peak 28.9% PAE is observed this corresponds
to 1.21W/mm linear power density. This 2-stage amplifier has a
flat S21 mid-band gain of 14-15dB, and the 1dB small-signal gain
roll-off is between 66-96GHz. The large-signal Psat bandwidth is
between 69.5-94GHz. This SSPA utilizes a novel, compact power
cell topology developed for multi-finger HBTs, which overcomes
the inability of the RF output interconnects and combiners to
carry the high DC bias currents required by the HBT PA cells in
the thin-film microstrip interconnect. Across the 76-94GHz
bandwidth, P1dB gain compression Pout is >118mW which
corresponds to 14.5% PAE; this is a relevant RF operating
point where higher linearity operation may be required. This
work improves upon the state-of-the-art for E-, and W-Band
SSPAs by demonstrating 6 higher bandwidth (24.5GHz largesignal bandwidth) while having high PAE > 23.5%. This compact
approach can permit an additional 4 or 8 power combining
and in-turn a monolithic 1-1.5W Pout SSPA in this 250nm InP
HBT technology at E- and W-band.

PA Cell
DC Block

PA Cell

Stage-2
PA Cell

DC Block

Output

Stage-1 PA unit cell: 2 x 4-finger HBT, 8um finger Le.

Stage-2 PA unit cell: 2 x 4-finger HBT, 12um finger Le.

Fig. 1 Circuit block diagram of the 2-Stage E-band SSPA.

structures with higher isolation than achieved by GaN HEMT

using thru-substrate reactive microstrip combining.
II. MMIC POWER AMPLIFIER DESIGN
A single power amplifier (PA) cell was designed into a
250nm InP HBT technology. Peak simultaneous 400GHz ft
2
and 730GHz fmax at 1.8Vce and 8.0mA/um is demonstrated
from a 5um single-finger HBT. For the amplifier reported
here, four-finger HBT cells are used one where the unit
finger length is 8um Le (32um total) and the other is 12um Le
(48um total). Figure-2 shows for a 12um Le unit finger length
HBT the simulated ft, fmax (extrapolated from 70GHz),
MAG/MSG in common-emitter (CE) configuration, and
MAG/MSG in common-base (CB) configuration plotted at the
Vce (or Vcb) and Ic pairs along the specified PA load-line at 70
and 100GHz operation. While the CB topology offers more
gain, there were a number of challenges identified with DC
bias current distribution and ensuring stable common-base
HBT operation. For the amplifier reported here, the CE
topology is used similar four-finger devices for operation at
190-250GHz in the same technology have been reported [7].
Figure-2 permits a closer examination of the linear power
density that may be achieved by the 250nm InP HBT
technology node for a common-emitter or common-base
configured device. For the CE topology with a 12um Le finger,
the load-line shows over the following span of voltage and
current that the device maintains appreciable gain where high
output power is achieved:

I. INTRODUCTION
Rapid development of E-band and W-band
communications, radar, and imaging systems has been
facilitated by the increased operating frequency of GaN
HEMT PAs [1, 2]. The 250nm InP HBT [3] is a formidable
technology to GaN HEMT [4] in this MMIC arena; while
having lower 5V collector-emitter breakdown voltage BVCEO,
the much higher operating Je of the 250nm InP HBT yields a
PA technology having 1.2-2W/mm linear power density at
these frequencies with 23-30% power added efficiency (PAE)
[5, this work]. With the same technology node, a 220GHz
SSPA in InP HBT has demonstrated 0.87W/mm power
density at 83mW Pout [6].
Key advantages of 250nm InP HBT over GaN HEMT
include much higher peak ft and fmax, higher MAG/MSG at E-,
W-band, and the use of multiple substrate-shielded
interconnect layers separated by low-loss BCB (2.7 r). While
single-chip 1-1.5W E-, W-band PAs are not easily achievable
by InP HBT, the technology may offer at Pout ~ 0.5-1W levels
higher PA bandwidth and PAE which are critically important
parameters for continued improvement to system SWAP
and/or reduced system complexity. Higher HBT gain yields
PA stages with 8-10dB per-stage-gain, compared to 56dB/stage for GaN HEMT; this strongly impacts PA PAE, as
fewer stages will satisfy a given gain objective. Higher HBT
bandwidths, when jointly considered with the aforementioned
interconnect scheme permit compact PA cells with high
bandwidth (25-30GHz at E-, W-band). Similarly, the
interconnect scheme permits lower loss divider and combiner

978-1-4799-3622-9/14/$31.00 2014 IEEE

DC Block

Stage-1

Input

2:1 Combiner

Total Stage-1 emitter

periphery = 64um

1:2 Splitter

Total Stage-2 emitter

periphery = 192um

Pce

/8 Vc,pp (Ic,pp / Le)

(W/mm)

(1)

/8 Vc,pp (Je,ppWe)
2

/8 (4.6-0.65)V (9.0-0.7)mA/um 250nm

= 1.02 W/mm , Common-emitter configuration

74

Table of Contents

10

ce

(GHz)

Load-line current

max

350
300

12um finger length

100

Common-emitter 250nm InP HBT

3
V (V)

ce

10
4
MAG/MSG @ 100GHz

Load-line current
12um finger length

(B)

3
V (V)

Common-emitter 250nm InP HBT

MAG/MSG @ 70GHz

0.65-V , 9-mA/um
ce

Load-line current
12um finger length

'k' @ 70GHz

Common-base 250nm InP HBT

Vcb (V)

Fig. 2 Simulations to determine for a 12um Le 250nm HBT the

(plot-A) ft, fmax (extrapolated from 70GHz), (plot-B) MAG/MSG in
common-emitter configuration, and (plot-C) MAG/MSG in
common-base configuration plotted at the Vce (or Vcb) and Ic pairs
along the PA load-line at 70 and 100GHz operation.

For the CB topology with a 12um Le finger, the load-line

shows over the following span of voltage and current that the
device maintains appreciable gain where high output power is
achieved:
Pcb

-5
-10

21,mid-band

S
S

1dB BW

= 14-15dB

11

22

= 694mW

60

70

80

90

100

110

frequency (GHz)

to state-of-the-art high-gain GaN HEMT technologies an

objective for the result presented here.
For the SSPA reported here, the input of the PA cell is
matched to 50-Ohm Zo for highest small- and large-signal RF
gain. The output is matched so the collector voltage and
current traverse a class-AB load-line coincident with high
performance operation of the HBT for E-, W-band operation.
The amplifier components were simulated in Agilent ADS
using an Agilent-HBT model for the 250nm InP HBT
technology. All interconnects, transmission lines, MIM
capacitors, probe pads, and power splitters/combiners were
designed using ADS Momentum. Thin film microstrip
transmission lines (TL) are formed using the lowest
interconnect layer (MET-1) as DC and RF ground potential,
and the upper two interconnect layers (MET-2 (1um thick)
1um interlayer dielectric spacing, and MET-3 (3um thick)
7um interlayer dielectric spacing to MET-1, respectively) for
signal routing. Use of a substrate-shielding MET-1 ground
plane prevents coupling between PA cells through the 12.8-r
InP substrate. This wiring scheme also permits accurate EM
simulations for the overall PA cells which are formed very
compactly. Additional details associated with the use of this
interconnect scheme can be found in [7, 8]
To satisfy the targeted objectives of this design (>12dB
large-signal gain and >250mW Pout from 79-88GHz), a PA cell
using two 48um (4 12um) HBTs would be needed to
generate ~ 140mW Pout, such that 2:1 cell power combining
would achieve the 250mW objective. To satisfy the gain
objective as well as provide sufficient drive power to the
output stage (for Pout = Psat), two 32um (4 8um) periphery
HBTs are used for the first stage pre-driver.
To address the many challenges associated with E- and
W-band PA design using a 250nm InP HBT technology, a
novel PA cell topology has been developed to present the

50

10

(C)

DC

10

21

Fig. 3 S-parameters of the 69.5-94GHz 2-stage SSPA.

PDC
(mW)
190
504
694

MAG/MSG @ 100GHz

10

J (mA/um ), Stability factor 'k'

14
12

IC
(mA)
70.4
189.4
259.8

ce

16

VC
(V)
2.58
2.54

66-96GHz S

15

-15

Max HBT Gain (dB)

Max HBT Gain (dB)

J , load-line (mA/um )

MAG/MSG @ 70GHz

15

20

10

0.65-V , 9-mA/um

IB
(mA)
3.1
8.2
11.3

Table-1 Amplifier DC bias summary.

ce

20

Stage-1
Stage-2
Totals

VB
(V)
2.80
2.75

200
150

(A)

f,f

250

max

J , load-line (mA/um )

400

DC bias

Amplifier gains (dB)

0.65-V , 9-mA/um

500
450

/8 Vc,pp (Ic,pp / Le)

(W/mm)

(2)

/8 Vc,pp (Je,ppWe)
2

/8 (5.0-0.65)V (9.0-0.0)mA/um 250nm

= 1.22 W/mm , Common-base configuration

Based on the simple analysis shown here, the 250nm InP HBT
technology node, with appropriate and well executed design,
has the capability of demonstrating RF power densities similar

75

Table of Contents

4 x 8um L HBT cells (dashed)

250

69.5GHz

71GHz

77.5GHz (squares)

4 x 12um L HBT cells (solid)

e

21

out

11

-5

-10
-15

, mW

Amplifier gains (dB)

10

50

60

22

70

90

100

76GHz
73.5GHz

150
100
50

80

79.5GHz (circles)

200

DC

10
P , mW

= 694mW

15

20

in

110

250

frequency (GHz)

out

, mW

Fig-4. S-parameters of PA cell structures (one cell only) for the

input stage using 48um HBTs and the output driver 412um
HBTs.

large DC bias currents to the PA cells. The DC bias

distribution satisfies two key design objectives: have high
isolation ~ 50dB between PA cells along the DC bus for f >
5GHz, and avoid the DC currents traversing the RF output
lines and combiner (between the HBTs to the RF load) as
lower interconnect layers and crossovers are lossy and have
inadequate PA-cell DC current handling for Zo > 30. The
output load-match tuning includes typical series TL and shunt
capacitor tuning towards the RF load. No resistive dampening
is used along the HBT collector DC bus that would decrease
PAE. The HBT base is biased through ballasting resistors. The
total MMIC dimensions are (including DC and RF pads)
1.56mm 0.56mm.
The insertion loss of a 50-Ohm Zo transmission line
(18.5um wide for 7um BCB 2.7 r between signal and ground)
is 0.46dB/mm @ 70GHz and 0.64dB/mm @ 94GHz. A 2-way
Wilkinson divider/combiner structure is used; its insertion loss
is ~ 0.4-0.5dB from 66-94GHz. A 4-way divider/combiner
structure was designed and measured for additional PA cell
power combining for a prospective >500mW Pout, high PAE E, W-band SSPA; its insertion loss is ~ 0.90dB at 75GHz and
0.60dB at 94GHz.

86GHz
81GHz

200

83.5GHz 87.5GHz

94GHz

150
100
50

DC

10
P , mW

= 694mW

15

20

in

Fig. 5 Pout for swept Pin (0 to 20mW). The top plot contains
frequency sweeps from 69.5-79.5GHz and the bottom plot from 8194GHz.

(mW)
out

25

240
220

out

15

180
in

65
DC

Gain

P = 15mW

160

III. AMPLIFIER MEASUREMENT RESULTS

20

200

30

70

= 694mW

75

80

85

90

10
5

Gain (dB), % PAE

PAE

260

95

frequency (GHz)

Fig-6. Pout, Gain, and PAE across 69.5-94GHz swept frequency

for fixed 15mW P in.

On-wafer SSPA MMIC VNA measurements were

performed from 0.1-110GHz by an Agilent 8510XF. All
measurements were performed on the unthinned (25-mil) InP
substrate. LRRM probe-tip VNA calibration was used. The
amplifier S-parameters are shown in figure-3 at the DC bias
summarized in table-1. The mid-band S21 gain is 14-15dB,
where the 1dB gain roll-off is between 66-96GHz. The PA
cells were designed to be biased at a collector-emitter voltage
Vce of 3.0V; however, a lower voltage was required as the
MMIC design does not have sufficient ballasting to avoid
thermal runaway destruction at Vce > 2.75V at the design DC
bias currents. Figure-4 shows the S-parameters of PA cell
evaluation structures (one cell only) for the input stage using
48um HBTs and the output driver using 412um HBTs
these measurements match simulation closely. Because the

output impedance of the input stage is load matched for

maximum stage-1 Pout, combined with the use of the 2:1
divider/combiner structures, the broadening of the gain
characteristics for the 2-stage MMIC was expected.
The large-signal measurements are presented in many
forms across figures 5, 6, and 7. Figure-5 shows the output
power Pout for swept input power Pin from 69.5-94GHz,
presented in linear form. From 76-94GHz, Pout is > 200mW
with simultaneously > 23.5% PAE, where at 86GHz 232mW
Pout with 28.9% PAE is observed this corresponds to
1.21W/mm linear power density, which includes the loss from
the combiner and DC output blocking capacitor. For all
measurements, PAE is determined using the higher PDC
76

25
20
P

10

= 200.3mW

sat

PAE

1dB

out

-4

DC

-2

sat

out

PAE
1dB

-4

= 235.7mW

-2

= 694mW

25

10 12

Gain

10

sat

= 202.1mW

PAE

1dB

-4

-2

= 694mW

Pin (dBm)

Approved for Public Release, Distribution Unlimited.

30
25
20
15
10
5
0

30
25
20
15
10
5
0

IV. REFERENCES
[1] M. Micovic, A. Kurdoghlian, A. Margomenos, D.F. Brown, K.
Shinohara, S. Burnham, I. Milosavljevic, R. Bowen, A.J.
Williams, P. Hashimoto, R. Grabar, C. Butler, A. Schmitz, P.J.
Willadsen, D.H. Chow, 92-96GHz GaN Power Amplifiers,
Proc. IEEE MTT International Microwave Symposium,
Montreal, Quebec, June 17-22, 2012.
[2] A. Brown, Ken Brown, James Chen, K.C. Hwang, N. Kolias, R.
Scott, W-Band GaN Power Amplifier MMICs, Proc. IEEE
MTT Int. Microwave Symposium, Baltimore, MD, June 5-10,
2011.
[3] M. Urteaga, M. Seo, J. Hacker, Z. Griffith, A. Young, R.
Pierson, P. Rowell, A. Skalare, M. Rodwell, InP HBT
Integrated Circuit Technology for Terahertz Frequencies, Proc.
IEEE Compound Semiconductor IC Symposium, La Jolla, CA,
Oct. 14-17, 2012.
[4] K. Shinohara, D. Regan, Y. Tang, A. Corrion, D. Brown, J.
Wong, J. Robinson, H. Fung, A. Schmitz, T. Oh, S-J. Kim, P.
Chen, R. Nagele, A. Margomenos, M. Micovic, Scaling of Gan
HEMTs and Schottky Diodes for Submillimeter-Wave MMIC
Applications, IEEE Transactions on Electron Devices, Vol. 60,
No. 10, Oct. 2013.
[5] H. Park, S. Daneshgar, J. Rode, Z. Griffith, M. Urteaga, B. Kim,
M. Rodwell, 30% PAE W-band InP Power Amplifiers using
Sub-Quarter-Wavelength Baluns for Series-connected Powercombining, Proc. IEEE Compound Semiconductor IC
Symposium, Monterey, CA, Oct. 13-16, 2013.
[6] Z. Griffith, M. Urteaga, P. Rowell, R. Pierson, A 50-80mW
SSPA from 190.8-244GHz at 0.5mW P in, Proc. IEEE MTT Int.
Microwave Symposium, Tampa, FL, June 1-6, 2014.
[7] Z. Griffith, M. Urteaga, P. Rowell, R. Pierson, Multi-finger
250nm InP HBTs for 220GHz mm-Wave Power, Proc. Indium
Phosphide and Related Materials Conference, Santa Barbara,
CA, Aug. 26-30, 2012.
[8] Z. Griffith. M. Urteaga, P. Rowell, R. Pierson, A 227.5GHz
InP HBT SSPA with 101mW Pout at 14dB Compressed Gain and
4.04%, Proc. IEEE Compound Semiconductor IC Symposium,
Monterey, CA, Oct. 13-16, 2013.

86GHz

out

15

out

@ 162mW

20

Pin (dBm)

This work was supported by the DARPA Mobile

HotSpots program, contract FA8750-12-C-0279. The views
expressed are those of the authors and do not reflect the
official policy or position of the Defense Advanced Research
Projects Agency or the Department of Defense. The authors
thank Program Manager Dr. Richard Ridgeway of DARPA
and Dr. Bobby Brar of Teledyne Scientific for their support of
this work. The authors also acknowledge and thank the
Teledyne Scientific Fabrication Operations team for
fabrication of this MMIC.

76GHz

DC

10 12

Gain

10

out

15

20

DC

Pin (dBm)

ACKNOWLEDGEMENTS

% PAE

25

= 694mW

@ 121mW

30
25
20
15
10
5
0

% PAE

(dBm), Gain (dB)

Gain

out

15

(dBm), Gain (dB)

% PAE

(dBm), Gain (dB)

Table of Contents

@ 118mW

10 12
94GHz

Fig. 7 Pout, Gain, and PAE for swept Pin at 76, 86, and 94GHz. The
Pout at 1dB gain compression and Psat is listed.

observed at a given RF Pout. Loss de-embedding below 75GHz

is challenging due to the insertion loss variation of the WR10
input and output wafer probes; because of this, the 73.5GHz
data and below may have as much as 10% discrepancy
between the Pout reported versus the real value. Nevertheless,
the measured data here at 69.5 and 71GHz shows >235mW
Pout and with simultaneously >28% PAE. Figure-6 reports at
15mW Pin the PA Pout, Gain, and PAE; this is done to show the
flatness of these values across the 18-24.5GHz of large-signal
bandwidth. Figure-7 presents at 76, 86, and 94GHz the Pout,
Gain, and PAE for swept Pin. Across the 76-94GHz
bandwidth, the P1dB gain compression Pout is 118mW which
corresponds to a PAE 14.5% -- a relevant RF operating
point where higher linearity may be required of the PA.

77

Table of Contents

Lin
near Opttical Moddulator ffor
DAC-baased Coh
herent Fiber
F
Com
mmunications Systems
Hiro
oshi Yamazaaki
NTT
N Photoniics Laborato
ories, NTT Corporation,
C
A
Atsugi, Kannagawa, 243--0198, Japann
Ph
hone: +81-46
6-240-2893,eemail: yamazzaki.hiroshi@lab.ntt.co.jjp
Abstract This

paper reviews our recentt study on a lineear

optical modulator (LOM). Th
he LOM has a highly linear fieeld
response, wh
hich is suitable for digital coherent optical
communicatio
ons systems where adva
anced multilevel
transmission signals are gen
nerated in the electrical doma
ain
using high-speeed digital-to-an
nalog converterrs (DACs). A tw
wostage lattice optical
o
configurration enables us to compensa
ate
for the nonlin
nearity (sinusoidal nature) of the response of a
modulator (M
conventional Mach-Zehnder
M
MZM), which is an
obstacle to ach
hieving low-losss and low-distorrtion electro-op
ptic
conversion off the multilev
vel signals. We
W experimenta
ally
proved that the LOM has an
a advantage over
o
the MZM in
terms of the trade-off betw
ween the linearrity and intrin
nsic
optical-power loss.
Index Term
ms Electroo
optic modulato
ors, optical fib
ber
communicatio
on, optical tran
nsmitters, quad
drature amplitu
ude
modulation.

modulaators (MZMs), which corresppond to in-phasse (I) and

quadratture (Q) compponents of the two orthogonaal optical
polarizaations, respecttively. Each M
MZM is driven with a
multileevel signal ggenerated by a DAC. W
With this
configuuration, we caan flexibly usse various moodulation
formatss and pulse shaapes.
A maajor constraintt with this DAC
C-based approoach used
to be thhe sampling ratte of the DACs, which has drrastically
improvved in recent yyears [2, 4]. A
Another probleem is the
nonlineear (sinusoidaal) response of an MZM, which,
though rather preferaable in binary-ddriven systemss because
of its cclipping-like (rrectification) efffect [5], is ann obstacle
in the D
DAC-based syystems as show
wn in Fig.1. Drriving an
MZM with a multileevel signal in a full-swing ccondition
(2V ppeak-to-peak, where V iss the half-waavelength
voltagee of the MZM
M) results in ddistortion in thhe output
optical signal (Fig. 1b). A comm
mon way to avvoid this
distortiion is to reducee the swing volltage and use tthe quasilinear rregion of the ssinusoidal respponse, but this causes a
large ooptical loss (Fiig. 1c). Arcsinne pre-distortioon in the
digital domain may aalso be a solution, but this redduces the
effectivve resolution of the DAC (Fig. 1d). A desirable
solutionn is a modulatoor with linear field response. Various
modulaators with a linear powerr response haave been
studiedd for use in anaalog optical traansmission sysstems [68], but those with a linear field reesponse have not been
exploreed.
This paper reviewss our recent sttudy on a lineaar optical
modulaator (LOM) [99]. We deviseed a two-stagge lattice

I. INTR
RODUCTION
Advanced digital
d
coheren
nt optical fiber communicatio
ons
technologies rely greatly on
o high-speed digital-to-anallog
DACs). Applicaations of the DACs
D
in the fieeld
converters (D
of fiber comm
munications in
nclude high-biit-rate high-ord
der
quadrature am
mplitude modu
ulation (QAM
M), pulse shapiing
for achieving
g high spectraal efficiency (SE) and/or hiigh
nonlinear tollerance, and flexible
fl
utilizattion of differeent
modulation fo
ormats [1-3]. In
I a typical DA
AC-based opticcal
transmitter, an optical du
ual-polarizatio
on in-phase-an
ndquadrature (D
DP-IQ) modulator and four DACs are useed.
The DP-IQ modulator co
onsists of fourr Mach-Zehnd
der

Fig. 1. (a) Co
onfiguration of a typical DAC-b
based transmitterr. (b - d) Responnses of the conveentional sub-MZ
ZM driven by muultilevel
signals with (b) large swing voltage, (b) smaall swing voltagee, and (c) arcsinee pre-distortion.

978-1-4799-3622-9/14/$31.00 2014 IEEE

78

Table of Contents

optical config
guration, in which
w
a princip
ple analogous to
the synthesis of a sawtooth
h waveform is used to obtain
na
ve with high liinearity. We faabricated a lineear
response curv
IQ modulatorr (LIQM), in which
w
two LOM
Ms are connectted
in parallel, using
u
a hybrid configuration
n of silica plan
nar
lightwave cirrcuits (PLCs) and
a an LiNbO3 (LN) chip with
w
an array of hiigh-speed straig
ght phase mod
dulators [10]. The
T
linearity of the
t response of
o the LOM was
w evaluated by
driving it with
h a sinusoidal signal and anaalyzing the outp
put
optical signall spectra. The results
r
show th
hat the LOM has
h
an advantagee over the conv
ventional MZM
M in terms of the
t
trade-off betw
ween linearity and
a intrinsic op
ptical-power lo
oss.
With the LIIQM, 16QAM
M signal geneeration was allso
demonstrated
d.

Fig. 2..Optical circuit ddiagram of the L

LOM.

Optical field

+1

II. PRINCIPLE
R

r sin(2 ) 2

Eout

-1

The opticall circuit diagram of the LOM

M is shown in Fig.
F
2. The modu
ulator has a tw
wo-stage latticce configuratio
on.
The first stag
ge is a standard
d MZM with dual
d
output, fro
om
which two co
omplementary optical signalss are output. The
T
second stage has another MZM embedd
ded in one arrm,
while the oth
her arm is justt a passive waveguide, and the
t
two arms aree connected to an asymmetriic coupler with
ha
power coupliing ratio of r:1
1-r. The two MZMs
M
are driv
ven
with a pair off complementarry voltage sign
nals, V and -V,, in
a push-pull co
ondition. The first
f
MZM is biased
b
so that the
t
output signaals from the upper and lower
l
ports are
a
expressed ass cos() and
d sin(), resp
pectively, wheere
=V/(2V) and V is the half-wavelength voltage of the
t
i MZM. The seecond MZM iss biased so thatt its response is
sin(). The output
o
from th
he asymmetricc coupler, Eout, is
expressed as

=0.12
r=

1 r sinn( )
= /(2V)*V

-V

0
Voltage, V

+V

Fig. 33. Response currves of the LO

OM.
intrinsiic optical loss at the peaks ((V=V) is eexpressed
as

r

sin ( )
Loss dB (r , ) = 20 log 1 r sin
2
2

[dB ] (2)

To qquantify the llinearity, we use the spurrious-free

dynamiic range (SFD
DR). We cann obtain an aanalytical
expresssion of the SFD
DR by setting V= Vsin(
t) in Eq.
(1) andd dividing thee squared Fouurier coefficiennt of the
fundam
mental term byy that of the strongest highher-order
term, nnamely,

r

J 1 ( )
SFDRdBB (r , ) = 20 log 1 r J 1
2 2

r
(1)
sin (2 )
2
No imaginaary term is foun
nd in Eq. (1), which
w
means th
hat,
in principle, the LOM opeerates withoutt causing opticcal
hirp. The resp
ponse curve off the LOM (E
Eout
frequency ch
plotted against V) when r=
=0.12 is shown
n in Fig. 3 with
ha
d second terms of the right siide
red solid linee. The first and
of Eq. (1) arre also plotted against V witth a blue dash
hed
and a green dotted line, respectively.
r
Since
S
the seco
ond
onlinearity of the
t first term, Eout
term compensates for the no
t range of -V
- V+V. The
T
has good linearity within the
upling ratio r depends on the
t
optimum vallue of the cou
modulation in
ndex , which is the swing vo
oltage divided by
2V. The r off 0.12 is the op
ptimized valuee for =1.0 (2V
Vpeak-to-peak swing). To make
m
a fair com
mparison betweeen
d the conventio
onal MZM, wee should consid
der
the LOM and
the trade-off between the optical
o
loss an
nd linearity. The
T
E out = 1 r sin ( )

r

J 2 n+1 ( )
20 log MAX 1 r J 2 n+1
n
2 2

(3)

[dB]

wherre Jm is the Beessel function oof the first kinnd. When

r<0.2 aand 1, whicch covers moost practical cases, the
maximuum in the dennominator is ggiven for 2n+11=3 or 5.
When =1.0, the loss and SFDR w
with the LOM (r=0.12)
are 0.66 and 36.8 dB
B, respectively, while those with the
MZM aare 0 and 18.3 dB, respectiveely. In other w
words, the
LOM ooffers the SFD
DR gain of 18.5 dB at the coost of the
optical transmittancee of 0.6 dB w
when =1. Thiis loss is
reasonaably small; witth the MZM, tthe SFDR of 36.8 dB is
obtaineed with =0.377, which resultts in the loss of 5.2 dB.
The traade-off plots bbetween the looss and SFDR for both
modulaators are shoown in Secction IV witth some
experim
mental results.

79

Table of Contents

field am
mplitude, whicch is obtained aas the square-rooot of the
data obbtained with thhe oscilloscope, while the hhorizontal
axis is the voltage off the triangularr wave normaliized with
the me asured V at 1150 Hz. Whenn r=0, which reepresents
ZM, the responnse shows an absolutethe connventional MZ
sine cuurve, as expectted. On the othher hand, whenn r=0.12,
the respponse is almosst linear.

III. FABRICATTED MODULATO

OR
To prove th
he concept, wee fabricated an
n LIQM with the
t
circuit config
guration show
wn in Fig. 4(aa). Two LOM
Ms,
LOM-I and Q, are connected in paraallel with phaase
ve a relative op
ptical phase off /2 between the
t
shifters to giv
two arms. We
W added a tesst port in each
h arm so that we
w
could check the stand-alon
ne performancee of each LOM
M.
To fabricate the modulatorr, we used a hybrid integratiion
d an LN chip
p [10], which is a promisiing
of PLCs and
technology for
fo fabricating various advan
nced modulato
ors.
As shown in
n Fig. 4(b), we
w used an LN
N chip with fo
our
push-pull paiirs of simple sttraight phase modulators
m
and
da
couple of passive straight waveguides. All
A other passiive
a fabricated in the PLCs. We
W used variab
ble
components are
couplers as th
he 3-dB coupleers and the asym
mmetric coupleers
at the outputss of the first an
nd second stag
ge of each LOM
M.
We employeed a U-turn layout to maake the modu
ule
compact. Thee total length of
o the hybrid chip is 127 mm.
m
The insertion
n loss of the faabricated LIQM
M is <8 dB ov
ver
the C and L bands. The 3--dB bandwidth
hs of the electrroncy responses are
a around 23 GHz
G for the fo
our
optic frequen
MZMs in the two LMs.
(a)

Fig. 5.. Measured low--frequency absollute-field-amplittude

responnses of the MZM
M and LOM.

Wee measured thee SFDR of the response of L

LOM-I by
drivingg it with a 12.5-GHz ssinusoidal siggnal and
measurring the opticaal-signal specttra of output from the
test-I pport, which aree shown in Figg. 6.The horizoontal axes
are thee relative frequuency with resspect to the innput CWDRs for the M
MZM and
light frrequency. The measured SFD
LOM aare 18.5 and 377.2 dB, respecttively, which aggree well
with tthe theoreticaal values of 18.3 and 336.8 dB,
respecttively.

LOM-I
Test-I

In

Out

LOM-Q

/2 phase ad
djuster

Normalized power, dB

Test-Q
Variable cou
upler

0
-10
-20

Peak order:0

MZM
M
=1
r=0

5 ...

18.5 dB

-30
-40
-50
-60
-70
-75

50
-5

-25

25

50

75

Relative frequency, GHz

Normalized power, dB

Fig. 4. (a) Cirrcuit diagram and (b) configuratiion of the

fabricated LIQ
QM.
MENTAL RESULT
TS
IV. EXPERIM

absolute-fieldFig. 5 shows
s
the low-frequency
l
amplitude ressponse of the LOM. The datta were obtain
ned
by driving th
he RF electro
odes with a 15
50-Hz triangu
ular
wave and recceiving the outtput from the test port with an
OE converterr followed by a digital osciilloscope. Fig.. 4
shows the ressults. The vertiical axis is thee absolute opticcal

0
-10
-20

Peak order:0

LOM
M
=1
0
r = 0.12

5 ...

37.2 dB

-30
-40
-50
-60
-70
-75

50
-5

-25

25

50

75

Re
elative frequen
ncy, GHz
Fig. 6. Optical signal sppectra of MZM and LOM drivenn with a
Hz 2V .-peak-too-peak.
12.5-GH

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Intrinsic opitcal
p
loss,, dB

The trade-off between the

t SFDR and intrinsic opticcalpower loss att the peaks (V=
=V) is shown in Fig.7. The
T
measured ressults, which agree well with
h the theoreticcal
curves, provee that the LO
OM outperform
ms the MZM in
terms of the trade-off.
t
Practtically, the insertion loss of the
t
LOM may bee larger by 2~3 dB than that of
o a simple MZ
ZM
because of th
he propagation loss in the seccond stage of the
t
lattice, but we
w still have an
n effective gaiin of 2.5~3.5 dB
d
for the SFDR
R of around 40 dB.
8
7
6
5
4
3
2
1
0
10

V. CONCLUSIO
ON
In fuuture DAC-based multilevel ooptical transmiitters, the
linearitty of the electtro-optic convversion will bee of key
importaance. The LOM
M, which provvides a clear aadvantage
over thhe conventionnal MZM in tterms of the trade-off
betweeen the linearity of the field ressponse and thee intrinsic
optical loss, will be a promising soluution.
REFERENCESS

MZM (me
eas.)
MZM (callc.)
LOM (me
eas.)
LOM (calc.)

20

30

40

50

[1] T. Kobayashi, A. S
Sano, A. Matsuuura, Y. Miyamoto, and K.
Tolerantt
Spectrallyy-Efficient
Ishhihara,Nonlineaar
TraansmissionUsingg PDM 64-QA
AM Single Carrrier FDM
WiithDigital Pilot-T
Tone, J. Lightw
w. Technol.,vol. 30,no. 24,
pp.. 3805-3815, Deecember 2012.
[2] S. Randel, D. P
Pilori, S. Cortteselli, G. Raaybon, A.
Addamiecki, A. Gnnauck, S. Chandrasekhar, P. W
Winzer, L.
Alttenhain, A. Biielik, and R. Schmid, All-E
Electronic
Fleexibly Programm
mable 864-Gb/s Single-Carrier PDM-64QA
AM, Proc. Oppt. Fiber Comm
mun. Conf. (OF
FC), paper
Th55C.8, March 2014.
[3] O. Gerstel, M. Jinnno, A. Lord, aand S. J. B. Yooo, Elastic
Opptical Networkinng:
A New
w Dawn for thhe Optical
Layyer?, IEEE Com
mmun. Mag., voll. 50, issue. 2, ppp. s12-s20,
Febbruary 2012.
[4] N. N
Nagatani, H. Noosaka, K. Sano, K
K. Murata, K. K
Kurashima,
andd M. Ida,A 660-GS/s 6-Bit D
DAC in 0.5-im InP HBT
tecchnology for opptical communiications system
ms, Proc.
IEE
EE Compound SemiconductorIIntegrated Circcuit Symp.
(CSSICS), paper G.33, October 2011.
[5] N. Kikuchi, Inteersymbol interfe
ference (ISI) suuppression
tecchnique for ooptical binary and multileveel signal
genneration,J. Lighhtw. Technol., vvol. 25,no. 8, ppp. 2060
20668, August 20077.
[6] T. Kishino, R. F. T
Tavlykaev, and R
R. V. Ramaswam
my, "A YCoupler Modulattor with a Highhly Linear
Fedd Directional C
Traansfer Curve," P
Photon. Technoll. Lett.,vol. 12, pp. 147414776, November 22000.
[7] S. Li, X. Zheng, H
H. Zhang, and B. Zhou, "Highhly Linear
Rad
adio-Over-Fiber System Incorpporating a Sinngle-Drive
Duual-Parallel MachhZehnder Moddulator," Photonn. Technol.
Lettt., vol. 22, pp. 11175-1177, Deceember 2010.
[8] B. Dingel, N. Madamopoulos,, A. Prescod, and R.
Maadabhushi, "An alytical model, analysis and parameter
opttimization of a super linear electro-optic m
modulator
(SF
FDR>130 dB)," Opt. Commun.,, vol. 284, pp. 5578-5587,
Deecember 2011.
[9] H. Yamazaki, H. Takahashi, T. Goh, Y. Hashhizume, S.
Miino, and Y. Miyyamoto, Linear Optical IQ Moodulatorfor
Higgh-Order Multillevel Coherent T
Transmission,P
Proc. Opt.
Fibber Commun. Coonf. (OFC), papeer OM3C.1, Marrch 2013.
[10] K. Tsuzuki, T. Saaida, M. Ishii, T
T. Goh, H. Yam
mazaki, Y.
Dooi, A. Aratake,T
T. Fukumitsu, M
M. Tamura, and S. Mino,
D
Design and evalluation of highhlyreliable silicaa-LiNbO3
hybbrid modulatorss for advanced fformats,Proc. O
Opt. Fiber
Coommun. Conf. (O
OFC), paper OM3J.5, March 20112.

60

S
SFDR,
dB
Fig. 7. Measu
ured and calculatted trade-off betw
ween SFDR and
d
intrinsic opticcal loss..

We also tested the LIQ

QM for 12.5-Gbaud 16-QA
AM
i a back-to-b
back setup. Each
E
LOM was
w
modulation in
driven with a four-level eleectronic signall with a peak-ttopeak voltage of ~1.8 V (
~0.9). The ou
utput signal was
w
u
self-hom
modyne coheren
nt detection with
w
analyzed by using
a sampling rate
r
of 50 GS
S/s followed by
b offline sign
nal
processing. Obtained
O
consstellations are shown in Fig
gs.
8(a) and (b), which represeent the data forr the MZM (r=
=0)
=0.11), respectiively. While th
he MZM shows a
and LOM (r=
constellation with the inneer symbols dissplaced outwaard,
ows an equally
y spaced consteellation. Residu
ual
the LOM sho
distortions arre attributed to
o the imperfect fabrication and
a
adjustment.

Fig. 8. 16QAM
M constellation for the (a) MZM
M and (b) LOM.

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A Compact Low-Power 224-Gb/s DP-16QAM

Modulator Module with InP-based Modulator and
Linear Driver ICs
Naoki Itabashi, Taizo Tatsumi, Tomoko Ikagawa, Naoya Kono, Morihiro Seki, Keiji Tanaka, Kazuhiro Yamaji,
Yasushi Fujimura, Katsumi Uesaka, Takashi Nakabayashi, Hajime Shoji and Shoichi Ogita
Transmission Devices R & D Laboratories
Sumitomo Electric Industries, Ltd.
1, Taya-cho, Sakae-ku, Yokohama, 244-8588, Japan
itabashi-naoki@sei.co.jp
In this paper, we review the recent activity of our compact
and low-power DP-16QAM modulator module including all of
InP-based dual I/Q modulator, differential linear driver ICs
with frequency peaking to compensate RF losses, and
polarization multiplexing micro-optics [6]. The newly designed
linear driver IC that is suitable for the multilevel modulation
format is presented in detail. The small module package size of
34.0 mm 16.5 mm 6.0 mm is realized using this new linear
driver IC. The total power dissipation of the modulator module
including four ICs and the thermoelectric cooler (TEC) is as
low as 3.2 W. A 224-Gb/s DP-16QAM modulation at a
differential driving voltage of 2.5Vpp, which is corresponding
to 1.0 V, is demonstrated. Finally, we verify that this module
has compatible BER performance with the commercially
available LiNbO3-based modulator in back-to-back operation.

AbstractWe have fabricated a compact 224-Gb/s dualpolarization 16-ary quadrature amplitude modulation (DP16QAM) modulator module consisting of InP-based MachZehnder modulators (MZMs), linear driver ICs and polarization
multiplexing micro-optics. We have demonstrated a very low
power dissipation of 3.2 W with comparable performance to
LiNbO3-based modulator in back-to-back operation.
KeywordsDistributed amplifiers, Double heterojunction
bipolar transistor, Electrooptic modulators, Quadrature amplitude
modulation

I. INTRODUCTION
Digital coherent technology with multilevel modulation
format has attracted much interest because of its possibility for
ultrahigh speed and ultra-long haul optical communication.
Recently the first commercial service using 100-Gb/s digital
coherent technology has been released. In the next generation
of the digital coherent technology, the application field will be
extended to metro systems which require much more port
density and larger transmission capacity per single port.
Therefore, compact and low-power optical components must
be developed [1]. We demonstrated the 128-Gb/s dualpolarization quadrature phase shift keying (DP-QPSK)
modulator module with the InP-based modulator and limiting
driver ICs [2], and showed the reduction of the module
package size and the power dissipation in comparison with the
conventional LiNbO3-based modulators. Additionally, the
driver ICs provided high speed differential signals with lower
power to InP-based modulator thanks to low RF losses between
drivers and the modulator and the limiting operation of the
driver. However, the modulator module could deal with only
the QPSK modulation format because the limiting driver IC
could not operate linearly.

II. DESIGN AND CHARACTERISTICS OF DIFFERENTIAL LINEAR

DRIVER IC
To realize DP-16QAM modulation, we newly develop the
linear driver IC which can achieve both low power
consumption and reduced assembly area. The driver IC is
fabricated with an InP double heterojunction bipolar transistor
technology with a maximum cut-off frequency (ft) of 150 GHz
and a maximum oscillation frequency (fmax) of 200 GHz. Fig.
1 shows a block diagram of the driver IC. Here, we adopt a
traveling wave amplifier (TWA) which is also included in the
limiting driver IC previously developed [2] to achieve the highspeed operation and low return losses [7]. The TWA stage

The dual-polarization 16-ary quadrature amplitude

modulation (DP-16QAM) is promising technology for 100Gb/s metro application and beyond because of its possibility to
increase transmission capacity resulting in the reduction of
power consumption per single port. 200-Gb/s-class DP16QAM transmission characteristics were already reported
using LiNbO3-based modulator [3, 4]. On the other hand, in
regard to the system using InP-based modulator, 256-Gb/s DP16QAM demonstration using a commercially available 43Gb/s DQPSK tunable transmitter assembly was reported [5].

Fig. 1.

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Block diagram of the differential linear driver IC.

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losses due to transmission lines and connecting wires in the

module. Fig. 2 (b) shows the total harmonic distortion (THD)
as a function of the differential output voltage. THD remains
below 3% even at the 2.5 Vpp differential output. Fig. 2 (c)
shows an electrical output eye diagram with 28-Gbaud/s 4level amplitude modulation. In this case, the differential input
voltage swing is 650 mVpp which can be supplied by the
digital-to-analog converter (DAC) directly [8]. The differential
output voltage swing is 2.5 Vpp. Clear 4-level eye openings are
observed. These results indicate that this linear driver IC has
desirable characteristics for 28-Gbaud/s multilevel modulation.

consists of 6 distributed linear amplifier unit cells, coplanar

lines, and differential 90- output termination. Comparing
with the limiting driver IC employing two-stage amplifier
configuration, this linear driver IC consists of only single TWA
stage in order to achieve both the high linearity and the low
power dissipation. Additionally, to further improve the
linearity and compensate RF losses due to module components,
we optimize emitter degeneration resistors and frequencydependent RC filters in unit cells. The typical differential
output voltage swing of the driver IC is 2.5 Vpp which
corresponds to 1.0 V of the Mach-Zehnder modulators
(MZMs) previously reported [2]. Although this driving voltage
of 1.0 V decreases the peak optical output power by 3 dB
compared with 2.0 V, this under-drive modulation can save
the power consumption of the ICs, eliminate inductors for DC
biasing and reduce a nonlinear distortion of a sinusoidal optical
field response of the MZM. The chip size of the IC is 1.1 2.1
mm2, and total assembly area for four ICs is only 9.0 2.1
mm2 thanks to the inductor-less design.

III. MODULE PERFORMANCE

Fig. 3 shows a block diagram and a photograph of the
fabricated module. The module includes an InP-based dual I/Q
modulator chip, polarization multiplexing micro-optics, a TEC
and four differential linear driver ICs mentioned above. The
dual I/Q modulator chip was already reported [2], which
contains four MZMs. The MZMs have 3-mm modulator
section and the differential characteristic impedance of the
modulator section is designed to be 90 . Under the reverse
bias condition, the V of the MZMs can decrease to 2.5 V and
less.

Fig. 2 (a) shows measured s-parameter. Both Sdd11 and

Sdd22 are below -10 dB up to 50 GHz. A 3-dB cut off
frequency of Sdd21 reaches 45 GHz. Sdd21 have a gradual
peaking from 3 GHz to 28 GHz which can compensate RF
(a)

(b)

(c)

0.4V/div
Fig. 2.
Measurement results of the linear driver IC. (a) S-parameter. In these results, the output port impedance is converted into differential 90 . (b)
THD at 1 GHz sinusoidal wave input. The differential output voltage is converted by differential 90- load resistance. (c) Electrical output eye diagram of
NRZ 4-level pulse-amplitude modulation at bit rate of 28-Gbaud/s and PRBS 223-1.

Fig. 3.

DP-16QAM optical modulator module : (a) Block diagram and (b) photograph.

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Fig. 4.

Measured small signal frequency response of the DP-16QAM module.

Fig. 5 shows experimental results of single polarization

(SP)-16QAM operation for both 14-Gbaud/s and 28-Gbaud/s.
Fig. 5 (a) and (b) show the bit error ratio (BER) as a function
of optical signal-to-noise ratio (OSNR). In this experimental
setup, tunable lasers with linewidth of about 500 kHz are used
for both transmitter and receiver. A 50-Gsamples/s
oscilloscope is used to digitize the coherent receiver electrical

Fig. 4 shows the measured small-signal E/O response and

the differential input return loss (Sdd11) of each channel of
modulators. There are two dips around 17.5 GHz and 21 GHz
due to mismatch losses in RF input interfaces, resulting in
relatively high Sdd11 of about -5 dB. Ignoring these mismatch
losses, a 3-dB cut-off frequency of this module is around 20
GHz.

Fig. 5.

Experimental results of SP-16QAM operation. (a) 14-Gbaud/s BER vs. OSNR. (b) 28-Gbaud/s BER vs. OSNR.
(c) Constellation of 14-Gbaud/s at OSNR 22 dB. (d) Constellation of 28-Gbaud/s at OSNR 30 dB.

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output. Results of commercially available LiNbO3-based dual

I/Q optical modulator (a 3-dB bandwidth is over 22 GHz) in
the same experimental setup and theory lines [9] are also
plotted for a comparison. In these results, the difference
between this work and LiNbO3-based modulator is negligibly
small. At 10-3 of BER curves, the results of this work are
within 2.8 dB for 14-Gbaud/s and 5.6 dB for 28-Gbaud/s from
theoretically expected values. Fig. 5 (c) and (d) show the
sample recovered 16QAM constellations of this work.

[2]

We also evaluate the power dissipation of this module over

specified case temperature range from -5 C to 75 C. Over the
whole temperature range, the total power dissipation is lower
than 3.2 W, in which 2.4 W for the four driver ICs and 0.8 W
for the TEC.

[5]

[3]
[4]

[6]

IV. CONCLUSION
We have presented the newly developed small-sized, lowpower linear driver IC and have demonstrated its excellent
electrical performance, which is desirable for the multilevel
modulation. A compact and low-power DP-16QAM modulator
module including four linear driver ICs has been successfully
realized. The optimized linear driver IC for the modulator
module contributes to a comparable 224-Gb/s DP-16QAM
modulation performance with the conventional LiNbO3-based
modulator.

[7]

[8]
[9]

REFERENCES
[1]

W. Forysiak, Progress in InP-based Photonic Components and

Sub-systems for Digital Coherent Systems at 100Gbit/s and
beyond, ECOC13, Mo.3.C.2, 2013.

85

85

N. Kono, T. Kitamura, H. Yagi, N. Itabashi, T. Tatsumi, Y.

Yamauchi, K. Fujii, K. Horino, S. Yamanaka, K. Tanaka, K.
Yamaji, C. Fukuda, and H Shoji, Compact and Low Power DPQPSK Modulator Module with InP-Based Modulator and Driver
ICs, OFC/NFOEC 2013, OW1G.2.
X. Zhou, and J. Yu, 200-Gb/s PDM-16QAM generation using a
new synthesizing method, ECOC2009, Paper 10.3.5, 2009.
A. H. Gnauck, P. J. Winzer, S. Chandrasekhar, X. Liu, B. Zhu,
and D. W. Peckham, 10 224-Gb/s WDM Transmission of 28Gbaud PDM 16-QAM on a 50-GHz Grid over 1,200 km of
Fiber, OFC/NFOEC 2010, PDPB8.
S. Chandrasekhar, X. Liu, P. J. Winzer, J. Simsarian, and R. A.
Griffin, Small-Form-Factor All-InP Integrated Laser Vector
Modulator Enables the Generation and Transmission of 256-Gb/s
PDM-16QAM Modulation Format, OFC/NFOEC 2013,
PDP5B.6.
Taizo Tatsumi, Naoki Itabashi, Tomoko Ikagawa, Naoya Kono,
Morihiro Seki,
Keiji Tanaka, Kazuhiro Yamaji, Yasushi
Fujimura, Katsumi Uesaka, Takashi Nakabayashi, Hajime Shoji
and Shoichi Ogita, A Compact Low-Power 224-Gb/s DP16QAM Modulator Module with InP-based Modulator and
Linear Driver ICs, OFC/NFOEC 2014, Tu3H.5.
Y. Baeyens, N. Weimann, P. Roux, A. Leven, V. Houtsma, R. F.
Kopf, Y. Yang, J. Franckoviak, A. Tate, J. S. Weiner, P. Paschke,
and Y.-K. Chen, High Gain-Bandwidth Differential Distributed
InP D-HBT Driver Amplifiers With Large (11.3Vpp) Output
Swing at 40Gb/s, IEEE JOURNAL OF SOLID-STATE
CIRCUITS, VOL.39, NO.10, OCT. 2004.
I. Dedic, High-Speed CMOS DSP and Data Converters,
OFC/NFOEC 2011, OTuN.1.
K. Kikuchi, and S. Tsukamoto, Evaluation of Sensitivity of the
Digital Coherent Receiver, JOURNAL OF LIGHTWAVE
TECHNOLOGY, VOL. 26, NO. 13, JULY 1, 2008.

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Silicon Photonic Modulator based on a MOSCapacitor and a CMOS Driver

M. Webster*, C. Appel, P. Gothoskar, S. Sunder, B. Dama, and K. Shastri,
Cisco Systems, Inc.
Allentown, PA, USA.
(*)email: mawebste@cisco.com
AbstractWe describe a silicon photonic optical modulator
based on a MOS-capacitor and a low power 1V CMOS inverterbased driver IC. In an MZI configuration, this efficient
modulator and driver IC combination can produce a 9dB
extinction ratio at 28 Gbps, at a wavelength of 1310nm.
Keywords modulator, silicon photonics, MOS, lumpedelement, CMOS driver

I.

INTRODUCTION

Optical communication applications are demanding higher

bandwidth densities, low-power, and low-cost solutions. The
field of silicon photonics is rapidly developing to address the
needs for both present and future applications. Silicon
photonics has been enabled by leveraging the performance and
manufacturing capabilities of commercial CMOS fabrication
processes and foundries.
Fig. 1: (a) The SISCAP device cross-section and optical
mode. (b) The electrical equivalent circuit model.

An efficient optical modulator is a key component in any

silicon photonics platform[1]. In this presentation, we shall
address the details and performance of a MOS-capacitor based
optical modulator and the CMOS drive circuits required for its
efficient operation. Most silicon photonic modulators utilize
the free-carrier dispersion effect [2] to induce a phase change
in an optical mode. This effect also results in a change of
attenuation for the optical mode due to the change in
absorption from the free-carriers. Silicon photonic modulators
consist of a waveguide region and a mechanism to modify the
free-carrier charge density within the optical mode intensity.
This can be achieved with device geometries that operate using
a MOS-based capacitor [3], a reverse-biased PN-junction [4],
and forward injection of a PIN device [5]. Here, we describe
the SISCAP (Silicon Insulator Silicon CAPacitor) device
which is a MOS-capacitor based silicon photonic modulator.
II.

Fig. 2: SEM image of fabricated SISCAP device.

when designing the driver circuit for the optical modulator.
The series resistance is primarily determined by the doping
profiles of the SOI and poly-Si layers. An SEM image of a
fabricated device is shown in Fig.2.
Compared with PN-junction based devices, the SISCAP
device can be operated in accumulation whereas PN-junction
devices are typically required to operate in reverse-bias. The
accumulation operation provides high charge densities on each
side of the gate-oxide, and with this high charge density
region centered within the optical mode, a large perturbation
overlap integral[5] is achieved. The result of this is an
efficient modulator that has a VL < 2V.mm at a wavelength
of 1310nm.

DEVICE STRUCTURE

A SISCAP device cross-section and the optical mode are

shown in Fig.1(a) The SISCAP device consists of a p-type
poly-Si layer, a gate-oxide layer, and a n-type SOI layer. The
overlapping poly-Si and SOI layers form a single mode optical
waveguide with the gate-oxide centered in the optical mode.
The equivalent electrical circuit for the SISCAP is a simple
series RC circuit as shown in Fig.1(b). This model is used for

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Fig. 3: (a) The SISCAP C-V curve, (b) Phase modulation, and (c) Attenuation versus applied voltage.
Fig.5(a). The power consumption of about 2-4 mW/Gbps is
achieved for the complete driver path from input to the IC,
through the inverter driver stage, and also power consumed in
the MZI. There is also an additional 20mW of DC power
required (worst case) to thermo-optically bias the MZI to the
nearest quadrature point.

The device C-V curve is shown in Fig.3(a) for operation

under accumulation, for both measured results and device
simulations. Figure.3(b) shows the phase modulation of the
SISCAP device as a function of voltage and Fig.3(c) shows
the change in attenuation as a function of voltage for the
SISCAP. The SISCAP background propagation loss (with no
applied voltage) and with sufficient dopant levels for 28 Gbps
operation is about 6.5 dB/mm. Most of this loss is due to the
p-type poly-Si layer.
III.

Optically the MZI modulator is DC biased at its quadrature

point by thermally heating the modulator. This tuning can
require up to 20mW depending on how far from the ideal
tuning point the MZI modulator initially is biased. The
modulator is then electrical switched around this bias point.

DEVICE OPERATION

The input range of the driver IC is 80 mV to 1600mV peakto-peak differential and the output signals are 2V peak-to-peak
differential. All input and output data is NRZ at 10.3125Gbs.
There are AC-coupling capacitorss on the board that couple the
data onto the chip through wire-bonds.

The SISCAP device was fabricated using a 0.13um

technology node CMOS process on SOI wafers. For 1310nm
NRZ applications at 28Gbps (such as IEEE 100G LR4
standard), we used an electrical driver IC fabricated using the
CMOS 40nm technology node. This allows for low-power and
high-speed CMOS inverters that can provide a 1V output
swing, that is described below. With this drive voltage of 1V
driving a SISCAP-based MZI, an RF section length of 400um
gives the optimum optical modulation amplitude (OMA) and a
resultant extinction ratio of about 9dB at 28 Gbps. A
photograph of the MZI section is shown in Fig.4(a).

The CML-to-CMOS stage is comprised of a differential

pair (Gm stage) and a TIA stage that produce a combined
voltage gain of Gm*R, where R is the feedback resistor of the
TIA. A schematic of the CML-to-CMOS stage is shown in
Fig.5(b). At the input of the differential pair there are 50 ohm
(100 ohms differential) input termination resistors and a
common mode bias circuit. The input differential pair provides
some supply noise immunity and common mode rejection and
is especially important with small input signals, which helps
with input sensitivity.
The TIA stage is used to match the
inverter trip point with the output of the CML stage using some
common mode feedback. The TIA, although being built from
a CMOS like inverter, does not produce rail-to-rail outputs
under all processing corners. This output is passed through a
few cross-coupled inverter stages to get a rail-to-rail CMOS
final output.

An advantage of operating the SISCAP structure in

accumulation mode is that for voltages greater than about 1V,
the phase modulation efficiency is greatly increased, as seen in
Fig.3(b). Therefore, with a voltage swing from the driver IC of
1V, it is better to drive the SISCAP voltage between 1.2V and
2.2V, instead of between 0V and 1V. Driving the SISCAP at
higher voltages increases the net capacitance which can impact
the RC bandwidth of the modulator. However, under these
drive conditions, the SISCAP bandwidth is sufficient to obtain
a 28 Gbps PRBS-31 NRZ optical eye with a 50% eye-crossing,
> 40% mask-margin, and an extinction ratio of 9dB (at a
wavelength of 1310nm). This is shown in Fig.4(b). Driving the
modulator at higher datarates is also possible, as shown in
Fig.4(c) where the 28Gbps design was tested at 40 Gbps to
obtain a PRBS-31 NRZ optical eye, with an extinction ratio of
~8dB.
IV.

If the differential pair was directly connected to the CMOS

inverter, without the TIA stage, there would be process
dependent voltage offsets between the differential pair
common mode output and the ideal trip point of the inverter.
These offsets can limit the gain at the first inverter and also
they tend to build along the chain and can completely squelch
the outputs in the worst case or at a minimum significantly
impact the optical performance. To mitigate these offsets, the
common mode is measured at the output of the TIA and
compared inherently with the trip point of an inverter
amplifier. The error is then filtered and fed back to the pchannel devices of the differential pair to adjust its common
mode output. The differential pair output common mode is

CMOS DRIVER CONFIGURATION

Here, we discuss the details of a driver IC for 10Gbps

applications that illuminates some of the design challenges. For
example in a 10G driver IC, the design consists of a CML-toCMOS input stage and a Data Mux followed by the CMOS
inverter output driver chain that connects to the modulator

87

Table of Contents

and close to rail-to-rail CMOS output levels are observed out

of the first invert. All inverters are identical and thus track over
process corners.

adjusted and feeds the input of the TIA. The input and output
of the TIA are shorted with the resistor R. This biases the TIA
at the trip-point of the inverter it sets the input and output
common of the TIA close to the trip point of the inverter. With
the common mode output of the TIA set close to the trip point
of the first inverter, a high gain is observed at the first inverter

After the CML-2-CMOS stage, the Data Mux, shown in

Fig.5(c), stage is provided for test purposes. User defined data

Fig. 4: (a) Photograph of MZI structure. (b) 28 Gbps PRBS-31 optical eye. (c) 40 Gbps
PRBS-31 optical eye.

Fig. 5: (a) MZI Driver + SISCAP MODEL. (b) CML-2-CMOS Stage. (c) Data Mux (d) Output
Driver Stage (e) Simulated 10G PRBS-31 optical eye

88

Table of Contents

segments. A typical 10Gbaud PAM-4 optical eye obtained

from a segmented MZI is shown in Fig.6(b).

can be muxed into the data path using this mux. This is useful
during system bring-up, testing and debug. It can also be used
to squelch the outputs and invert the polarity. The mux is built
out of transmission gates.

The SISCAP device was recently demonstrated the in an IQ

modulator configuration for QPSK applications[8], which can
also be extended to QAM-16 using the segmented MZI
approach.

The last stage in the driver is the output driver stage whose
schematic is given in Fig.5(d). It consists of a complementary
inverter build-up chain that drives the MZI modulator. The
input signal to output driver stage is a rail-to-rail CMOS 10G
data signal from the Data Mux. The output drives the
capacitive load of the MZI modulator through wire bonds and
inductive traces on the modulator IC.

VI.

In order to simulate the driver IC, an accurate model of the

elctro-optical behavior of the SISCAP has been developed. It
presents an accurate R-L-C load to the driver output but also
performs the electrical to optical mapping needed to generate
an optical eye. The dominant component is the capacitor from
the SISCAP structure (0.5pF-2pF) but other components, such
as the wirebond inductance, also have significant impact.
Using this model the electrical parameters are tuned to meet
the key optical requirements such as extinction ratio, OMA,
and optical rise and fall times, etc. Examples of the simulated
10 Gbps optical eye are shown in Fig.5(e)

REFERENCES
[1]

[2]
[3]

The design approach is applicable to higher frequency

drivers, for example 28G drivers. Compared with other
approaches, such as CML based designs, the complementary
inverter based approach is highly efficient. However, the
design is not fully differential and hence may be sensitive to
supply noise. On chip noise must be carefully managed by
adding sufficient on chip supply bypass capacitors and the
driver circuits should be isolated from other sensitive node.
V.

CONCLUSION

We have demonstrated an efficient MOS-capacitor based

silicon photonic modulator and the CMOS-based electrical
driver IC design approach used. This approach to optical
modulators should further advance the field of silicon
photonics.

[4]

[5]

[6]

ADVANCED MODULATION APPLICATIONS

[7]

A key feature of having an efficient optical modulator that

can be treated as a lumped element electrical load is the ability
to form a segmented MZI for advanced modulation formats.
Here, it is possible to drive each segment of the MZI with the
digital data directly from the CMOS driver circuit. Thus there
is no need for an electrical digital-to-analog conversion stage,
as this is performed directly in the optical domain by the
different length segments. A 10Gbaud PAM-4 demonstration
of this was presented earlier[7]. A diagram of a segmented
MZI is presented in Fig.6(a), which in this case illustrates three

[8]

M. Webster, P. Gothskar, An Efficient MOS-Capacitor based

Silicon Modulator and CMOS Drivers for Optical Transmitters,
Group IV Photonics, (invited) submitted, 2014.
R.A. Soref and B.R. Bennett, Electrooptical effects in silicon, IEEE
J. Quant. Electronics, vol. QE-23, no. 1, pp.123-129, 1987.
A. Liu , R. Jones , L. Liao , D. S. Rubio , D. Rubin , O. Co0hen , R.
Nicolaescu and M. Paniccia "A high-speed silicon optical modulator
based on a metal-oxide-semiconductor capacitor", Nature, vol. 427,
pp.615 -618, 2004.
G.T. Reed., G.Z. Mashanovich, F.Y. Gardes, M. Nedeljkovic, Y. Hu,
D.J. Thomson, K. Li, P.R. Wilson, S.-W. Chen, and S.S. Hsu,
"Recent breakthroughs in carrier depletion based silicon optical
modulators", Nanophotonics, pp.1-18, 2013
W. M. Green, M. J. Rooks, L. Sekaric, and Y. A. Vlasov, "Ultracompact, low RF power, 10 Gb/s silicon Mach-Zehnder modulator",
Opt. Express 15, 17106-17113, 2007.
H. Kogelnik, "Theory of Optical Waveguides," in Guided-wave
Optoelectronics, T. Tamir, ed., pp.7-87 (Springer Verlag, Berlin
1990).
X. Wu, et al. "A 20Gb/s NRZ/PAM-4 1V transmitter in 40nm CMOS
driving a Si-photonic modulator in 0.13m CMOS, " IEEE ISSCC,
pp.128-129, Feb. 2013.
B. Milivojevic, C. Raabe, A. Shastri, M. Webster, P. Metz, S. Sunder,
B. Chattin, S. Wiese, B. Dama and K. Shastri, 112Gb/s DP-QPSK
Transmission Over 2427km SSMF Using Small-Size Silicon
Photonic IQ Modulator and Low-Power, Proc. Opt. Fiber Commun.
Conf./Nat. Fiber Optic Eng. Conf., 2013, Paper OTh1D.1

Fig. 6: (a) A diagram of the segmented MZI approach. (b) A PAM-4 optical eye obtained using a
segmented MZI (from [7]).

89

Table of Contents

Gaallium Arrsenide Electro-O

E
Optic M
Modulatorrs
R. G.
G Walker1, M. F. OKeeefe1, N. Cam
meron1, H. E
Ereifej2, T. Brast3
1) Finisar
F
UK Ltd,
L NETParrk Incubator,, Thomas W
Wright Way, S
Sedgefield, T
TS21 3FD, U
U.K.
2) Finisar Inc.
I 200 Preccision Road,, Horsham, P
PA 19044
3) Fin
nisar German
ny GmbH, Reuchlinstrae
R
e 10/1, 10553
3 Berlin, Geermany
epitaxiaal growth annd a rectifyiing Schottky top-contact
complettes the basic vvertical diode sstructure. Thiss is operated
under rreverse-bias to drop an electtric-field verticcally through
the centtre of the guideed optical modde. This E-fieldd is designed
to interract efficiently with the lightt via one or m
more electrooptic eeffects. Optim
mization compprises adjustm
ments to the
compossitions, layer thhicknesses andd the position oof the doped
back-plane relative too the surface aand optical proofile. We try
mode-size (larrge for fiber
for a ssuitable balancce of optical m
interfaccing) versus electro-optic efficiency annd electrical
capacitaance, with tolerrable optical loosses due to freee-carrier and
metal-ellectrode absorpption [1].

A
Abstract GaA
As/AlGaAs pro
ovides an envirronmentally sta
able
and
d rugged gu
uided-wave sysstem for rea
alisation of high
h
fun
nctionality elecctro-optic modu
ulators for tellecommunicatio
ons,
aviionics and aerrospace. We detail the guideed-wave buildiingbloocks required to
o build complex modulator com
mponents.
IIndex Terms - Electrooptic modulators, Gallium
G
arseniide,
Op
ptical modulatio
on, Semiconducttor waveguides

INTR
RODUCTION

Ever higher daata-rates beyon

nd 100Gbaud are
a being encod
ded
ontto optical com
mmunication ch
hannels using coherent
c
system
ms,
driiving the deevelopment off high-functio
onality photo
onic
inttegrated devicees based on fasst electro-opticc modulators. The
T
ubiiquitous Mach
h-Zehnder Interrferometer (MZ
ZI) configuration
uniiquely provides the spectrally
y clean modulattion required.
f such system
ms to operate in
n military, avio
onic
There is need for
andd aerospace en
nvironments as well as civil. Gallium
G
Arsen
nide
(G
GaAs) is traditio
onally the mateerial of choice for devices to be
operated at mm-w
wave frequenccies owing to the
t availability
y of
w-loss, low-co
ost high-resistiivity substratee in large waafer
low
sizzes. Characterristics of envirronmental stab
bility, including
g a
goood degree of raadiation hardneess make GaAss an ideal materrial
forr systems wh
hich must su
urvive and operate
o
in haarsh
envvironments. The
T
high intriinsic resistivitty and electro
onmoobility (6 timess higher than Si
S and almost 60% higher th
han
InP
P) make for low
w optical loss and
a high RF baandwidth.
Foundry proceesses developeed for the fabrrication of GaaAs
MM
MICs (Monoliithic Microwav
ve Integrated Circuits)
C
are well
w
suiited for extension into the op
ptical domain; indeed, much
h of
thee early develop
pment of GaAss modulators was
w undertaken by
insstitutions with established exp
pertise in MMIICs for aerospaace
andd defence appliications.
II

Fig.1 GaaAs waveguide types, showingg computed opptical intensity

profiles with SEM imagges below. Leftt: Shallow-rib w
waveguide with
top electtrode; Right: deeep-etched ridge w
waveguide. c) aalso shows the
plated aiir-bridge contactt.

A)
Waveguide P
Process Technoology
Our GaAs modulattor technologyy is built uponn an existing
pHEMT
T process whicch has demonsttrated high yielld under high
volume conditions oof up to 10000wspw. A weell-controlled
producttion sequence ttranslates into a robust process backed by
high levvels of manufaccturability. Thee foundry-baseed fabrication
process starts with sixx-inch semi-inssulating GaAs wafers upon
which tthe epi-layers are grown byy Molecular Beeam Epitaxy
(MBE).. Standard i-linne steppers are used for opticaal waveguide
and eleectrode photollithography. A dry Reactivve Ion Etch
(RIE) pprocess is usedd to ensure thaat the waveguiide walls are
essentiaally vertical. T
This is the onlyy step that deviaates from the
standardd pHEMT seqquence and iss based on a frontside-tobacksidde via processs, modified tto ensure highh verticality
(>99.7) and edge acuuity required foor low scatteringg loss.

GAAS FOR PHOTONIC

H
INTEG
GRATION

d AlxGa1-xAs are
GaAs and thee related ternaary compound
latttice-matched for all Al. fractions
f
(x). The band-g
gap
inccreases with x,
x and this red
duces the refrractive-index. An
epiitaxial GaAs/A
AlGaAs multilaayer system can
n provide vertiical
opttical confinemeent using a high-index GaAs core wavegu
uide
layyer and lower index AlGaA
As cladding layers
l
above and
a
bellow. Lateral co
onfinement is provided
p
by ettching the surfa
face
to create rib or rid
dge waveguidees (Fig.1).
The ability to engineer the conductivity
c
of the material by
dopping confers a real advantag
ge over alternaative guided-waave
sysstems based on
n insulating maaterials. An elecctrical back-plaane
(n--type) is creatted beneath th
he waveguide during the MB
BE
978-1-4799-3622-9/14/$31.00 2014 IEEE

90

Table of Contents

intensityy function chaaracterised by the half-wavee voltage V

(the ON
N/OFF voltage swing of the m
modulator).

A
After waveguiide definition, metal electrod
des are deposiited
by e-beam evapo
oration and standard lift-offf techniques. The
T
hat ensures go
ood
meetallization is a standard Ti::Pt:Au stack th
adhhesion and con
nductivity. Low
w loss in the RF transmissio
onlinne is achieved by
b gold-plating to >5m.

Velocity and Impedance Maatching

A)
Traveeling-wave dessign aims to maatch the phase--velocity of a
forwardd-propagating R
RF wave with the velocity oof the optical
modulat
ation group whiich it is creatinng through the electro-optic
effect. IIf this is done perfectly, thenn the modulatioon-depth can
accumuulate monotonnically along the entire lenngth of the
electrodde. If the veloccity-match is noot perfect thenn phase walkoff will reverse the accumulation, inncreasingly as thhe frequency
rises. Since a countter-propagatingg RF wave reepresents the
mismatch (i.e. a negative RF velocity) we
worst-c ase velocity m
m to suppresss the reflecteed RF wave by properly
also aim
terminaating the line.

B
B)
Wavegu
uide Types
Both deep-etch
hed ridge wav
veguides and sh
hallow-etched rib
waaveguides (Fig.1) are used in
n our designs. Rib waveguid
des
aree used where electro-optic waveguide is required. Deeep
riddge waveguidees are used fo
or high-curvatu
ure 90 or 18
80
bennds or where multimode behaviour
b
is wanted
w
for MMI
M
struuctures. Wav
veguides of bo
oth types show
w similar lossses,
bellow 0.3dB/cm
m including freee-carrier abso
orption from the
bacck-plane (~ 0.0
05dB/cm). Ad
dditional loss from
fr
the electro
ode
meetallization is around 0.05dB/cm.

Loaded Line Configurationn

B)
In thhe loaded-line configuration (Fig. 3) - whiich has been
generallly adopted foor traveling-w
wave modulatoors in III-V
material
als - the moduulation electrodes are segmeented into a
periodicc array of quaasi-lumped eleements isolatedd by passive
spaces. Low RF loss iis achieved by the use of a brroad coplanar
transmission-line, sppatially distincct from the modulation
electroddes, and isolateed from the dooped waveguidde backplane.
The opttical waveguiddes pass downn the coplanar gap and the
electroddes sample the line-volttage via thee air-bridge
connecttions shown in Fig.1 and Fig. 2.

C)
Electro-optic Effects
Compound sem
miconductors such
s
as GaAs have
h
a non-centtrosym
mmetric crystaal and are sligh
htly polar. Th
his gives rise to
oa
linnear electro-op
ptic (LEO) efffect an E-field
E
depend
dent
reffractive-index change
c
whose magnitude is dependent on the
relative orientation of crystal, field and optical-polarization.
mal
Moost convenientlly in these matterials, light propagating norm
to a set of cleaved facets will experience thee maximum LE
EO
p
to the wafer surface (TE modes) and
a
forr polarization parallel
witth E-field ap
pplied verticallly into that surface. Smalller
seccondary effeccts are indeependent of orientation and
a
pollarization: the quadratic elecctro-optic (QEO
O) effect and the
carrrier sweep-ou
ut effect the latter due to depletion
d
chang
ges
witthin the doped back-plane [1]. Crucially, alll can be arrang
ged
to w
work together by suitable cho
oice of crystal-orientation.

Fig. 3 L
Loaded line traveeling wave MZII modulator baseed on coplanar
stripline (CPS) or (dottedd) coplanar waveeguide (CPW).

Loadded-line configgurations proviide good conttrol over the

RF veloocity and impedance owing too its slow-wavee property as
a capac itively loaded transmission liine [1]. In GaA
As and other
semiconnductors the opptical mode is fully buried inn the material
and expperiences the fuull dielectric annd dispersive sllowing effect
of the semiconducttor material (group-index ~3.55). By
contrastt, the RF copplanar field iss 50% air-loaaded, so the
effectivve dielectric coonstant is the much lowerr air/GaAs
averagee. The ratio off these two essentially fixed index values
defines the required sllow-wave factoor (~1.34)
The ffinal characteriistic impedancce and RF veloocity are both
subject to the same sllow-wave factoor [1]. Serendiipitously, the
requiredd loading cappacitance to aachieve both vvelocity and
impedannce match to 550 is easily rrealised in GaA
As. RF losses
in metalls and the dopeed backplane im
mpose ultimatee limits to the
high-freequency perforrmance.

Figg. 2 MZI active-zone cross-sectio

on with process--flow (below)

III

GAAS TRAVELIING WAVE MOD

DULATORS

The Mach-Zeehnder Interferrometer (MZI)) consists of an

opttical splitter fo
ollowed by a pair
p of electro-optic wavegu
uide
phaase modulatorss and subsequeent recombiner.. Fig. 2 illustraates
thee bias and RF drive arrangem
ment set-up to operate in serries
pussh-pull [1].Th
he inbuilt back
k-to-back conn
nection createss a
serries-chain so th
he effective caapacitance is halved,
h
while the
RF
F drive-voltagee is split equaally. Upon reecombination the
diffferential phasse-shifts add. The result iss a raised-cossine

IV

ESSEN
ENTIAL GUIDED
D-WAVE FUNCT
TIONS

It is iimportant to opptimise all the basic workhoorse guidedwave suubcomponentss of a complexx high-functionn modulator.
91

Table of Contents

bution may seeem small, but the

t compounding
Eaach loss contrib
efffect of many su
uch can accumu
ulate to a signifficant total.

bends m
must be long, w
with limited ddeviation; majoor directional
change for path-foldiing requires deeep-ridge waveeguides with
Loss by laterall radiation is
very higgh lateral indeex-contrast. L
generallly negligible bbut several bouund-modes aree likely to be
present unless the rridge is very narrow. Bennds in such
waveguuides exhibit ssimilar mode--coupling and interference
behavioour to MMIs ((Fig. 6) and aare optimised similarly for
low-los s and good proocess-tolerancee.

A
A)
Y Junctiions
A waveguidee Y-junction is relativelly process and
a
waavelength toleraant. Because it requires mono
o-mode behavio
our
at tthe septum it is
i implemented
d using shallow
w rib waveguid
des.
Ouur Y is based on a pair off overlapped, tapering S-ben
nds
creeating a narrow
w septum to give a clean split. In reverrse,
actting as the reco
ombiner in an OFF-state
O
MZII (Fig. 4) it yieelds
goood dispersal off the light merg
ged from the an
nti-phase inputss.
Experimental trials
t
showed th
he excess loss per Y-junction
n to
aveerage at 0.05dB
B, close to that of similar sing
gle S-bends.

Fig. 6 Siimulated deep-riddge bends: a) R=

=100m; b) R=11.6m
Figg. 4 Y-junction split
s
and recombination after 180
0 phase-shift

90 ccorner-bends aare often comb

mbined in S coonfigurations.
Optimissation using grraded-curvaturee minimises ressidual higher
mode w
which can caause coherent interactions aand degrade
perform
mance. Small radius bends oof this type caan also cause
unwanteed polarisationn conversion an effect thhat is nearly
eliminat
ated when the riidge walls are ttruly vertical (F
Fig.1).

B
B)
Multimo
ode Interferencce Structures (M
MMIs)
Frequently a four-port 2x2 coupler is required (e.g. for
moonitoring, or fo
or a polarizatio
on combiner). The direction
nalcouupler, based on
n parallel weak
k waveguides, is well-known
n to
be extremely sen
nsitive to the lateral confineement parametters
ode
andd is essentiallly unmanufaccturable; thereefore multimo
intterference cou
uplers (MMIs)) are generallly used insteead.
MM
MIs offer N to
o N re-imaging
g based on ord
dered interferen
nce
of the modes in
n a multimodee waveguide. The
T lowest-order
inttermodal beat-llengths dominaate this process. Crucially, these
aree stable again
nst variation in
n etch depth in a deep rid
dge
waaveguide.
U
Using a symm
metric launch so
o that only even
n-order modes are
exccited, 1xN spliitting can be ob
btained. The im
mportant 1x2 case
hass similar functtionality to a Y-junction.
Y
In a 2x2 MMI with
w
porrts placed at th
he 1/3, 2/3 positiions, modes wiith zero-crossin
ngs
at these positions are suppreessed. Lackin
ng these speciific
maging is possib
ble in a reduced
d length.
moodes, 2x2 re-im

MODU
ULATORS FOR A
ADVANCED FOR
RMATS

A)
IQ Modulatoor
The IQ modulatoor (In-Phase/Q
Quadrature) iss a generic
parallel configuration of two high-sppeed MZI moddulators with
wo inner childd units (Fig.
outer pparent system comprising tw
7). The two RF drivess are independeent in general.

Figg. 5 2x2 MMI reecombiner with deep-ridge

d
sine-b
bends.

Fig. 7

Since the lengtth of a MMI co

oupler increasees as the squaree of
thee port-spacing there
t
is consideerable incentiv
ve to minimise the
lattter. Closely-spaced ports with
h shallow rib waveguides
w
sufffer
unw
wanted directiional-coupling which generaally degrades the
exttinction-ratio of
o a modulato
or. The 2x2 MMIs
M
of Fig. 5
intterface with deeep-ridge S-bends, to avoid thiis problem.

The IIQ configuratiion is most coommonly used for DQPSK

(Differeential Quadratuure Phase Shifft Key) encodiing of a CW
optical input. Each chhild MZI is biaased to a Null oof the cosine
light-vooltage characteeristic and driven with a ppeak-to-peak
data-siggnal level of 2 . Adjacent inntensity peaks are naturally
in anti-pphase, so the reesulting outputt is always ON
N, with binary
symbolss represented bby anti-phase ppulses. Both ddata channels
are encooded in this duuobinary fashioon and finally combined in
phase qquadrature. Byy defining addditional amplituude levels in
QAM
(Quadrature
Amplitude Modulationn), further

C)
Deep-Ettched Corner and
a U bends
Strategies fo
or directional change off GaAs optiical
waaveguides will depend on wh
hether the wav
veguide is of the
deeep-ridge or sh
hallow-rib type [2]. Generrally shallow rib
92

IQ modulator w
waveguide confi
figuration for DQ
QPSK

Table of Contents

O
muultiplication off the number off symbol-statess is possible. Our
IQ devices have been
b
used to deemonstrate up to
t 64 QAM [3]].
In our GaAs im
mplementation
n, each wavegu
uide path uses Ubennds to implem
ment a tromb
bone-slide folded-back section
inccorporating thee child and p
parent phase-ccontrol electrod
des,
reccombiners and
d monitor-tapss (Fig. 7). Th
he resulting to
otal
waaveguide path is
i almost twice the chip-length
h.
is 2.9V and
a
moodulation band
dwidths of 25-3
30GHz are ach
hieved. The fib
berto--fiber insertion loss is below 7dB. 45Gb/s DQPSK
D
coding
g is
dem
monstrated witth EVM below 8% (Fig. 8).

Fig. 9 GaAs DP-IQ m

modulator respoonse: 25GBd = 100Gb/s. X
polarisattion above, and Y below.

Whille discrete IQ ddevices can be used to encodde DP-QPSK,

integrattion onto a singgle die is advanntageous, beingg much more
compacct, of lower coost and enablinng the four-chaannel timingskew too be tightly coontrolled. Moddulation characcteristics are
essentiaally as for the ssimple IQ moddulator, with sppecific design
challengges largely in the optical gguided-wave configuration.
Compleex routing is rrequired in the optical-domaain to avoid
significaant timing pproblems and secure a coompact chip
footprinnt. Such a device makes heeavy use of coorner and Ubends and other components, justifying the careful
optimizzation of guidedd-wave elemennts outlined herre.
Exceellent preliminaary results havve been obtainned (Fig. 9).
Polarisaation channel bbalance is witthin 1dB and ffiber-to-fiber
loss is bbelow 8.5dB (bboth polarisatioons).

Figg. 8 GaAs IQ mo
odulator DQPSK
K responses: 22.3
3GBd = 44.6 Gb//s.

B
B)
Analog Modulation
M
Syystems
The IQ modulaator configurattion can also bee used to generrate
sinngle-sideband (SSB)
(
modulattion for RF-ov
ver-Fiber system
ms.
Thhe MZIs are biaased to the inteensity null and each child MZI
M
gennerates a doublle-sideband, su
uppressed-carrier spectrum. The
T
unw
wanted sideban
nds are cancellled at the paren
nt recombiner due
d
to a 90 phase differential betw
ween the two matched RF inpu
uts,
brid RF splitterr.
typpically secured by means of a quadrature hyb
mple of an anaalog requiremeent.
SSB modulatiion is one exam
R
systems
s
may require
r
the nattive
Othher, mainly RF-over-fiber,
inttensity modulattion yielded by
y a simple MZI, but without the
priimarily 3rd harm
monic distortio
on due to the raaised-cosine MZI
M
chaaracteristic. Gu
uided-wave con
nfigurations to
o achieve this can
c
alsso be based on a variant dual MZI.
M

ACKNOWLEDG
GMENT
A porrtion of the workk described in thhis paper was caarried out with
the suppport of the 7th ICT-Framew
work project IP
PHOBAC-NG
Photonic Broadbband Radio Acccess Units for
(619870)) - Integrated P
Next Geeneration Opticcal Access Netw
works and by the European
project B
BEACON (FP7-S
SPACE-607401)).

REFERENC
CES
[1] R. G. Walker andd J. Heaton, Gallium arseniide modulator
techhnology in B
Broadband Optiical Modulators
rs Science,
Tecchnology and Appplications, (Ed.. A. Chen and E
E. J. Murphy),
Bocca Raton, FL: CR
RC Press, 2012, Chapter 8, pp. 2207-221.
[2] R.G
G. Walker, N.I. C
Cameron, Yi Zhoou, S.J. Clementts, "Optimized
galllium arsenide m
modulators for addvanced modulaation formats",
IEE
EE J. Sel. Topiccs in Quant. Eleect., vol.19, no.66, pp.138,149,
Novv.-Dec. 2013.
[3] P.C
C. Schindler, D
D. Korn, C. Stamatiadis, M.F.. O'Keefe, L.
Stam
mpoulidis, R. S
Schmogrow, P. Zakynthinos, R
R. Palmer, N.
Cam
meron, Yi Zhouu, R.G. Walker, E. Kehayas, S. Ben-Ezra, I.
Tom
mkos, L. Zimmeermann, K. Peterrmann, W. Freudde, C. Koos, J.
Leuuthold, "Monollithic GaAs eelectro-optic IQ
Q modulator
dem
monstrated at 1550 Gbit/s with 64QAM", J. L
Lightw. Tech.,
vol..32, no.4, pp.7600,765, Feb.15, 20014.

C)
Dual Po
olarization IQ (DP-IQ)
(
Modulator
Possibly the most important of the current
c
extend
ded
moodulation form
mats is dual-polarization QP
PSK (DP-QPS
SK)
whhereby pairs off channels are QPSK
Q
encoded
d onto orthogo
onal
pollarization-statees of the fibeer to further double the data
d
cappacity. DP-QPS
SK is encoded using a Dual IQ modulator.
Most modulato
or types show different charaacteristics for TE
andd TM polarizaations; in GaAss the TM is trransmitted larg
gely
unm
modulated. Because of this,, both polarizaation channels are
enccoded initially onto TE light with final transsformation of one
o
chaannel to TM prior
p
to adiabattic combination
n onto the outp
put
fibber. This polarization duplex stage can be in
ntegrated onto the
moodulator chip using
u
guided-w
wave methods, or
o into the outp
put
fibber-coupling arrrangements usiing micro-opticcs.
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Wafer-Scale Millimeter-Wave Phased-Array RFICs

(Invited Paper)
Gabriel M. Rebeiz, Woorim Shin, Faith Golcuk, Ozgur Inac, Samet Zihir, Ozan Gurbuz, Jennifer
Edwards and Tumay Kanar
University of California, San Diego, La Jolla, CA, 92093-0407, USA
Abstract This invited talk will present a summary of
the millimeter-wave wafer-scale phased array work at UCSD.
This concept can drastically reduce the cost of millimeterwave phased arrays by combining the RFIC blocks,
antennas, power distribution and summing, digital control
and up and down converters all on the same wafer (or large
piece of silicon), and eliminates all RF transitions in and out
of the chip, therefore resulting in more efficient systems and
lower cost systems. Examples at 90-100 GHz, 108-114 GHz
and 400 GHz will be presented in this paper, together with
their measured antenna patterns.

Also, the entire phased array should be integrated on a

single piece of silicon so that no mm-wave interconnect
occurs between different substrates. The wafer-scale
phased array can then be placed on a low-cost printedcircuit board where the input/output data signals (up to
Gbps), control and power are placed. The entire mm-wave
functionality is contained on the chip and the wafer-scale
implementation is therefore easy to implement, and
requires no RF design from the end user. It is a selfcontained solution.
This paper will present some of these wafer-scale

I. INTRODUCTION
Silicon phased-array chips have now arriving to a level
of complexity which has never been imagined. This is
especially important at millimeter-wave frequencies where
there is very little space for electronics in a twodimensional phased array with an antenna spacing of 0.5
(=3 mm at 100 GHz). One way to build such arrays is to
integrate as much as possible of the SiGe (or CMOS) chip,
and this not only includes the phase shifters and VGAs,
but also, the transmist/receive switch and transmit/receive
phased-array modules, Wilkinson power combining
network, digital and SPI control, bias circuitry, and in
some cases, entire down-converters and up-converters.
Such chips become very complex to test and therefore, it
is also essential to design a complete built-in-self-test
(BIST) system in order to test these chips in a low-cost
manner.
Another important aspect is the packaging of such
chips. This has been done using bond-wires, flip-chip
techniques and C4 bumps, but requires expensive
millimeter-wave substrate which contains a low-loss
distribution network between the chip and the antennas,
and low-loss antennas. Such substrates are typically
expensive to manufacture since they must be composed of
multiple layers of low-loss Teflon-based or LTCC
substrates. This is what the industry has typically done at
60-80 GHz [1-2], but it is hard to extend it to 90 GHz and
above.
One radical solution, proposed by UCSD, is to integrate
everything required for a phased array on a single chip,
not only the electronics, but also the high-efficiency
antennas leading to a wafer-scale implementation (Fig. 1).

978-1-4799-3622-9/14/$31.00 2014 IEEE

Fig. 1. Wafer-scale concept where the electronics and antennas

are all integrated on the same chip.

phased-arrays developed at UCSD.

II. 108-114 GHZ WAFER SCALE PHASED ARRAY
TRANSMITTER

Fig. 2 presents a SiGe wafer-scale phased array

transmitter at 108-114 GHz transmitter with highefficiency on-chip antennas [3]. The 4x4 array is based on
an RF beamforming architecture with an equi-phase
distribution network and phased shifters placed on every
element. The differential on-chip antennas are
implemented using a 100 m thick quartz superstrate and
with a simulated efficiency of 45% at 110 GHz (Fig.
3).This type of antenna, pioneered at UCSD, requires the

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use of a 50-100 m thick quartz (or low-loss dielectric)

superstrate above the silicon wafer so as to increase the
volume for the electric field under the antenna and
increase its efficiency (Fig. 3). The phased array is also
designed with low mutual coupling between the antenna
elements and results in a very stable active antenna
impedance versus scan angle. The phased array is built in
the Jazz SBC18H3 SiGe BiCMOS process, and is 6.5x6.0
2
mm .

(a)

(b)
Fig. 3. (a) Superstrate antenna on top of a silicon RFIC. The
antenna is placed on a 100 m thick quartz substrate for
improved efficiency. (b) Differential dipole antenna (yellow)
on the top side of the quartz and the feed line (dark blue) on the
top side of the silicon substrate.

(a)

(b)
Fig. 2. (a) A 108-114 GHz 16-element transmit wafer-scale
phased- array with integrated high efficiency differential dipole
antennas. (b) Block diagram showing the integration on the chip.

Fig. 4. Measured patterns at 114 GHz for the 16-element waferscale phased array transmitter.

Measurements show two-dimensional pattern scanning

capabilities up to 30 degrees, limited only by the two bit
phase shifter used on each cell (0, 90, 180, 270 degrees)
and the size of the array (Fig. 4), with a directivity of 17.0
dB, an array active gain of 26.5 dB at 110 GHz, and an
EIRP of 2325 dBm at 108114 GHz. The power
consumption is 3.4 W from a 1.9 V supply. To our
knowledge, this work represents the first wafer-scale
phased array to-date. The application areas are in point-topoint communication systems in the 100120 GHz range.

III. 90-100 GHZ 4X4 POLARIMETRIC RADAR CHIP

Fig. 5 presents a 4x4 transmit/receive (T/R) SiGe
BiCMOS phased-array (IBM8HP) chip at 90100 GHz
with vertical and horizontal polarization capabilities, 3-bit
gain control (9 dB), and 4-bit phase control [4,5]. The 4x4
2
phased array fits into a 1.6x1.5mm grid, which is required
at 94 GHz for wide scan-angle designs. The chip has
simultaneous receive (Rx) beam capabilities (V and H)
and this is accomplished using dual-nested 16:1 Wilkinson

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combiners divider with high isolation. The phase shifter is

based on a vector modulator with optimized design
between circuit level and electromagnetic simulation and
o
results in 1 dB and 7 rms gain and phase error,
respectively, at 85110 GHz. The V and H Rx paths result
in a gain of 22 and 25 dB, respectively, a noise figure of
99.5 (at max. gain), and 11 dB (at min. gain) measured
without the T/R switch, and an input P1dB of -31 to -26
dBm over the gain control range. The measured output
Psat is +1 dBm per channel, limited by the T/R switch
loss. The chip consumes1100 mA from a 2-V supply in
both the Tx and Rx modes.

IV. 390-440 GHZ WAFER-SCALE POWER COMBINING

MULTIPLIER ARRAY
Fig. 6 presents a 2x4 amplifier/quadrupler array in
45nm CMOS technology [6]. The distribution is one at Wband (90-110 GHz) and the quadruplers are placed just
before the antennas so as not to incur the high loss in the
CMOS backend at 400 GHz. In this case, the antennas are
slot-ring antenna with a 75 m thick quartz superstrate on
top [7], and this equalizes the TEM mode and the TM0
modes, resulting in efficient elimination of these modes in
the substrates from the slot-ring antenna and a high
efficiency antenna. The simulated antenna efficiency is
55% with no metal fill and 35% with the aggressive metal
fill encountered in advanced CMOS processes.

(a)
Fig. 5. A 90-100 GHz 16-element transmit/receive phased array
with simultaneous receive beams and dual nested Wilkinson
couplers. This chip contains 48 different phased array channels
2
and is 6.6x5.8mm . The channels fit into a 1:1 antenna grid
which is placed on top of the chip using polyimided RDL
(redistribution layers).
o

Measurements show +/-6 and +/-0.75 dB variation

between the 4x4 array elements in the Tx mode and Rx
mode, respectively, and -40 dB coupling between the
different channels on the chip.
In this design, the antennas are not integrated on chip,
and 5-10 m thick polyimide redistribution layers are used
on top of the cihp in order to attach the internal antenna
ports on the RFIC (32 of them, 16 for V and 16 for H) to
the external dual polarized antenna. This is still a waferscale implementation since the completed product will
contain the RFIC and the antennas on a single chip, and no
mm-wave transitions are used (assuming that an up/down
converter is used on chip). To our knowledge, this chip
has 48 independent T/R channels and two 16:1 Wikinson
combiners, and is the largest phased-array chip ever
developed.

(b)
Fig. 6. A 2x4 amplifier/quadrupler array for 390-440 GHz
operation (a): Block diagram and (b) micrograph. An EIRP of 34 dBm was measured from this array resulting in one of the
highest powers achieved from silicon at these frequencies.

The 390-440 GHz array performed as designed, with the

quadrupler generating 120 W of power at 400 GHz with
a conversion loss of 20 dB (8-10 mW of input power at
100 GHz). This is better than most GaAs quadruplers, and
is due to the high ft and the non-linearity of CMOS
transistors when biased in the class C mode. The entire

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[2] Bon-Hyun Ku, Ozgur Inac, Michael Chang and Gabriel M.

Rebeiz, A 75-85 GHz Flip-Chip Phased Array RFIC with
Simultaneous 8-Transmit and 8-Receive Paths for
Automotive Radar Applications, IEEE Radio Frequency
Integrated Circuits Conf. (RFIC), June 2013, pp. 1-4.
[3] W. Shin, B. Ku, O. Inac. Y.C. Ou, and G.M. Rebeiz, A
108-116 GHz 4x4 Wafer-Scale Phased Array Transmitter
with High-Efficiency On-Chip Antennas, IEEE Journal
Solid-State Circuits, vol. 48, no. 9, pp. 2041-2055,
September 2013.
[4] Fatih Golcuk, Tumay Kanar, and Gabriel M. Rebeiz, "A 90100 GHz 4x4 SiGe BiCMOS Polarimetric TransmitReceive Phased Array with Simultaneous Receive-Beams
Capabilities," IEEE Transactions on Microwave Theory and
Techniques, vol. 61, no. 8, pp. 3099-3114, August 2013.
[5] Ozgur Inac, Fatih Golcuk, Tumay Kanar, and Gabriel M.
Rebeiz, "A 90-100 GHz Phased-Array Transmit/Receive
Silicon RFIC Module with Built-In Self-Test," IEEE
Transactions on Microwave Theory and Techniques, vol.
61, no. 11, pp. 3374-3782, October 2013.
[6] Fatih Golcuk, Ozan Gurbuz, and Gabriel M. Rebeiz, "A
0.39-0.44 THz 2x4 Amplifier-Quadrupler Array with Peak
EIRP of 3-4 dBm," IEEE Transactions on Microwave
Theory and Techniques, vol. 61, no. 12, pp. 3614-3623,
December 2013.
[7] J. M. Edwards and G. M. Rebeiz, High-Efficiency
Elliptical Slot Antennas With Quartz Superstrates for
Silicon RFICs, IEEE Trans. Antennas and Propagation,
vol. 60, no. 11, pp. 5010-5020, November 2012.

array, with the amplifiers driving the multipliers at 3-4

mW of W-band power, generated an EIRP of 3-4 dBm at
400 GHz, and this shows that wafer-scale techniques can
be used for power combining up to THz frequencies (Fig.
7). Note that in this case, the input is at W-band and the
output is at 360-440 GHz (in terms of a radiated wave).

Fig. 7. Measured H-plane patterns from the 2x4 array at 360-432

GHz with an EIRP of 3-4 dBm at 420 GHz.

IV. CONCLUSION
This paper presented several wafer-scale silicon RFIC
chips with complex capabilities. In all cases, the antennas
are integrated with the silicon chip to result in wafer-scale
phased arrays and power combining chips. It is our
opinion that this topology will be used extensively at mmwave and THz frequencies.
ACKNOWLEDGEMENTS
This work was supported by the DARPA GRATE,
DARPA MFRF, and the DARPA/SRC-FCRP center.

REFERENCES
[1]

Ku, P. Schmalenberg, S. Kim, C. Kim, O. Inac, J. Lee, K.

Shiozaki, and G.M. Rebeiz, A 16-Element 7781-GHz
o
Phased Array for Automotive Radars with 50 BeamScanning Capabilities, IEEE Int. Microwave Symposium,
June 2013, pp. 1-4.

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245 GHz SiGe Transmitter Array for Gas Spectroscopy

Klaus Schmalz1, Johannes Borngrber1, Wojciech Debski2, Mohamed Elkhouly, Ruoyu Wang1,
3
3,4
Philipp Neumaier , and Heinz-Wilhelm Hbers
1

IHP, 15236, Frankfurt (Oder), Germany

Silicon Radar, 15236, Frankfurt (Oder), Germany

Deutsches Zentrum fr Luft- und Raumfahrt (DLR), 12489 Berlin, Germany

4
Technische Universitt Berlin, 10623 Berlin, Germany

Abstract A 245 GHz transmitter (TX) array with an

integrated antenna-array for a gas spectroscopy system has
been realized, which consists of a push-push VCO with a 1/64
frequency divider, power amplifiers, frequency doublers, and
on-chip antennas with localized backside etching. The
TX-frequency is tunable in the range from 238 GHz to
252 GHz. The TX-array is fabricated in 0.13 m SiGe:C
BiCMOS technology with fT/fmax of 300GHz/500GHz. Its
estimated output power is 7 dBm at 245 GHz, and the EIRP
reaches 18 dBm at 245 GHz. The spectroscopy system
includes a TX and a receiver in SiGe. The sensitivity of this
spectroscopy system is demonstrated by the high-resolution
absorption spectrum of methanol and will be increased
further by this TX-array.
Index Terms SiGe, mm-wave, 245 GHz, transmitter,
antenna-array, gas spectroscopy.

II. CIRCUIT DESIGN

The TX array is fabricated in a new generation of IHPs
0.13m SiGe BiCMOS technology. The TX array includes
four TXs for spatial power combining, which consists of a
two-stage power amplifier, a frequency doubler, and an
integrated antenna, see Fig. 1. The inputs of these TXs are
connected to a Wilkinson power divider network, which is
fed by a local oscillator (LO). The LO consists of a
120 GHz push-push voltage controlled oscillator (VCO)
with an 1/64 frequency divider for the fundamental
frequency, a 120 GHz differential two-stage power
amplifier as used also for the TX, and an external phaselock loop (PLL). Fig. 2 presents the schematics of the
VCO, the power amplifier (PA) and the frequency
doubler. The 1/64 frequency divider is coupled inductively
to the push-push oscillator core at fundamental frequency.
The PA uses two stages with a transformer-coupled
topology [5]. The PA draws 53 mA at 4 V supply voltage.

I. INTRODUCTION
The implementation of transmitters (TX) with high
output power in SiGe for applications in the mm-wave
range requires an innovative architecture to fulfill the
requirements concerning performance and low power
dissipation. Efficient high-power generation can be
addressed by spatial combining the output power from
several TXs using an antenna array. Recently, sensor
systems for mm-wave gas spectroscopy, which are based
on commercially available components using frequency
multiplication to 210270 GHz have been reported [1].
These sensor systems may become the technique of choice
for detection of a broad range of chemicals [2]. The
implementation of integrated mm-wave TX and receiver
(RX), [3] - [6], offer a path towards a compact and
low-cost system for gas spectroscopy. A higher output
power of the TX is required for an increased sensitivity.
This paper presents a 1x4 TX-array for 245 GHz in
0.13m BiCMOS SiGe. The TX-array shows about 7 dBm
output power at 245 GHz. It is used in a gas spectroscopy
system, whose performance is demonstrated by the high
resolution absorption spectra of methanol.

978-1-4799-3622-9/14/$31.00 2014 IEEE

Fig. 1. Schematic of the 245 GHz transmitter-array.

Fig. 2. Schematic of the VCO, and the two-stage 120 GHz power
amplifier coupled to the frequency doubler.

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Fig. 3 shows the micrograph of 2the fabricated TX array

chip. The die area is 3.7 x 5.4 mm .

LBE area due to the minimum metal density requirement

of the silicon technology. The ground plane of the module
acts as a reflector for the antenna. The distance between
the radiator and the reflector is determined by the chip
thickness, which was optimized to be 200 m.

a)

Fig. 3. Photograph of the 245 GHz transmitter array chip.

The antenna array was realized on-chip, and directly

integrated with the TXs by on-chip interconnects of
microstrip transmission lines. The used silicon substrate
has a permittivity of about 11.9 and a resistivity of
50 ohmcm, which will result in strong surface wave
effects and considerably high loss hence very low antenna
efficiency. The localized backside etching (LBE) process,
available in IHPs 0.13m BiCMOS SiGe technology,
offers an effective way to improve the radiation efficiency
of the on-chip antenna by removing the lossy silicon under
the radiators. The layer stack, and the antenna design are
illustrated in Fig. 4a and Fig. 4b, respectively. There are
seven aluminum layers buried in the SiO2 insulator layer
above the silicon substrate. The top thick metal layer TM2
is used to construct the radiators and the feeding
microstrip transmission lines, while the bottom metal layer
M1 is used to realize the ground plane for both the circuits
and the antennas. The antenna array is composed of four
identical double-folded dipole antenna elements (see
Fig. 3), but only two of them are drawn in Fig. 4b for
better visualization since the array is symmetric. They are
placed 1200 m apart so that the single folded dipole
elements are 600 m (~0.5 lamda at 245 GHz) apart from
each other. The dipole elements are grounded by TM2-M1
vias. The LBE area for each radiator is optimized to be
2
400800 m by compromising between better radiation
efficiency (larger LBE area) and good mechanical stability
of the chip (smaller LBE area). The opening of the ground
plane under the radiator (M1 open) is smaller than the

b)
Fig. 4. Parameters of the layer stack (a), and the antenna array
(b). The LBE areas are indicated by dashed rectangles. Two
double-folded dipole-antennas are shown only.

Fig. 5.
array.

Simulated gain and radiation efficiency of the antenna

The four double-folded dipole antennas are excited

in-phase simultaneously by the four TXs to achieve spatial
power combining (antenna elements with port3 and port4
are not drawn). The simulated reflection coefficient at the
ports (S11, referenced to 50 ohm) and the coupling level
between the two neighboring antennas (S21) are as
follows: S11 is lower than -10 dB in the range of 220 GHz

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260 GHz, while S21 is lower than -20 dB. The simulated
gain and efficiency of the antenna array are plotted in
Fig. 5. The gain (in broad-side direction) is about 14 dBi
at 245 GHz, and the radiation efficiency is about 76%.
The used 120 GHz power divider network consists of
two stages of cascaded Wilkinson power dividers, in total
it includes three dividers, see Fig. 1. The Wilkinson power
divider is implemented using microstrip lines. It is
implemented in the top most metal layer with thickness of
3 m. The substrate height is about 9.8 m and the
conductor width of the 50 ohm transmission line is about
16 m. 50 ohm transmission lines are used to connect the
three Wilkinson power dividers. The Wilkinson power
divider is simulated with Momentum EM simulator. It
exhibits an insertion loss of 1.5 dB at 120 GHz and more
than 20 dB of isolation.

respectively, using the same experimental set-up as

described above, to obtain the relative difference in EIRP
between the single TX and the TX-array. Fig. 6 presents
the uncalibrated received power for the TX-array and the
single TX, respectively.
We observed an EIRP difference of about 11 dB at
245 GHz, which is close to the simulated difference of
13 dB (7 dB due to increased antenna gain, plus 6 dB due
to four TXs). Table I compares the performance of our
TX-array, see Table II, with previous work, demonstrating
that high EIRP values at these frequencies were achieved
only when using integrated array arrays.
TABLE I
COMPARISON OF MM-WAVE TRANSMITTER-ARRAYS
Sengupta
[7]

Frequency
276-285GHz
CMOS

This
work

238-252GHz
SiGe

III. PERFORMANCE OF THE TX ARRAY

The mm-wave signal of the TX-array was received by a

commercial receiver (R&S ZVA-Z325 Converter)

attached to a standard WR-3.4 horn antenna with 25 dBi
gain (specified at 270 GHz). The distance between the
horn antenna and the TX array on wafer was set to 9.9 cm.
The output power of the single TX without antenna is
1 dBm at 245 GHz [5]. The antenna gain was calculated
by subtracting this output power from the measured EIRP
(effective isotropic radiated power) of 7 dBm [5]. This
estimated value of 6 dBi around of 245 GHz is in
agreement with the simulation results (7 dBi) for the
single LBE antenna.

Circuit
4x4 PowerGeneration and
Beam-Steering
Array
1x4 TX-array

EIRP
9.4dBm
broadside
18dBm at
245GHz

TABLE II
PERFORMANCE OF TRANSMITTER ARRAY
VCO: DC current
Divider: DC current
PA:
DC current
Doubler: DC current
Frequency range
Output power, estimated
EIRP

32 mA at 3.3 V
29.5 mA at 3 V
5x 53 mA at 4 V
4x 19 mA at 2.8 V
238GHz 252 GHz
7 dBm at 245 GHz
18 dBm at 245 GHz

IV. DEMONSTRATOR MODULE

We have developed a gas spectroscopy system with
frequency modulation (FM) operating from 238 GHz to
252 GHz using the 245 GHz TX-chip and RX-chip,
described in [5][6]. A LO is used for the TX and the RX,
respectively, whose frequency is tuned by using the PLL.
The reference signals for the two PLLs were delivered
from two signal generators. The spectrum was obtained by
applying frequency ramps for the reference frequency of
TX and RX, respectively, with constant frequency offset
to generate 50 MHz IF signal of RX. Plug-in boards with
TX- and RX-chips, respectively, were mounted on carrier
boards with PLL device, and a 0.6 m long gas absorption
cell between TX and RX was used, see Fig. 7. The
effective antenna gain of the TX and RX, respectively, is
increased by external dielectric lenses mounted in front of
the TX and RX. FM with a frequency deviation of 675 Hz
(corresponding to 2048 x 675 Hz = 1.38 MHz for the TX
frequency) and modulation frequency of 50 kHz was

Fig. 6. The power received by horn antenna from the 245 GHz
TX-array and single TX, respectively, for the same measurement
set-up (received power is not calibrated, distance is 9.9 cm).

We measured the received power for the single TX with

on-chip antenna and the TX-array with antenna-array,

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Fig. 8 shows the measured 2f absorption spectrum of

methanol (CH3OH) at a gas pressure of 13 Pa and
measurement time of 467 s after baseline correction (top),
and the simulated spectrum of the absorption coefficient
(bottom), Fig. 8a, and an enlarged portion of the spectrum,
which demonstrates the excellent signal-to-noise (S/N)
ratio (Fig. 8b).
The S/N ratio will be further improved by using the
TX-array in the demonstrator module due to its four times
higher output power compared to the TX.

performed for the reference frequency of the TX PLL. The

second harmonic content (2f) of the absorption spectrum
was obtained by detecting the IF power of the RX using a
diode power sensor connected to a lock-in amplifier.

VII. CONCLUSION

Fig. 7.

A 1x4 TX-array for a gas spectroscopy system in the

range 238 GHz 252 GHz has been presented consisting
of a push-push VCO, power amplifiers, frequency
doublers, and an integrated antenna-array. It is fabricated
in 0.13m SiGe:C BiCMOS technology with fT/fmax of
300GHz/500GHz. It reaches 18 dBm EIRP at 245 GHz.
Gas spectroscopy using TX and RX in SiGe has been
demonstrated by the absorption spectrum of methanol.
The TX-array gives the advantage to increase further the
performance of this gas spectroscopy system.

Photograph of the demonstrator-module.

REFERENCES
[1] I. R. Medvedev, C. Neese, G. M. Plummer, and F. C. De
Lucia, Submillimeter spectroscopy for chemical analysis
with absolute specificity, Opt. Lett. 35(10), pp. 1533-1535
(2010).
[2] A. M. Fosnight, B. L. Moran, and I. R. Medvedev,
Chemical analysis of exhaled human breath using a
terahertz spectroscopic approach, Appl. Phys. Lett. 103,
133703 (2013).
[3] E. jefors, B. Heinemann, and U. Pfeiffer, Active 220and 325-GHz Frequency Multiplier Chains in an SiGe HBT
Technology, IEEE Trans. Microwave Theory & Tech., vol.
59, no. 5, pp. 1311-1318, May 2011.
[4] E. jefors, B. Heinemann, and U. Pfeiffer,Subharmonic
220- and 320-GHz SiGe HBT receiver front-ends, Trans.
Microwave Theory & Tech., vol. 60, no. 5, pp. 1397-1404,
May 2012.
[5] K. Schmalz et al.,245 GHz SiGe transmitter with
integrated antenna and external PLL, IEEE MTT-S IMS
Symp.Proc., June 2013.
[6] K. Schmalz et al.,Subharmonic 245 GHz SiGe Receiver
with Antenna, IEEE Proc. European Microw. Int. Circuits
Conf. (EuMiC), pp. 121-124, October 2013.
[7] K. Sengupta and A. Hajimiri,A 0.28THz 44 PowerGeneration and Beam-Steering Array, ISSCC Dig. Tech.
Papers, pp. 9-11, Feb. 2012.

a)

b)
Fig. 8. a) Measured 2f absorption spectrum of methanol (top),
and simulated spectrum of absorption coefficient (bottom), and
(b) zoomed-in spectra with S/N ratios.

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Table of Contents

A Compact 340 GHz 2x4 Patch Array with

Integrated Subharmonic Gilber Core Mixer as a
Building Block for Multi-Pixel Imaging Frontends
Yogesh Karandikar, Herbert Zirath, Yu Yan, Vessen Vassilev
Microwave Electronics Laboratory, Dept. of Microtechnology and Nanoscience
Chalmers University of Technology, Gothenberg, Sweden. Email: yogesh@chalmers.se
AbstractFor linear multi-pixel imaging systems, a linear
stack of pixels comprising of an antenna and a heterodyne
receiver are needed. Such pixels can be realized using MMIC
processes. The main constraint for such multi-pixel system is a
compact array of pixels giving high coupling to quasi-optics used
for focusing. This paper addresses this trade-off and presents a
novel solution based on beam synthesis of two consecutive subarrays.
One such sub-array along with heterodyne receiver is described as half-pixel in this paper and it is realized using 2x4
patch array and Gilbert core sub-harmonic mixer using a 250nm
DHBT process. The patch array has ohmic loss better than 8 dB
and mixer conversion loss is 6-8 dB over 320-350 GHz RF band.
The chip size is 1mm x 2mm and therefore for 7 simultaneous
beams a MMIC of 8 half-pixels is foreseen.
Index TermsGaussian Coupling, Patch Array, Sub-Harmonic
Mixer, Gilbert Core, HBT

The technology used to realize this concept is 250nm DHBT

process with ft = 340 GHz and fmax = 680 GHz. The
advantage in using this process is its multi-dielectric backend
based on BCB offering 4 interconnect metal layers. [9][11].
The antenna sub-array chosen for half-pixel is 2 x 4 microstrip
patch array and its design and performance is stated in section
II.
The sub-harmonic mixer used in this work is Gilbert Cell
with an emitter follower stage at IF to improve conversion loss.
Also for compactness a new LO phasing network with Marchand balun and broadside coupled line hybrids is designed and
its details are presented in section III. The measurements are
presented in section IV and discussion is made towards the
effectiveness of the proposed solution.
II. 2 X 4 PATCH S UB -A RRAY AS A H ALF -P IXEL

I. I NTRODUCTION
The THz imaging system, either active or passive, are
gaining popularity for several applications such as biology,
security, drug detection etc. The security imaging is one
such application where a stand off imaging at video rates
is required to asses threats. Attempts have been made by
various research groups to achieve this goal using CMOS,
Bolometer and Schottky technologies. [1][4]. Apart from
these technologies recent advances in III-V semiconductor
based transistor technologies have made it possible to realize
the components for such systems in the THz regime [5]. Even
so video rate imaging using simultaneous data reception over
number of pixels is seen as a challenge [6].
In order to address this issue, a compact integration of
antennas with heterodyne frontends is needed. To achieve this
both HEMT / HBT based antenna integrated circuits have
been demonstrated but this work has been limited to single
pixel only [7], [8]. Taking forward from this ground work,
the authors foresee a integration of antenna sub-arrays with
heterodyne frontends as a superficial pixel which is in this
paper referred as half-pixel.
In system perspective, two such consecutive half pixels can
then be combined to form a full-pixel with desired antenna
beam pattern offering high coupling to focusing Quasi-Optics.
The main advantage in this approach is the pixel can be
arranged in a compact way. This concept has been described
in section II of the paper.

978-1-4799-3622-9/14/$31.00 2014 IEEE

Typically for imaging systems Corrugated horns, spline

horns, Conical horns or Diagonal horns are used as a radiating
antenna element to couple energy to Quasi-optics and their
Gaussian coupling efficiencies ranges from 82 98% [12].
However, for MMIC based solution a planar antenna topology is needed which could offer high coupling to the quasioptics. With MMIC approach, an array of Microstrip Patches
is feasible and a quadratic array of 4x4 patch elements can
offer moderate gain of the order of 15-17 dB. To achieve
compactness, it is possible to split such 4x4 array in to two
sub-arrays of 2x4 each and full array can be formed by
combining downconverted received signal in the IF band. This
technique is similar to beam synthesis as shown in Fig. 1.
If the size of such quadratic 4x4 microstrip patch array is
M M , then for N simultaneous beams the total physical
size of the linear array would be N M 2 . But if the subarrays of 2x4 are stacked together then the overall size of the
array would become (N + 1) (M 2 /2). Thus effectively an
area of (N 1) M 2 /2 is saved on MMIC while retaining
N full arrays. Therefore a 2x4 patch array with its active
downconverting frontend is considered as a half pixel in
this paper and a f ull pixel is then formed by adding the IF
signal of two consequtive sub-arrays.
For 250nm DHBT process, the Microstrip patches are made
using top metal layer (MET4) and with bottom most metal
layer (MET1) as a ground plane. These two layers are separated using 5m BCB dielectric (r = 2.7). Also considering

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Table of Contents

M/2
N+1 Sub-Array

2 Sub-Array

Antenna Sub-Array @ 340 GHz

X4 Multiplier
@ 160-170 GHz
Sub-Harmonic
Mixer
Pin
40-42.5 GHz

1 Sub-Array

Antenna Sub-Array @ 340 GHz

X4 Multiplier
@ 160-170 GHz

X4 Multiplier
@ 160-170 GHz
Sub-Harmonic
Mixer

Pin
40-42.5 GHz

IF LNA
2-12 GHz

Antenna Sub-Array @ 340 GHz

Nth Beam

IF LNA
2-12 GHz

Sub-Harmonic
Mixer
Pin
40-42.5 GHz

IF LNA
2-12 GHz

1st Beam

Fig. 1. Concept of Half-Pixel with antenna sub-array and sub-harmonic mixer to synthesize N simultaneous beams

its integration with the sub-harmonic mixer, the output of the

array is deliberately made differential, similar to that of [7].
It is well understood that at such high frequencies feeding
lines of the array cause unwanted radiation which results
in increased cross-pol levels and reduced beam symmetry.
Therefore, the advantage in having differential excitation of the
array for the broadside beam is, the microstrip feed network
always carry out of phase currents which in turn results in onaxis cancellation of spurious radiation from microstrip feed
lines. Thus an on-axis null for the cross-pol is maintained
over entire frequency band.
A physical layout of such array with integrated receiver is
shown in Fig. 6. This array is simulated in 3D EM solvers
with entire feed-network into consideration. Thus all effects
such as conductive, dielectric as well as radiative losses from
the corporate feed network is considered in the simulations.
The performance of this array is shown in Fig. 2c. After
optimization, an impedance bandwidth 6.5% is achieved
with 6 8 dB loss in ohmic efficiency.
The far-field function of this 2x4 array when combined with
next 2x4 array results in 4x4 Microstrip patch array. This
resultant far-field is plotted in Fig. 2a for = 45 plane. This
far-field is also compared with the analytical 4x4 slot array farfield for exact same element spacing. In Fig. 2a it is interesting
to note that for slot array as well as microstrip patch array
a on axis null for cross-pol is obtained, but the peak crosspolar side lobes are 7-8 dB higher for the microstrip patch
array than that of ideal slot array. This indicates that there is
spurious emission from the feed lines but due to that fact that
lines carry out of phase currents, it cancels out on-axis while
for other angles it causes increased cross-polar levels.
The 3-D far-field of this array at 340 GHz is also plotted
in Fig. 2b and it is seen that the 2x4 patch array has large
inequality in E- and H-plane beam widths. But when this same
array get combined with the next 2x4 patch array, its directivity
improves by 3 dB and high circular symmetry in the main
beam is achieved which is required for better coupling to the
quasi-optics.

To further evaluate the concept, now a Gaussian beam

analysis is made on this effective far-field of 4x4 microstrip
patch array using [13]. The resulting G is between 75 80%
over 10% bandwidth proving effectiveness of the proposed
scheme. The beam waist (o ) has a moderate size of
@340 GHz and its location (Zo ) is computed to be 250m
below the MET 1 ground plane. These details are shown in
Fig. 2d.
III. S UB - HARMONIC G ILBERT C ORE M IXER WITH
E MITTER F OLLOWER
With an array antenna design chosen to 2x4 with differential
output, a corresponding sub-harmonic mixer can be designed
and integrated with the array. Similar to [7], a differential
Gilbert core sub-harmonic mixer is chosen in this work. The
DHBT process makes it practical to implement Gilbert core
with 340 GHz RF front end with sub-harmonic LO of 160170 GHz. The schematic of the mixer is shown in Fig. 3. For
better conversion loss of the mixer, the emitter follower stage
has been added at the IF before output. For Gilber core mixer
the LO phases are obtained by a Marchand balun followed by
coupled line hybrids [14][16].
IV. M EASUREMENTS
With the complete design integrated and fabricated using
the DHBT process, measurements were performed by setting
up a RF link in WR-03 band similar to presented in [7]. The
chip photo is shown in Fig. 6 and measurements were made
using two discrete LO frequency points at 161 and 167 GHz
are shown in Fig. 4 and 5 respectively. From the measured
IF power, the mixer conversion loss is de-embedded with
uncertainty of 2 dB. The measurements as plotted in Fig.
4 and 5 show resemblance between simulated and measured
conversion loss of the chip. The IF were received over all
tested RF frequency points and measured bias point currents
were close to simulated values, proving working solution of
2x4 microstrip patch array with sub-harmonic Gilbert core
mixer.

103

Directivity (dBi)

Table of Contents

15

Slots CO

10

Slots XP

Patch CO

Patch XP

-5
-10
-15
-20
-25
-30
-90-75-60-45-30-15 0 15 30 45 60 75 90

Do (dBi)

14
13.8
13.6
13.4
13.2
13
12.8
300
310
320
330
340
-6
-7
-8
-9
-10
-11
-12
300
310
320
330
340
-4
-6
-8
-10
-12
-14
-16
-18
-20
300
310
320
330
340
(c) Directivity, Ohmic Efficiency and Input Reflection
Patch Array

(b) Far-field @ 340 GHz : i) 2x4 Patch Array and ii) 4x4 Patch Array

Gauss (%)

(a) Comparison of Co- and Cross-polar patterns of 4x4 analytical

slot array and Patch Array with microstrip feed network ( =
45 P lane@ 340 GHz)

78
74
70

66
300
310
320
330
340
350
870
860
850
840
830
820
300
310
320
330
340
350
500
250
0
-250
-500
300
310
320
330
340
350
(d) Gaussian Coupling Efficiency of 4x4 array of Quadratic
Microstrip Patches realized using TSC 250nm DHBT process
o (m)

ohmic (dB)

350

(dB)

Zo (m)

350

350
for 2x4

Fig. 2. Simulated Microstrip Patch Array Patterns and key performance parameters

V. CONCLUSION

A concept of half-pixel with integrated 2x4 patch array

and Gilbert core sub-harmonic mixer has been presented as
a compact way to realize multi-pixel imaging frontends. The
2x4 patch array when combined with the another consecutive
half-pixel could offer high coupling to the quasi-optics. The
integrated sub-harmonic mixers on chip can operate over
moderate LO powers of 2-4 dBm offering conversion loss
better than 8dB over RF band. This solution with integrated
multiplier chain and IF amplifiers can be foreseen as a building
block for video rate security imaging systems.

ACKNOWLEDGMENT
Authors thank the Swedish Foundation of Strategic Research, SSF, within the Charmant-Liniment project, and the
VINNOVA Banbrytande Elektronik program BIKT for funding this research.

104

R EFERENCES
[1] F. Friederich, W. Von Spiegel, M. Bauer, F. Meng, M. Thomson, S. Boppel, A. Lisauskas, B. Hils, V. Krozer, A. Keil, T. Loffler, R. Henneberger,
A. Huhn, G. Spickermann, P. Bolivar, and H. Roskos, Thz active
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[2] E. Ojefors, U. Pfeiffer, A. Lisauskas, and H. Roskos, A 0.65 thz focalplane array in a quarter-micron cmos process technology, Solid-State
Circuits, IEEE Journal of, vol. 44, no. 7, pp. 19681976, 2009.

Table of Contents

EF

EF

Vcc

Rc1

Rc2

Q13

-IF

Q14

LO

Q1

Q2

LO

180

LO

+RF

90

Q3

+IF

Q4

LO

LO

270

Q5

Q6

LO

Q9

180
V

LO

Q10

90

Q7

Q8

LO

270

-RF

CM

c
Q11
e

Current Source

Fig. 6. Chip Photo (Area= 2.56 mm x 0.96 mm)

Q12
e

Fig. 3. Gilbert Core Sub-Harmonic Mixer with Emitter Follower

16

[6]

Measurements
14

Lc (dB)

12

LSB Sim

[7]

USB Sim

10

[8]

8
6

[9]

4
312 314 316 318 320 322 324 326 328 330 332
Freq (GHz)
[10]
Fig. 4. Measured Lc for FLO = 161 GHz and PLO = 3.5 dBm
[11]

16
Measurements

Lc (dB)

14

LSB Sim

[12]

USB Sim

[13]

12
[14]

10
[15]

8
[16]

6
324 326 328 330 332 334 336 338 340 342
Freq (GHz)
Fig. 5. Measured Lc for FLO = 167 GHz and PLO = 3.5 dBm

[3] M. Alonso, N. Llombart, C. Lee, C. Jung, G. Chattopadhyay, L. Jofre,

and I. Mehdi, Silicon micro-lens antennas for thz integrated arrays,
in Infrared, Millimeter and Terahertz Waves (IRMMW-THz), 2011 36th
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X. Zhao, N. Wadefalk, and J. Nicholson, Development of integrated

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H. Zirath, 340 ghz integrated receiver in 250 nm inp dhbt technology,
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of sub-harmonic resistive mixer with differential double slot antenna in
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Inp hbt ic technology for terahertz frequencies: Fundamental oscillators
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P. Rowell, A. Skalare, and M. Rodwell, Inp hbt integrated circuit
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Integrated Circuit Symposium (CSICS), 2010 IEEE, 2010, pp. 14.
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European Conference on, 2012, pp. 868872.
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2008. [Online]. Available: http://dx.doi.org/10.1002/mop.23169

Table of Contents

Diverse Accessible Heterogeneous Integration (DAHI) at Northrop

Grumman Aerospace Systems (NGAS)
Augusto Gutierrez-Aitken, Kelly Hennig, Dennis Scott, Ken Sato, Wesley Chan, Benjamin Poust,
Xiang Zeng, Khanh Thai, Eric Nakamura, Eric Kaneshiro, Nancy Lin, Cedric Monier, Ioulia
Smorchkova, Bert Oyama, Aaron Oki, Reynold Kagiwada, Greg Chao
Northrop Grumman Aerospace Systems, One Space Park M/S ST70AA/D1, Redondo Beach, CA
90278. (310)-812-5536, augusto.gutierrez@ngc.com
Abstract
Northrop Grumman Aerospace Systems
(NGAS) under the Diverse Accessible Heterojunction
Integration (DAHI) DARPA program is developing
heterogeneous integration processes, process design kit (PDK)
and thermal analysis tools to integrate deep submicron CMOS,
Indium Phosphide (InP) heterojunction bipolar transistors
(HBTs), Gallium Nitride (GaN) high electron mobility
transistors (HEMTs) and high-Q passive technologies for
advanced DoD and other government systems.

There are several approaches to perform heterogeneous

integration. At NGAS we have developed in the past
several years selective epitaxial growth, metamorphic
growth, wafer level packaging (WLP), and COSMOS
heterogeneous integration processes [1] and demonstrated
state of the art circuit performance [2]-[3]. Fig. 1 describes
schematically these integration approaches.

Index Items Semiconductor devices, heterojunction

bipolar transistors, field effect transistors, electronic circuits,
CMOS integrated circuits.

Device
type A

Substrate
(a)

I. INTRODUCTION
The requirements for future systems are increasingly
demanding not only from the point of view of performance,
but also from size, weight, power and cost (SWAP-C)
considerations. This translates into the need for advanced
integration of additional complexity and performance of
electronic functions into smaller volumes. In addition, to
enable higher performance of the microelectronic
technology in which these functions are implemented, it is
not enough to use one single semiconductor technology but
to combine or integrate several high performance
technologies in an efficient and cost effective way. In some
cases this involves the integration of semiconductor
technologies based on different substrates and in other cases
it involves the integration of two types of devices on the
same substrate. The combination of two or more dissimilar
microelectronic technologies, or heterogeneous integration,
leads to significant higher design flexibility capability, and
lower size, weight and power.
The more adaptable and more intimate is this
heterogeneous integration between two or more
technologies, the more flexibility is given to the designer
for the selection of the technology for a specific function, or
for an optimum combination of different transistor
technologies in the same function or cell in the design.

Device with
lattice
constant N

Device
With lattice
constant M

Buffer

Substrate with lattice constant M

(b)
Wafer 2
Device type 2
Device type 1
Wafer 1
(c)
Technology
2 Chiplet

Heterogeneous
Interconnects

Wafer (CMOS) Technology 1

(d)

Fig. 1. Heterogeneous integration methods used or being

developed at NGAS. (a) Selective epitaxy, (b) metamorphic
growth, (c) wafer level packaging and (d) COSMOS integration.

In the selective epitaxy heterogeneous integration

technique (Fig. 1a), two (or more) different types of devices
(typically HBT and HEMT) are grown on the same
substrate (For example InP or GaAs) either sequentially,
one on top of the other, or grown, etched back selectively

II. HETEROGENEOUS INTEGRATION METHODS

978-1-4799-3622-9/14/$31.00 2014 IEEE

Device
type A

Device
type B

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Table of Contents

and grown again to create the cross-section shown in Fig.

1a. Metamorphic growth combined with selective epitaxy
enables the integration of semiconductor devices of one
material system on a substrate of a different material system
where the device material system lattice constant is
significantly different than the substrate lattice constant
(Fig. 1b). There are several approaches to achieve this that
in general use one or more buffer layers between the
substrate and the device. The key factor in this approach is
to design and implement a buffer layer that provides a high
quality virtual substrate on which to grow the device. The
buffer layer should be carefully designed to minimize the
increase on thermal resistance due to this added layer.
In the wafer level packaging approach (Fig. 1c) the
wafers of the individual technologies to be integrated are
fully fabricated and bonded together at the wafer level using
a metal to metal thermo-compression process.
This
technology, also referred as wafer scale assembly (WSA),
has several advantages that include no device performance
degradation, no change in device fabrication process and
preservation of existing high-reliability production
processes. The COSMOS heterogeneous integration process
(Fig. 1d) developed by NGAS under the COmpound
Semiconductor Materials On Silicon (COSMOS) DARPA
program is a chiplet to wafer metal to metal thermocompression bonding with highly scaled heterogeneous
interconnects (HICs). The COSMOS process combines the
desired characteristics of low temperature bonding with
high yield, low electrical and thermal resistance
heterogeneous interfaces. Fig. 2 shows a scanning electron
microscope (SEM) picture of focused ion-beam (FIB)
cross-section of the COSMOS HIC. And Fig. 3 shows a
CMOS wafer with InP HBT chiplets integrated using the
COSMOS heterogeneous integration process.

Fig. 3. Picture of a CMOS wafer with integrated InP HBT

chiplets using the COSMOS integration process.

III. DAHI INTEGRATION PROCESS

In the DAHI program, NGAS is developing a process to
integrate several high performance III-V semiconductor
technologies and a high-Q passive technology onto deep
submicron CMOS wafers. For Phase 1 of the program, the
selected technologies for integration are IBMs 65nm
CMOS, NGAS TF4 InP HBT and GaN20 GaN on SiC
HEMT technologies. A top level integration process flow is
illustrated in Fig. 4. NGAS is also investigating the
integration of a third party high cut-off frequency (fT) GaN
technology on the same CMOS wafer. In addition, NGAS
and Nuvotronics are developing the process to integrate
Nuvotronicss high-Q passives in later phases of the
program. NGAS DAHI integration process uses the same
metal-metal bond heterogeneous interconnect developed in
the COSMOS DARPA program.
Standard deep
submicron CMOS
fabrication

Standard GaN HEMT

fabrication including thinning
/ backside via etching /
Backside metal deposition

InP HBT
Device Layers
Metal 1 (InP side
Interconnect)

Bonding
Interface

HIC Interface
deposition

Deep Submicron CMOS (Tech. 1)

Transfer to
carrier wafer and
singulation

Alignment of carrier
wafer and bonding of
GaN chiplets.
GaN Chiplet (Tech. 2)

M2 (InP side
Interconnect)

Deep Submicron CMOS (Tech. 1)

Standard TF4
InP HBT fabrication
including thinning
CMOS Metal
Layers

Transfer to
carrier wafer and
singulation

Alignment of carrier
wafer and bonding of
InP HBT chiplets

InP HBT Chiplet

GaN Chiplet (Tech. 2)
(Tech. 3)

Deep Submicron CMOS (Tech. 1)

Fig. 4.

Fig. 2. SEM picture of a FIB cross-section of the COSMOS

heterogeneous interconnect.

NGAS DAHI integration process.

The NGAS DAHI integration process has several

advantages. It is scalable to 200 mm CMOS wafers and
fully compatible with all Si technologies. All the
technologies to be integrated are independently fabricated in
parallel for optimum cycle time and decoupled line yield.
The DAHI HIC is robust, reliable and high yield. Since the

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integration process does not change device performance nor

reliability qualification level, existing models and process
design kits (PDKs) can be integrated in a common core
environment DAHI PDK with a modular design level that
enables flexibility to allow integration of future
technologies.
The NGAS DAHI integration approach also offers
advantages from the thermal management point of view.
The low thermal resistance metal HICs enable flexible
electrical and thermal routing. The GaN HEMT is
integrated with its backside facing the CMOS frontside to
allow large inter-chip HIC heat sink arrays. Fig. 5 shows a
schematic cross-section of the heat flow on a DAHI chip.
The thickness of the Silicon Carbide (SiC) substrate in the
GaN HEMT chiplet is designed to be thick enough to allow
optimum lateral heat spreading before reaching the thermal
HIC interface.

Fig. 6. Singulated SiC chiplets integrated to a mechanical

Silicon wafer.

IV. DAHI PROCESS DESIGN KIT

GaN HEMT
InP HBT Chiplet

GaN / SiC
HEMT
Chiplet

A very important task in the development of the DAHI

technology is the creation of an integrated DAHI process
design kit (PDK). The objective of the DAHI PDK
development is to have a flexible design environment that
can accommodate schematics, layouts and simulations of
integrated DAHI circuits with device-level integration
designs of a wide variety of technologies. The approach is
to use a modular technology PDK with a common design
software base. Driven by commercial PDK availability, we
have selected Cadence as the common environment. The
modular approach allows the straight forward integration of
additional technologies to the DAHI PDK. A key
component of the DAHI PDK is the DAHI translator
software that provides links between PDKs for layout
versus schematics (LVS) and the DAHI design rule check
(DRC). The DAHI PDK top level design capture/
implementation and the design analysis approaches are
shown in Figs. 7 and 8, respectively.

HBT

CMOS
Interconnects

CMOS

Si CMOS
Chip
Die Attachment Boundary

Fig. 5.

NGAS DAHI thermal dissipation approach.

During the COSMOS program NGAS developed the

integration of InP chiplets onto CMOS wafers. This
integration process includes the temporary bonding of the
thinned InP wafer to a carrier wafer, then chiplet
singulation, alignment, chiplet bonding to a Si wafer and
finally the de-bonding of the carrier wafer. In the DAHI
program one of the key challenges is the development of the
singulation process for the GaN/SiC chiplets. In the initial
part of Phase 1 of the program, we have made significant
progress on this effort. Fig. 6 shows a picture of a wafer
with singulated SiC chiplets integrated to a mechanical
Silicon wafer. In this picture the transparent carrier wafer is
still attached to the chiplets

Commercial
PDK (IBM CMOS)
TF4
InP HBT

GaN20
GaN HEMT

Fig. 7. DAHI
implementation.

108

PDK

Third Party
Technology

Cadence
Virtuoso

approach

DAHI
Translator LVS/DRC
(HIC Alignment, etc)

for

design

capture

and

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Fig. 10 shows the individual technology reticle layouts

for the MPW0.

Spectre

Golden
Gate

Third Party
Tools

Fig. 8.

ADS
Cadence

NGAS
Thermal
Tool/Calculator

DAHI PDK approach for design analysis.

V. DAHI MULTI-PROJECT WAFER RUN

In Phase 1 of the DAHI program, NGAS is running a
preliminary multi-project wafer run zero (MPW0) to
develop and test the integration of 3 technologies. As
mentioned previously, these technologies are 65nm CMOS,
InP HBT and GaN HEMT. A layout screen capture of the
MPW0 reticle is shown in Fig. 9.

Fig. 10. Individual technology layout of the MPW0 reticle.

ACKNOWLEDGMENT
This work is supported by DARPA DAHI Program under
AFRL contract No. FA8650-13-C-7312, Daniel Green
DARPA program manager and Robert Fitch AFRL COTR.
REFERENCES
[1] A. Gutierrez-Aitken, P. Chang-Chien, D. Scott, K. Hennig,
E. Kaneshiro, P. Nam, N. Cohen, D. Ching, K. Thai, B.
Oyama, J. Zhou, C. Geiger, B. Poust, M. Parlee, R. Sandhu,
W. Phan, A. Oki, R. Kagiwada, Advanced Heterogeneous
Integration of InP HBT and CMOS Si Technologies, IEEE
Compound Semiconductor Integrated Circuit Symposium
(CSICS), Monterey, CA, Oct 5, 2010.
[2] B. Oyama, D. Ching, K. Thai, A. Gutierrez-Aitken, V.J.
Patel, InP HBT/Si CMOS-Based 13-b 1.33-Gsps Digital-toAnalog Converter With > 70-dB SFDR, IEEE Journal of
Solid-State Circuits, Vol. 48 , No.10, Oct. 2013, pp. 2265 2272 .
[3] P. Chang-Chien, X. Zeng, K. Tornquist, M. Nishimoto, M.
Battung, Y. Chung, J. Yang, D. Farkas, M. Yajima, C.
Cheung, K. Luo,D. Eaves, J. Lee, J. Uyeda, D. Duan, O.
Fordham, T. Chung, R. Sandhu, R. Tsai,
MMIC
Compatible Wafer-Level Packaging Technology, IEEE 19th
International Conference on Indium Phosphide and Related
Materials (IPRM), May 2007, pp. 14 17.

Fig. 9. Reticle layout for the DAHI MPW0 including 65nm

CMOS, InP HBT and GaN HEMT technologies.

The mask set contains several process development

structures including singulation, alignment, electrical
process control monitors (PCM) test structure groups
(TEGs), electrical and thermal modeling structures, RF
calibration structures and yield test circuits. The mask also
contains designs from five other participants in the DAHI
DARPA program and three government laboratories.

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Enabling Power-Efficient Designs with III-V Tunnel FETs

Moon Seok Kim, Huichu Liu, Karthik Swaminathan, Xueqing Li, Suman Datta, Vijaykrishnan
Narayanan
The Pennsylvania State University, University Park, PA, 16802, U.S.A.
Email: {mqk521, hxl249, kvs120, lixueq}@cse.psu.edu; sdatta@engr.psu.edu, vijay@cse.psu.edu
Abstract III-V Tunnel FETs (TFET) possess unique
characteristics such as steep slope switching, high gm/IDS, unidirectional conduction, and low voltage operating capability.
These characteristics have the potential to result in energy
savings in both digital and analog applications. In this paper,
we provide an overview of the power efficient properties of
III-V TFETs and designs at the device, circuit and
architectural level.
Index Terms Steep-slope devices, ultra-low power, lowvoltage, III-V Tunnel FET (TFET).

features of TFETs such as asymmetrical source/drain

design, and uni-directional conduction provide new
opportunities and challenges for analog and digital design.
This paper highlights on how advances in GaSb-InAs
(III-V) HTFET design influence circuit and architectural
level implementations of digital and analog systems. The
rest of the paper is organized as follows: Section II
describes the TFET device design and introduces recent
progress and modeling efforts. Section III discusses TFET
architecture and digital designs for energy efficient
systems. Section IV focuses on the TFET advantages for
analog systems. Conclusions are followed in Section V.

I. INTRODUCTION
As technology continues to scale down to the nanometer
regime, circuit designers and architects are forced to
grapple with problems related to power constraints at
various levels of abstraction. The limitation in available
power results in a variety of design implications, ranging
from reduced battery life in low end mobile processors to
increased cooling costs in high performance systems and
data centers. Consequently, efforts are being made to
realize new power-efficient designs. At the device level,
this focuses on new efforts to lower supply voltage by
exploring new device architectures and material systems.
Supply voltage scaling in silicon based CMOS
transistors has been a significant challenge due to the
conflict between the scaling down of threshold voltage for
performance and the increased leakage. Enhancements to
device architecture such as improved electrostatics using
multi-gate devices help to lower supply voltage while
retaining the threshold voltage constant. Similarly, III-V
materials offer the ability to improve the electron mobility
at the same field strength. Recent technology nodes have
seen concurrent enhancements in both the device and
material systems. However, the switching slope of the
CMOS transistors is fundamentally limited to the
60mV/decade swing. This paper focuses on III-V Steep
slope Tunnel Field-Effect Transistors (TFETs) that aim at
overcoming this limit.
TFET [1, 2] has emerged as a strong candidate for lowenergy applications due to its superior energy efficiency
arising from the sub-thermal (Sub-kT) switching
characteristics at low supply voltages. In addition to the
steep switching characteristics, a combination of unique

978-1-4799-3622-9/14/$31.00 2014 IEEE

II. OVERVIEW OF THE TUNNEL FET DEVICES

A. Tunnel FET Device Design
TFETs have become one of the most promising
candidates to enable the voltage scaling [1]. Unlike
MOSFETs, a TFET is essentially a gated p-i-n tunnel
diode with asymmetrical source/drain doping [2].
Benefitting from the band-to-band tunneling (BTBT)
induced carrier injection at the source-channel junction,
the high energy carriers with an energy slope of kT (where
k is the Boltzman constant, T is the absolute temperature)
are filtered by a tunneling window, leading to a subthermal energy switching slope in TFETs.
Double-Gate N-type TFET Schematic

Heterojunction Tunnel FET

Gate
Source (P+)

Channel (i) Drain (N+)

Gate
Band-to-band Tunneling (BTBT)

Eg
Source

Ebeff~ Eg-Ec
Ec
channel
Eg

Tunneling Current from Kanes Model:

Fig. 1. TFET schematic and band diagram of a hetero-junction TFET for

effective tunnel barrier (Ebeff) reduction.

Recent progress in prototype device and circuit

demonstration has shown prominent advantages of TFETs
for various energy efficient applications. To outperform
CMOS at low supply voltages, the device characteristics
such as high on-current at low voltage, high on/off ratio

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and steep sub-threshold swing at room temperature are the

key performance aspects of a TFET. Hence, choices of
material system and device architecture are critical in
TFET design, such as using the hetero-band alignment and
low bandgap material to improve the tunneling current,
improving the gate electrostatic control from planar to
nanowire or ultra-thin body, and reducing defect states to
suppress the trap-assisted tunneling [3] (Fig. 1). Knoll et
al [4] demonstrated the first strained Si nanowire inverter
showing sharp transition at 0.2 V. Considering the low
tunneling current of Si TFETs, III-V semiconductor
materials offer more freedom of engineering the tunnel
junctions and improving the tunneling current [5]. Dewey
et al in [6] first explored InGaAs homojunction and
heterojunction TFET (HTFET) with improved on-current
than Si TFET. Mohata et al [7] demonstrated a MOSFETlike on-current in GaAs0.35Sb0.65/In0.7Ga0.3As heterojunction TFET, by taking advantage of the effective
tunneling barrier reduction at the source-channel junction
without reducing the band-gap of the channel material,
which led to a simultaneous enhancement of the ION and
ION/IOFF ratio. Later on, a further improvement of oncurrent of 180 A/m has been achieved by Zhou et al [8]
in a GaSb-InAs TFET. Recent advancement in
complementary TFET process [9, 10] has further
highlighted both the performance improvement and
process compatibility for TFET technology.

Ultra-low power
Energy harvesting,
Wearable
computing

Heterogeneous
multicores

Simple/complex
pipelined processors

High
Performance
Computing

Hotspots
P1

Embedded systems
Mobile/tablet
Processors

Hotspots

Q
P

Q2

Thermal-aware
design

3D Stacking

Domain-specific
accelerators

Fig. 2. Design Spaces for Device Heterogeneous Systems.

but still superior compared to CMOS [27]. Moreover, the

electrical noise performance has been evaluated in [15] for
III-V HTFETs including the flicker, shot and thermal
noise. At a nominal operation voltage of 0.3 V, HTFET
exhibits a competitive input-referred noise in KHz and
MHz frequency range compared to the baseline Si
FinFET. When the operating voltage exceeds 0.3 V for a
frequency range of 10GHz or higher (RF domain), the
input-referred noise of the HTFET increases moderately
due to the presence of shot noise.
The progress in TFET modeling for circuit simulation
has enabled the circuit-level and architecture-level
explorations of the energy efficiency benefits of TFETs,
such as TFET digital and analog circuits [16-19], TFETCMOS heterogonous architecture [20] as well as the
TFET standard cell library development [21].

B. Tunnel FET Modeling for Circuit Simulation

To enable the TFET-based circuit designs and system
analysis, compact model development is critical for
emerging devices. Several works [11, 12] have explored
analytical modeling for different designs of TFETs. Zhang
et al [11] have developed a compact model of double-gate
Si TFET for SPICE simulations, showing good agreement
with TCAD simulation. Recently, Lu et al [12] present a
continuous semi-empirical model to accurate describe the
current-voltage characteristics suitable for both InAs
homojunction TFETs and broken-gap AlGaSb/InAs
TFETs. Given the variety of TFET designs and lack of
mature SPICE models for III-V TFETs, look-up based
Verilog-A models derived from atomistic simulation [13]
or TCAD [14] have been widely used to explore
circuit/architectural designs.
Process variation and electrical noise pose a growing
reliability concern for optimal system design for both
digital and analog/RF applications at scaled technology
nodes, especially due to the preferred low supply voltage
operation of TFETs. The process variation for III-V
HTFETs has been studied for TFET SRAMs [14] and
logics [13]. When variations are considered, the energy
savings of III-V HTFET logic gates are slightly reduced,

III. TUNNEL FET CIRCUITS EXPLORATION

By taking advantage of the unique III-V hetero-junction
TFET device characteristics, it is promising to design
analog and digital circuits with novel functions and/or
superior performance. In the rest of this section, a review
of recent reported TFET circuits and applications is
provided in comparison with Si FinFET designs.
A. Tunnel FET Digital Logic Design Opportunities
These characteristics of HTFETs can manifest
themselves in various system-level design techniques that
make this technology attractive across a wide range of
application domains. Fig. 2 shows the potential scope of
applications domains that would benefit from the adoption
of HTFET technology into their design. For instance,
heterogeneous CMOS-TFET multicores could be used to
optimize a wide range of sequential and parallel
workloads. The efficiency of TFET at low voltage makes
it highly energy-efficient in executing highly parallel
workloads using tens of low-voltage cores operating at
low frequencies. Similarly, it is possible to duplicate the
performance of a high frequency CMOS processor with

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delay performance for two types of the popular master/

slave flip-flop topologies with an additional port (reset) at
various supply voltage ranges. From the simulation results,
HTFET flip-flops shows the high power-efficiency and
fast transition performance at a power supply lower than
0.5 V due to steep slope switching.

TFET processors of higher micro-architectural complexity

by consuming much less power, by simply lowering the
operating voltage and frequency. In a similar manner, the
lower power density of TFET processors can translate into
more effective elimination of temperature hotspots,
making them feasible candidates for thermal-aware
systems. This aspect would also be useful in state-of-theart techniques like 3D stacking of processors and memory,
where thermal effects are a significant concern. Finally,
HTFET designs can also be extremely useful in realizing
power-efficient, domain-specific accelerators [20].
Designing the HTFET processors used in the domains
stated above require efficiently re-designing constituent
digital circuit components present in these processors.
Energy-efficient adders, inverters and other combinational
logic have been demonstrated in prior efforts [22]. For
example, for the energy-delay performance of 32-bit
adders, the energy consumed by the HTFET adder is one
order less than that of a Si FinFET adder for the
requirement of 1 nS delay.

TG

One unique feature of TFET is the uni-directional

conduction ability, which turns out to be useful in
applications like charge pumps where the TFET are
working as switches. Fig. 5 shows a widely-used
conventional switch design using one single MOSFET.
When the switch is turned on, current could flow from
either terminal of the switch to the other, with the current
direction depending on the terminal voltage. When the
MOSFET in Fig. 5 is replaced by a TFET, this
bidirectional current conduction phenomenon is changed
to be uni-directional.

clkb

TG

D TG

B. Tunnel FET Analog Circuits Design Opportunities

TG

(a)
reset

reset
reset
clk
D
clkb

clkb

reset

clkb

Fig. 5. (a) Ideal On/Off switch; (b) NMOS switch with bidirectional
current conduction; (c-d) Uni-directional/bidirectional N-type/2N-type
TFET switches; (e) RF rectifier using TFETs.

clk

(b)

clkb
clk

clk
clkb

Fig. 5(e) shows a conventional rectifier topology in

which transistors behave as switches [18]. One major
power loss that limits the power conversion efficiency
(PCE) in CMOS rectifiers is the reverse leakage current.
Such leakage current transports the charge at the output
towards the input, resulting in significant undesirable
output voltage drop and efficiency degradation. In contrast,
the reverse leakage could be simply prevented using TFET
devices without modifications to the circuit topology.
Therefore, the PCE could be improved. Similarly, for
conventional DC-DC charge pumps, such bidirectional
conduction could also result in reverse leakage current.
[23]. In contrast, utilizing TFET in such designs could
reduce the reverse leakage current and improve the PCE.
Another feature that contributes to a higher PCE is the
steep-slope switching at low input voltage that helps to
reduce the turn-on resistance and accordingly, reduce the
power loss. As a result, compared with the Si FinFET, the
TFET enables both AC-DC conversion and DC-DC
conversion under a low input voltage with a higher PCE.
High gm/IDS helps to achieve high power efficiency in
analog designs. In [19], the authors presented a TFET

250
200

350

HTFET C MOS
HTFET TGFF
2
Si FinFET C MOS
Si FinFET TGFF

300

fCLK=80MHz

150
100
50
0

HTFET C MOS
HTFET TGFF
2
FinFET C MOS
FinFET TGFF

300

Delay [psec]

Average Power [nW]

Fig. 3. (a) TG (transmission gates) flip-flop and (b) C2MOS flip-flop.

250
200
150
100
50

0.3

0.4

0.5

0.6

VDD [V]

0.7

0.3

0.4

0.5

0.6

VDD [V]

0.7

Fig. 4. (a) Average power consumption, and (b) delay of C2MOS and
double TGs flip-flops at 0.3-0.7 V.

Flip-flop is a key component in digital circuits. In [17],

the energy efficiency and performance of TFET flip-flop
designs are discussed, where HTFET flip-flops reduce 2.5
times power consumption compared with the Si FinFET
designs. Fig. 4 shows the average power consumption and

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[2] A. Seabaugh et al, Low-Voltage Tunnel Transistors for Beyond

CMOS Logic, IEEE Proc., vol. 98, iss. 12, pp. 2095-2110, 2010.
[3] J. Knoch et al, A novel concept for field-effect transistors - the
tunneling carbon nanotube FET, in DRC '05, p.153-156, 2005.
[4] L. Knoll et al, Demonstration of improved transient response of
inverters with steep slope strained Si NW TFETs by reduction of
TAT with pulsed I-V and NW scaling, in IEDM, pp.4.4.1-4.4.4,
2013.
[5] S. Datta, et al., "Tunnel Transistors for Energy Efficent Computing"
in IEEE Int. Rel. Physics Symp. (IRPS), 2013.
[6] G. Dewey et al, Fabrication, characterization, and physics of III-V
heterojunction tunneling field effect transistors (HTFET) for steep
sub-threshold swing, in IEDM, p.33.6.1-33.6.4, Dec. 2011.
[7] D. K. Mohata et al. Demonstration of improved heteroepitaxy,
scaled gate stack and reduced interface states enabling
heterojunction Tunnel FETs with high drive current and high on-off
ratio in VLSIT, pp. 5354, Jun 2012.
[8] G. Zhou et al, "Novel gate-recessed vertical InAs/GaSb TFETs with
record high ION of 180A/m at VDS=0.5V," in IEDM, p.32.6.132.6.4, 2012.
[9] K. Tomioka et al, Integration of III-V nanowires on Si: From highperformance vertical FET to steep-slope switch, in IEDM,
pp.4.1.1,4.1.4, 2013.
[10] R. Rooyackers et al, A new complementary hetero-junction vertical
Tunnel-FET integration scheme, in IEDM, pp.4.2.1-4.2.4, 2013.
[11] L. Zhang et al, SPICE modeling of double-gate tunnel-FETs
including channel transports, TED, vol.61, no.2, p.300,307, 2014.
[12] H. Lu et al, Continuous Semiempirical Model for the Current
Voltage Characteristics of Tunnel FETs, in ULIS, 2014.
[13] U. E. Avci et al, Energy efficiency comparison of nanowire
heterojunction TFET and Si MOSFET at Lg=13nm, including PTFET and variation considerations, in in IEEE IEDM Tech. Dig.,
pp.33.4.1, 33.4.4, Dec. 2013.
[14] V. Saripalli et al., Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design, IEEE/ACM Int. Symp. on
Nanoscale Arch. (NANOARCH), vol. 1, pp. 4552, Jun. 2011.
[15] R. Pandey et al, Electrical Noise in Heterojunction Interband
Tunnel FETs, TED, vol.61, no.2, pp.552,560, Feb. 2014.
[16] I. Palit et al, TFET-based cellular neural network architectures, in
ISLPED, pp.236,241, Sept. 2013.
[17] M. Cotter et al, Evaluation of tunnel FET-based flip-flop designs
for low power, high performance applications, in ISQED,
pp.430,437, 2013.
[18] H. Liu, et al, TFET-based ultra-low power, high-sensitivity UHF
RFID rectifier, in ISLPED, pp.157-162, 2013.
[19] H. Liu et al, Tunnel FET-Based Ultra-Low Power, Low-Noise
Amplifier Design for Bio-signal Acquisition, in ISLPED, 2014
(accepted).
[20] K. Swaminathan et al, An Examination of the Architecture and
System-level Tradeoffs of Employing Steep Slope Devices in 3D
CMPs, in ISCA14, June, 2014 (accepted).
[21] K. Swaminathan et al, Modeling steep slope devices: From circuits
to architectures, in DATE, pp.1,6, 24-28 2014
[22] R. Mukundrajan, et al, Ultra Low Power Circuit Design using
Tunnel FETs" in ISVLSI2012, 2012.
[23] Dongsheng Ma, Rajdeep Bondade, Reconfigurable Switched
Capacitor Power Converters, Springer, 2013.
[24] Anne-Johan Annema et al, Analog circuits in ultra-deep-submicron
CMOS, JSSC, vol. 40, pp. 132-143, Jan. 2005.
[25] Murmann, B., "Digitally assisted data converter design," in 2013
Proc. of ESSCIRC, pp.24, 31, 2013.
[26] Staszewski et al, "All-digital PLL and transmitter for mobile
phones," JSSC, vol.40, no.12, pp.2469,2482, Dec. 2005.
[27] K. Swaminathan et al, Steep Slope Devices: Enabling New
Architectural Paradigms, in DAC, 2014 (accepted).

neural amplifier design employing a telescopic operational

trans-conductance amplifier (OTA) for multi-channel biosignal recording. For such amplifier design, low power to
prevent burning the body tissue, high gain and low inputreferred noise to sense weak signals are key design
specifications. By exploring the high gm/IDS advantage of
TFETs, the neural amplifier exhibited high current
efficiency, high voltage gain, and also low input-referred
noise. A noise efficiency factor was reduced significantly
compared to the theoretical limit of CMOS amplifiers.
With the transistor process scaling and the system
application developing, the analog circuits design is
becoming challenging [24]. On the one hand, the
requirements are more stringent with higher resolution,
faster speeds, lower power, and larger dynamic range. On
the other hand, the transistors are getting less dependable
in terms of matching, voltage range, leakage and
reliabilities even if getting faster. Under such
circumstances, more and more digital assisted/enhanced
techniques are being proposed to compensate these nonidealities, and analog circuits design are becoming more
and more digital. For example, digital calibration is
widely used in analog-to-digital converters (ADC) to
improve the effective number of bits (ENOB) and signalto-noise-and-distortion ratio (SNDR) [25]; Pre-distortion
could be applied to improve the linearity of power
amplifier (PA) and digital-to-analog converters (DAC)
[25]; Phase-locked loops (PLL) could even be built nearly
digitally [26]. Considering the fact that the advantage of
using TFET to build these digital assisting blocks remains,
TFETs will be showing more advantages in designing
future analog and mixed-signal circuits.
VII. CONCLUSION
In this paper, new opportunities of using the III-V
hetero-junction Tunnel FETs have been reviewed from
device, circuits, and system-level perspectives. Progress in
III-V Tunnel FET devices can have a significant impact on
the landscape of energy-efficient systems.
ACKNOWLEDGMENT
This work was supported by the LEAST, one of the six
SRC STARnet Centers, sponsored by MARCO and
DARPA. The NSF award 1205618 supported equipment
used in this effort.
REFERENCES
[1] Nikonov, D. E., et al, "Uniform methodology for benchmarking
beyond-CMOS logic devices," in IEEE IEDM Tech. Dig., p.25.4.125.4.4, 2012.

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Device Perspective on 2D Materials

Peide D. Ye
School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA
Tel: 1-765-494-7611, E-mail: yep@purdue.edu
be demonstrated. The third issue is related with transistor
dimension, which determines the packing density for a
single chip. For potential applications, the performance
limitation of MoS2 transistors associated with channel
length/width scaling must be investigated [5,6]. Due to the
surphur vacancy or charge neutral level of metal/MoS2
interface located at the vicinity of the conduction band
edge, MoS2 FETs perform as n-channel Schottky barrier
transistors. Phosphorene, complementing to MoS2, is a ptype channel material.[7,8] It provides a good addition to
the existing 2D family and provides great opportunities for
2D hetero-structures and hetero-integrations. Two
important building blocks for modern microelectronics,
CMOS and PN diode, are demonstrated using MoS2 as ntype and BP as p-type 2D materials.[7,10]

Abstract The rise of two-dimensional (2D) crystals has

given new challenges and opportunities to the device
research. The semiconducting MoS2 as n-channel and fewlayer phosphorene as p-channel have been considered as
promising
ultra-thin
body
channels
for
future
microelectronic and optoelectronic devices. In this paper, we
focus on the fundamental device properties of these 2D
transistors. In the first part of the paper, we demonstrate
high-performance MoS2 FETs with record drain current of
460 mA/mm and record low contact resistance of 0.5 mm
enabled by molecular chemical doping of 1,2 dichloroethane
(DCE). In the second part of the paper, we introduce a new
p-type 2D material called phosphorene which is one
monolayer of layered black phosphorus (BP). At room
temperature, the few-layer phosphorene field-effect
transistors with 1.0 m channel length display a high oncurrent of 194 mA/mm, a high hole field-effect mobility of
286 cm2/Vs, and an on/off ratio up to 104. We demonstrate
the possibility of phosphorene integration by constructing the
first 2D CMOS inverter of phosphorene PMOS and MoS2
NMOS transistors and the first BP/MoS2 PN diode for
photonic applications.

II. HIGH-PERFORMANCE MOS2 FETS

Fig. 1(a) schematically shows the MoS2 back-gate FET
fabricated in this work. Few-layer MoS2 flakes were
mechanically exfoliated from bulk MoS2 on a 90 nm
SiO2/p++ Si substrate and then soaked in 1, 2dichloroethane (DCE).[9] Acetone and isopropanol rinses
were used to remove the residue of the chemical. After ebeam lithography, Ni (30 nm)/Au (60 nm) were deposited
to form S/D contacts. The thickness of the MoS2 flake was
identified by the optical image and measured by the AFM.
The flake thickness was about 4 nm, corresponding to ~6
layers. The presence of Cl in DCE treated MoS2 film was
confirmed by XPS and SIMS. We observe a relative blue
shift in the binding energies of the core level peaks of the
MoS2 sample that was treated with DCE, which results
from an upward shift in the Fermi level, and hence can be
attributed to an n-type doping of the sample. However, we
note that Cl, when acts as an adatom dopant, results in ptype doping in MoS2 film. Thus, such n-type doping can
be attributed to the donation of extra electron when
substitution of S2- by Cl- takes place, particularly at the
sites of sulphur vacancies in the MoS2 film.

Index Terms 2D materials, MoS2, black phosphorus,

phosphorene.

I. INTRODUCTION
Transition metal dichalcogenides (TMDs), typically MoS2,
show good potentials in device applications due to a
satisfied band gap, thermal stability, carrier mobility, and
compatibility to silicon based CMOS process [1-3]. In
order to realize high-performance MoS2 MOSFETs, three
major issues need to be completely addressed: how to
achieve a high-quality interface between 2D crystal and
dielectric, how to achieve a low-resistivity metalsemiconductor junction, and device performance at scaled
dimensions. Although the high-k dielectric has been
successfully demonstrated previously [4], the interface
quality between high-k dielectric and 2D crystal needs to
be systematically studied. High-k dielectric thickness
needs to be scaled along with the channel length and
width. Secondly, as the material cannot be effectively
implanted due to the ultrathin nature, the contact
resistance (Rc) is mostly determined by the Schottky
barrier height (SBH) at the MoS2/metal interface. Contact
metal and doping engineering are needed to realize low
resistivity contacts so that high-performance 2D FETs can

978-1-4799-3622-9/14/$31.00 2014 IEEE

The TLM resistances of MoS2 FETs at Vbg = 50 V with

and without the Cl doping are plotted as a function of
contact separations in Fig. 2. The extracted Rc is
significantly reduced from 5.4 km to 0.5 km after
the Cl doping. Such an improvement in Rc is attributed to
the doping induced thinning of tunneling barrier width.

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at Vds = 1.6 V, which is twice of the best reported value so

far on MoS2 FETs at the same Lch [9]. The components of
total resistance (Rtotal) indicate mitigation of the adverse
dominance of high Schottky S/D contact resistance (Rsd) at
100nm Lch. Such reduction in Rsd also results in excellent
current saturation, as observed in Fig. 3. The transfer
characteristics of the two devices are also measured. Due
to its relatively large bandgap and ultra-thin channel, we
achieved an excellent Ion/Ioff of ~6.3105. Considering the
large gate oxide thickness (90 nm) used in this work, the
Ion/Ioff ratio can be further improved by EOT scaling down.
The intrinsic long channel field-effect motility (FE) as a
function of gate electric field is calculated with different
Lch, with a peak FE of 50-60 cm2/Vs.

We observe that the extracted Rc is a weak function of

temperature, indicating the dominance of tunneling
component of the current over thermionic component at
(a)

(b)

Cl
S
Mo

Source
Ni/Au

Drain
Channel

Ni/Au

Gate (90 nm SiO2)

P++ Si Substrate

600

w/ Cl doping
w/o Cl doping
500
Vg = -50 V to 50 V

Fig. 1 (a) Schematic of the MoS2 back-gate FET fabricated in this

work. The gate dielectric is 90 nm SiO2. The S/D contact metal is Ni
(30 nm)/Au (60 nm). (b) Process flow for the MoS2 back-gate FETs
with the exfoliated MoS2 flakes.

Ids (A/m)

the contact interface. In order to determine the c, the

transfer lengths (LT) of Ni-MoS2 junctions are extracted
by the TLM and are determined to be 60 and 590 nm for
the contacts w/ and w/o the Cl doping, respectively.
Compared with the Ni-MoS2 contacts without the Cl
doping, the c is reduced from 310-5 cm2 to 310-7
cm2 when the DCE treatment time is 36 hours. The
doping concentration (Nd) is ~2.31019 cm-3 extracted
from the slope of the TLM fitting when Vbg is 0 V. The
present Cl doping technique with DCE treatment is also
valid for the other TMD materials such as WS2 [11],
whose EF is pinned near the middle of the bandgap.

Rtotal (km)

25

0.8
1.2
Vds (V)

1.6

Preceding the current interest in layered materials for

electronic applications, research in the 1960s found that
black phosphorus combines high carrier mobility with a
fundamental band gap. We introduce its counterpart,
dubbed phosphorene, as a new 2D p-type material as
shown in Fig.4. Same as graphene and MoS2, single-layer
phosphorene is flexible and can be mechanically
exfoliated. We find phosphorene to be stable and, unlike
graphene, to have an inherent, direct and appreciable
band-gap that depends on the number of layers. The
observed photoluminescence peak in the visible
wavelength from single-layer phosphorene indirectly
confirms the widening of the bandgap as predicted by
theory. Our transport studies indicate a hole mobility that
reflects its structural anisotropy and is complimentary to
MoS2. At room temperature, our few-layer phosphorene
field-effect transistors with 1.0 m channel length display

10
Rc = 5.4 km
0.5 km

0.4 0.8 1.2

gap (m)

0.4

III. WELL-BEHAVED FEW-LAYER PHOSPHORENE FETS

15

0
0.0

200

Fig. 3 Output characteristics of the 100 nm Lch MoS2 FETs w/ and

w/o the Cl doping. A record high Ids of 460 A/m is obtained.

20

Lch= 100 nm

0
0.0

(b)

w/ Cl doping
w/o Cl doping

300

100

(a)

30

400 step = 20 V

1.6

Fig. 2 (a) TLM resistances of MoS2 FETs w/ and w/o the Cl doping
at Vbg = 50 V. The Rc is reduced from 5.4 km to 0.5 km (b)
Band diagram of the metal-MoS2 contacts w/ and w/o the Cl doping.

Fig. 3 shows the output characteristics of 100 nm Lch

MoS2 FETs with and without the Cl doping. The reduced
Rc helps to boost the Ids from ~ 110 A/m to 460 A/m

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Table of Contents

a high on-current of 194 mA/mm, a high hole field-effect

mobility of 286 cm2/Vs, and an on/off ratio up to 104.

Fig. 4 Crystal structure and band structure of few-layer phosphorene.

Left: a perspective side view of few-layer phosphorene. Right: side and
top views of few-layer phosphorene.

We proceed to fabricate transistors of this novel 2D

material in order to examine its performance in actual
devices. We employed the same approach to fabricate
transistors with a channel length of 1.0 m as in our
previous transport study. We used few-layer phosphorene
with a thickness ranging from 2.1 to over 20 nm. The I-V
characteristic of a typical 5 nm thick few-layer
phosphorene field-effect transistor for back gate voltages
ranging from +30 V to -30 V, shown in Fig. 5, indicates a
reduction of the total resistance with decreasing gate
voltage, a clear signature of its p-type characteristics.
Consequently, few-layer phosphorene is a welcome
addition to the family of 2D semiconductor materials,
since most pristine TMDs are either n-type or ambipolar
as a consequence of the energy level of S vacancy and
charge neutral level coinciding near the conduction band
edge of these materials. Only in few cases, p-type
transistors have been fabricated by externally doping 2D
systems using gas adsorption, which is not easily
practicable for solid-state device applications. The
observed linear I-V relationship at low drain bias is
indicative of good contact properties at the
metal/phosphorene interface. We also observe good
current saturation at high drain bias values, with the
highest drain current of 194 mA/mm at 1.0 m channel
length at the back gate voltage Vbg=-30 V and drain
voltage Vds=-2 V. The transfer curves for drain bias values
Vds=0.01 V and 0.5 V, which indicate a current on/off
ratio of ~104, a very reasonable value for a material with a
bulk band-gap of 0.3 eV. We also note that the band gap
of few-layer phosphorene is widened significantly due to
the absence of inter-layer hybridization between states at
the top of the valence and bottom of the conduction band.

Fig. 5 Device performance of p-type transistors based on few-layer

phosphorene.

transistors, field-effect mobility shows a strong thickness

dependence. It peaks at around 5 nm and decreases
gradually with further increase of crystal thickness. Such
trend can be modeled with screening and inter-layer
coupling in layered materials, as proposed in several
previous studies. A more dispersive mobility distribution
is observed for few-layer phosphorene transistors. This is
due to the fact of anisotropic mobility in few-layer
phosphorene or black phosphorous as discussed in
previous parts, and the random selection of crystal
orientation in device fabrication. Thus carrier transports
along at any directions between the two orthogonal ones
in the x-y plane. Therefore, two curves are modeled for
phosphorene transistors, as shown in Fig. 6, where the red
and green curves showing the fittings with mobility peak
and valley, respectively. Current on/off ratio is a typical
decreasing trend along with increase of crystal thickness.
It steeply drops from ~105 for a 2 nm crystal to less than
10 once the crystal thickness is over 15 nm. This suggests
the importance of crystal thickness selection of
phosphorene transistors from the device aspects.
Transistors on a 4-6 nm crystal display the best tradeoff
with higher hole mobility and better switching behavior.
IV. 2D CMOS AND PN DIODE
We demonstrate the possibility of phosphorene integration
by constructing the first 2D CMOS inverter of
phosphorene PMOS and MoS2 NMOS transistors.[7]
Phosphorene in combination with other 2D materials also
provides unique 2D heterojunctions whose electrical and
optical properties need to be further explored. One of the
examples is a BP/MoS2 2D heterojunction as a 2D PN
diode, a basic building blocks of modern electronic and
optoelectronic devices. In Ref. 10, we demonstrate a gate
tunable p-n diode based on a p-type black phosphorus/ntype monolayer MoS2 van der Waals PN heterojunction.
Upon illumination, these ultra-thin p-n diodes show a

We further compare field-effect mobility in few-layer

phosphorene transistors with various crystal thicknesses.
Field-effect mobilities extracted from devices fabricated
on phosphorene crystals with various thicknesses are
displayed in Fig. 6. Similar to previous studies on MoS2

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Table of Contents

maximum photodetection responsivity of 418 mA/W at

the wavelength of 633 nm, and photovoltaic energy
conversion with an external quantum efficiency of 0.3%.
These PN diodes show promise for broadband
photodetection and solar energy harvesting.

Fig. 7 (a) and (b) Schematics of the device structure. A p+ silicon

wafer capped with 285 nm SiO2 is used as the global back gate and
the gate dielectric. Few-layer black phosphorus flakes were
exfoliated onto monolayer MoS2 in order to form a van der Waals
heterojunction. Ni/Au were deposited as contacts. During the
electrical measurements, a voltage Vd is applied across the device.
The voltage bias Vg is applied to the back gate. (c) Gate tunable IV
characteristics of the 2D p-n diode. The current increases as the
back gate voltage increases.

ACKNOWLEDGMENT
The work presented here is in close collaborations with H.
Liu, L.M. Yang, A.T. Neal, Y. Du, Y. Deng, Z. Luo, N.J.
Conrad, X. Xu, Z. Zhu, D. Tomanek, K. Majumdar, W.
Tsai, Y. Gong, S. Najmaei, P. M. Ajayan, J. Lou, and
others. The work is supported by SEMATECH, SRC and
NSF.

Fig. 6 Mobility summary of few-layer phosphorene and black

phosphorus thin film transistors with varying thicknesses. Red and
green lines are models with light and heavy hole masses for
phosphorene, respectively.

We studied the electrical characteristics of the fabricated

device shown in Fig. 7(a) and (b). All the measurements
were performed in ambient atmosphere. Fig. 7(c) shows
the gate tunable I-V characteristics of the p-n diode, and
the inset shows the I-V curves on a semi-log plot. By
using a -30 V back gate voltage, a ~105 on/off ratio is
obtained at Vd = -2/+2 V. These strong current-rectifying
characteristics indicate that a good van der Waals p-n
heterojunction formed between p-type black phosphorus
and n-type MoS2. The modulation effect of the back gate
voltage can be more obviously seen in the transfer curves.

REFERENCES
[1] B. Radisavljevic, A. Radenovic, J. Brivio, V. Giacometti and A. Kis,
Nat. Nanotechnol. 6, 147 (2011)
[2] H. Liu, and P. D. Ye, IEEE Elect. Dev. Lett. 33, 546 (2012)
[3] H. Liu, M. Si, S. Najmaei, A. T. Neal, Y. Du, P. M. Ajayan, J. Lou
and P. D. Ye, Nano Lett. 13, 2640 (2013)
[4] H. Liu, K. Xu, X. J. Zhang and P. D. Ye, Appl. Phys. Lett. 100,
152115 (2012)
[5] H. Liu, A. T. Neal and P. D. Ye, ACS Nano 6, 8563 (2012)
[6] H. Liu, J. J. Gu and P. D. Ye, IEEE Elect. Dev. Lett. 33, 1273 (2012)
[7] H. Liu, A.T. Neal, Z. Zhu, Z. Luo, X. Xu, D. Tomanek, and P.D. Ye,
ACS Nano 8, 4033 (2014)
[8] L. Li, Y. Yu, G.J. Ye, Q. Ge, X. Ou, H. Wu, D. Feng, X.H. Chen,
and Y. Zhang, Nature Nanotechnology 9, 372 (2014)
[9] L. M. Yang, K. Majumdar, Y. C. Du, H. Liu, H. Wu, M.
Hatzistergos, P. Y. Hung, R. Tieckelmann, W. Tsai, C. Hobbs, P. D.
Ye, Symposia on VLSI Technology and Circuits (VLSI 2014),
pp.192-193, 2014.
[10] Y. Deng, Z. Luo, N.J. Conrad, H. Liu, Y. Gong, S. Najmaei, P.M.
Ajayan, J. Lou, X. Xu, and P.D. Ye, ACS Nano 8,
10.1021/nn5027388, (2014)

IV. CONCLUSION
We use MoS2 and phosphorene as examples to show that
well-behaved transistors can be demonstrated on these van
der Waals 2D materials for both n-type and p-type
channels. To compete with the existing transistor
technology, much more efforts are needed in dielectric
integration, contact engineering, scaling research are
needed. We also demonstrate the feasible way to integrate
n-type and p-type 2D materials on the same platform to
form CMOS and PN diodes for future microelectronics
and photonics applications.

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Table of Contents

Advances on III-V on Silicon DBR and DFB Lasers for WDM

optical interconnects and Associated Heterogeneous Integration
200mm-wafer-scale Technology
S. Menezo, H. Duprez, A. Descos, D. Bordel, L. Sanchez, P. Brianceau, L. Fulbert, V. Carron, and B. Ben Bakir
CEA-Leti, Minatec Campus, 17 rue des Martyrs, F-38054 Grenoble cedex 9, France
sylvie.menezo@cea.fr
Silicon photonic devices and integrated circuits have
considerably increased in manufacturing maturity, being
recently transferred from research to industrial foundries
for the commercialization of high speed electro-optical
transceivers. The development of 300mm-Silicon
photonics platforms was recently reported with a broad set
of integrated devices, including surface grating couplers,
modulators, photo-detectors [1] and Wavelength Division
Multiplexing (WDM) devices [2]. The opportunity to
tightly integrate the Silicon Photonic Integrated Circuits
(Si-PIC) with their driving and reading CMOS-Electronic
Integrated Circuitries (CMOS-EIC) leverages transceivers
performances. 3D-assemblies are preferred to front end
integration, as the EIC and PIC dont scale identically in
terms of processing nodes and footprints. The authors of
[1] recently reported the capability for 25Gb/s
transceivers, where the EIC and PIC are assembled by
means of 3D-copper pillars, with 40m-pitch and 20mdiameter.
In the absence of practically efficient lasers achievable
directly in Silicon or other group IV materials, Si-photonic
transmitter sources must be made by Hybrid integration
of III-V chips or Heterogeneous integration with III-V
gain materials.
Hybrid integration technologies consist in
integrating processed (and finished) chips in a photonic
microsystem. One commercial solution (from LUXTERA)
makes use of a InP-bulk-processed laser-chip [3]. The
laser chip is attached to the PIC, and its light is coupled
into the PIC-waveguide by means of a lens, followed by
an optical isolator, and a mirror for directing the light to a
surface grating coupler in the Si-PIC. Other approaches
(from KOTURA/ORACLE) consist in but-coupling a IIIV-semiconductor reflective-SOA to the PIC-3m-thickSi-waveguide that comprises a Bragg-mirror for defining
the laser cavity [4]. This forms an external-cavity DBR
laser, with reported Waveguide-Coupled Wall-PlugEfficiencies (WC-WPE) for the uncooled lasers of up to
9.5% at powers of 6 mW. In spite of the good
demonstrated performances, this solution requires an
accurate alignment between the R-SOA and the Si-PIC,
limiting the capability for a low cost fabrication.

978-1-4799-3622-9/14/$31.00 2014 IEEE

As a more economical route that we opted for,

Heterogeneous integration technologies were proposed
[5], [6] together with new laser architectures. An InPwafer having the III-V-gain-layers grown on top is bonded
with loose alignment requirements (~50m), the III-V
gain-layers facing down to the bottom Silicon-OnInsulator (SOI) wafer on which silicon waveguides are
pre-processed.

III-V dies
Processed SOI
wafer

InP substrate

Figure 1:
Top: III-V bonded dies on
on a processed SOI wafer.
Middle: Zoom on a
bonded III-V die: InP
substrate with III-V
gain epi-layers facing
down.
Bottom: III-V die after
removal of the InP
substrate.

In a more economical route,

the InP-substrate having the
laser III-V-gain-layers on top
300 m
is first diced, and the dies are
bonded where needed (Figure
1). Then the InP-substrate is
removed, and the laser process
III-V gain epiis continued on the remaining
layers
III-V gain epi-layers, in a
300 m
regular wafer level process
flow. Putting the expensive IIIV-gain material only where needed saves on cost. In
addition to lower cost, photonic integration promises
improved reliability and performances and reduced
footprints over discrete components systems.
This paper will report on our recent advances on both,
1) the developed III-V on Silicon lasers (DBR and DFB
types) built up from heterogeneous integration, and, 2) the
development of the integration technology for processing
the lasers on 200mm-wafers, with industrial CMOS tools.
III-V gain epi-layers

118

Table of Contents

In a first part, our III-V

V/Si laser arch
hitecture will be
nd the design and performan
nces of differeent
reminded, an
types of reson
nators will be reported.
r
They are:
- tunable DBR
R-laser-arrays with 4 waveleengths, thresholdcurrents belo
ow 20mA, and
d Waveguide--Coupled opticcal
powers in thee range of 15mW
W [7],
- a newly-deemonstrated DFB laser with
h a WC-WPE of
>13% at a 40mW-opticaal-power (20m
mW at the tw
wo
outputs of thee Si-waveguidee).
The reported lasers are fabrricated from 200mm-processsed
P-wafers. Affter
SOI-wafers, with bondeed 75mm-InP
bstrates, the SOI
S
wafers are
a
removal of the InP sub
o 100mm-diam
meter-wafers, an
nd the lasers are
a
downsized to
further processsed on 100mm
m-wafers.
In a seco
ond part, an overview
o
will be given of the
t
integration technology
t
wee have been developing for
f
processing th
he lasers on 200mm-wafers
2
, with industrrial
CMOS tools,, in a cost efffective way. This
T
includes the
t
front end fabrrication steps of
o collective bonding
b
of III-Vdies to SOI-w
wafers and ettching of the IIII-V-laser-mesaa.
The backend
d processing of the laser-ccontacts will be
detailed in a future communication. The fiirst
n will be reported of Con
ntinuous Waveedemonstration
operating-DF
FB lasers that are fabricated on the 200mm
mwafer-platform
m.

surfacee-grating coupller for couplinng the laser outtput light

into a ffiber, if neededd (without thee latter, the laser output
is kept within the siliccon waveguidee).
4 00m
a)

Adiiabatic taper

R~
~100%

~50%
R~
III-V Gaiin epi-layers

b)

Fiber
co
oupling

Si waaveguide

c)

AA

6m

Si-waveguide
co
oupling

AA
III-V epii-layers
SOI wav
veguide

Figure 2 Schematic Sketch of the ddevice architectture: DBR

structurre. The III-V waaveguide, providding with the opttical gain,
is superrimposed over a silicon rib tappered waveguidee enabling
adiabatiic coupling from
m/to the upper waaveguide. The laaser cavity
is defineed by the two sidde DBRs, and ligght can be colleccted in the
Silicon w
waveguide or byy a fiber via a suurface grating cooupler.
a) top view b) sidee view c) crross section off the twowaveguiide-system.

The DB
BRs are definned in a 10-
m-wide Si-waaveguide.
Their ggratings have a 50% filling factor, and arre 10nmetched. The total refleection-DBR is 300m-long, w
while the
R is 100m
m-long. The grating
partial--reflection-DBR
strengthh is 83 cm-1, leading to a modal reflecctivity of
97.3% and 46.4%, respectively. Current injeection is
achieveed via a protoon-implanted InGaAsP-baseed tunnel
junctionn and a 2m-thhick graded p-doped InP connfinement
layer iss used for prevventing implantt defects from reaching
the actiive region.

PART I- III-V
V/SI LASER ARCHITECTURE
E DBR & DF
FB
LASER STRU
UCTURES AND MEASURED PERFORMANCE
ES
Several resonator strructures havee been alreaady
implemented for the heterogeneous III-V laser integratiion
w
on SOI. Sincce the first III--V on SOI raccetrack laser was
realized back
k in 2007 [5], [6], electricallly-pumped lasser
prototypes su
uch as DBR- and DFB-baseed emitters weere
demonstrated
d by INTEL UCSB, and AURRION
A
In
nc.,
respectively [8], [9]. In alll these approaaches, the opticcal
i mainly con
nfined within the
t
mode in the laser cavity is
passive silico
on waveguide. It is evanescently coupled in
the III-V mesa structure for light am
mplification. Th
his
results in a poor confinem
ment in the IIII-V gain layeers,
which limits the modal gaain experienced by the opticcal
field.
oup at CEA-L
Leti
The approach developeed in our gro
s
skettch
implements a two-waveguide-system. A schematic
of the devicee architecture is reported in Figure 2, forr a
DBR-resonator-structure. A III-V wav
veguide and an
on waveguidee are verticaally
adiabatically--tapered silico
stacked by means
m
of a 100-nm-thick silicca bonding lay
yer.
The top wav
veguide, fabriccated in a III--V InP/InGaA
AsP
hetero-structu
ure, provides the optical gaain. The botto
om
Silicon waveeguide comprises, 1) two distributed
d
Braagg
reflectors (D
DBR) for defin
ning the laserr cavity, 2) tw
wo
adiabatic tapers for couplin
ng the opticall mode from the
t
silicon waveg
guide to the IIII-V top waveeguide, and, 3)) a

P-ccontact

Adiabaatic taper

Surfa
ace
coup
pler

DBR

N-ccontact

DBR

F
Figure 3: -top:
measuured DBR-laser
outpuut power versus
drivving current, at
several dietempeeratures; power
coupleed in the silicon
waveguuide (right) and
in the opttical fiber (left)
bottom
m: fiber coupled
powerr versus current
(lef
eft), laser diode
vvoltage (right).

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Table of Contents

Static and dy
ynamic characterizations of th
he 1.55m-ran
nge
DBR laser were
w
performeed, collecting the laser outp
put
power throug
gh a multi-mod
de fiber aligned
d over the surfaace
grating coupller. As reporteed in Figure 3,
3 the DBR lasser
operates con
ntinuous-wave up to a diee-temperature of
65C. At 20C, the threshold current is 17 mA and the
t
output powerr coupled in the
t Si-waveguide (respectiveely
coupled in the multi-mode fiber) is above 15 mW
m
ving current. The
T
(respectively 4.5mW) at a 160 mA-driv
h a turn-on voltage of 1 V and a series
laser diode has
resistance of 7.5 ohms. Thee laser Side Mode
M
Suppressiion
R) is above 50
5 dB (see Figure
F
4 with
h a
Ratio (SMSR
118mA-drivin
ng current).

BR-laser arrayy designed wiith a 12-nm sppacing is

A 4-DB
reporteed in Figure 7. A fine tailorinng of the DBR
Rs period
matching
is usedd for adjustingg longitudinal modes phase-m
and achhieving precisee wavelength aaddressing. Thee average
SMSR is 40 dB.
0

DB
BR period (nm):

-10

235
237
239
241

10 dB/div

-20
-30
-40
-50
-60
-70
-80

Figuree 4: Lasing
spectrum measured att
118 mA
A.

1520

1540

1560

1580

1600

Wavelength ((nm)

Figure 7: 4 DBR-laser arrray spectrum

By adding
a
on the
t
total-rreflection DBR
Ra
resistiive NiCr fiilm
used as a heaater
peeak
elemeent,
reflecctivity and phasse-

As a coonclusion for the DBR laserr structure, higgh-indexcontrasst shallowly-coorrugated gratiings can be efficiently
used a s DBR reflecttors of Fabry--Prot lasers, ensuring
modal selectivityy and low thresshold devices.
high m
more stronglyy corrugated silicon
Annalogously, m
gratinggs can be usedd for implem
menting other rresonator
DFB). As
structurres such as, diistributed feeddback lasers (D
illustratted in Figuree 8, a distribbuted feedbackk (DFB)
gratingg is etched oover the bottoom-silicon waaveguide,
providiing enough moodal reflectivitty to achieve lasing at
low thrreshold. A /4--long defect att the center of the DFB
gratingg ensures moddal selection an
and precise waavelength
addresssing. By usingg the aforementtioned adiabatiic silicon
400m
Si

SiO
O2

InP

Figure 5: Wavelengtth tuning of the DBR

D laser

Figure 8: Sidee view of the DFB

B laser structuree

matching condition of lon

ngitudinal mo
odes are varieed,
w
tun
ning range of 20
resulting in a continuous wavelength
nm as shown in Figure 5.

tapers, the optical moode is guided aand amplified iin the IIIV activve region. Theere, it is evaneescently coupleed to the
Si/SiO22 DFB gratingg. A III-V phootodiode and a surface
gratingg coupler are inntegrated at the two ends of the DFB
laser ffor measuring the laser ouutput power aavailable,
respecttively, in the siilicon waveguiide and in a m
multimode
fibre. T
The optical behhaviour of the laser is determ
mined by
the DFB
B grating desiggn and how thhe supermode iin the IIIV reggion overlap with it. Thherefore, the grating
dimenssions and corruugation strengtth factors as well as the
SiO2 gaap between thee silicon and thhe III-V wavegguides are
crucial for the laser design, as theese parameters strongly
impact on the couppling strengthh. Figure 9 ggives the
computted strength,
, of the DFB ggrating as a fuunction of
both thhe thickness and the widdth of the sillicon rib

The electro--optic
(EO) small-ssignal
modulation
response obtaained
for
drriving
currents betw
ween
6 x Ith and 8 x Ith
indicates a -3dB
bandwidth off 7.2
GHz.
Figure 6: DBR laser Reesponse to small signal modulatiion

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Table of Contents

the III--V photodiode coupled at onne end of the laaser. The

generatted photocurreent is measured to be ~27 m
mA when
the DF
FB laser is ddriven with 1150 mA (Figgure 11).
Assumiing that all thhe light is couppled and absorrbed into
the phhotodiode (eqquivalent to aassuming a 1.25A/W
responssivity at 1.55
m), we conseervatively estim
mate that
the onee-side emitted power at 150 mA is well abbove 21.6
mW. A >13% W
WC-WPE is estimated frrom this
measurrement and froom the measuurement of thee voltage
versus current at the llaser diode.

waveguide, when
w
using a 100nm-SiO2 bo
onding layer. The
T
choice is mad
de for Si rib widths above 0.7
7 m, for which
hk
is above 10ccm-1. The .L value is set from
fr
1 to 1.5 by
varying the grating lengths between 400 m
and 1000 m,

m
reflectiv
vity R, R = tan
leading to a modal
nh 2 ( DFB .LDFB ) in
the range of [60[
80]%.

Figure 9: Stren
ngth of the DFB
B grating as a function
fu
of both the
thickness and the
t width of the silicon rib waveeguide, when usiing
a 100 nm-SiO2 bonding layer.

The DFB graatings were deffined by 193-n

nm-deep DUV or
by electron-beam lithograph
hy, leading to similar
s
results.
Static measurrements of the first fabricated
d DFB lasers are
a
reported belo
ow. The laserr operates con
ntinuous-wave at
room-temperaature, with currrent threshold
ds below 60 mA
m
(Figure 10). The
T laser outpu
ut power can be
b measured with
w

F
Figure 12: Laserr spectrum at sevveral bias currents

SMSR is abovee 30 dB.

As repoorted in Figuree 12, the laser S

PARTT II- OVERVIE

EW OF THE 200
0MM-WAFER-S
SCALE
INTEGR
RATION TECH
HNOLOGY
As the heterogeeneous III-V//Si laser designs are
progresssing quickly, showing perfoormances closee to bulk
III-V laasers, effort iss put in paralleel for developing large
scale annd low cost fabbrication technnologies. A fulll CMOScompattible processinng technologyy is being ddeveloped
within the frame of the Frennch national program
Avenir, IRT N
Nanoelec
prograamme dInvesttissements dA
ANR-100-AIRT-05: this includes thee front end faabrication
steps oof collective bbonding of III--V-dies to SOII-wafers
wafers.
and ettching of the IIII-V-laser-mesaa on 200mm-w

Figure 10: DFB

B output power coupled in the multimode
m
fiber
(left), laser diode voltage (right), versus curren
nt

As view
wed in the inntroduction parrt, III-V-dies to SOIwafer bbonding is prreferred to IIII-V-wafer to SOI-wafer
bondingg, as puttingg the expensivve III-V-gain material
only w
where needed saves on costt. Figure 13 ggives the
differennt stages of thee process. Thee direct bondinng is very
sensitivve to any partticle contaminnation. As an example,
when bbonding two waafers, the diam
meter of a bondded defect
is 1,0000 to 10,000 tim
mes bigger thatt the defect it ooriginates
from, pprior to the bbonding. The dicing is theerefore a
critical step as it geenerates particlles. A fret-saw
w with a
andard dicing ttool. The
40m-tthick blade is used as a stan

Figure 11: DFB

FB output power coupled, in the multimode
m
fiber
(left), in the IIII-V photodiode (right)
(r
versus currrent

121

Table of Contents

We further develooped the III-V dry etching prrocess on

m-wafers for defining thhe laser messa.
A
200mm
CH4/C
Cl2/Ar based chhemistry is useed on an AMAT DPS II
mm. The
HT chhamber retrofittted from 3000mm to 200m
chuck ttemperature haas been fixed at 200C wherreas wall
and toop electrode are at 60C. Optical emission
spectrooscopy is used for controllinng the etching depth. A
SEM ccharacterizationn of the etchedd III-V-mesa iss showed
in Figuure 15.

dicing is fo
ollowed by a high pressurre spraying. An
A
intermediate silicon wafer serving
s
as a ho
older is used: the
t
t
III-V dies arre placed insiide cavities ettched within the
holder, the IIII-V epi-layerss facing up. An
n automatic piick
and place eq
quipment is being assessed for loading the
t
holder with high through
hput (1,000 dies
d
per 300m
mm
a then colleectively clean
ned
wafer). The III-V dies are
d processed SOI
(plasma and brush). The receiving and
ned and bonded
d on the holderr.
wafer is clean
Pick and place the III-V dies
on an intermediiate Si-wafer,
III-V epi-lay
yers facing up
III-V epi-lay
yers
InP
III-V epi-layers
grown on a 75m
mmInP wafer

o the
Dicing of
75mm-InP
P wafer
200mm- in
ntermediate Si wafeer
holder
Collective bonding of the III-V
dies by direect bonding of the
intermed
diate wafer to the
processsed-SOI wafer.
III-V epi-lay
yers facing down.
200mm- receiv
ving
processed SOI wafer

Figure 13: Stag

ges of the collecctive bonding of III-V-dies
I
to
SOI-wafer

Figure 14 iss a collection

n of acoustic characterizatio
onpictures of seeveral bonded InP-dies, each
h 1x1mm. No
ote
that the dies appear to be tilted
t
while th
hey are not wh
hen
p
A 80
0%
bonded (tilts come from assembling the pictures).
bonding yield is estimated
d while 70% of the dies are
a
bonded witho
out any defect.

Figuure 15: SEM chaaracterization off the etched III-V

V mesa

Figgure 16 is a picture of the completeed laserm wafers.

fabricattion on 200mm

Figure 16: IIII-/SOI laser fabriication [200mm wafer]

Figure 14: colllection of acousttic characterizattion-pictures of

several bonded
d InP-dies, each 1x1mm - tits beetween dies comee
from assemblin
ng the pictures

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Table of Contents

This firstt fabrications lead to DFB lasers operatiing

Continuous Wave
W
at room temperature. A laser spectru
um
is given in Fig
gure 17 for a 250mA-bias
2
cu
urrent.

REFERENCESS
[1] F. Boeuf, et. al., A Multi-Waavelength 3D-C
Compatible
m SOI Wafers fo
for 25Gb/s
Silicon Photonics Platfform on 300mm
Applicaations, IEDM 20013
[2] D. F
Fowler, e.a., C
Complete Si-Phootonics Device-llibrary on
300mm wafers, OFC 22014
[3] P. De Dobbelaeree, e.a., Silicoon Photonics teechnology
platform
m for high speed interconnect, S
Semiconwest, occt. 2013.
[4] A.J. Zilkie, Power--efficient III-V/S
Silicon external ccavity
DBR lassers, Optics Exxpress 2012.
[5] A. W
W. Fang, R. Jonnes, H. Park, O. Cohen, O. Radday, M. J.
Panicciaa, and J. E. Bowers, Integrated AlGaInA
As-silicon
evanesccent race track llaser and photoddetector, Opt. Exp., vol.
15, pp. 22315-2322, 20077.
[6] B. Ben Bakir, e.a.., Hybrid Si/IIII-V lasers withh adiabatic
couplingg, Optics Expreess 2011.

Figure 17: DF
FB laser spectrum
m from a fabrica
ation on 200mm
wafers

[7] A. D
Descos, e.a., Heeterogeneously Inntegrated III-V/S
Si
Distribuuted Bragg Refleector Laser with Adiabatic Couppling,
ECOC 22013.

CONC
CLUSION

[8] M. JJ. R. Heck, e.a., Hybrid silicon photonics for opptical

interconnnects, Selectedd Topics in Quanntum Electronicss, IEEE
Journal of , vol. 17, no. 2, pp. 333-346, March-April 20011.

As the heeterogeneous III-V/Si laseer designs are

a
progressing quickly,
q
showing performancces close to bu
ulk
III-V lasers,, we develop
p in parallel the associatted
fabrication teechnologies, with
w
large scale and low co
ost
manufacturin
ng capability. We
W further ded
dicate our curreent
work to the improvement
i
of
o the temperaature behavior of
the lasers fo
or uncooled and
a
semi-coolled operation at
1.31m, tarrgeting opticaal interconneects with lin
nkconsumptionss below 1mW/Gbps [10].

[9] B. R
R. Koch, e.a., Inntegrated Siliconn Photonic Laserr Sources
for Teleecom and Datacoom, in OFC 20013, paper PDP5C.8.
[10] S. Menezo, e.a., Evaluation of ooptical interconnnects built
m a complete CMOS-Photoniics-devices-libraary, OIC
up from
2013.

ACKNOW
WLEDGMENT
This work waas supported by
b the French national
n
prograam
programme dInvestissemeents dAvenir, IRT Nanoellec
RT-05.
ANR-10-AIR

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OPTICAL PHASE-LOCKING AND WAVELENGTH SYNTHESIS

M.J.W. Rodwell1, H.C. Park1, M. Piels1, M. Lu1, A. Sivananthan1,
1
2
2
1
1
1
E. Bloch , Z. Griffith , M. Urteaga , L. Johansson , J. E. Bowers , L.A. Coldren
1

ECE Department, University of California, Santa Barbara, CA 93106.

2
Teledyne Scientific, Thousand Oaks, CA 91360 USA.
consideration of increasing concern as optical links
approach the fiber capacity [5].

Abstract We describe techniques for phase-locked

coherent optical communications, including wavelength
synthesis for wavelength-division-multiplexed optical
communications, compact coherent BPSK receivers, and
coherent demodulation of WDM in the electrical domain.
Index Terms Coherent optical communications, phaselocked-loops, frequency synthesis, wavelength-divisionmultiplexing

I. INTRODUCTION:
Prior to the widespread adoption of phase-locked loop
frequency synthesizers [1], transmitter carrier frequencies
and receiver tuning frequencies in RF/microwave systems
were widely set by simple resonators, whether LC, quartz,
or waveguide. Radio channels were spaced widely to
accommodate frequency variabilities. To select stations,
receivers were manually, mechanically tuned. This might
have been by the user, as in an AM or FM radio. In TV
sets, fine channel tuning was set by trimming capacitors,
adjusted first in the factory and again in the TV repair
shop. Compact monolithic phase-locked frequency
synthesizers (Figure 1) entered widespread use in the late
1970's and early 1980's. These enabled radio transmit and
receive frequencies to be precisely set, and readily tuned
under digital control, with frequency precision set by a
single quartz-crystal reference oscillator. Frequency
synthesizers enabled precision phase and frequency
control and efficient use of the radio spectrum, and
eliminated frequency drift, making receivers much more
reliable.

(a)

(b)

(c)
Figure 2: Optical phase lock loop (a) and BPSK receiver.
Coherent receiver (b) with QPSK Costas phase detector. phase
detector output polarity (c) and stable PLL lock points
superimposed on the BPSK (left) and QPSK (right)
constellations.

Using optical phase-lock-loops (OPLLs) and

wavelength synthesis, optical signal frequency spacings
can be set precisely under digital control. This will enable
sensitive,
compact,
spectrally efficient,
optical
communications. OPLL applications include wideband
laser phase-locking to improved laser spectral purity
without external optical cavities. OPLLs will enable
BPSK/QPSK coherent receivers; these will serve short- to
mid-range links, will use inexpensive wide-linewidth
lasers, and do not require fast DSP for optical carrier
recovery. OPPLs will enable tunable wavelength-selection
in optical receivers, permitting electronic channel

Figure 1: Frequency synthesizers set transmit and receive

frequencies in most RF/microwave systems.

Signal frequency control in today's optical systems

resembles that of pre-1970's RF/wireless systems. In
wavelength-division multiplexed (WDM) links [2],
channel frequencies and spacings are controlled by sets of
optical resonators [3], while receivers separate wavelength
channels using optical filters [4]. To accommodate laser
and filter tuning errors, channel spacings must exceed
modulation bandwidths. This impairs spectral efficiency, a

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bandwidth, the full optical field information, enabling

BPSK/QPSK receivers, wavelength synthesizers, and
optical/electrical SSB mixers for electrical WDM
receivers..

selection for WDM. OPLLs will enable electronic

wavelength tuning and sweeping, and generation WDM
channel combs, all under digital control. Finally, together
with modern wideband electronics, OPLLs enable
electrical demodulation of WDM, enabling compact
single-chip multi-wavelength coherent receivers

(a)

(a)

(b)
Figure 3: Optical PLL (a) showing the photonic IC (PIC),
electrical IC (EIC), and hybrid loop filter, and (b) the PIC,
incorporating tunable SGDBR laser, star coupler, and detectors.

(b)

II. OPLL DESIGN

In an OPLL [6,7] (Figure 2a) an LO laser is phaselocked to a stable reference laser or to a received signal.
The phase detector, an optical mixer, is a photodiode
illuminated by the LO and reference (RF) lasers. The loop
has gain and a filter, and the LO laser a frequency tuning
electrode [8]. If the reference has narrow linewidth (low
phase noise), then phase-locking the LO laser will
improve its linewidth. If we are to use inexpensive lasers
lacking external optical cavities for linewidth suppression,
then ~1 GHz OPLL loop bandwidth is required. Optical
and electrical path lengths must be small, forcing tight (~5
mm) dimensions.
A 1.55 m laser oscillates at 194THz; upon turn-on the
LO and RF lasers may be initially offset by as much as
20GHz. With a maximum ~1GHz loop bandwidth set by
path lengths and LO laser tuning dynamics, the initial
frequency offset far exceeds the loop bandwidth and an
OPLL with a simple phase detector will not reliably
acquire lock. To ensure that the OPLL reliably locks, it is
equipped (Figure 2a) with a Costas phase-frequency
difference detector constructed from a quadrature (I,Q)
optical mixer, delay stage, and electrical mixer (XOR
gate). The (I,Q) mixing maintains, within the loop

Figure 4: Phase-locked BPSK receiver. Locking transient (a)

showing 600ns frequency acquisition and ~10ns phaseacquisition times. The yellow trace is the Q output, while red
trace is the transmitter/receiver laser beat note, offset by
100MHz. Beat note (b) between the transmitter & receiver lasers,
showing LO laser phase noise suppression.

III. PHASE-LOCKED BPSK/QPSK RECEIVERS

In a phase-locked receiver, an OPLL synchronizes the
LO laser to the received modulated data stream. The phase
detector output must not vary with the data modulation.
OPLLs having Costas phase detectors appropriate for
BPSK and QPSK are shown in Figure 2; the phase
detector characteristics are also shown (Figure 2c). We
have demonstrated coherent phase-locked coherent
receivers [9]; Figure 3 shows the assembly and the
photonic ICs [8]; the electrical ICs [10] are ECL, using
Teledyne's 500nm, 350GHz-( f , f max ) InP HBT process.
The frequency difference detector functions over +/40GHz [10]. The OPLL acquires frequency lock in 600 ns
(Figure 4a) and phase-lock in 10 ns. The loop greatly
suppresses (Figure 4b) the LO laser phase noise. The
receivers operate to 35Gb/s, and are sensitive (Figure 5)

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IV. OPTICAL WAVELENGTH SYNTHESIS

Similar to an RF/microwave synthesizer, OPLLs can
generate precise optical frequency spacings. Unlike an
RF/microwave [1] synthesizer (Figure 1), OPLL
frequency ratios cannot be scaled by counting optical
cycles; instead (Figure 6a) the laser frequency is swept by
introducing, by a mixer, a frequency offset into the loop.
To control without ambiguity the sign of this introduced
frequency offset, a single-sideband (SSB) mixer must be
employed, which demands (I,Q) quadrature optical
mixing. The SSB mixer is digital (Figure 6a), with the
optical beat note represented with 2-bit precision and
added in phase to that of the frequency offset signal [10].
Figure 6a shows the wavelength synthesizer tuning
from 5GHz to 25GHz offset. There are four phase
additions for each cycle of the offset signal. By cascading
(Figure 7) such offset-frequency OPLLs, sets of WDM
carrier wavelengths can be precisely generated and tuned.

(a)

Figure 7: Synthesis, by offset OPLLs, of channel spacings within

wavelength-multiplexed optical communications.

(b)
Figure 5: Phase-locked BPSK receiver output (a) at various data
rates and transmission ranges and (b) receiver error rate.

(a)
(a)

(b)

(b)

Figure 8: Receiver for demodulation of optical wavelengthdivision-multiplexing demodulation in the electrical domain;
block diagram (a) and die photograph of prototype six-channel
receiver (b) in a 500nm InP HBT technology.

Figure 6: Optical wavelength synthesis: block diagram (a)

showing loop with 2-bit digital single-sideband frequency
mixing. Measurement (b) of OPPL laser frequency tuning over a
20GHz range.

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multiple LO lasers, and the multiple electrical receivers

presently used in a WDM coherent receiver array.
We have fabricated both 2-channel [11] and 6-channel
(Figure 8b) WDM electrical receivers incorporating the
SSB frequency conversion but omitting the baseband
signal processing. In tests of the two-channel receiver,
both SSB image-wavelength channel (Figure 9a) and
adjacent-wavelength channel rejection tests (Figure 9b)
show minimal crosstalk between channels in the WDM
receiver.
The present ICs used 50 interconnects and ECL
design techniques throughout, and have very high power
consumption. Power might be saved using CMOS mixer
arrays using analog FFT techniques [14] and chargesteering logic [15]. If an optical pilot is transmitted, the
receiver can phase-lock even given high optical
dispersion; further, it may be possible in this receiver to
compensate for fiber dispersion using analog filters at
baseband, thus avoiding the power consumption of DSP.
Total DC power relative to WDM receivers using backend DSP [5] will determine feasibility.

(a)

(b)

ACKNOWLEDGMENT
Work supported by the DARPA PICO program
REFERENCES
[1] V. Reinhardt et al., 40th Annual Symposium on Frequency
Control, 28-30 May 1986, pp.355-365
[2] C.A. Brackett, IEEE Journal on Selected Areas in
Communications, vol.8, no.6, pp.948-964, Aug 1990
[3] Y. Yokoyama et al., IEEW Photonics Technology Letters,
vol.15, no.2, pp.290-292, Feb. 2003
[4] P. J. Winzer et al., IEEE Journal of Lightwave Technology,
vol.28, no.4, pp.547-556, Feb.15, 2010
[5] P. J. Winzer IEEE Photonics Technology Letters, vol.23,
no.13, pp.851-853, July1, 2011
[6] R. J. Steed et al., Optics Express, Vol. 19, No. 21, 10 October
2011, pp. 20048-20053
[7] L. N. Langley et al., IEEE Transactions on Microwave
Theory and Techniques, 47(7), 1257-1264 (1999).
[8] L. A. Coldren et al., European Conference on Optical
Communication, Amsterdam Netherlands, Sept. 16-20, 2012
[9] H-C Park et al., Optics Express, Vol. 22, Issue 1, pp. 102-109
(2014)
[10] E. Bloch et al., IEEE Trans. Microwave Theory and
Techniques. Vol. 61, No. 1, January 2013, pp 570-580
[11]H-C Park et al., Optics Express, Vol. 22, Issue 1, pp. 102109 (2014)
[12] M. Urteaga et al., IEEE Device Research Conference
pp.281-282, 20-22 June 2011
[13]M. Seo et al., 2013 IEEE International Microwave
Symposium, 2-7 June 2013, Seattle.
[14] C. Andrews, A.C. Molnar, IEEE J. Solid-State Circuits,
vol.45, no.12, pp.2696-2708, Dec. 2010
[15] B. Razavi, 2013 IEEE Custom Integrated Circuits
Conference, 22-25 Sept. 2013

(c)
Figure 9: Electrical WDM receiver tests. Image-wavelength
rejection tests showing rejection (a) of the image channel and (b)
interference-free eye patterns when both image channels
operated. Adjacent-channel (c) rejection tests showing high Q,
i.e. signal/(interference+noise), even with optical channels
carrying 2.5 Gb/s BPSK at 5 GHz spacing.

IV. ELECTRONIC WAVELENGTH- DEMULTIPLEXING

In coherent receivers, WDM signals can be
demultiplexed electrically [11] (Figure 8), replacing many
WDM receivers with one PIC and one electrical IC. WDM
signals at 25GHz separation first become electrical
subcarriers at 25GHz separation, and then are
downconverted to DC using a cascade of (I,Q) optical and
microwave mixers in a Weaver single-sideband
configuration. With modern THz InP HBT processes [12],
IC bandwidths can exceed 600 GHz [13], hence in
principle one such electrical IC might recover 48 WDM
channels at 25 GHz channel spacing. In a SiGe BiCMOS
process, >200GHz electrical IC bandwidths are feasible
today, and the receiver of Figure 8 could recover 16 WDM
channels at 25GHz spacing. Such a design would
eliminate the receiver WDM optical filter bank, the

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InP DHBT Mux-Drivers for very high symbol rate optical

communications
J. Godin, J-Y. Dupuy, F. Jorge, F. Blache, M. Riet, V. Nodjiadjim, P. Berdaguer,
B. Duval and A. Konczykowska
III-V Lab, Joint lab between Bell Labs, TRT, and CEA/LETI,
Route de Nozay, 91460 Marcoussis, France; mail:Jean.Godin@3-5lab.fr
Abstract This paper reports on very high speed large
swing drivers suitable for the generation of high symbol rate
spectrally efficient optical transmission signals. To
accommodate available data rate, these circuits integrate
multiplexing stages. Fabricated using our InP DHBT
technology (FT and FMAX >300 GHz, BVCE0 ~5 V), these
circuits include NRZ and Multi-Level drivers; they have
been used to generate OOK, QPSK and QAM signals in
optical transmission experiments at bitrates beyond 100
Gbps.
Index Terms Driver circuits; DHBT; InP; Modulation
Formats; Optical Transmissions.

A. HBT technology
HBT structures were home-grown by Gas Source MBE
on a 3 inches semi-insulated substrate. The structure is
described in [1]. The self-aligned triple mesa process is
used to make devices with an emitter width of 0.5 and
0.7 m. The majority of process steps are controlled using
stepper lithography, while the emitter and base contacts
are defined by e-beam lithography.
Device DC characteristics include a maximum current
gain of 25 and a breakdown voltage above 5 V
@IC=100 A. FT and Fmax peak at 340 GHz and 400 GHz
respectively for 0.7x5 m HBTs at JC ~7mA/m (Fig. 1).

I. INTRODUCTION
As 100 Gb/s transponders are now deployed
commercially, attention has shifted towards 400 Gb/s and
even Tb/s optical transmission. Achieving these higher
rates is contemplated based on using simultaneously
multiple carriers (super-channels), higher modulation
order and higher symbol rates. Trade-offs are driven by
considerations about cost, compactness, power
consumption and availability of needed parts, taking into
account the intended reach.
In this paper, we report on beyond 100 Gbit/s
transmitter ICs, suitable for experimentations up to 1 Tb/s
thanks to symbol rates between 50 and 100+ GBaud.
Various driver ICs, suitable for different modulation
formats are described, and some experiments made
possible thanks to these circuits are summarized.

Fig. 1 FT and FMAX vs. collector current of 0.7x5 m InP

DHBTs at an emitter-collector voltage of 1.6 V

II. CIRCUIT ARCHITECTURE AND FABRICATION

For the circuit fabrication, the process also includes

NiCr thin film resistors, SiN MIM capacitors and three
Au-based interconnection levels.

Transmitters for very high capacity optical transmission

have to cater to following requirements: (i) as large as
possible swing to drive the optical modulator; (ii) very fast
operation, with clock >50 GHz. InP DHBT technology is
well suited to deliver these characteristics. Another
requirement stems from the difficulty to generate data
beyond 50 Gb/s, as these are prone to signal integrity
issues; the driver architecture hence includes a
multiplexing stage.

978-1-4799-3622-9/14/$31.00 2014 IEEE

B. 100G NRZ Selector-Drivers (SELDRV)

Two architectures, lumped and distributed, have been
developed, corresponding to various trade-offs, to provide
a large NRZ signal at 100 Gb/s. Both include a 2:1
multiplexing stage to combine input data at 50 Gb/s, based
on a Gilbert cell.
Differential implementation, which has intrinsic
advantages like better common mode rejection and

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immunity to temperature or process variations, is used in

both architectures.
Lumped architecture is characterized by a very
compact design. In this architecture, transistors are
operating in saturation mode which allows obtaining
shorter rise/fall times and well defined 0 and 1 levels. A
drawback of this compact design is associated with the
relatively high DHBT thermal resistance, which has to be
taken into account during layout. A cascode driver stage is
used to provide high quality NRZ 100G 2x2V differential
output (Fig. 2).
A microphotograph of this very compact 1.2 x 1.5 mm
fabricated SELDRV circuit is presented in Fig. 3. Power
consumption is 2 W for 100G operation.

drive the distributed amplifier, which is made of eight

cells (in a uniform way for simplicity). The base and
collector artificial transmission lines of the distributed
amplifier consist of coplanar lines realized using the
second metal level of our technology. Optimization of
lines parameters and implementation is fundamental for
achievement of optimal operation at 100 Gb/s [2]. Fig. 4
shows high quality NRZ 110G 2x3 V differential output.
The total power consumption is 3.8 W.

Fig. 4 112 Gb/s operation of distributed SELDRV

C. 50+G Multi-Level Mux-Drivers (MLMD)

For the generation of higher order modulation formats,
like 16- and 64-QAM, we developed 2- and 3-bit powerDACs [3]. First developed circuits operated at up to
50 GBaud, and were used in various experiments [4].
Here, we report on improved multi-level drivers, operating
beyond 50 GBaud, and including multiplexing stages. Fig.
5 shows the MLMD architecture.

Fig. 2 100G operation of lumped SELDRV (one SE output)

Fig. 3 Microphotograph of SELDRV circuit

Distributed architecture is well known to provide

larger output swing, at the cost of larger circuit size.
Designed distributed SELDRV combines a modified
lumped SELDRV with a fully differential distributed
amplifier. The resulting circuit occupies 1.5x3.6 mm. The
lumped stage output is limited to 2x1Vpp, to optimally

Fig. 5 MLMD architecture

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Single-ended inputs, which are used to limit the number

of high-speed ports, are converted to differential signal in
the input buffers. Operation is kept differential up to the
cascode output buffer, and implementation is kept
symmetric. Fig. 6 shows the microphotograph of
2.25x1.8 mm 2-bit MLMD, comprising 216 transistors,
providing well defined four levels and opened eyes up to
70 GBaud (Fig. 7) , for a power consumption of 2.8 W.
Fig. 8 packaged 100G OOK transmitter
More recently, within same project, scalability of this
approach was demonstrated by the transmission of
2x100 GBaud OOK signals at up to 500 m. The packaged
transmitter (Fig. 9) uses a pair of distributed SELDRV to
provide a larger swing to the modulator.

Fig. 6 Microphotograph of 2.25x1.8 mm MLMD

Fig. 9 packaged 2x100G OOK transmitter

To overcome the distance limitation, and relax

modulator bandwidth limitation, it was shown [9], in
another experiment using the same SELDRV circuit in a
simpler box, that reliable transmission can be achieved
over 1 km if the received signal is detected as a duobinary signal.
These various successful experiments demonstrate the
suitability of 100G OOK modulation for intra-datacenter
links, with relevance for scalability toward Tb/s links.

Fig. 7 64 (left) and 70 (right) GBaud MLMD output signal

III. SYSTEM EXPERIMENTS

Experiments achieved using previously described
circuits are summarized below. For shorter distances,
where compactness, power consumption and scalability
are the main factors, intensity modulation and direct
detection schemes (IM/DD) are to be preferred [5]. For
longer distances, larger capacity and longer reach are
achieved thanks to advanced signal processing able to
recover the information carried by more complex
modulation formats.

B. Longer reach transmission experiments

[10] describes a 400 Gb/s transmission using all-ETDM
107-GBaud PDM-QPSK modulation. The generation of
the signal relies on a pair of 100G SELDRV to drive the IQ double-nested Mach-Zehnder modulator. Bit Error Rate
is above forward-error correction (FEC) limit for distance
up to 4,800 km.
For higher data rate toward Tb/s, formats like PDM16-QAM are needed. While experiments using MLMDs
are planned, first transmissions were set up using the
SELDRV. [11] describes this set-up, in which the multilevel signals are achieved thanks to external combiner
(Fig. 10). Operating at 80 GBaud, 640 Gb/s were
generated. In [12] an experiment using this set-up
achieves the transmission of 5 (WDM) x1 Tb/s over

A. Short reach transmission experiments

[6] describes the error-free transmission of 100 Gb/s
OOK data done in EU-funded program POLYSYS. This
experiment relies, for the transmitter, on the close (hybrid)
association of a DFB laser, a wideband polymer
modulator and previously described lumped SELDRV
(Fig. 8); and on the receiver [7], on the association of a
large bandwidth photodiode and InP HBT DMUX [8].

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[4] J. Godin, A. Ko czykowska, J.-Y. Dupuy, M. Riet,

V. Nodjiadjim, F. Jorge, G. Charlet, O. Bertran-Pardo,
J. Renaudier, H. Mardoyan, A. Gnauck, and P. J. Winzer, "
High Speed Multi-Level Drivers for Spectrally Efficient
Optical Transmission Systems", Bell Labs Technical
Journal vol. 18, no 3, pp. 6794, December 2013
[5] J. Cartledge, and A. Karar, "100 Gb/s Intensity Modulation
and Direct Detection," to appear in IEEE J. Lightwave
Technol. (2014)
[6] V. Katopodis, C. Kouloumentas, A. Konczykowska, F.
Jorge, P. Groumas, Z. Zhang, A. Beretta, A. Dede, J.
Dupuy, V. Nodjiadjim, G. Cangini, G. Von Bren, E.
Miller, R. Dinu, J. Choi, D. Pech, N. Keil, H. Bach, N.
Grote, A. Vannucci, and H. Avramopoulos, "Serial 100
Gb/s connectivity based on polymer photonics and InPDHBT electronics," Opt. Express vol. 20, no 27, pp.
28538-28543 (Dec. 2012).
[7] G.G. Mekonnen, H.-G. Bach, R. Kunkel, C. Schubert, D.
Pech, T. Rosin, A. Konczykowska, F. Jorge, A. Scavennec,
and M. Riet, Hybrid co-packaged receiver module with
pin-photodiode chip and DEMUX-IC for 107 Gb/s data
rates, Proc. ECOC09, paper 9.2.6 (2009).
[8] A. Konczykowska, F. Jorge, J-Y. Dupuy, M. Riet, J. Godin,
A. Scavennec, H-G. Bach, G-G. Mekonnen, D. Pech, C.
Schubert, "InP HBT demultiplexing ICs for over 100 Gb/s
optical transmission," Microwave Radar and Wireless
Communications (MIKON), 2010 18th Int. Conf., 14-16
June 2010
[9] J. Lee, N. Kaneda, T. Pfau, A. Konczykowska, F. Jorge, J.
Dupuy, and Y. Chen, "Serial 103.125-Gb/s Transmission
over 1 km SSMF for Low-Cost, Short-Reach Optical
Interconnects," in Optical Fiber Communication
Conference, post-deadline paper Th5A.5 (2014),.
[10] G. Raybon, A. Adamiecki, P. Winzer, C. Xie, A.
Konczykowska, F. Jorge, J. Dupuy, L. Buhl, C.
Sethumadhavan, S. Draving, M. Grove, and K. Rush,
"Single-carrier 400G interface and 10-channel WDM
transmission over 4800 km using all-ETDM 107-Gbaud
PDM-QPSK,"
in
Optical
Fiber
Communication
Conference, post deadline paper PDP5A.5 (2013),
[11] G. Raybon, A. Adamiecki, S. Randel, C. Schmidt, P.
Winzer, A. Konczykowska, F. Jorge, J-Y. Dupuy, L. Buhl,
S. Chandrasekhar, Xiang Liu, A. Gnauck, C. Scholz, R.
Delbue, "All-ETDM 80-Gbaud (640-Gb/s) PDM 16-QAM
Generation and Coherent Detection," Photonics Technology
Letters, IEEE , vol.24, no.15, pp.1328,1330, Aug.1, 2012
[12] G. Raybon, A. Adamiecki, P. Winzer, S. Randel, L.
Salamanca, A. Konczykowska, F. Jorge, J. Dupuy, L. Buhl,
S. Chandrashekhar, C. Xie, S. Draving, M. Grove, K. Rush,
and R. Urbanke, "High Symbol Rate Coherent Optical
Transmission Systems: 80 and 107 Gbaud," IEEE J.
Lightwave Technol. Vol. 32, no 4, pp. 824-831, February
2014.
[13] G. Raybon, A. Adamiecki, P. J. Winzer, M. Montoliu, S.
Randel, A. Umbach, M. Margraf, J. Stephan, S. Draving, M.
Grove, and K. Rush," All-ETDM 107-Gbaud PDM-16QAM
(856-Gb/s) Transmitter and Coherent Receiver", Proc.
ECOC 13, PDP 2-D3 (2013)

3,200 km thanks to LDPCC (low-density parity-check

convolutional) coding.

Fig. 10: 16-QAM transmitter set-up (from [11])

The same set-up operated successfully at 107 GBaud,

generating 856 Gb/s on a single optical carrier, recovered
with a BER compatible with 20% overhead FEC [13].
CONCLUSION
We have described various high symbol rate drivers,
integrated with a multiplexing stage to relax data integrity
issues. These drivers are suitable for the generation of
simple (OOK) or more complex (QPSK, 16-QAM)
formats. Experiments using some of these drivers have
been summarized.
ACKNOWLEDGMENT
The support of the European commission for ICT
projects FP7/POLYSYS and FP7/PANTHER, and
significant contributions by the project partners is
acknowledged.
Work on MLMDs has also been supported by French
Government-funded project ANR/HENIAC.
REFERENCES
[1] V. Nodjiadjim, S. Cros-Chahrour, J.-Y. Dupuy, M. Riet, P.
Berdaguer, J.-L. Gentner, B. Saturnin, J. Godin,
"InP/GaInAs DHBT with TiW emitter demonstrating
fT/fmax ~340/400GHz for 100 Gb/s circuit applications",
IPRM 12, pp. 192-195, Aug. 2012
[2] Dupuy, J.; Konczykowska, A.; Jorge, F.; Riet, M.;
Berdaguer, P.; Nodjiadjim, V.; Godin, J.; Ouslimani, A., "A
6.2-Vpp 100-Gb/s Selector-Driver based on a differential
distributed amplifier in 0.7-m InP DHBT technology,"
Microwave Symposium Digest (MTT), 2012 IEEE, 17-22
June 2012
[3] Godin, J.; Konczykowska, A.; Dupuy, J-Y; Jorge, F.; Riet,
M.; Moulu, J.; Nodjiadjim, V.; Berdaguer, P.; Blache, F.;
Gnauck, A., "InP DHBT Very High Speed Power-DACs for
Spectrally Efficient Optical Transmission Systems,"
Compound Semiconductor Integrated Circuit Symposium
(CSICS), 2011 IEEE , 16-19 Oct. 2011

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A 25Gb/s Common-Cathode VCSEL Driver

Kwan Ting Ng, Yeung Bun Choi and Keh Chung Wang
Hong Kong Applied Science and Technology Research Institute (ASTRI)
2 Science Park West Avenue, Hong Kong Science Park, Shatin, Hong Kong
Email: kashng@astri.org

AbstractA common-cathode VCSEL driver is presented in

this paper. Overcoming the large parasitics introduced by the
current source at the output node, this VCSEL driver is able to
operate at data rate of 25Gb/s. With different rising/falling edge
speed, it is able to address the non-linear issues of VCSEL diode.
The VCSEL driver was fabricated using IBM8HP BiCMOS
technology, dissipating less than 60mW and featuring a core area
of 0.45mm200mm.

I. I NTRODUCTION
Optical Fiber Communication (OFC) offers the highest date
rate (<10 Tb/s over a single fiber) and the longest distance
(<10,000km) among all communication technologies. Highspeed ICs at data rates of 25 Gb/s and higher are key enablers
of OFC. Such high data rates are demanded in applications
such as broadband local access, backbone networks and
consumer optoelectronics.
For some of consumer applications, especially for portable
devices, power consumption is as important. The vertical
cavity surface emitting laser (VCSEL) offers low threshold
current hence making VCSEL a favorable choice in portable
OFC transmitters. However, as data rate increases to tens
of Gb/s, the bandwidths of both the VCSEL diode and the
electronics are not capable to catch up with such high speed
and result in distorted waveforms. Moreover, the parasitics of
the VCSEL diode and circuit routing become critical at high
data rate that limit the transmitter bandwidth of the OFC
transmitters.
To overcome these speed bottlenecks, researchers have
been striving on both the laser device level and the circuit
design level. On device level, VCSEL injection locking
techniques have been widely adapted to increase the VCSEL
bandwidth [1]. On the other hand, circuit designers employ
the most advanced technology to boost the data rate [2].
Various circuit design techniques have also been applied on
VCSEL driver to compensate for the parasitics. One most
common approach is to pre-emphasis the electrical signal
during the electrical-to-optical conversion using finite impulse
response (FIR) filters [3], [4]. These implementations are
able to successfully tackle the parasitic issues at moderate
high speed. However, at higher data rates, the non-linearity
properties of VCSEL diodes become severe while most of
these pre-emphasis techniques are linear approaches so that
it does not handle the non-linear issues. Frequency chirping
is the most severe non-linear side effect of VCSEL diodes. It
is a phenomenon due to laser instability, causing frequency
dispersion on the laser wavelength during rising edge [5].

978-1-4799-3622-9/14/$31.00 2014 IEEE

Asymmetric compensation has been used in VCSEL drivers

to pre-emphasis the rising/falling edge at different level in
order to reduce the impact of VCSEL frequency chirping [6].
Yet, the clock signal is essential to this technique where it
is not available in some applications. Also, extra power is
consumed on pre-emphasis circuits that shorten the battery
life for portable devices.
In this paper, we present a low power 25Gb/s VCSEL driver
that inherently generates a sharper falling edge than rising
edge. This property is desirable to relax the negative impact
due to VCSEL frequency chirping at high data rate. The
transmitter architecture and implementation is described
in Section II. The measurement results are subsequently
discussed in Section III followed by the conclusion in Section
VI.
II. T RANSMITTER A RCHITECTURE AND I MPLEMENTATION
The architecture of the transmitter is illustrated in Fig. 1(a).
It comprises of a pre-amplifying stage to buffer the input
signal and a driving stage to control the output current. The
input differential signal is AC-coupled via a pair of external
capacitor then buffered by the 50 differential buffer, which
also serves as an impedance matching circuit and a self-biasing
circuit (Fig. 1(b)).
The signal is subsequently amplified by the limiting amplifier,
which must be designed to possess good driving capability in
order to drive the main driver without sacrificing the speed.
It is realized by a series of cascaded current-mode-logic
(CML) stages with incremental driving capability to maintain
the speed (Fig. 1(c)). A common approach to achieve such
capability is to use center-tap inductors. However, we intended
not to employ inductors in this design in order to miniaturize
silicon area. The differential signal is amplified from as low
as 100mVpp to about 400mVpp , whereas the signal edges
are being sharpened during amplification.
A buffer is inserted between the limiting amplifier and the
main-driver that servers two purposes. One of which is to drive
large capacitive load of the input devices in the main-driver,
and the other is to act as a voltage shifter. Since the VCSEL
modulation current is in the order of tens of mA, the maindrive input devices are designed to be large enough to sustain
such current density. As a result, the input capacitance of the
main-driver is relatively large that needs a fast buffer.
On the other hand, the forward voltage of VCSEL diodes
varies in a vast range depending on manufacturers. The

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Fig. 1. (a) Block diagram of optical transmitter; (b) Schematic of 50 input buffer; (c) Schematic of limiting amplifier constructed by multiple cascading
CML stages; and (d) Schematic of voltage shifter

VCSEL driver must be designed to comply with such voltages

without forward-biasing the collector-base junction of the
main-driver input devices. Thus, the buffer is designed in an
emitter follower configuration as shown in Fig 1(d) because it
fulfills both of the above purposes.
The main-driver can either designed to connect to the laser
directly for modulation, to connect in an AC coupled configuration if voltage swing is a concern. Due to the VCSEL
characteristics, the voltage swing at the output node is less
than 1V, hence direct modulation is used to minimize power
consumption. Since no back-termination for impedance is
available for impedance matching, careful considerations are
to be taken when designing direct modulation laser drivers.

Fig. 2. (a) Common-anode VCSEL driver design; and (b) Common-cathode

VCSEL driver design

Two conventional approaches of the main-driver are the

common-anode (CA) configuration and the common-cathode

(CC) configuration as shown in Fig 2. The CA type driver

has been extensively used in high-speed VCSEL drivers due
to its inherent benefit of low parasitic capacitance. However,
due to the physical structure, the VCSEL cathode is tied to
ground in most of the commercial VCSELs, which is not
available as a driving node. Moreover, the CA VCSEL driver
only actively drains current from the VCSEL cathode, which
results in a fast optical rising edge; while the falling edge speed
completely depend on the parasitics because there is no active
devices to discharge the VCSEL cathode. Unfortunately, this
type of driving scheme is not suitable for VCSELs due to its
characteristics. This is because VCSEL suffers from frequency
chirping, which results in optical wavelength spread during a
rapid rise edge [5].
On the other hand, the common-cathode (CC) configuration
provides the bias current and the modulation current via the
VCSEL anode. During the optical falling edge, the driver
actively drains current from the current source, which results
in a fast falling edge. By the matter of fact, the falling edge
can be even further enhanced by proper design of the driver.
This can be explained by the equivalent schematic shown in
fig 3.
At t = 0, the switch is closed and the modulation current Imod
is drained from the top current source. Meanwhile, there is a
charge sharing between the total capacitance at the output node
Cvcsel , and the capacitance at the emitter Cc . The total current
flows through the VCSEL diode Ivcsel can be represented by

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Fig. 3. Equivalent schematic of a common-cathode VCSEL driver at falling

edge

the following equation:

dv
dv
+ Ivcsel Cvcsel
dt
dt
(1)
dv
Ivcsel = Ibias (Cc Cvcsel )
dt
When Cc << Cvcsel , the current falling edge through the
VCSEL is proportional to the capacitance Cc . This effect can
be seen in the simulated eye-diagram in fig. 4, where in the
simulation, extra capacitance is added to Cc . It is clear that
a faster falling edge with undershoot is obtained with extra
Cc loaded. One should note that only the falling edge speed
is enhanced by Cc without affecting the rising edge. In other
words, this is a non-linear implementation to compensate for
the VCSEL characteristics. In CC circuit implementation,
there already exists a large parasitic capacitance at this node
due to the large transistor used for bias. As a result, CC
configuration is inherently suitable for VCSEL driver design.
Ibias + Imod = Imod + Cc

from the advanced technology, the SiGe process consists

of hetero-junction bipolar transistors (HBTs) that has low
parasitics and a fT up to 200GHz.
The schematic of the VCSEL driver shown in fig. 5 consists
of a npn differential pair, two tunable current sources and
a PMOS current mirror in a ratio of N . The modulation
current Imod is defined by regulating Vmod across a fixed
resistor. To maximize the voltage headroom, a single PMOS
transistor is used to mirror and amplify Ibias,ref . The PMOS
current mirror is designed in a large ratio to retain low power
consumption. One should note that Vbias,ref is defined in a
slight different manner from Vmod . Vbias,ref controls the total
VCSEL current (Imod + Ibias ) and hence Vbias,ref is always
higher than Vmod when the resistors Rmod and Rbias,ref are
designed with ratio N .
As aforementioned, the CC configuration in this work
introduces extra prasitics at the high speed node, which
could deteriorate the modulation speed severely. The PMOS
current mirror and corresponding routing metal are hence
miniaturized to minimize parasitic capacitance.

Fig. 5. Schematic of main-driver with tunable modulation current and bias

current

III. R ESULTS AND D ISCUSSION

Fig. 4. Simulated eye-diagram of common-cathode VCSEL driver with (top)

Cc = 1fF and (bottom) Cc = 1pF

Compare to the CA configuration, the CC design is loaded

with extra parasitic capacitance Cp due to the top current
source. In high speed communication applications, this could
be the major limitation that forbids the VCSEL driver to be
designed in CC configuration.
As a counterpart to the large output parasitic capacitance
from the CC architecture, Silicon Germanium (SiGe) process
is used to design the VCSEL driver in this work. Benefits

The VCSEL driver was designed and fabricated using the

IBM8HP BiCMOS technology. The die photo is illustrated
in fig 6. Self-built prototypes were implemented for measurements. The die was attached to the prototype board directly
with gold bond wire using ball bond technique. To minimize
the bond wire inductances, the bond wires on critical pads
were limited to be less than 0.5mm.
During measurement, different PRBS patterns were used to
test the transmitter, with the differential amplitude of the
signal being as small as 100mVpp . No significant difference
at the output was observed due to limiting amplifiers was
used. The electrical measurement result of the VCSEL driver
presented in fig. 7 and fig. 8 are the voltage eye-diagrams of
the output node, with a 50 load, at two modulation current
levels (Imod = 1mA and Imod = 2mA). In this work, extra
capacitance has been integrated to the npn emitter of the main
driver for the benefit of falling edge speed as discussed in

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Fig. 6. Microphotograph of VCSEL driver fabricated in IBM8HP 0.13m

BiCMOS technology.

the previous section. As a result, sharp falling edge with

undershoot can be observed in the eye-diagram. Also, as
presented in Eq. (1), the falling edge speed is independent
of the modulation current Imod .

Fig. 8. Electrical measurement of VCSEL driver with PRBS 23 1 input.

Modulation current Imod = 2mA.

entire transmitter is less than 60mW under a nominal condition

of 2mA bias current and 4mA modulation current.
IV. C ONCLUSION
In this paper, a common-cathode (CC) VCSEL driver has
been demonstrated at data rate of 25Gb/s. This VCSEL driver
was designed to generate a sharp falling edge with undershoot
to compensate for the inherent non-linear effect of VCSEL
diodes, namely a slow falling edge. Unlike some other VCSEL
driver designs with pre-emphasis, the VCSEL driver in this
work does not sharpen the rising edge so that no extra sideeffects from frequency chirping was resulted. The VCSEL
driver dissipates only less than 60mW and features an core
area of 0.45mm 200mm.

Fig. 7. Electrical measurement of VCSEL driver with PRBS 23 1 input.

Modulation current Imod = 1mA.

Due to the fact that there are limited commercially available

25Gb/s VCSEL didoes in the market, no optical measurements
are yet available at the time of this paper submission. However,
one should note that the undershoot demonstrated in the
electrical test is expected to be reduced in optical test even if
the measurements were obtained under similar test conditions.
This is due to the VCSEL characteristics and the electrical
undershoot was used as a counterpart for its slow falling edge
property as discussed previously. Moreover, a slower falling
edge is expected if the emitter of the driver was not loaded
with excessive capacitance.
The pre-amplifying stage and the driving stage use a 2.5V
supply a 3.3V supply, respectively. The pre-amplifying stage
operates in a lower supply to power reduce power consumption; while the driving stage needs to operate in higher supply
in order to comply with the vast variation of VCSEL diode
forward voltage. The measured power consumption for the

ACKNOWLEDGMENT
We would like to acknowledge IBM for sponsoring chip
fabrication with 8HP BiCMOS technology.
R EFERENCES
[1] Chih-Hao Chang, L. Chrostowski, C.J. Chang-Hasnain, Injection locking
of VCSELs, in IEEE Journal of Selected Topics in Quantum Electronics,
Vol.9, No.5, pp.1386-1393, Sept. 2003.
[2] X. Wu, B. Dama, P. Gothoskar, P. Metz, K. Shastri, S. Sunder, J. Van der
Spiegel, Y. Wang, M. Webster and W. Wilson, A 20Gb/s NRZ/PAM-4 1V
transmitter in 40nm CMOS driving a Si-photonic modulator in 0.13m
CMOS in IEEE International Solid-State Circuits Conference, Digest of
Technical Papers , pp.128-129, Feb. 2013.
[3] A.C.Y. Lin, M.J. Loinaz, A Serial Data Transmitter for Multiple 10Gb/s
Communication Standards in 0.13?m CMOS, in IEEE International SolidState Circuits Conference, Digest of Technical Papers, pp.108-109 , Feb.
2008.
[4] S. Palermo, A. Emami-Neyestanak, M. Horowit, A 90nm CMOS 16Gb/s
Transceiver for Optical Interconnects, in IEEE International Solid-State
Circuits Conference, Digest of Technical Papers, pp.6-7, Feb. 2007.
[5] V. Alwayn, Optical Network Design and Implementation, Cisco Press,
2004.
[6] K. Ohhata, H. Imamura, Y. Takeshita, K. Yamashita, H. Kanai, N. Chujo,
Design of a 410 Gb/s VCSEL Driver Using Asymmetric Emphasis Technique in 90-nm CMOS for Optical Interconnection, in IEEE Transactions
on Microwave Theory and Techniques, Vol.58, No.5, pp.1107-1115, May
2010.

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Power Amplifier Design Optimized for Envelope Tracking

Gayle Fran Collins1, Jeremy Fisher2, Fabian Radulescu2 Jeff Barner2, Scott Sheppard2, Rick Worley3, Don Kimball1
1

MaXentric Technologies, La Jolla, CA, 92037, USA, (858) 605-6337, gcollins@maxentric.com,

2

Cree, Inc., 4600 Silicon Drive, NC 27703, 3AFRL, Wright Patterson AFB, OH 45433

Abstract In this paper, we present the design of an

inverse Class F power amplifier GaN MMIC, specifically
designed for an envelope-tracking application. Power
transistors are not typically characterized for the drain
modulation that is fundamental to envelope tracking, and the
available device models are not usually validated over the
required drain bias range. Here, we used fundamental loadpull to characterize a 6x100m GaN HEMT device over the
range of drain bias voltages that would be used in the
envelope-tracking PA. This data was scaled to an 8x100m
device to achieve the target output power, and these
empirical load-pull models were then used in the design of
the power MMIC along with harmonic design in
simulation. A total of eight 8x100 m HEMTs were used in
the final design, achieving a maximum power output of 32 W
at 10 GHz with a drain efficiency of greater than 45% in
back-off, on a die size of less than 4 x 4 mm2 under envelope
tracking.
Index Terms High power amplifiers, MMICs, Gallium
nitride, X-band, load-pull, baseband, modulation.

employs a wideband ET amplifier that provides dynamic

supply biasing to the PA that tracks the modulation of the
input signal. In doing so, the power consumed and
dissipated by the PA is reduced thereby increasing the
efficiency of the PA in back-off. In the context of ET,
back-off refers to the signal and not the PA as the PA is
run in compression at all times.
In power amplifier design, the impedance seen at the
fundamental has the largest contribution to the
performance of the PA. Additionally, reduced conduction
angle PAs have long been used to increase the efficiency
of a PA. Harmonic terminations that are added to
optimize the efficiency require a robust device with high
breakdown. Of the reduced conduction angle classes of
PA, Class F-1 is well suited for envelope tracking
applications. As the number of available harmonics
increases, the Class F and Class F-1 are one of the few
classes in which the power increases along with the
efficiency [1]. Here Class F-1 is chosen for the square
current waveforms and the dynamic range of the voltage.
Due to the requirement of high fT and high breakdown, the
PA was designed in the Cree optical 0.14m GaN HEMT
MMIC process to obtain the requisite power and the
harmonics required for Class F-1 operation.
In the design of ET systems, the PA design has often
been given the least attention resulting in a build and test
approach to optimizing the system [2]. A large variation
of the voltage dependent output capacitance will degrade
the average efficiency since the optimum impedance
matching for the output of the PA varies with the supply
voltage [3]. It has been shown that that the drain
modulation has an impact on the stability of the PA as
well [4]. In this work, a deterministic approach to the PA
design for the ET application has been taken. The voltage
dependence of the device has been overcome by
characterizing the device in the range of supply voltage
that it will see under ET. A 32W MMIC was designed in
the Cree optical 0.14 m MMIC process after
characterizing a single 6x100m device.

I. INTRODUCTION
Power amplifiers (PA) are necessary in communications
systems to boost the power of an input signal so that it can
be transmitted over distance. The PA is a DC to RF
converter, amplifying the signal and providing a carrier for
the baseband information and driving the antenna. While
linearity is important to preserve the content of the
baseband information, linear PAs are not efficient,
consume large amounts of energy and dissipate heat.
Transmit PAs take up a significant portion of the wireless
base station power budget as well as that in mobile user
equipment.
Wireless communication systems have an increasing
requirement for linearity and efficiency while modern
techniques such as OFDM and WCDMA demand wider
bandwidths and higher data rates. Multicarrier modulation
has clear benefits with adjustable user data rates and
bandwidths. These techniques mean that the PA must be
designed for a high peak to average power ratio (PAPR)
necessitating methods of providing high efficiency at
average power levels. High efficiency is an important
figure of merit as it is indicative of the power consumption
of the PA and thus the heat dissipation.
An effective solution that increases the efficiency of the
RFPA at average power is envelope tracking (ET). ET

978-1-4799-3622-9/14/$31.00 2014 European Union

II. CHARACTERIZATION OF THE GAN HEMT

To characterize the die for the optimized MMIC design
for envelope tracking, fundamental loadpull measurements

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In all, the measurements were takeen at 24 impedances at

each drain bias.
d for maximum output
The RFPA is generally designed
power and efficiency and the output impedance match is
chosen with these performance mettrics in mind. From the
efficiency plot, the choice of this impedance match for

were taken with drain bias voltages of 8-28 V in 4 V

increments.
The input power was driven up and
measurements were taken as the impedannce was varied at
the output of the device. A 6x100m sizzed discrete GaN
HEMT from the G28V5 0.14m MM
MIC process was
characterized. The 100 m gate widthh was chosen in
order to meet the desired 30 W output, annd the 6x100 m
device was close in size to the 8x1000 m that were
eventually used in the design.
The importance of this kind of chaaracterization for
devices destined to be used in PA desiggns for envelope
tracking applications became clear. As nno model existed
at that time that could accommodate thee range of drain
modulation accurately, the measurements help to inform
the design when the amplifier is run att average power,
using a lower drain bias, (i.e. where thhe RFPA spends
most of its time). For envelope tracking, back-off means

Figure 3 Eff. v. output power at ZL= 38.2+j47.8,

3
10GHz

Figure 1 Eff. v. output power, ZL= 22.5+j366.2, 10GHz

Figure 4 Gain v. output power at ZL= 38.2+j47.8,10GHz

w
not yield good
efficiency at the peak power would
efficiency at backed-off power wh
here signals with high
peak to average ratios will spend most
m
of their time. To
get good performance, efficiency att the envelope back-off
is key.
A better impedance choice is shown in the figures 3 and
4. The peaks of the efficiency currves now have a better
shape to meet the goal. The efficieency is higher in backoff with a drain voltage of 12V and reasonable at the
higher output powers. It is clearr that at this value of
impedance the device could have beeen driven harder at the
higher drain voltages and the efficieency peaks would have
had even greater uniformity.

Figure 2 Gain v. output power, ZL= 22.5+j366.2, 10GHz

the signal is at a lower level as the PA is run in saturation

all the time (at every signal level). Figurres 1 and 2 show
the gain and efficiency against output poower for a single
impedance point at different values of thhe drain voltage.

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The G28V5 0.14 m MMIC process paarts also are very

promising for envelope tracking becauuse even at the
lowest voltage of 8 V the gain is above 110 dB at 5 dB of
compression. It is important to keep thhe gain up at the
lower voltages to keep the efficiency highh and still get the
power out at the backed off levels.
III. MMIC DESIGN

The MMIC design was carried out in ADS. The

fundamental impedance was determined by the loadpull
model. The Cree
data and then optimized using the Cree m
model is valid to over 40 GHz alllowing for the
optimization of the harmonic terminationss. The simulated
time domain current and voltage waveforrms are shown in
Fig. 5.

Figure 6 RFIV characteristic

order to meet the power target of grreater than 5 W average

power, 8 devices were used in the design
d
with a saturated
output power of 32 W. The devices are biased in deep
Class AB for the inverse Class F design.
The block diagram of the Class F-1 design is shown in
d a corporate combiner
Fig. 7. It is a symmetric design and
is used for the power splitting and
a
combining. Each
device has a prematch at the input to prevent the
w from the combining
impedance from becoming too low
and increases the bandwidth of the
t input match. The
prematch is a low-pass that filtters out higher order
harmonics at the input.
The second harmonic is
terminated with a capacitor to proviide the high impedance
at the second harmonic. The fundaamental /8 and the /4
transmission lines become a /4 an
nd the /2 at the second
harmonic, isolating the circuit up to
o the termination at the
second harmonic frequency. The part is matched to 50
ohms at the input and output and the input DC block is
a
prevents RF from
provided off-chip. The /4 line also
riding on the bias line at the fundam
mental frequency.

Figure 5 Inverse Class F voltage and current waveforms

The second harmonic termination cauuses the current

waveform to become square. This is dessired to decrease
the overlap in the voltage and current thuus increasing the
efficiency. The knee voltage of the devvice prevents the
voltage waveform from reaching zero, degrading the
efficiency of the PA. The high dynamic raange of the Class
F-1 facilitates the modulation of the dynaamic supply bias.
For the first design iteration the secondd harmonic was
targeted, as that will have the greaatest impact on
performance. The simulated waveforms are taken at the
intrinsic node of the PA as the Cree modeel allows. This is
a great feature of the Cree model because the internal node
is where the waveform shaping needs to taake place.
The RF loadline of the MMIC is shownn in Fig. 6. The
RF IV characteristic shows the effectt of the output
capacitance of the device. For ET a constant capacitance
over drain voltage is ideal. The IV charaacteristic for this
design shows that the capacitance iss staying pretty
constant over the range of drain voltages.
The Cree G28V5 0.14 m MMIC proccess demonstrates
a power density of ~5 W/mm at 10 GHzz. For the 8x100
m FET layer this gives a power of 4 W per device. In

IV. MMIC
The devices were laid out with co
onsideration for thermal
dissipation and spaced as far apartt as possible given the
4x4 mm2 footprint. To simplify th
he design a symmetric
approach to the design and layout was
w taken. The MMIC,
fabricated using a highly-manufacturable 0.14 m optical
process is shown in Figure 8. The matching is integrated
with the combining and splitting neetworks and can clearly
be seen on the die. Each half of the
t symmetrically split
input network uses a low pass topollogy to match the input
impedance of the FET that is leess than 1 ohm to an
intermediate impedance. This inteermediate impedance is
then matched to 100 ohms and the parallel
p
combination of
the two halves provides 50 ohms at the input.

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Figure 7 Schematic diagram of the Class F-1 amplifier

Figure 9 Power drive-up at 10GHz VD

DD = 12V, Average
Power = 10W

The fabricated PA is run at saturation aat average power

under envelope tracking and the projectedd drive-up in Fig.
9 shows an efficiency of almost 60% att average power.
The projection is based on the 60% meassured data of the
6x100 m device at 12 V drain bias. The E
ET amplifier that
will be paired with this device, has an effi
ficiency of 76.2%
leading to an expected overall system
m efficiency at
average power (6.6dB back-off) of 45%.

ON
V. CONCLUSIO

A 10W average power, 32W peak power,

p
MMIC PA has
been designed for the dynamic supp
ply modulation that is
intrinsic to envelope tracking. A neew approach to the
characterization of the die to optimiize PA design for ET
has been taken. This method provid
des a viable alternative
to the build and test strategies that have
h
been used up until
this work. After fabrication using an
a optical 0.14 m GaN
HEMT MMIC process, the circuit achieved
a
over 45%
efficiency at 10 W of average power at 10 GHz.

ACKNOWLEDGME
ENTS
The authors would like to thaank David Via, Ryan
Gilbert and Karynn Sutherlin at AFRL, Wright-Patterson
t measurements.
AFB for their support in obtaining the
REFERENCESS
[1] F.H. Raab, Class-E, Class-C, and
d Class F power amplifiers
based upon a finite number of harmonics,
h
IEEE Trans.
Microwave Theory & Tech., vol. 49,
4 no. 8, pp. 1462-1468,
August 2001.
[2] Z. Wang, Envelope Tracking Poweer Amplifiers for Wireless
Communications, Artech House, Ju
une 2014
[3] J. Jeong, et. al., High-Efficieency WCDMA Envelope
Tracking Base-Station Amplifier Implemented with GaAs
HVHBTs, IEEE J. Solid-State Circuits, vol. 44, no. 10, pp.
2629-2639, October 2009.
A
N., Collins, G.,
[4] J. Pelaz, Collantes, J.M., Otegi, Anakabe,
Combined Control of Drain Video
o Bandwidth and Stability
Margins in Power Amplifiers for Envelope Tracking
osium (IMS), 2014 IEEE
Applications, Microwave Sympo
MTT-S, Tampa FL

Figure 8 Photograph of the GaN MMIC.

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GaN Technology in Base Stations Why and When?

Eric Higham
Strategy Analytics, Newton, MA, 01749, USA, 617-614-0721 ehigham@strategyanalytics.com
Abstract GaN technology for RF applications has been
widely adopted in defense applications, but commercial
acceptance has been much slower. Wireless base stations
seemed like the most likely commercial early adopter of GaN,
but this market has been slow to take off. This paper will
review the material properties of GaN material and how
these translate to device parameters. Developments with
incumbent LDMOS technology, along with new linearization
schemes will illustrate future direction for the wireless base
station market. The paper will close with forecasts for the
overall power market and how quickly GaN revenue will
grow.
Index Terms Base stations, Gallium arsenide, Gallium
nitride, LDMOS, power amplifiers, market research.

II. ADVANTAGES OF GANTHE WHY

The allure of GaN-based devices stems largely from the
attractive intrinsic physical properties of the material. The
material exhibits wide bandgap, high electron mobility,
high breakdown voltage, extremely high power density
and high gain at microwave frequencies. These properties,
coupled with excellent thermal conductivity make GaN
devices well suited for high power, high frequency and
wide bandwidth applications in extreme environments.
The bandgap, approaching 3.4eV, enables GaN devices
to support peak internal electric fields approximately five
times higher than either silicon or GaAs. This allows for
higher breakdown voltages, which is a critical attribute for
high-power requirements and for achieving higher
electrical efficiencies with higher supply voltages. GaN
material also has low intrinsic carrier concentrations at
device operating temperatures, which allows hightemperature operation and high radiation stability.
If we focus on RF applications, the material
characteristics of GaN offer clear advantages. GaN RF
transistors offer many times the theoretical maximum
output power density of GaAs or silicon transistors.
Additional key characteristics of GaN transistors for RF
applications include high cut-off frequency and good
thermal conductivity. GaN devices offer the best solution
for simultaneous high power, high frequency and high
temperature operation. Table 1 shows characteristics for
several of the materials commonly used in devices for RF
applications.

I. INTRODUCTION
The unique material properties of Gallium Nitride
(GaN) have been of interest to scientists and researchers
for some time. Preliminary research into GaN for LED
applications began in the 1970s and GaN HEMT devices
for RF applications began appearing in the early part of
the 2000s. GaN technology has been a mainstay of
defense-related RF power applications, with product and
process developments attracting a significant amount of
government and research funding. While many of the
advantages of GaN translate, the technology has held
much more promise than reality for commercial RF
applications, with products being a year or so away for
some time now!
The overwhelming majority of the existing revenue
comes from the LED market where GaN-on-sapphire or
GaN-on-SiC-based LEDs are currently being produced in
high volume, at very low prices. The volume in this market
is also pushing development of GaN-on-silicon and GaNon-GaN processes to further reduce costs and ease some of
the manufacturing challenges. While GaN has been very
successful in the LED market, the same has not generally
been true for RF or power electronics applications. There
are some very strong signs that this situation is changing
rapidly, with RF applications in market segments like base
station amplifiers leading the charge.

978-1-4799-3622-9/14/$31.00 2014 IEEE

III. BASE STATION POWER AMPLIFIERS

Initially, driven by need and transistor performance, the
high power amplification function in a base station was
achieved by a single channel power amplifier (SCPA). The
predominant early wireless technology was GSM with 200
KHz carrier bandwidth and 400 KHz separation. The
typical SCPA had 15 MHz channel bandwidth and could
accommodate 25 GSM carriers. Operators developed their
network planning around this capacity equation. With data
demand increasing explosively, the GSM standard could
not keep up and WCDMA (5 MHz) and then LTE (up to

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TABLE I
COMPARISON OF PROPERTIES FOR VARIOUS MATERIALS [1]

Si
5.4
7
1 x 10
1350
1.1
20
0.2
1.5
N/A

Lattice constant ()
Saturation velocity (cm/s)
2
e mobility (cm /Vs)
Eg bandgap (eV)
Ft (GHz) FET
Power density (W/mm)
Thermal conductivity (W/cmK)
Emission wavelength (m)

GaAs
5.7
7
0.8 x 10
8000
1.4
150
0.5
0.5
0.6-0.9

20 MHz) wireless standards were developed. Operators

could not turn off or migrate their existing GSM voice
services without losing revenue, so they were forced to
upgrade existing base station sites to enhance the data
capacity. This accentuated the challenges to SCPAs and as
Fig. 1 shows, an SCPA could accommodate 25 GSM
carriers, or three 5 MHz WCDMA carriers, or one 10
MHz LTE carrier, at most. If the operator needed to use
multiple standards at a single base station site, the carriers
would decrease accordingly.
PA

Bandwidth

GSM

WCDMA

LTE

SCPA

15 MHz

25

MCPA

60 MHz

48

Fig. 1.

InP
5.9
7
2.2 x 10
10000
1.3
300
----1.0-1.5

SiGe
5.5
--3000
0.7-1.1
50
0.3
--N/A

SiC
3.1
7
2 x 10
900
3.3 (4H)
20
10
4.9
N/A

GaN
3.2
7
2.5 x 10
1500
3.4
150
>30
~2.0
0.4

IV. GAN IN BASE STATIONS WHEN?

The base station power amplifier discussion to this point
has been technology agnostic. Requirements favor power
amplifiers that enable the rapid growth in data
consumption, while optimizing the business case for the
operators. GSM, with its narrow carrier bandwidth and
constant envelope, saturated power amplifier scheme has
some serious data shortcomings. As the need for more data
capability became apparent, the industry shifted to an
OFDM-based wireless standard. CDMA, WCDMA,
WiMAX and LTE all rely on linear amplifiers to meet the
evolving performance requirements.
With the need for high output power, high frequency
and high efficiency, base station power amplifiers were
identified early in the development process as a good
match for the advantages of GaN technology. Specifically,
WiMAX (IEEE 802.16) in the 3.5 GHz range was viewed
in the mid-2000s as the perfect driver for widespread GaN
deployment. The WiMAX base stations required linear
output powers up to about 80 watts per sector, with
channel bandwidths up to 20 MHz. The specification
allowed for operating bands in the 2 66 GHz frequency
range, but most of the activity was centered on the 2.5 and
3.5 GHz bands. Revisions to the original specification
ultimately allowed for data rates up to 1 Gb/sec, resulting
in linearity, spectral efficiency and power added efficiency
greater than existing wireless standards. All these
parameters were a good fit for GaN-based power
amplifiers. However, the reality was that outside of some
deployments in Japan, GaN-based power amplifiers did
not catch in on base stations. So, what happened?
Like any new technology, GaN devices had to
successfully address concerns about reliability,
manufacturability and cost. There were other competitive
technologies that were very mature and there was initial
reluctance in using the unproven GaN technology because
of the lack of data from other users. Essentially, no one
wanted to use it because no one was using it. Perhaps the

Carriers allowed by different PA architectures. [2]

The need for increasing wireless data capacity has

driven improvements to device technology. The 15 MHz
channel bandwidth shown in Fig. 1 for SCPAs has evolved
to multi-carrier PAs (MCPAs) with at least 60 MHz
channel bandwidth. The increase in capability is
significant. Where the SCPA of Fig. 1 could accommodate
the specified number of carriers for each individual
standard separately, the 60 MHz MCPA can accommodate
the specified number of carriers for the standards at the
same time!
With wireless data growing strongly, amplifier and
device manufacturers continue to expand the channel
bandwidth capability. The 60 MHz bandwidth shown
above has been expanded to 115 MHz, with development
activity aimed at 160 MHz bandwidth. This development
allows power amplifiers to accommodate more and higher
bandwidth LTE carriers as a means of increasing data
capacity. The latest technique to make use of the broader
channel bandwidths is carrier aggregation. In this scheme,
adjacent or non-adjacent frequencies will be combined to
increase the data capacity of the carrier.

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biggest impediment at the time was the lack of scale for

WiMAX deployments. Originally envisioned as the first
global wireless broadband standard, WiMAX never
fulfilled those expectations and it has settled into a small
niche as a fixed broadband technology.

the base station market too easily. Fig. 2 shows how

successive generations of LDMOS technology are
reducing RDSon and improving device efficiency in the
process. The storyline for the base station power amplifier
market has been that as soon as a technology begins to
threaten LDMOS, developers release a new generation of
the technology that has better performance and is cheaper
than the previous generation. Inputs from LDMOS
suppliers indicate that the technology is ~$0.20/Watt.

A. The Competition
One of the reasons that WiMAX saw so much
development activity during the mid-2000s was this was
the beginning of the broadband wireless revolution.
Consumers were embracing the benefits of anywhere,
anytime mobile voice and data connectivity, with the
switch to digital communications fueling demand. The
result was strong growth in base station deployments to
improve coverage and upgrades to improve quality and
capitalize on the emerging wireless data demands.
The preferred technology for base station power
amplifiers continues to be laterally diffused metal oxide
semiconductor (LDMOS) transistors. LDMOS is a siliconbased process where the MOSFET structure is formed
laterally, rather than vertically to reduce parasitic
capacitance and extend the operating frequency range. The
LDMOS community addressed the initial WiMAX
opportunity by releasing a generation of the technology
that extended performance to 3.5 GHz. With WiMAX
diminishing in importance, most of the existing and
planned wireless standards are between 600 and 2700
MHz, well within the frequency range of LDMOS.

B. The Base Station Power Semiconductor Market

A challenge for GaN is the dominance of LDMOS in the
market. Fig. 3 shows our estimate of the 2013 base station
power semiconductor market. A quick word of
explanation: we define power as the driving and output
stages of the transmit amplifier. The small cell concept
for base stations is anticipated to be the driving trend
going forward. These base stations will likely have
transmit powers of less than 2W. The relatively large
gallium arsenide (GaAs) revenue shown is the result of
these small cells and driver functions. While LDMOS is
the dominant technology, there is no doubt that GaN is
finally seeing wider adoption in base station power
applications.

HV8

Source: Strategy Analytics (unpublished)

Fig. 3.

2013 base station power semiconductor market share.

V. GAN IN BASE STATIONS THE FUTURE

There are several factors that will influence the growth
trajectory of GaN in base station power applications. The
current dominance of LDMOS, the eventual rise of the
small cell architecture with much lower transmit powers
and the increasing saturation of the mobile market will all
act to slow the penetration of GaN. Despite these hurdles,
there are several trends that will speed the adoption of
GaN into base station applications.

S
Source: Freescale presentation
Fig. 2.

Progression of performance with LDMOS generation.

While the performance benefits of GaN are undeniable,

the incumbent LDMOS technology is not ceding control of

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These trends all relate to the performance improvements

GaN transistors offer. Fig. 4 shows the most obvious
example of the advantage of GaN versus LDMOS
transistors. This chart shows GaN has roughly 5 times the
power density of LDMOS and can achieve efficiencies
almost 20 percentage points higher.

revenue attributed to the highest power applications will

decline from about $480 million to $434 million.

Source: Strategy Analytics (unpublished)

Fig. 5.

We estimate that revenue from GaN-based devices will

reach approximately $43 million in 2018. While not
explosive, this growth reflects a flattening market.
Developments aimed at making GaN-on-silicon mainstream,
coupled with the larger diameter substrates common with
silicon promise to keep reducing the cost of GaN devices. As
the price keeps dropping, GaN-based devices will continue to
offer a compelling argument for the base station power
amplifier segment.

Source: 2013 IEEE Phased Array Conference

Fig. 4.

Base station power forecast.

LDMOS vs. GaN performance at 28V.

Network efficiency is of critical importance. For the

operators, higher efficiency means lower operating costs.
This, in turn, makes for a greener solution and this is a
feature the operators and equipment manufacturers are
touting heavily. Efficiency is such an important topic that
techniques such as Doherty linearization, both symmetric
and asymmetric, digital predistortion, envelope tracking,
along with different biasing schemes are being
implemented to improve the efficiency of the higher power
macrocell PAs, along with the lower power small cell PAs.

VI. CONCLUSION
The benefits of higher efficiency, operating frequency,
bandwidth, linearity and power density, along with the
capability to operate in harsher environmental conditions will
allow GaN-based amplifiers to increase market share in base
station applications. The dominant technology will continue to
be LDMOS and it will continue to be a formidable competitor,
but we expect the stranglehold on the market will loosen. Both
technologies will face a challenge from the small cell
architecture that relies on many, lower power base stations.
The rate of adoption of this new architecture will likely be the
biggest determining factor in the size of the market for GaNbased power amplifiers in base station applications.

C. Base Station Power Forecasts

Taking all these factors and trends into account, we have
arrived at the forecast shown in Fig. 5. There are several
important trends that surface. First, we believe that the
entire power market will increase to roughly $700 million
in 2018, but this will be driven by the development of the
small cell architecture. This concept has been very slow to
develop, so this profile may change. We anticipate a drop
in LDMOS revenue. Some of this will be the result of
losing share to GaN, but the larger trend is that there are
very few greenfield mobile developments. The vast
majority of areas that justify mobile deployments already
have them, so the need for the highest power macrocells is
declining. The decline in LDMOS revenue will not be
offset by the increase in GaN revenue and the total

REFERENCES
[1] E. Higham, GaN Microelectronics Market Update 20122017, Strategy Analytics Forecast and Outlook Report,
p.23, May 2013.

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[2] E. Higham and C. Taylor, Wireless Infrastructure RF Power

and Amplifier Device Demand: 20112016, Strategy
Analytics Forecast and Outlook Report, p.33, November
2013.

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Development of High-Efficiency X-band Outphasing

Transmitter
Chenggang Xie, David Cripe, John Reyland, Don Landt and Anders Walker
Advanced Technology Center, Rockwell Collins, Inc., 400 Collins Road, Cedar Rapids, IA 52498
chenggang.xie@rockwellcollins.com 319-263-0790, david.cripe@rockwellcollins.com 319-295-1118,
don.landt@rockwellcollins.com 319-295-3936 and anders.walker@rockwellcollins.com 319-263-2140
Abstract:
We describe an advanced X-band outphasing
power amplifier as a promising solution to provide high
power output and wide modulation bandwidth for nextgeneration RF digital communication. Our proposed PA
system consists of a high efficiency X-band GaN HEMT
based Class-E outphasing PA MMIC.

available techniques for attaining efficient power

amplification of a complex-modulated waveform, an
outphasing transmitter system utilizing Class-E power
amplifiers appears to offer the best combination of high
efficiency and high modulation bandwidth.

Index Terms Outphasing, Efficiency, Gallium Nitride,

Chireix, Lossless Combining,

This paper discusses a new X-band PA MIMC based

transmitter design employing lossless, non-isolated
combining of outphased PAs to accomplish amplification
of high-bandwidth complex modulated waveforms, while
maintaining high efficiency DC-to RF conversion.

I. INTRODUCTION
The expansion of capability in both military and
commercial communication systems will be enabled
through the enhancement of wireless system bandwidths.
Due to the congestion of existing allocations, and the
availability of unoccupied spectrum at higher frequencies,
there is significant motivation to develop communications
systems capable of operating at higher carrier frequencies,
and at higher modulation bandwidths.

II. BACKGROUND
Outphasing modulation, invented by Chireix [2] is a
technique in which amplitude modulated signals are
produced by the vector addition of the complementarilyphase-modulated outputs of two highly efficient power
amplifiers. Amplitude modulation of the transmitter
output occurs when the phase differential between the
drive signals of the two power amplifiers creates an
effective load modulation of each PA through the
combiner circuit.

While developing the next-generation communication

transmitter, there is considerable motivation to maximize
the system power efficiency of the system. In
communication systems where a complex modulation
waveform is to be reproduced, the ubiquitous Class-AB
linear amplifier may typically exhibit efficiencies of 10 to
20 percent. Improvement of the efficiency of the radio
frequency (RF) power amplifiers (PA) would reduce
power dissipation in PA semiconductor devices along with
thermal stress, allowing the generation of more power per
device. Further, reduction of junction temperatures
improves device reliability and MTBF.

While conventional design practice employs use of an

isolated, hybrid combiner for the summation of outputs of
two or more power amplifiers, this is not the preferred
implementation for an outphasing transmitter. Out-of
phase energy in an isolated combiner is dissipated in a
reject load so that the impedance presented to the power
amplifiers is constant regardless of their phase difference,
and power input to the transmitter is constant regardless of
the amount delivered to the antenna, degrading system
efficiency. In contrast, a Chireix circuit employs an
asymmetrical, non-isolated combining means, which
preserves efficiency when the transmitter is operated at
less than peak power.

To this end, non-linear classes of switching power

amplification have been devised, such as Class-D, -E, -F,
possessing drain efficiencies surpassing 80%, and with
theoretical maxima approaching 100%. Because these
circuits operate with their active devices as switches, the
RF output amplitudes are fixed as a function of supply
voltage and output loading. The development of schemes
for efficiently impressing amplitude modulation upon the
outputs of these amplifiers has proven challenging. Of

978-1-4799-3622-9/14/$31.00 2014 IEEE

The choice of power amplifier class has bearing on the

operation of the transmitter during outphasing. Generally
speaking, the highly efficient Class-D, -E-, -F, etc, power

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amplifiers reduce device loss through specifically tailored

drain voltage and current waveforms which are shaped so
that within the device, the simultaneous occurrence of
non-zero voltage and current is avoided. This is attained
through specific load impedances presented to the power
amplifier drain circuit at the fundamental operating
frequency and its harmonics. During outphasing, these
impedances are upset due to the mutual load modulation
from one power amplifier to the other occurring due to the
phase difference of the drive signals, leading to increased
losses in the amplifier devices.
Of power amplifier classes available, Classes D and F
are optimized through inclusion of specific harmonic
content so that device drain voltage waveforms approach
square waves, maximizing the dV/dT of the drain
waveforms. In contrast, a Class-E power amplifier
operating at a given voltage and power will possess drain
voltage and current waveforms with comparatively lower
dV/dt and dI/dt. Consequently, for a given amplifier
device, the effects on efficiency resulting from a non-ideal
load impedance are less Class-E power amplifier than for
other classes. For this reason, a Class-E circuit was
selected as the basis for the outphasing transmitter.

Fig. 1.

PA Test Module with 7 W MMIC

The MMIC test was initially done by measuring the

power output of the MMIC as a function of the outphasing
angle between two inputs to the MMIC. In the test setup
depicted in Fig. 1, a common RF source was split into two
equal RF inputs by a resistive splitter. The phase angles of
two identical RF signals prior to being applied to the
MMIC were alternated by two phase shifters respectively.
The output power from the MMIC depends on the phase
angle difference between two identical RF signals driving
the MMIC. The test setup was calibrated for both
amplitude and phase.

III. X-BAND GAN HEMT BASED OUTPHASING PA

MMIC DESIGN AND CHARACTERIZATION
The X-band outphasing PA MMIC in this work was
realized with TriQuints 0.15 um GaN-on-SiC process.
The size of the die shown in the insert of Fig. 4 is 4 mm x
3 mm. The chips are adhered to the copper base plate
using high thermal conductive paste and wire-bonded to
the ceramic substrate. All DC bias circuit components,
including RF choke and DC blocking capacitors are
integrated on the chip. Only small bypass capacitors are
required externally.

Fig. 2 shows the measured output power, power added

efficiency (PAE), and drain efficiency from the
outphasing PA MMIC as a function of the outphasing
angle (OPA) at a frequency of 9.8 GHz. For the poweroutphasing angle measurement, the MMIC is biased at the
quiescent current density over device periphery of
100mA/mm at a drain voltage of 16V. The maximum
output power, 38.2 dBm, occurs at -10 degree phase
difference, while the maximum PAE occurs at a -60
degree outphasing angle. The output power curve is fairly
symmetric with 10 degree offset to the left due to the
asymmetry of the drain chokes between the two amplifier
sections. As opposite, the PAE curve is designed to be
asymmetric with 50-60 degree offset. Due to asymmetric
nature of the design, the power-OPA relationship differs
depending on the positive or negative change of the phase
angle. Illustrated in Fig. 2, as the OPA becomes more
positive, the PAE quickly decreases. However, as the
angle becomes more negative, at the beginning, the PAE
actually increases slightly and then slowly drops over -50
degrees. At below -100 degrees, the PAE decreases very
quickly. For PA applications, in order to maximize the
efficiency of PA, the outphasing angle change must be
restricted between 0 to -180 degrees.

The Class-E amplifiers employed Grebennikov tuning

of the output network, employing drain chokes with finite
impedance. The RF outputs of two of these die were
combined using a pair of non-isolated quarter-wave
transmission line circuits. A degree of asymmetry was
included in the drain choke sections of each die in a quasiChireix circuit. While the Cds of the GaN die employed
exceeded the Sokal limit for Class-E operation at the
design frequency, a moderate amount of Class-F-1
harmonic peaking in the drain current waveform of the
devices was employed to preserve zero-voltage switching
and enhance efficiency.

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For better illustration, the efficiency is plotted as a

m the maximum
function of back-off-power (BOP) from
output power in Fig. 3.

IV. DYNAMIC TEST RESULTS

E

To test the dynamic modulation performance of a realworld implementation of an X--band outphasing PA

modulated through digital control the MMIC depicted in
boratory.
Outphasing
Fig. 1 was set up in the lab
modulation for each PA, plus dig
gital pre-distortion was
implemented in Simulink. The simulation output signal
files, one for each PA branch, weree downloaded to a pair
of Agilent M9330A arbitrary wavefform generators (ARB)
and clocked out at 1.25 GHz sam
mple rate. Finally the
ARB outputs were upconverted
d to 9.8 GHz real
outphasing signals to drive the PA.
Sampled estimates of the PA
A output phase were
collected and used to calculate the
t phase error model
parameter vector to determine the pre-distortion function.

Fig. 2.

Fig. 4 is the PA output constellaation using the MMIC,

the exciter circuitry, operating upon
n 64K sample files that
represent a random / 4 DPSK sig
gnal at 78 MHz symbol
rate.
The error vector magniitude (EVM) of the
constellation points is <1%. The yellow
y
traces show the
signal trajectory between signal points; the peak to
average power ratio of about 3 dB is apparent.

MMIC Output Power, PAE and Draain Efficiency as a

Function of Outphasing Anglle

As seen in Fig. 3, depending on the diirection of phase

angle change, at the same back-off-pow
wer, there are 25
percentage point change in PAE. For typical applications,
the PA is limited to be operated along thhe top half of the
curves. The results show that the PAE
E is above 60%
within 3 dB back-off power and 45% aat 6 dB back-off
power. Good efficiency over wide rangee of the back-off
power
could
provide
significantt
performance
improvement for commercial and militaryy applications.

Fig. 4.

DQPSK at PA Outtput, 78 MHz Rate

Fig. 5 is the power spectrum of the

t signal in Fig. 4. To
demonstrate the effect of phase pre--distortion, the blue and
red traces show the adjacent channeel interference with and
without the phase error model enab
bled. The green trace is
the calculated ideal PA output.
Further tests indicated the capab
bility of the MMIC PA
to accommodate modulation bandw
widths of 512 MHz.

Fig. 3. MMIC PAE and Drain Eficiency as a Function of

Back-off Power

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Table of Contents

Fig. 5.

DQPSK PA Output Spectrum, 78MHz Rate

ACKNOWLEDGEMENTS

REFERENCES

This research was funded through the DARPA MTO

Microscale Power Conversion (MPC) program, sponsored
by the Air Force Research Laboratory (AFRL).
Distribution Statement "A - Approved for Public
Release, Distribution Unlimited.
The views expressed are those of the authors and do
not reflect the official policy or position of the Department
of Defense or the U.S. Government.
Copyright 2014 Rockwell Collins, All rights
reserved.
"In the event permission is required, DARPA is
authorized to reproduce the copyrighted material for use
as an exhibit or handout at DARPA-sponsored events
and/or to post the material on the DARPA website."

[1] Cripe, D.W. and Walker, A.P., High-Efficiency

Outphasing Transmitters for Wide-Band
Communications, Presented at Government Microcircuit
Applications and Critical Technology Conference, Las
Vegas, NV, March 11-14, 2013
[2] Chireix, H., High Power Outphasing Modulation,
Proceedings of the IRE, vol. 23, issue 11, November 1935,
pp. 1370-1392.
[3] Ampem-Darko, S. and Al-Raweshidy, Gain/Phase
Imbalance Cancellation Techniques in LINC
Transmitters, Electronics Letters, vol. 34, no. 22, pp.
2093-2094, Oct. 1998
[4]Sokal, N.O.; Sokal, A.D.; Class E A New Class
Of High-Efficiency Tuned Single-Ended Switching
Power Amplifiers IEEE Journal of Solid-State Circuits,
Volume 12, Issue 5, October 1975, pp. 168 - 176

Document classification is 3E001, License Required

under Department of Commerce.

148

Table of Contents

Broadband Doherty Alternative with Filter Design Considerations

Jeff Jones (j.jones@freescale.com), Basim Noori (basim.noori@freescale.com), Jeff Frei
(jeff.frei@freescale.com) and Enver Krvavac (enver.krvavac@freescale.com)
Freescale Semiconductor INC, 2100 E. Elliot Rd. Tempe, AZ USA
Abstract Doherty Amplifiers have become the standard
architecture for high-efficiency cellular infrastructure
applications, but most designs in production and in the field
are limited in RF bandwidth (RFBW). Though it would be
desirable to have Doherty amplifiers that operate over
several adjacent bands, the importance of system efficiency
under corrected linearity conditions has limited the
deployment of wider-bandwidth Doherty amplifiers. This is
particularly true where amplifiers require peak power
capability of 500W or greater. This paper discusses filter
design techniques related to RF power semiconductors
targeted for wideband Doherty operations, as well as an
amplifier technique that we call Frequency Selective
Broadband (FSBB) Doherty designthis technique allows an
alternative amplifier design covering multiple operating
bands, without trade-offs in efficiency performance.
Index Terms Doherty amplifiers, LDMOS, GaN,
Integrated Passive Device (IPD), Broadband.

broadband Doherty circuit (20% fractional BW in total),

that has no degradation in key parameters such as gain and
efficiency (compared to a single-band design), but
provides many of the same manufacturing benefits that a
more traditional 20% RFBW Doherty circuit would bring.
II. PACKAGED RF POWER TRANSISTORS
For many years, traditional packaged RF transistors
consisted of an RF package, active die blocks, and
MOSCAPs connected with wire bonds. The internal
matching for narrow BW systems such as single-carrier
GSM was typically a single section low pass network on
the input, and a single section high-pass network on the
output, as shown in Figure 1. The filter poles for each
network were typically close together in frequency to
maximize the gain and impedance transformation, making
the device relatively easy to match at the next level
assembly (PCB). As the industry transitioned to wider
bandwidth systems and Doherty amplifiers, the poor phase
linearity caused by this simplistic use of Chebychev filter
elements became a limiting factor in the RFBW capability
of the entire amplifier architecture.

I. INTRODUCTION
The expansion of frequency bands used for cellular voice
and data transmission has lead to a significant amount of
research work on broadband capability for Doherty
amplifiers [1], since equipment providers would prefer to
use a single amplifier design to cover multiple adjacent
frequency bands. An example of multiple adjacent bands
all operating below 1GHz are band 20 (791-821 MHz),
band 5 (869-894 MHz), and band 8 (925-960 MHz). To
cover all of these bands with a single Doherty amplifier, it
would need to cover 20% fractional RFBW. It is certainly
feasible to design such an amplifier, particularly with the
very low Cds/watt available with Gallium Nitride (GaN).
The bigger challenge is to do so in a Doherty circuit
suitable for mass-production, at high power (500W peak
power), while maintaining the power gain, at average
power (60W at the antenna), and drain efficiency
equivalent to a single-band amplifier (approximately 4%
fractional bandwidth).
One source of Doherty RFBW limitation stems from
limitations in the packaged RF power transistor used at the
core of the Doherty amplifier. Filter design techniques,
with emphasis on phase distortion properties such as
group delay (GD) ripple and deviation from linear phase,
can remove the RF transistor as the limiting factor.
An alternative technique for Doherty circuit design
using a broadband transistor, creates a frequency-selective

978-1-4799-3622-9/14/$31.00 2014 IEEE

Fig. 1. Typical packaged RF transistor with internal pre-match

using MOSCAPs and wire bonds

Separating the poles creates a broadband filter response,

with improved phase linearity, but the impedance
transformation is limited, making the input impedance at
the package very low. The effect of the broadband filter
response is shown in Figure 2. This improves both
bandwidth and isolation, which is very important in the
high gain devices used today. The main advantage,
however, can be seen in Figure 3, which shows
improvement in deviation from linear phase, with only a
very small degradation in max stable gain.

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Table of Contents

frequency. There are some obvious problems with the GD

ripple in both Chebychev and Butterworth filters
approaching the cut-off pole.

Fig. 2. S-parameters plots of a 200W LDMOS pre-matched

Xstr with narrow pole spacing (before), and wider pole spacing
(after).

Fig.4. Fractional Bandwidth limits of /4 transmission line

transformers.

Fig. 3. Max stable gain and deviation from linear phase under
the same Xstr before and after conditions from figure 2.

III. FILTER DESIGN FOR PRE-MATCHING

The Doherty BW limiting factor would seem to be the
quarter-wave transformer [2]-[3] used as the
combining/modulating element, but this can be examined
using (1).

(1)

Fig. 5. Low pass filter response where (A) is the upper BW

limit for the application pass-band (Chebychev & Butterworth)

From this equation, Figure 4 shows that for a symmetric

(2:1 transformation ratio) or asymmetric (3:1
transformation ratio) Doherty bandwidth is significantly
greater than 20% with a return loss of 20dB. This
bandwidth, however, is considering the impedance
transformation from one transmission line impedance to
another. The GD ripple of a TEM transmission line,
however, is ideal, so the goal of the transistor and prematch is to emulate a transmission line as closely as
possible. There are practical aspects as discussed, such as
maintaining package-level impedance, as well as keeping
gain and efficiency as high as possible, but by optimizing
for phase properties, we can meet these requirements with
very low group delay ripple. Figure 5 shows the response
of Chebychev, Butterworth and Bessel low-pass filters in
terms of magnitude of loss and group delay ripple versus

Though Bessel filters have the best GD response, they

are not practical as they provide no impedance
transformation. To minimize GD ripple using Chebychev
or Butterworth filters, the upper limit of the application
frequency needs to be significantly lower than the cut-off
pole. For instance if the transistor is for use between 1.8
2.2 GHz, the cut-off pole should be at approximately 2.4
GHz. To accomplish good GD while also keeping the
package level impedance up, additional poles are needed.
This requires low-loss passives, to enable integrating
multiple sections on chip.

cos

m2

0 L

L- 0

IV. INTEGRATED PASSIVE DEVICES

With our rich history in relatively high power RFIC
design, Freescale has been a leader in integrated

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Table of Contents

passives on silicon. New processes havee been developed

to raise the quality factor of these inntegrated passive
devices (IPDs) so that they make sense ffor use in singlestage pre-matched RF transistor products. With the ability
to design multi-section matching, IPDs allow broadband
capable RF products that are ideal for highh-power Doherty
amplifiers.

Vdd = 48V
Freq. (MHz)
728
790
822
865
895
920
960

PD MATCHING
V. HIGH-POWER 48V LDMOS WITH IP
By designing with IPD technology, we successfully
LDMOS product
created a broad-band high-power 48V L
suitable for a 20% RFBW Doherty ampllifier. The design
consists of 2-section input IPD that trannsforms the low
FET input impedance to a broad-band and manageable
impedance at the package plane, see Figure 6, while
maintaining very good group delay riipple, shown in
Figure 7. With the latest generation oof 48V LDMOS
technology, which provides high Rp andd low Cds, there
was no need to design a pre-match on the output side.
Two of these input-pre matched devices are housed in a
mmetric Doherty
dual-path package, NI780-4, for sym
applications targeting 500W of peak-poower, with largesignal loadpull characterization shown in Table 1, and the
internal matching of one path of the devicce in the package
shown in Figure 8.

Tuned at Max Power (P3dB)

Zload () Pout (dBm) Gain (dB) Eff. (%)
2.77-j0.74 55.14
20.6
62.2
2.42-j0.29 55.02
20.9
64.5
2.22-j0.30 55.04
21.1
64.7
2.37-j-0.71 54.90
20.7
62.4
2.46-j0.95 54.82
20.3
60.8
2.51-j1.13 54.74
20.2
59.6
2.68-j1.42 54.67
20.1
59.1

Tuned at Max Efficiency (P3dB)

Zload () Pout (dBm) Gain (dB) Eff. (%)
2.29+j1.02 53.94
21.9
71.2
2.99+j1.60 53.68
22.4
74.6
2.32+j1.44 53.27
23.1
75.3
1.90+j1.21 52.97
23.2
73.5
1.73+j1.06 52.67
23
71.7
1.73+j0.83 52.75
22.5
70.7
2.07+j0.52 53.03
21.8
69.5

Table 1. Broadband Device (1-path) perrformance, 728-960 MHz,

under P3dB load-pull.

Fig.8.

Active VHV LDMOS device with IPD input block

VI. FREQUENCY-SELECTIVE BROADBAND

B
(FSBB)
DOHERTY DESSIGN

Fig.6.

Two different Doherty circuit approaches

a
were taken
with this deviceboth use one-p
path of the dual-path
transistor as the main and the other path as the peaking
s
925 960
device. The first approach was a single-band,
MHz Doherty, while the second approach was a multipleband, 790 960MHz Doherty covering
c
20% RFBW.
These will be compared to the FSBB
B Doherty circuit.
Here we introduce a unique Do
oherty design approach
referred to as Frequency Selectiv
ve Broadband (FSBB)
Doherty. FSBB targets Doherty peerformance levels equal
to single-band designs, but wiith only minor chip
component changes, are capable to operate across the
0 MHz.
three major bands between 790-960
Since the transistor product is broadband
b
capable, the
goal of this technique is to use th
he same PCB artwork,
splitter and input match circuiit (to 50), with a
combination of distributed and lum
mped elements used to
make up the output match and Do
oherty combiner. This
means the designer must consid
der all frequencies of

Broadband input impedance, 600-1200 MHz.

HV RF device.
Fig.7. Group Delay for a single path of the VH

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Table of Contents

operation during the design phase, but there is

considerable re-use in the final manufacturing of the
Doherty amplifier. In Figure 9, examples of the FSBB
band 20 and band 8 Doherty amplifier circuits are shown
(same situation for band 5). Only minor changes to chip
capacitors in the output are made (circled area).

791-821
MHz

Fig.10.

Doherty circuit comparisons

IX. CONCLUSION
Broadband Doherty circuits are of considerable
importance as new frequency bands and standards come
online. Managing amplifier design for each single band of
spectrum has become increasing difficult for base-station
suppliers. An alternative approach using FSBB Doherty
design has been introduced and does have some
performance advantages, and maintains most of the
manufacturing efficiency of a full-BW design approach.
Both approaches are validwe will leave it to the basestation suppliers to weigh the benefits and limitations.

925-960
MHz

Fig.9.

FSBB Doherty for 791-821 and 925-960 MHz.

VII. DOHERTY COMPARISON

Figure 10 shows the compared performance between the
Doherty circuits, in terms of efficiency at 7dB back-off
from peak power, and gain over the 20% bandwidth. The
full 20% BW Doherty circuit was realizable, but it did
take some performance hit compared to the FSBB Doherty
as well as the single band Doherty.
The first thing to be noted was a power loss of roughly 1
dB in the full BW Doherty. Peak power of the FSBB and
single band circuits are 57dBm at 48V Vdd, while the full
BW circuit is 56.5dBm at 50Vdd. Additionally, each
circuit met digital pre-distortion (DPD) linearization
criteria of -55dBc using 2 WCDMA carriers with 40 MHz
signal bandwidth, (composite PAR of 6.5dB).
All circuits showed Doherty gain of approximately
19dB across the 20% BW, but the broadband circuit gain
drops at the upper band edge. Drain efficiency of the
single band circuit was equivalent to the FSBB circuit in
the upper band, but in comparing the FSBB and the full
BW Doherty circuits across the 20% BW, the FSBB
circuit had 2-5 points higher efficiency.

ACKNOWLEDGMENT
The authors wish to acknowledge and thank David YuTing Wu for his work to realize the full BW Doherty
circuit used for the comparison to the FSBB Doherty.
REFERENCES
[1] W. H. Doherty A new high efficiency power amplifier for
modulated waves. Proc. IRE vol. 24, pp. 1163-1182,
September 1936.
[2] K. Bathich, A. Markos, G. Boeck, A wideband GaN
Doherty amplifier with 35% fractional bandwidth
th
Proceedings of the 40 European Microwave Conference,
pp. 1006-2009, September 2010
[3] R. M. Fano Theoretical limitations on the broadband
matching of arbitrary impedances. J, Franlin Inst., vol.
249, pp. 57-83, January 1950, pp. 139-154 February 1950.

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Status of the GaN HEMT standardization effort at the Compact

Model Coalition
Samuel D. Mertens
Keysight, EEsof EDA, Santa Clara, CA, 95051, USA, 1-408-553-4466, samuel_mertens@agilent.com
Abstract The Compact Model Coalition (CMC), a part
of the Silicon Integration Initiative (Si2), is standardizing a
compact model for Gallium Nitride High Electron Mobility
Transistors (GaN HEMTs). After a global search for model
candidates, eight were selected to present at a CMC meeting.
In the next phase, selected candidates will be evaluated for
their ability to fit a common set of hardware data. After a
third round of more comprehensive testing, a standard GaN
HEMT model will be selected.
Index Terms

Gallium Nitride HEMTs,

Standardization, Semiconductor device modeling.

different design and tool flow. In addition, because CMC

standard models are used by many, if they have any shortcomings, they tend to be exposed and fixed quickly.
Recent dynamical models that push the boundaries of
conventional compact models have achieved excellent
fits using artificial neural networks to model multivariate
constitutive relations coupling trap and temperature
variables to electrical nonlinearities [18].
II. THE STANDARDIZATION PROCEDURE

I. INTRODUCTION

There is a standardization procedure which needs to be

followed. First, the committee collects requirements from
member companies and the wider industry on what they
need to see in a GaN HEMT compact model. These were
broadcast to the world in a call for standard model
candidates in April 2013. During this first phase, the
model candidates were asked to self-evaluate how well
their model complies with the requirement list. The
committee also reviewed the literature to evaluate the
candidate models separately.
During the second phase, selected candidates and their
sponsor are fitting their model to a common set of
hardware data and are asked to ultimately demonstrate
how well the model fits the data and show some measures
of how well it performed during circuit simulation. The
models which are deemed successful, then move to the
third phase in which all members are asked to evaluate the
model, according to their requirements and asked to
report. In the end, a vote occurs to standardize.
There are at least two distinct applications for GaN
HEMTs, the power-switching and RF applications, which
pose different requirements on the model. The committee
is hopeful that a single standard model will cover both. If
this is not possible, a second standard model could be
considered.

The CMC has been the premier standardization

organization for compact transistor models since its'
inception in 1995. The coalition has standardized ten
transistor models [1], which are the work horses for
analogue circuit simulation. Table 1, shows the list of
CMC standard transistor models, starting with the BSIM3
model [3], and most recently the BSIM-CMG model [8].
The coalition has also standardized API's and netlist
languages, as these are needed to efficiently share models
among companies. This effort is its' first foray into
standardizing a III-V semiconductor transistor model.
CMC membership which represents a large portion of
the traditional silicon semiconductor industry, formed a
sub-committee to start the process of standardizing a GaN
HEMT model in 2011. While the silicon semiconductor
industry has benefited from standardized models, which
are uniformly available across a wide set of EDA tools,
the III-V semiconductor industry has largely relied on
proprietary models. The technological advantages of GaN
HEMTs make the technology attractive to both market
segments [15].
Compact HEMT models have been available for a while
[16], and [17] provides a review and history. Yet, most
GaN HEMT foundries seem to use a proprietary compact
model, or a proprietary adaptation of a published compact
model. This makes it more difficult to share model
information with customers, who might have a very

978-1-4799-3622-9/14/$31.00 2014 IEEE

III. FIRST PHASE

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A check-list of 4 supporting requirements and 16 must

have features were given to the candidates. The supporting
requirements are there to ensure that the model can be
used by industry, similar to every other CMC standard
model. Upon standardization, it will be released as open
source code and model documentation. Working samples
and a documented extraction flow will be made available.
An infrastructure has to be formed to provide equal and
timely access to model information, with a commitment to
the CMC model QA and release procedures. The final part
is that a working and efficient supporting mechanism is
put in place, for which the CMC provides funding to the
model developer.
There were sixteen technical requirements for the model
to fulfill. The model needs to be physical, with a
dependence on geometrical dimensions. It needs to
accurately model the charges and currents at the terminals
for all working modes, including the high-power and subthreshold regions. The charge model needs to be charge
based (in contrast to capacitance based) and charge
conserving. Charge and current needs to be selfconsistently derived using the same charge formulation.
An accurate model for the Schottky gate currents should
be included, just like all the physical noise sources. An
important requirement is that the model passes Gummel
and McAndrew symmetry tests [19].
Charges and currents need to be modeled accurately
across a wide temperature range, with self-heating enabled
using a thermal node. GaN HEMT technology can operate
in a very wide range of temperatures compared to more
commonly used semiconductors.
The following requirements are more specifically
needed for GaN HEMTs, and might not be a part of most
CMC models. The model has to be capable of modeling
dynamic trapping effects. The model has to feature an
accurate representation of the parasitic, bias-dependent
resistances and capacitances, taking the true asymmetry of
the device into account. The standard model needs to have
the capability to model field plates, and large periphery or
unit gate width scaling for both trapping and mechanical
stress effects.
Last but not least, the model needs to show good
convergence in circuits of an appropriate scale, for both
frequency and time-based simulation. This implies that the
model works for reverse and forward drain-to-source
voltage.
Ultimately, eight candidates were considered close
enough to be selected to speak at the CMC meeting in
December 2013: Angelov [20], Anwar [21], Chan [22],
Khandelwal [23], Martin [24], Radakrishna [25], Shur
[26] and Trew [27]. The committee decided it would
prefer the standard model would use a surface-potential-

TABLE I
CMC STANDARDS
Model

Year of
Reference
standardization
MOSFETs

BSIM3
BSIM4
PSP
HiSIM2

1996
2000
2006
2011
Silcon-On-Insulator MOSFETs
BSIMSOI
2002
HiSIM_SOI
2012
Multigate MOSFETs
BSIM-CMG
2012
BJTs
MEXTRAM
2004
HiCUM
2004
LDMOSFETs
HiSIM_HV
2007
Resistors
R2_CMC
2005
R3_CMC
2007
Junction Diodes
DIODE_CMC
2009
Application Program Interface
TMI2
2010
Netlist Language
2012
CMC Standard Netlist
Language and Model File
Format

[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]

[14]

based or charge-based current model approach. It decided

against excluding candidates on this criterion alone. The
surface-potential approach has demonstrated to have
benefits for silicon FET models [4].
The candidates showed that there were many different
approaches to approach the same problem. All showed
good fits to self-selected measured data. Most
demonstrated that they passed the McAndrew symmetry
tests.
A. Angelov model
This model is the most empirical of the model
candidates, but it has been successfully used in industry,
and is implemented in a wide range of EDA tools [20]. It
is very accurate in the frequency domain, as the modeler
has excellent control over the derivatives of the current

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Table of Contents

and charge vs. voltage relations. Some extensions of the

model are worked on to add scaling [28].

Four of these candidate models found a CMC member

company which is willing to sponsor them in the second
phase and moved on: Angelov, ASM-HEMT, MVSG and
HSP.

B. Anwar model
As much of the physical material properties as possible
are employed to reduce the parameters needed to get a
good fit [21]. It uses a Volterra series technique, which
also should enable an excellent fit in the frequency
domain [29].

IV.SECOND PHASE AND BEYOND

We have entered the second phase of our
standardization process. In this phase, the model
developer and their CMC member sponsor are asked to fit
their model to two common sets of hardware data. The
model developer and their sponsor have to agree on a
partition of work. Two of our members have offered to
provide hardware data for this comparison. One set is
measured using RF devices, while the other set is
extracted from power switching devices.
There will be regular updates during this phase from the
different participants. The quality of the model is tested by
overlaying the measured data with the predicted values of
the extracted model. The goal is to finish this phase before
the middle of 2015, though this will depend on the
progress of the different candidates and the availability
and completeness of the hardware data. A vote will decide
at the end of this phase to decide which candidates are
ready to move to the third phase, after the final evaluation
reports have been presented by the candidates and their
sponsors.
In the third phase, the model code is made available to
all CMC members, so they can perform their own testing.
There is no established set of tests for this phase, but it
gives membership an opportunity to check if the model
candidate also fits to their own technology, or if the model
fulfills their needs in robustness and performance in
circuit simulation. At the end of this phase, there will be a
ballot asking members if a candidate model is ready for
standardization. Ideally, this will lead to a single standard
model which can be used for all applications.
Once a model is deemed ready for standardization, the
CMC funds the model developer to make their model
industry-ready and maintain the model. No amount of
evaluation can bring the same level of exercise to a model
as wide spread industrial use. The CMC commits itself to
supporting its standard models for a long time.

C. Tsinghua model
A surface-potential based approach is used to calculate
the currents and charges [22]. They are integrating the
model into an on-line modeling platform, so it is available
for testing. They are working on implementing a few of
the missing requirements, but should be ready in time if
selected to move to the next phase.
D. ASM-HEMT model
This model derives the surface-potential from the
charge to calculate the currents [23]. It is being supported
through a collaboration of several research groups across
the world. They seem to have included most if not all of
the required features in their model.
E. HSP model
This is a surface-potential based model, which has been
developed with power switching applications in mind
[24]. Their core model seems as advanced and physical as
any of the other models, but several of the requirements
are not yet developed.
F. MVSG model
This model uses a charge-based current modeling
approach to avoid the problems of threshold voltage based
models [25]. They seem to have included most, if not all
the effects on the requirements list.
G. Shur model
It also uses a charge-based current approach, and
includes reliability modeling [26]. They have studied all
of the effects on the requirements list, but it is unclear how
much of it is incorporated into the model.
H. NCSU HFET model

III. CONCLUSION

To calculate the currents and charges, the channel is

divided in several zones, and solved at the boundaries
between them. Some of the requirements still seem to be
needed to be included in the model, but it should be
feasible to do so.

The compact model coalition is busy evaluating

different GaN HEMT compact models to find a suitable
candidate for standardization. Several promising
candidates have been identified, and are now being fitted
to two common hardware data-sets Hopefully, this will

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[13] C. C. McAndrew, R3, an Accurate JFET and 3-Terminal

Diffused Resistor Model, Proc. Nanotech WCM, vol. 2,
pp. 86-89, 2004.
[14] "CMC Standard Netlist Language and Model File Format",
CMC documentation
[15] A Katz and M Franco, GaN Comes of Age, IEEE
Microwave Magazine, Dec 2010, pp S24-S34.
[16] I Angelov, H Zirath, N Rosman, "A new empirical
nonlinear model for HEMT and MESFET devices",
Microwave Theory and Techniques, IEEE Transactions on
40 (12), pp. 2258-2266, 1992
[17] L Dunleavy, C Baylis, W Curtice and R Connick,
Modeling GaN: Powerful but Challenging, IEEE
Microwave Magazine, Oct 2010, pp 82-96.
[18] J. Xu, R. Jones, S. A. Harris, T. Nielsen, and D. E. Root,
Dynamic FET Model DynaFET - for GaN Transistors
from NVNA Active Source Injection Measurements,
International Microwave Symposium Digest, Tampa, FL.
June, 2014
[19] C. C. McAndrew, "Validation of MOSFET model Source
Drain Symmetry", IEEE Transactions on Electron Devices,
Vol. 53, No. 9, pp. 2202-2206, September 2006
[20] I. Angelov, M. Thorsell, K. Andersson, A. Inoue, K.
Yamanaka, H. Noto ,"On the Large Signal Evaluation and
Modeling of GaN FET ,IEICE Transactions, pp. 12251233, July, 2010
[21] S.S. Islam, A.F.M. Anwar, R.T. Webster, "A Physics-based
Frequency Dispersion Model of GaN MESFETs", IEEE
Transactions on Electron Devices, Vol. 51, No. 6, pp. 846853, June 2004
[22] X. Cheng, Y. Wang, A Surface Potential Based Compact
Model for AlGaN/GaN MODFETs, IEEE Transactions on
Electron Devices, vol. 58, no. 2, pp. 448-454, Feb. 2011.
[23] S. Khandelwal, C. Yadav, S. Agnihotri, Y.S. Chauhan, A.
Curutchet, T. Zimmer, J.-C. Dejaeger, N. Defrance, T.A.
Fjeldly, "A robust surface-potential-based compact model
for GaN HEMT IC design", IEEE Trans. Electron Devices,
vol. 60, no. 10, pp. 3216-3222, 2013
[24] P. Martin, R. Hah, L. Lucci,"A Surface-Potential-Based
Compact Model of AlGaN/GaN HEMTs Power
Transistors", NSTI Nanotec Conference, vol. 2, pp. 544547, 2013
[25] U Radhakrishna, T Imada, T Palacios, D Antoniadis, "MIT
virtual source GaNFEThigh voltage (MVSGHV) model:
A physics based compact model for HVGaN HEMTs",
physica status solidi (c) 11 (34), pp. 848-852, 2014
[26] K. Lee, M. S. Shur, T. A. Fjeldly, T. Ytterdal,
"Semiconductor Device Modeling for VLSI", Prentice Hall,
1993
[27] H. Yin, G.L. Bilbro, R.J. Trew, Y. Liu, and W. Kuang, A
New Physics-Based RF Model for AlGaN/GaN HFETs,,
IEEE Wireless and Microwave Technology Conference,
Clearwater, FL, Dec. 4-5, 2006.
[28] T. Oishi, H. Otsuka, K. Yamanaka, Y. Hirano, I. Angelov
Semi-physical nonlinear model for HEMTs with simple
equations, INMMIC, Goteborg, 2010
[29] S.S. Islam, A.F.M. Anwar, "Nonlinear Analysis of GaN
MESFETs With Volterra Series Using Large-Signal Models
Including Trapping Effects", IEEE Transactions on
Microwave Theory and Techniques, Vol. 50, No. 11, pp.
2474-2479, November 2002

lead to an adoption of a standard model in 2015 or early

2016.
ACKNOWLEDGMENT
The author would like to acknowledge the GaN HEMT
standardization subcommittee of the CMC, and especially
its' two previous chairs, Pascale Francis (National
Semiconductor/Texas Instruments) and Rick Poore
(Agilent).
REFERENCES
[1] http://www.si2.org
[2] Y. Cheng, C. Hu, MOSFET Modeling and BSIM3 User
Guide, Kluwer Academic Publishers, 1999
[3] W. Liu. C. Hu,BSIM4 and MOSFET Modeling for IC
Simulation, World Scientific Publishing, Singapore, 2011.
[4] G. Gildenblat, X. Li, W.Wu, H. Wang, A. Jha, R. van
Langevelde, G.D.J. Smit, A.J. Scholten and D.B.M.
Klaassen, "PSP: An Advanced Surface-Potential-Based
MOSFET Model for Circuit Simulation", IEEE
Transactions on Electron Devices, Vol. 53, No. 9, , pp.
1979-1993, September 2006
[5] M. Miura-Mattausch, H.J. Mattausch and T. Ezaki, "The
Physics and Modeling of MOSFETS: Surface-potential
Model HiSIM", World Scientific, 2008
[6] P. Su, An International Standard Model for SOI Circuit
Design, Ph. D. Dissertation, Department of EECS,
University of California at Berkeley, December 2002.
[7] Miyake, M.; Kusu, S.; Kikuchihara, H.; Tanaka, A.;
Shintaku, Y.; Ueno, M.; Nakashima, J.; Feldmann, U.;
Mattausch, H.J.; Miura-Mattausch, M.; Yoshida, T. "The
flexible compact SOI-MOSFET model HiSIM-SOI valid
for any structural types", Simulation of Semiconductor
Processes and Devices (SISPAD), 2011 International
Conference on, pp. 167 170, 2011
[8] M. V. Dunga, C-H. Lin, A. Niknejad, C. Hu, BSIM-CMG:
A compact Model for Multi-gate Transistors, Chapter 3 in
FinFETs and Other Multi-Gate Transistors, J. P. Colinge,
Ed., Springer, pp.113-153, 2007.
[9] R. van der Toorn, J.C.J. Paasschens, W.J. Kloosterman and
H.C. de Graaff, "Mextram", Chapter 7 of: Compact
Modeling, Principles, Techniques and Applications,
Gildenblat, Gennady (ed.), Springer, New-York, pp. 199227, 2010.
[10] M. Schroter and A. Chakravorty,"Compact Hierarchical
Bipolar Transistor Modeling With HiCUM",", World
Scientific, 2010
[11] Y. Oritsuki, M. Yokomichi, T. Sadachika, M. Miyake, T.
Kajiwara, H. Kikuchihara, T. Yoshida, U. Feldmann, H. J.
Mattausch,
and
M.
Miura-Mattausch,
HiSIMLDMOS/HV: A complete surfacepotential-based MOSFET
model for high voltage applications, Proc. NSTI-Nanotech,
pp. 893896, Boston, June, 2008.
[12] "r2_cmc: Two-Terminal Nonlinear Resistor Model",CMC
documentation

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Table of Contents

Symmetrical Modeling of GaN HEMTs

Ankur Prasad*, Christian Fager*, Mattias Thorsell*, Christer M. Andersson, and Klas Yhland
*Department of Microtechnology and Nanoscience, Chalmers University of Technology, Gteborg
Sweden SE-41296, Email: ankur@chalmers.se

Information Technology Research and Development Center, Mitsubishi Electric Corporation,

Kamakura, Japan 247-8501

SP Technical Research Institute of Sweden, Box 857, Bors, Sweden SE-50115

GigaHertz Centre, Chalmers University of Technology, Gteborg, Sweden SE-41296

Abstract This paper presents a symmetrical small
signal model for GaN HEMTs valid for both positive and
. The model takes advantage of the intrinsic
negative
symmetry of the devices typically used for switches. The
parameters of the model are extracted using a new
symmetrical optimization based extraction method,
optimizing simultaneously for both positive and negative
drain-source bias points. This ensures a symmetrical small
signal model with lower modeling error. The small signal
model can be further used to simplify the development of a
large-signal model. The small signal model is validated with
measured S-parameters of a commercial GaN HEMT.
Index Terms Gallium Nitride, HEMTs, modeling,
parameters extraction, semiconductor device modeling.

Source
Gate
Drai n
Line of Symmetry
Semi-insulating Substrat e

Fig. 1. Cross-section of a symmetrical GaN HEMT typically

used for switches and mixers.

symmetry to a corresponding symmetry of a small signal

circuit.
A new symmetrical intrinsic model is introduced in [6]
where extracted parameters for a commercial GaAs FET
show symmetry. In this paper, the symmetrical model has
been extended to GaN HEMTs where, the intrinsic model
parameters in the negative
region are obtained by
region. Contrary to
mirroring those from the positive
the mirroring of direct extraction results in [6], the small
signal extraction result is further improved by
optimization. A new symmetrical error function is used
for the optimizer based extraction method based on [7]
where the direct extraction result corresponding to the
positive
bias points is fed as the seed value. Both the
regions are simultaneously
positive and negative
optimized with the mirrored model to ensure the intrinsic
symmetry. It is shown that such an optimization process
improves the small signal model extraction which can
further be used to simplify large signal modeling due to
symmetry between intrinsic drain and source terminals. In
this paper, a symmetrical small signal model is extracted
for a commercial GaN HEMT from measurements, and
the reduction in modeling error is shown between
optimizer based extraction and direct extraction in the
complete bias region.

I. INTRODUCTION
Gallium-Nitride
(GaN)
high
electron-mobility
transistors (HEMTs) are an excellent choice for
application areas where high power, wide bandwidth, high
efficiency, and high linearity are required. Some of the
widely used areas for such a technology are power
amplifiers (PAs) and transceivers. With a wide range of
circuits under consideration, modeling of GaN HEMTs
becomes an important research area.
GaN transistors used in amplifiers and many other
circuits have gate field plates and larger gate-drain
separation compared to gate-source. In these circuits,
transistors operate mainly in the positive drain-source
( ) bias region. Therefore, most of the modeling work
targets such a bias region. However, in circuits like
resistive mixers, switches, etc., the transistors are often
symmetrical with equal gate-drain and gate-source
separation. These transistors operate in both positive and
negative
regions. This disqualifies many existing FET
models e.g., [1]-[3]. Some models which considers
operation in the negative
region are found in literature
e.g. [4], [5]. However, the models in [4], [5] only consider
the symmetry in current and fail to incorporate the
symmetry present in the charge modeling. Furthermore,
none of the models in [4], [5] propagate the large signal

978-1-4799-3622-9/14/$31.00 2014 IEEE

II. BUILDING A SYMMETRICAL MODEL

The traditional FET model in [8] and similar models are
widely used as an equivalent circuit for small signal
operation. However, for a switch device with equal gatesource and gate-drain separation (see Fig. 1), one can
expect to see the symmetry between intrinsic drain and
source ports in the model. The traditional small signal
model fails to incorporate the symmetry around the gate.

157

Table of Contents

Gext

Rg

Rj
Vgdi

_
_
ic =jCm Vgdi

+
(Cpg)/2

Vgsi
Ri

Ld

Rd
_
gm

(Cpd)/2

+Vgsi
ic+=jCm

Cgs

_
Cm

C+
m

gm+

Lg

Dext

_ _
ids=gm Vgdi

Cgd

Rs

+ =g+V
ids
m gsi

Ls

Fig. 2. The complete small signal model with symmetrical intrinsic circuit. The model contains extrinsics in -configuration. For
simplification, the control voltages are taken across the capacitance and series resistance for the two transconductances.

,
,
(2a)
gd
,
,
(2b)
,
,
(2c)
,
,
.
(2d)
i
j
If in Fig. 2 the extrinsic resistances
and
are
,
) and (
,
) can be replaced by
similar, then (
( ,
) and ( , ) respectively in (2). This equivalent
small signal model is used for model extraction and
verification in the next section.
gs

TABLE I: Extrinsic parameters from multibias optimizer

based extraction.
45 fF

1.2

0.9

1.1

50.4 fF

70 pH

22 pH

54.7 pH

Therefore, the traditional intrinsic model is modified to

create a symmetrical equivalent circuit in [6].
Building a symmetrical model for the device shown in
Fig. 1 is briefly explained from [6, Sec. II-B]. For such a
device, its physical symmetry should give an electrical
symmetry of the intrinsic drain and source ports in the
small signal model. Furthermore, the negative
operation for this model is equivalent to positive
operation with drain and source ports interchanged.
Therefore, two independent current sources

and

are used to model the three port

device, thus replacing the traditional parameters
and
(see Fig. 2) [6]. For simplification in the direct
is voltage taken across
extraction, the control voltage
and (and similarly for
). It is important to note
that while
is the derivative in constant
direction,
and
are derivatives in constant
and
directions respectively. Similarly, two transcapacitances
and
replace
and
of the traditional model.
These modifications make the small-signal model
symmetrical. The common-source intrinsic Y-parameters
for the proposed model are then given by
(1a)
11
(1b)
12
(1c)
21
(1d)
22
1
(1e)
gs

1
.
(1f)
gd
The intrinsic small signal equivalent circuit shown in
Fig. 2 is symmetrical, therefore the following symmetry
conditions are met:

III. EXTRACTION OF NEW MODEL PARAMETERS

The complete symmetrical model consists of eight
extrinsic and eight intrinsic parameters. These parameters
are extracted from S-parameter measurements from 500
MHz to 40 GHz on a commercial GaN HEMT (UMS
GH25-10 V9C). The measurement bias points are chosen
to be on a square grid in the extrinsic
plane.
A cold FET extraction technique [8] is used to obtain
the extrinsic parameter values. These extrinsic parameters
are de-embedded from the measured data to obtain the
intrinsic admittance matrix. The intrinsic model
parameters (see Fig. 2) are then found using the intrinsic
admittance matrix given by (1) [9]. To further reduce the
modeling error, optimizer based extraction method is used
with direct extraction results from the positive
region
as seed value.
The extrinsic parameters are first optimized used the
multibias optimization method in [10] for a few bias
points in the positive
region. The error used for
optimization is defined as

. (3)
The extrinsic parameters value for the minimum error
are shown in Table I.
For extraction of the intrinsic model parameters, it is
beneficial to take into account the symmetry of the
intrinsic equivalent circuit shown in Fig. 2. Therefore, the
model parameters are simultaneously optimized in both
the positive and negative
plane in accordance with (2).

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Table of Contents

(fF)
700

400

-10

(mS)

-5

-5

-15
-15

Vds < 0 V
-10

-5

100
B

-10

-5

200

-10

4
3
B

-10

100

200
0

6 ()

300

300
C

400

200
Vgs (V)

Vgs (V)

500

600
-5 V > 0 V
ds

D (fF)
300

Vgs (V)

Vgs (V)

-15
-15

-10

-5

Vgd (V)

Vgd (V)

(a)

(b)

-15
-15

-100

-10

-5

-15
-15

-10

-5

Vgd (V)

Vgd (V)

(c)

(d)

Fig. 3. Bias dependence of symmetrical small signal model intrinsic parameters of the DUT obtained using optimizer based
bias grid covering both positive and negative
region: (a)
(fF), (b)
(fF), (c)
(mS), (d)
extraction in an extrinsic
. Other intrinsic parameters are mirrored according to (2).

The optimization of the intrinsic parameters is performed

in the following steps:
1. The optimizer is iterated through the constant
plane, where the starting
bias points in positive
value of the model parameters are chosen from the
direct extraction results corresponding to the lowest
bias point.
2. At any bias point (A:
V,
V) in the
positive
region, the modeling error is computed
as follows:
a. At A, the error
is computed using (3).
b. For bias point A, a corresponding bias point in
region is found (B:
the negative
V,
V).
c. The model parameters at bias point B is obtained
by mirroring the intrinsic model parameters given
by (2).
d. At bias point B, the error
is computed from
the mirrored model and the measurements at bias
point B using (3).
e. The total modeling error for intrinsic optimizer
is calculated as the average of the modeling error
bias points
in the positive and negative
respectively.
and
3. The modeling error is minimized to achieve good
match between the measured and the modeled Sparameters.
4. For the next
bias in the constant
line, the
model parameters optimized from the previous bias
point are used as seed values and steps 2 and 3 are
repeated.
Four of the eight intrinsic parameters from optimizer
based extraction are shown in Fig. 3 in the extrinsic
bias grid. The four remaining intrinsic
parameters are mirrored using (2). The modeling error in
the direct extraction and the optimization based extraction
are compared in Fig. 4. In Fig. 4b, the proposed extraction
has generated higher error at
3.25 V and
3.25 V, which is along the constant
0V

line. This error is arising near pinch-off where the

transistor start conducting and the model parameters like
,
,
,
,
and
show a steep gradient in
extraction as seen in Fig. 3. The optimizer based
extraction is unable to model this steep gradient change in
the parameters values, hence the rise in error is observed.
Similar rise in error is observed at
0 V,
4V
and vice-versa. These errors can be minimized either by
using a dense measurement grid around these points or by
using the values from the corresponding direct extraction
bias points as seed points or the average of direct
extraction results from positive and negative
plane.
However, the overall improvement in modeling error is
clearly seen in the comparison, both for the positive and
region. This improvement would result to a
negative
better large signal model with a single charge function
similar to [6]. The improvement in error thereby verifies
the symmetrical assumption of the intrinsic model.
X 10-3
20

0
A

X 10-3
20

0
A

18

18
16

16
14

Vgs (V)

12
10
B

-10

14

-5

12

Vgs (V)

-5

10
B

-10

2
-15
-15

-10

-5
Vgd (V)

-15
-15

-10

-5

Vgd (V)

(a)
(b)
Fig. 4. Comparison of modeling error between (a) direct
extraction, and (b) modified optimizer-based extraction.

IV. VALIDATION OF THE MODEL

To validate the symmetrical model in the complete
region under consideration, four bias points A - D are
selected (see Fig. 3).
1. A:
2.5 V,
9 V (positive
).
2. B:
9 V,
2.5 V (negative
).
3. C:
13 V,
13 V (deep pinch-off).
4. D:
0 V,
0 V (open channel).

159

Table of Contents

The S-parameter comparison is shown in Fig. 5. In Fig.

at bias point B is greater than 1 as the gate terminal
5a,
bias.
is observing negative resistance in the negative
However, the overall good agreement between the
modeled and measured behavior confirms the accuracy of
the symmetrical model.

REFERENCES
[1] I. Angelov, K Andersson, D. Schreurs, D. Xiao, N.
Rorsman, V. Desmaris, M. Sudow, and H. Zirath, Largesignal modelling and comparison of AlGan/GaN HEMTs
and SiC MESFETs, in Proc. Asia-Pacific Microw. Conf.,
pp. 279-282, Dec 2006.
[2] G. Torregrosa, J. Grajal, M. Peroni, A. Serino, A. Nanni,
and A. Cetronio, Large-signal modeling of power GaN
HEMTs including thermal effects, in European Microwave
Integrated Circuit Conference, pp. 36-39, Oct 2007.
[3] A. Jarndal, Genetic algorithm-based neural-network
modeling approach applied to AlGaN/GaN devices,
International Journal of RF and Microwave ComputerAided Engineering, vol. 23, no. 2, pp. 149-156, 2013.
[4] I. Angelov, V. Desmaris, K. Dynefors, P.-A. Nilsson, N.
Rorsman, and H. Zirath, On the large-signal modelling of
th
AlGaN/GaN HEMTs and SiC MESFETs, in Proc. 13
GAAS Symp., pp. 309-312, 2005.
[5] G. Callet, J. Faraj, O. Jardel, C. Charbonniaud, J.-C.
Jacquet, T. Reveyrand, E. Morvan, S. Piotrowicz, J.-P.
Teyssier, and R. Qur, A new nonlinear HEMT model for
AlGaN/GaN switch applications, Int. J. Microw. Wireless
Technol. (Special Issue), vol. 2, no. 3-4, pp. 283-291, Jul.
2010.
[6] A. Prasad, C. Fager, M. Thorsell, C. M. Andersson, and K.
Yhland, Symmetrical Large-Signal Modeling of
Microwave Switch FETs, IEEE Trans. Microw. Theory
Techn., accepted for publication.
[7] C. van Niekerk, P. Meyer, D. M. M. P. Schreurs, and P.
Winson, A robust integrated multibias parameterextraction method for MESFET and HEMT models, IEEE
Trans. Microw. Theory Techn., vol. 48, no. 5, pp. 777-786,
May 2000.
[8] G. Dambrine, A. Cappy, F. Heliodore, and E. Playez, A
new method for determining the FET small-signal
equivalent circuit, IEEE Trans. Microw. Theory Techn.,
vol. 36, no. 7, pp. 1151-1159, 1988.
[9] N. Rorsman, M. Garcia, C. Karlsson, and H. Zirath,
Accurate small-signal modeling of HFETs for millimeterwave applications, IEEE Trans. Microw. Theory Techn.,
vol. 44, no. 3, pp. 432-437, 1996.
[10] C. van Niekerk and P. Meyer, A new approach for the
extraction of an FET equivalent circuit from measured S
parameters, Microwave and Optical Technology Letters,
vol. 11, no. 5, pp. 281-284, 1996.

V. CONCLUSION
In this paper, a small signal model is proposed for
symmetrical GaN switch HEMTs using a new optimizer
based extraction. This extraction method is advantageous
because it ensures symmetrical modeling and further
producing better results than direct extraction in both the
positive and negative
bias. This method shows rise in
modeling error at a few bias points which can be observed
in the gradients of intrinsic parameters at those bias points.
Hence, this extraction method can be further improved by
using a dense measurement grid or changing the seed
value for optimization. The seed value can be defined as
the direct extraction results of the positive
bias point
bias points.
or the average of the positive and negative
Furthermore, this model can also be extended into a
symmetrical large signal model of GaN HEMTs similar to
[6]. Therefore the symmetry around the gate can be used
to simplify the modeling of reactive part of the device.
This would lead to a simpler model with fewer number of
parameters for symmetrical GaN switch HEMTs.
ACKNOWLEDGMENT
This research has been carried out in the GigaHertz
Centre. This work was supported by the Swedish
Governmental
Agency
of
Innovation
Systems
(VINNOVA), Chalmers University of Technology, SP
Technical Research Institute of Sweden, ComHeat
Microwave AB, Ericsson AB, Infineon Technologies AG,
Mitsubishi Electric Corporation, NXP Semiconductors
BV, Saab AB and United Monolithic Semiconductors.

30
S12 A
11

A(S )
11

D(S22)

S21 A

S21 B

S21 C

S21 D

10

B(S22)

C(S11 )

S12 B

20
S 12, S21 (dB)

D(S )

A(S22 )

B(S )

0
-10
-20
-30

11

C(S22)

-40
0

10

15

20

25

30

35

40

Frequency (GHz)

(a)
(b)
, (b)
, (c)
and
Fig. 5. Comparison of S-parameters (a)
500 MHz to 40 GHz for bias points A to D used for validation.

(c)
, of the symmetrical model (-) with measurements (marker) from

160

Table of Contents

First pass multi cell modeling strategy for GaN package devices
Subrata Halder, John McMacken, Joseph Gering

IN

T1

T2

T5

Output flange multiport

Abstract A generic modeling topology is proposed for

high power packaged GaN HFET devices leading to first pass
design/modeling success. In addition to the EM environment
of the package parasitics, the model considers thermal cross
coupling and electrode cross coupling effects at the multi-cell
device array to arrive at sufficiently accurate model. The
model derived by studying a 5-cell GaN part is played back
against 1, 3 and 7 cell packaged devices from different types
of GaN process to show model agreements at 0.9, 2.14, and
3.5 GHz demonstrating acceptable first pass design success.
Index Terms Power transistors, GAN HEMTs,
semiconductor device modeling, semiconductor device
packaging, powerbars.

Input flange multiport

RFMD Greensboro, NC USA Subrata.halder@rfmd.com

OUT

I. INTRODUCTION
Designing or modeling multi-cell GaN package
devices requires careful attention to all the details of the
package itself, some of which have been studied well
recently [1] leading to some high power PA designs[2][3].
One popular approach is having EM simulation by parts,
i.e. I/O flanges, on die metal manifolds, and bond-wires
and cascade them together to form the passive
environment. While cascading of elements may be
adequate, some critical details may still be left out such as
thermal cross coupling among the unit cell and parasitic
coupling effect. This may leave a wide gap between
measured and simulated results and may often call for
further design iteration increasing design cycle and
underlying cost. In this presentation, a modeling approach
will be described based on an unmatched 5-cell GaN-A
packaged part where the array of unit cells inside the
package is formed by including the electrical and thermal
cross coupling networks which helps to align measured to
simulated results closer over wide frequency range up to
3.5GHz. The lessons learned are then ported to 1, 3, 5 and
7 cell unmatched GaN-B process based parts to validate
their large signal behavior at 2.14GHz to demonstrate
acceptable first pass design success.

Fig.1 Top level schematic of a 5-cell GaN packaged

transistor
effects. The former problem can be solved by adopting a
suitable EM simulation technique like Momentum or FEM
for the package including the I/O flanges and package lids
and cascading them with the bond-wire models found in
the simulators or by using another 3D EM simulation for
the bond-wires at the expense of increased simulation
complexity. For this work, a 5-cell GaN packaged device
is studied by combining a package model and the unit cell
model of an AlGaN/GaN HFET device grown on a SiC
substrate using the GaN-A process. The unit cell consists
of 6 fingers, each with 370um gate width and 0.5um gate
length. The die is attached to the package through Au-Sn
alloy to the Cu-Mo carrier. The gate and drain package
leads are separated from the bottom plate by an alumina
substrate. The I/O flanges are simulated using momentum,
and gate, drain and source bond-wires are simulated using
the Philips bond-wire model in ADS and cascading them
to form the entire package, as in Fig.1. A few advantages
of this method are 1) easy portability across designs, 2)
tune-ability, and 3) scalability. The packaged model, thus
constructed, is calibrated against measured open/short S11
and S22 parameters of a known geometry. The bond-wire
length and shapes are adjusted to align the S11 and S22
parameters[3]. As the width of the input/output flanges are
fairly large, significant phase difference may exist
between inner and outer points where bond-wires are
connected[4], so the flange has been simulated as multiports rather than a two port component.

II. PACKAGE MODELING

Modeling of a packaged device can be divided into two
parts, one devoted to the passive package structures
including the bond-wires and flanges on the substrates and
the other the GaN device array itself which include the
unit cell model and thermal and electrical cross-coupling

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Rth1

Cxds

2.14GHz

S2 Cxds

Cth

D2
Rth2

Cxgd

Cxgd

0.9GHz

Cth

Cth_HS

Rth_HS

Rth_FL

Cth

D5

3.5GHz

Cth

Cxds

Cxds
Rth2

D4

Rth1

S5

Rth3

S4

Cxds

Cxds

Cxgd

Cxgd
Cxgd

G4

S3

Cxgd

D3

G3

G5

Cxds

Cxds

Cxgd

Cxgd
G2

S1

Cth

D1

G1

Fig.2 Die level schematic of a 5-cell GaN FET array

with parasitic coupling between unit cells.

Fig.3 Measured (blue) and modeled (red) gain loadpull contours of a 5-cell packaged transistor at
Vdq=48V, Idq=220mA and at three frequencies

III. MULTI-CELL ARRAY MODELING

empirical fit is found to be better choice. It is also noted

that the coupling capacitor is not very significant against
the large intrinsic gate-source capacitances and can be
neglected; however the gate-drain and the drain-source
capacitances may compete well with their intrinsic
counterparts. It is noted that although there are about 16
capacitances of these types in Fig.2, knowing only two
values for Cxgd and Cxds is sufficient.

The unit cell GaN devices are normally connected to

their corresponding gate, drain and source bond-wire ports
in the package model to complete the schematic. This
leaves out two important aspects at device level modeling,
1) thermal coupling and 2) electrical coupling between the
unit cells, which are the central themes of this paper.
Looking at the temperature gradient from IR scan data, an
approximated idea of the thermal resistances variations
may be determined. It was found that a 15-20% linear
taper between adjacent cells was sufficient. For more
accurate simulation, a thermal simulator may be coupled
to the electrical simulator[6][7]. The tapered thermal
network, as shown in Fig. 2, is formed by bringing out the
thermal node external to the model and weighting the
intrinsic thermal resistance by a suitable factor
symmetrically around the center . Finally, the network is
completed by connecting the Rth||Cth combinations for
the flange and the heat sink.
The electrical coupling between unit cells arise from the
proximity of gate, drain and source electrodes and can be
modeled as additional capacitors between these terminals
as shown in Fig 2. Again, adjacent device coupling has
been considered here as the other cells are too far away to
have influence on a particular unit cell. The exact value of
these capacitors cannot be ascertained easily, as they
range in 20-50fF. EM simulation may be difficult for a
fine array of metal lines in the devices area, so an

IV. RESULTS AND DISCUSSION

In order to evaluate the modeling scheme above, a 5cell GaN packaged device is mounted on an aluminum
heat sink with a transition to APC-7 coaxial connectors.
The transitions consist of a tapered micro-strip PCB
transmission lines transitioning to lower impedances from
50 Ohm to 12.5 Ohm. A TRL calibration procedure is
followed to establish the reference plane at the gate and
drain flanges. Pulsed load-pull measurements at 0.9, 2.1
and 3.5GHz are performed at a quiescent drain bias of
48Volts and 20mA/mm in 50us pulses with a 10% duty
cycle to avoid thermal and dispersion effects. As shown in
Fig.3, the measured and simulated load contours of gain at
saturated power coincide well. Also, the gain and drain
efficiency versus output power match well at three
frequencies, as seen in Fig.4. This validated the modeling
approach. The significance of capacitive coupling, as
shown in Fig.5, can be seen to improve the high frequency

162

Outp
put power (dBm)

3.5GHz
Output powerr (dBm)

Output power (dBm)

(a)
2.14
4GHz

Outp
put power (dBm)

Outp
put power (dBm)

DE (%)

Gain (dB)

2.1GHz

DE (%)

Gain (dB)

Outp
put power (dBm)

Gain (dB)

0.9G
GHz

Gain (dB)

DE (%)

Gain (dB)

Table of Contents

3.5G
GHz

Outtput power (dBm)

(b)
Fig.55 Measured (soolid blue) and m
modeled (red) ggain
(a)sw
weeps and (b)looad contours att 3.5GHz of 5--cell
learnning transistor aat Vdq=48V, IIdq=220mA wiithout
(solidd red) and withh (dashed blue)) coupling capaacitors
Cxgdd and Cxds.

Outp
put power (dBm)

Fig.4 Meassured (symbolss) and modeled

d (lines) gain
and drain efficiency(DE)
e
of 5-cell learn
ning transistor
at Vdq=48V
V, Idq=220mA
A and at three frequencies.
f

bondwiire model annd an array oof unit cell iis found

adequaate to describe parts behavioor provided thee electrothermall coupling efffects are accouunted for by w
weighting
thermall resistors andd using coupliing capacitors between
unit ceells. The firstt pass successs of such a m
modeling
strategyy is demonstrrated by deveeloping a 5-ccell GaN
packagge model on a process and transferring thhe model
topologgy to other 1 through 7 celll structures inn another
processs technology.

gain and the load-pull

l
conto
ours. A value of
o 22fF for Cx
xgd
and 45fF fo
or Cxds wass found adeq
quate for enttire
simulations in
n this paper.
Next the model schem
matic is tran
nslated to oth
her
ke 1, 3, 5, and 7 cell packaged transistors on
structures lik
the same pacckage styles and
a bond wiree dimensions. In
addition, the GaN die with identical unit cell geometry of
om GaN-B, another proceess
6x370um waas picked fro
technology, to evaluate versatility off the modeliing
nly the model parameters
p
relaated to number of
approach. On
bond-wires an
nd the multiport I/O flange s--parameters weere
adjusted acco
ording to the number
n
of uniit cell. The loaadpull data measured on eacch of these cellls showed clo
ose
w
the first--pass simulatiion
agreement on all cases with
king any modeel parameters, as seen in Fig
g.6.
without tweak
This facilitatees a smooth an
nd systematic modeling/desiign
flow across various
v
designs.

AC
CKNOWLEDGM
MENT
The aauthors acknow
wledge Carl Hiinshaw and Tim
m Howle
for fabrrication and meeasurement suppport.
REFERENCESS
[1] Fluucke, J.; Schmuuckle, F.-J.; Heiinrich, W.; Ruddolph, M."
Ann accurate pacckage model for 60W GaN
N power
trannsistors" Europ
opean Microwaave Integrated Circuits
Coonference Proc., pp.152-155, 20009.
[2] K. Yamanaka, M. Kimura, S. Chaaki, M. Nakayam
ma, and Y.
GaN with
Hirrano S-band Innternally Harmonic Matched G
3300W Output Power and 62% PAE Proc. of the 6th
Eu ropean Microw
wave Integrated Circuits Conferrence, pp2444-247, 2011.
[3] Jerrome Cheron, M
Michel Campovvecchio, Denis Barataud,
Tibbault Reveyrandd, Michel Stanislawiak,Philippe Eudeline,
Diddier Floriot, W
Wideband 50W
W Packaged GaN
N HEMT

V. CON
NCLUSION
The non-ttrivial task of modeling//designing larrge
periphery GaaN packaged trransistors can be simplified by
adopting a uniform
u
modeling approach. Combining EM
E
simulated mu
ultiport I/O flan
nge, EM simulated on-die draain
/ source / gate
g
access metallization
m
with
w
a standaard

163

1-Cell

HB.PAEdat[nFr,nLd,::]
DE (%)
HB.OEsim[nFr,nLd,::]

18

Gain (dB)

17
16
15

3-Cell

13
12
11
20

25

30

35

40

45

50

5-Cell

Output power (dBm)

DE (%)

Gain (dB)

HB.P1sim_dBm[nFr,nLd,::]
Output
power (dBm)
HB.P1dat_dBm[nFr,nLd,::]

Output power (dBm)

7-Cell

Output power (dBm)

Output power (dBm)

DE (%)

Gain (dB)

[4] Subrata Halder, Faramarz Kharabi, Tim Howle, John

McMacken, Christopher Burns, Michael LeFevre,Dave
Runton and Joe Gering, Broadband lumped package
modeling for scaling multi-cell GaN HEMT power devices
Microwave Measurement Conference (ARFTG), 2012,
10.1109/ARFTG79.2012.6291193
[5] Subrata Halder, John McMacken, Dave Runton, Bondwire engineering to improve power performance in multicell GaN package devices 2013 IEEE MTT-S International
Microwave Symposium Digest, 978-1-4673-21419/13/$31.00
[6] Frank Schnieder, Olof Bengtsson, Franz-Josef Schmckle,
Matthias Rudolph, and Wolfgang Heinrich, Simulation of
RF Power Distribution in a Packaged GaN Power Transistor
Using an Electro-Thermal Large-Signal Description IEEE
Transactions on Microwave Theory and Techniques, Vol.
61, No. 7, pp.2603 2609, 2013.
[7] A. Xiong, E. Gatard, C. Charbonniaud, M. Faqir, M.
Kuball, M. Buchta, S. Rochette, L. Favede, Z. Ouarch, D.
Floriot A Distributed Electro-thermal Model of
AlGaN/GaN HEMT Power-Bar derived from the
Elementary Cell Model" European Microwave Integrated
Circuits Conference (EuMIC), pp. 64-67,2012

Output power (dBm)

Output power (dBm)

14

With Over 60% PAE Through Internal Harmonic Control in

S-Band 2012 IEEE MTT-S International Microwave
Symposium Digest , 10.1109/MWSYM.2012.6259389

DE (%)

Gain (dB)

Table of Contents

Output power (dBm)

Fig.6 Measured (blue) and modeled(red) gain and

drain efficiency(DE) of 1,3,5and 7-cell packaged
transistor at Vdq=48V, Idq=20mA/mm at 2.1GHz at
their optimum source/load impedances.

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Table of Contents

Model Development for Monolithically-Integrated E/D-mode

Millimeter-Wave InAlN/AlN/GaN HEMTs
Jun Ren1, Bo Song1, Huili Grace Xing1, Shuoqi Chen2, Andrew Ketterson2, Edward Beam2, Tso-Min Chou2,
2
2
3
2
1*
Manyam Pilla , Hua-Quen Tserng , Xiang Gao , Paul Saunier , and Patrick Fay
1

University of Notre Dame, Notre Dame, Indiana, 46556, USA; TriQuint Semiconductor, Richardson, TX; IQE
RF, Somerset, NJ; *pfay@nd.edu

Abstract Device models to support circuit design efforts

using monolithically-integrated enhancement- and depletionmode high-speed InAlN/AlN/GaN HEMTs are reported.
Physically-motivated modifications to the conventional
empirical compact models have been included to enhance
model accuracy over bias and temperature. The models have
been extracted from DC through 110 GHz at baseplate
temperatures from 25 C through 100 C; good agreement is
obtained between measurement results and the extracted
model.
Index Terms Gallium nitride, HEMTs, semiconductor
device modeling

II. DEVICE TECHNOLOGY

I. INTRODUCTION
Due to the unique material properties of GaN and
related materials, transistors in this material system are
widely appreciated for their performance in high-power
RF applications. More recently, however, demonstrations
of millimeter-wave frequency performance obtained
through aggressive device scaling have also indicated that
III-N based devices may offer advantages in the
millimeter-wave arena as well (see e.g., [1, 2]). To
translate these promising recent advances in device
performance into circuit level performance improvements,
models suitable for circuit design in these technologies are
needed.
In this work, we report the results of recent efforts to
develop
accurate
millimeter-wave
models
for
aggressively-scaled,
self-aligned,
monolithicallyintegrated
enhancementand
depletion-mode
InAlN/AlN/GaN HEMTs [2]. The models are based on
the empirical models reported previously by Angelov et al.
[3-6] and implemented in commercially-available design
software,
but
incorporate
physically-motivated
modifications in order to more accurately capture the biasand temperature-dependencies observed in our devices,
particularly of the gate characteristics. Good agreement
between the measured device characteristics and the
model are obtained for DC I-V characteristics as well as
on-wafer s-parameters from 100 MHz 110 GHz.

978-1-4799-3622-9/14/$31.00 2014 IEEE

165

The devices used for this modeling effort were

fabricated on 4 SiC substrates at TriQuint. The epitaxial
wafer structure included a lattice-matched ~8 nm InAlN
thick barrier and 1 nm AlN interlayer on the GaN channel.
T-shaped Pt/Au Schottky gates with lengths of
approximately 30 nm were fabricated using a dielectricassisted electron-beam lithography process, and a selfaligned process was used in conjunction with etching and
regrowth of n+ GaN by molecular beam epitaxy to form a
source-drain spacing of ~140 nm. To create enhancementand depletion-mode devices on the same epitaxial
structure, selective dry gate recess etching was performed
on the enhancement-mode devices, placing the gate at the
surface of the AlN interlayer, while for depletion-mode
devices the gate is deposited on the as-grown surface. The
devices employ a thin passivation layer (to minimize
parasitic capacitance) and were completed with a
simplified version of TriQuints 3MI (three metal
interconnect) back-end interconnect process. This device
technology has resulted in measured ft and fmax exceeding
300 GHz for both E- and D-mode devices; additional
details on the device structure, processing, and
performance have been previously reported in [2].
III. DEVICE MEASUREMENTS
The models were developed using DC current-voltage
and on-wafer s-parameter measurements obtained over
bias and temperature. Measurements were performed at
room temperature as well as three elevated baseplate
temperatures (55 C, 85 C, and 100 C) on devices with
50 m total gate width (2 gate fingers). For the sparameter measurements, the network analyzer was
calibrated using off-wafer standards and an LRRM
calibration, followed by de-embedding of the device from
the pad parasitics by using the measured s-parameters of
on-wafer open- and short-circuit de-embedding structures.

Table of Contents

IV. DEVICE MODELING

source and gate-to-drain currrents and voltages,

respectively, A is the effective Ricchardson constant, is
the effective Schottky barrier heigh
ht, and It and Eo are the
saturation current and effectiv
ve activation energy
associated with the non-thermionic current component.
Figure 2(a) shows the improved fit obtained at room
v gate and drain bias
temperature for the gate current vs.
that is obtained. In addition, thee explicit temperature
dependence allows for good fits to the measured data over
ng additional model
temperature without introducin
parameters, as shown in Figure 2(b--d).
This approach also results in im
mproved fits for the DC
drain current and s-parameters as well.
w
Figure 3(a) shows
typical measured and modeeled common-source
characteristic using our model at 25
5 C and 100 C; as can
be seen, good agreement between the measurement and
model is obtained.
Figuree 3(b) shows DC
transconductance at 25 C and 10
00 C, also indicating

To extract the device model parameters, the commonsource transfer characteristics, gate diode characteristics,
and common-source family of curvess were used in
conjunction with on-wafer s-parameterss from pinchoff,
triode/ohmic, and saturation modes. While reasonable fits
could be obtained over a limited bias range using the
conventional model formulations, it waas found that in
particular the enhancement-mode deevices exhibited
significant deviations that could not bbe overcome by
parameter adjustment. The gate recess process used to
shift the threshold voltage from depletion- to
enhancement-mode also introduces an interfacial oxide
layer (which has also been observed byy cross-sectional
TEM) that significantly impacts the gatee modulation and
in particular the gate current-voltage chaaracteristics. As
an example, Fig. 1 shows the measured aand modeled gate
current at room temperature for gate biasses from 0 to 0.8
V at drain-to-source bias voltages of 1.55 V to 3 V for a
typical enhancement-mode device. As ccan be seen, the
conventional model does not fully captuure the behavior
observed experimentally.
To address this limitation, a physics-innspired approach
was used to enable incorporation of temperature
dependence in a straightforward way. Too model the gate
characteristics, a two-diode model w
was used; one
connected between intrinsic gate and sourrce, and the other
between intrinsic gate and drain to account for the
significant drain-source bias expectedd in operation.
Identical current-voltage expressions aree used for each
diode, but with distinct parameters to aallow for device
asymmetry. To account for mechanismss other than just
conventional thermionic emission, the expression was
augmented with an additional term to capture trap-assisted
tunneling, etc:
,

Fig. 2. Improved fitting of gate I-V characteristics

c
for a
typical E-mode device at (a) room temp
perature; (b) 55 C; (c)
85 C and (d) 100 C using model repo
orted here.

In this expression, Igs,d and Vgs,d are the intrinsic gate-to-

Fig. 3. Comparison of measured and

d modeled enhancementmode HEMT (a) DC common-source trransfer I-V characteristics
and (b) DC transconductance at room temperature (left) and
100 C (right). Good match is demonsstrated over the full bias
range.

Fig. 1. Comparison of measured and modeeled gate current

characteristics with conventional model. Signnificant
deviations are apparent.

166

Table of Contents

good measurement to model agreementt. Measured sparameters at 25 C and 100 C are also shown in Fig. 4
for several selected bias points, indicatingg good agreement
between the measurement and the modeel, including the
positive gate bias conditions.
Similar results have been obtained forr depletion-mode
devices, as shown by the common-ssource DC I-V
characteristics and s-parameters shown in Fig. 5 and Fig. 6.
It should be noted that despite the verry different gate
aspect ratio for the enhancement- and depletion-mode
devices due to the gate-recess process useed (aspect ratio ~
10 for the enhancement mode devices,, vs. ~3 for the
depletion mode devices, assuming a barrier-to-2DEG
spacing of 2 nm), the model is able to maatch the measured
performance well.

Room temp.

100
0 C
Fig. 5. Comparison of measured and
d modeled depletion-mode
HEMT (a) DC common-source transferr I-V characteristics and (b)
DC transconductance at room temperatture.

Fig. 6. Comparison of measured and

d modeled s-parameters for
depletion-mode HEMT from 100 MHzz to 110 GHz vs. bias at
room temperature.

Fig. 4. Comparison of measured and modeeled enhancementmode HEMT s-parameters from 100 MHz to 110 GHz vs. bias
at room temperature (left) and 100 C (right). The model
presented here enables good matches to be acchieved over the
full range of biases (including positive gate biias),
temperatures, and frequencies evaluated.

d
have also been
The models for E- and D-mode devices
compared to the typical measured on-wafer current gain
and maximum available gain. Fig. 7 shows a comparison
between the measured and modeleed short-circuit current
gain and Masons unilateral figure of merit for E- and D-

167

Table of Contents

mode devices. As can be seen, the measurement and

model matches reasonably well, indicating that the model
accurately captures the ft and fmax of the devices, and that
the devices exhibit nearly balanced values of ft and fmax.
For the devices shown in Fig. 7, the E-mode devices
exhibited ft=278 GHz, fmax=291 GHz, while the D-mode
devices had an ft of 241 GHz and an fmax of 249 GHz.
These results are modestly lower than those reported
previously [2], possibly due to slightly longer gates for the
devices shown here, as well as a the more limited
maximum drain voltage used for the model extraction.

V. CONCLUSION
A model for aggressively-scaled, monolithicallyintegrated InAlN/AlN/GaN HEMTs for millimeter-wave
applications has been developed and demonstrated.
Physically-motivated modifications to the model allow
good fidelity between the measured DC and RF device
performance and the model to be achieved over bias,
temperature and frequency.
ACKNOWLEDGMENT
This work was supported by the DARPA NeXT
program, contract HR0011-10-C-0015, Dan Green,
program manager.
REFERENCES
[1] K. Shinohara, D. Regan, Y. Tang, A. Corrion, D. Brown, J.
Wong, J. Robinson, H. Fung, A. Schmitz, T. Oh, S. Kim, P.
Chen, R. Nagele, A. Margomenos, and M. Micovic,
Scaling of GaN HEMTs and Schottky Diodes for
Submillimeter-Wave MMIC Applications, IEEE Trans.
Electron Devices, vol. 60, no. 10, p. 2982, 2013.
[2] M. Schuette, A. Ketterson, B. Song, E. Beam, T.-M. Chou,
M. Pilla, H. Tserng, X. Gao, S. Guo, P. Fay, H. Xing, and P.
Saunier, Gate-Recessed Integrated E/D GaN HEMT
Technology WithT/MAX>300 GHz, IEEE Electron Device
Lett., vol. 34, no. 6, p. 741, 2013.
[3] I. Angelov, H. Zirath, N. Rorsmann, "A New Empirical
Nonlinear Model for HEMT and MESFET Devices," IEEE
MTT vol. 40, no. 12, pp. 2258-2266, December 1992.
[4] I. Angelov, L. Bengtsson, M. Garcia, "Extensions of the
Chalmers Nonlinear HEMT and MESFET Model," IEEE
MTT vol. 44, no. 10, pp. 1664-1674, October 1996.
[5] I. Angelov, M. Thorsell, K. Andersson, N. Rorsman, E.
Kuwata, H. Ohtsuka, and K. Yamanaka, On the LargeSignal Modeling of High Power AlGaN/GaN HEMTs,
IEEE
Microwave
Symp.
Digest,
DOI
10.1109/MWSYM.2012.6258335, 2012.
[6] I. Angelov, M. Thorsell, D. Kuylenstierna, G. Avolio, D.
Schreurs, A. Raffo, and G. Vannini, Hybrid measurementbased extraction of consistent large-signal models for
microwave FETs, 2013 European Microwave Conf., p.
267, 2013.

Fig. 7. Comparison of measured (dashed) and modeled (solid)

short-circuit current gain (h21) and Masons unilateral figure of
merit (U) for E-mode (a) and D-mode (b) devices. Good
agreement in measured and modeled ft and fmax is obtained.

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SiGe Transmitter and Receiver Circuits for

Emerging Terahertz Applications
U.R. Pfeiffer1) , J. Grzyb1) , R. Al Hadi1) , N. Sarmah1) , K. Statnikov1) , S. Malz1) , and B. Heinemann2)
1) University of Wuppertal, Rainer-Gruenter-Str. 21, D-42119 Wuppertal, Germany
2) IHP GmbH, Im Technologiepark 25, D-15236 Frankfurt (Oder), Germany

AbstractThis paper presents recent developments on transmitter and receiver circuit in advanced SiGe technologies for
emerging applications in the sub-millimeter wave region of the
electromagnetic spectrum. This includes high-power harmonic
oscillators, multiplier chains, and heterodyne I/Q transmitters for
terahertz signal generation, as well as direct detectors, heterodyne
receivers and Radar transceivers for wide-band signal detection.
The circuits are attached to a secondary silicon lens and packaged
on low-cost FR4 printed circuit boards.

pixel can be powered down through a power-down switch.

Fig. 1 shows the chip micrograph implemented in a 0.13 m
SiGe BiCMOS technology SG13G2 [7]. The chip has been
pacakged in a module and provides a total radiated power of
up to 1 mW (0 dBm) with 62.5 W (-12 dBm) per source
pixel on average, which is sufciently high to be used in real
THz imaging applications. This has been demonstrated in an
all-silicon real-time active THz imaging setup with a CMOS
1k-pixel THz video camera [10].

Todays THz technologies have promised rapid growth

in emerging markets [1] such as airport security screening
[2], medical imaging [3], communication [4], biological [5],
and material analysis [6]. However, the speed at which new
markets emerge is slow because available technologies exhibit high-cost and low-level of integration, which substantially limits their mass-deployment. SiGe process technologies,
however, offer low-cost industry standards with the required
reliability and high frequency of operation. For THz circuits,
however, transistors have to be operated close to or even above
their cutoff frequency. Current state-ofthe-art SiGe HBT devices exhibit a peak fT /fmax of 300 GHz/500 GHz [7]. Such
technologies features SiGe HBTs with an open-base collectoremitter breakdown voltage of 1.6 V, and a peak current gain of
650. The HBTs are integrated in a 130 nm CMOS process with
seven aluminum interconnect layers. Power generation beyond
the cutoff frequency of such devices are done in either one
of two ways, (i) directly extracted from harmonic oscillators,
or (ii), up-converted from lower frequencies by the help of
frequency multiplier chains. This paper presents some of the
recent developments in the eld of THz signal generation
and detection with heterodyne circuits operationg as high as
820 GHz.

2.1 mm

I. I NTRODUCTION

2.0 mm

Fig. 1. Chip micrograph of the 2.02.1 mm2 large 16-pixel source array. The
array exhibits a 520 m center-to-center pixel spacing in a honeycomb-like
tessellation.

Conventional THz sources coherently lock all oscillators in

phase to create a single THz beam. Unlike this, the circuit
scheme locks oscillators only on the pixel-level to drive a
differential on-chip antenna. A synchronous operation of all
source pixels is not desired in this work. Each pixel can
be powered down independently such that arbitrary pattern
congurations can be loaded.
III. C OHERENT CW

II. H ARMONIC OSCILLATOR ARRAYS FOR DIFFUSE

SOURCES FOR

LO

GENERATION AND

ILLUMINATION

ACTIVE ILLUMINATION

One possibility to generate THz signal power is to use

harmonic oscillators, e.g. triple-push oscillators as presented
in [8], [9]. In this case, a source consists of a primary
on-chip ring-antenna and two triple-push oscillators locked
180 out-of-phase. The circuit implementation is scalable in
2-D such that arbitrary array sizes with very large overall
output power can be realized for diffuse illumination in active
imaging applications. For instance, 16 source pixels have
been implemented in a 44 array conguration where each

At lower mmWave frequencies, state-of-the-art SiGe power

ampliers have demonstrated saturated output powers as high
as 20 dBm at 60 GHz [11], up to 10 dBm at 160 GHz
[12], and recently up to 5 dBm at 240 GHz [13]. This power
is sufciently high to drive multi-stage frequency multipliers
to reach the sub-millimeter-wave band. Frequency multiplierchains with an output power of -3 dBm at 325 GHz (x18), and
-6 dBm (40 GHz BW) at 240 GHz (x16) were reported in a
0.13 m SiGe HBT process [14][16]. This approach makes it

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IV. S I G E I/Q TRANSMITTER AND RECEIVER CHIP - SETS

Fundamentally pumped SiGe I/Q Tx and Rx chipsets have
been reported at 160 GHz [17]. Recent developments suggest
that such circuits could be pushed up to 240 GHz [13], [16],
[18]. The performance limiting building block of the receivers
is the LNA, as it not only determines system bandwidth,
but also overall noise gure. In terms of circuit topology at
very high millimeter-wave frequencies, multi-stage commonbase or cascode structures are typically favored, because they
provide high enough gain at the very rst stage, essentially
blocking the noise contribution of the second and following
stages. At frequencies above 1/3 of fmax , practical amplier
design becomes increasingly difcult due to the transistor
power gain roll-off. Current designs have shown 12 dB gain
at 245 GHz over a bandwidth of 25 GHz and a noise gure
of roughly 11 dB for a 4-stage single ended common-base
topology [19]. A 5-stage differential amplier based on a
cascode structure provides 18 dB gain with a measured NF
of 11 dB over an 8 GHz bandwidth [20]. To reduce the
power consumption of these multi-stage ampliers without
decreasing the available power gain, more sophisticated circuit
topologies become necessary. In a more recent publication
[18], a 4-stage cascode-based LNA utilizing unilateralization
through inductive feedback demonstrated 22.5 dB gain at
233 GHz with a 3 dB bandwidth of 10 GHz. Showing a
simulated noise gure of 12.5 dB, it only draws 17 mA
from a 4-V supply, effectively cutting power consumption of
comparable cascode topologies in half.
Boyond this point, harmonic-mixer based receiver frontends without LNAs are an alternative because they allow
the LO to be generated at a lower frequency than the input
RF signal. This operation has been successfully demonstrated
up to a frequency of 825 GHz [21] in SiGe. The Rx, for
instance, is based on a x16 frequency multiplier chain with a
harmonic mixer operated at the 5th harmonic. The TX chip
delivers 17 dBm EIRP at 823 GHz. Unfortunately, such
harmonic mixers suffer from a relatively low conversion gain
and high noise gures due to an inefcient mixing process,
which relies on generation of the required LO harmonics by
the non-linearties of the HBT device itself. As an alternative, a
subharmonic downconversion architecture, where the LO can
be generated at half the RF frequency, can be implemented
with a two-stage mixing process. Such a sub-harmonically
pumped I/Q transmitter operating from 150-168 GHz was
reported in [22]. The peak conversion gain is 29 dB and Psat
is 10.6 dBm. The mixers are driven by an integrated VCO
with prescaler and is operating at 74-81 GHz.

V. S QUARE - LAW S I G E DIRECT DETECTOR ARRAYS

Unlike heterodyne receivers, direct power detectors are
preferable for their low-power consumption and their compactness which make them suitable for large arrays. Recently,
a realtime THz camera system has been demonstrated in a
65-nm CMOS technology [10], [23] with NMOS fT /fmax
of 160/200 GHz. Generally, SiGe HBTs exhibit fairly higher
fT /fmax and hence better sensitivity can be expected at THz
frequencies. SiGe HBT power detectors have been implemented in a 0.25m SiGe process technology with a peak
fT /fmax of 280/435 GHz. Fig. 2 (left) presents the commonbase detector circuit schematic. Based on the nonlinearity of
the base-emitter junction, the detector operates as a direct
detector. A 35-pixel array with differential on-chip ring
antennas has been fabricated and is shown in Fig.
2 (right).
A noise equivalent power (NEP) of about 50 pW/ Hz has
been measured at 0.7 THz [24]. The high cut-off frequency
of the HBT device has been achieved by device optimisation
and parasitic capacitance and resistance reduction, which is
benecial for the detector sensitivity.
1 mm

T1
Ve

Vb

Vc
I out

0.8 mm

possible to capitalize on the high performance in terms of output power and tuning range of low frequency components. For
reasonable output power generation at harmonic frequencies,
it is required for the multiplier to have high output power
capability, dynamic range and conversion efcency. Oddharmonic frequency generation using x3 and x5 multipliers
require driving the multiplier stages with large input power
for sufcient odd harmonic generation. The generation of large
input power to drive multipliers require power ampliers that
increases the overall power consumption.

T2
Antenna
Detector

Fig. 2. SiGe direct power detector circuit (left) and chip micrograph (right).

VI. FMCW R ADAR S YSTEM FOR SENSING APPLICATIONS

A 0.32 THz homodyne FMCW radar system for shortrange applications based on a low-cost SiGe HBT chip-set
was presented in [25]. The architecture is based on frequency
multiplication, which offers a large operational bandwidth of
27 GHz. After successful calibration procedure, a measured
range resolution of 6.8 mm was achieved, which comes close
to the theoretical limit of 5.6 mm. The chips are fabricated with
STMicroelectronics 0.13 m SiGe HBT process with cutoff
frequencies fT /fmax of 300/350 GHz. They are equipped with
on-chip antennas and packaged with a 4.5-mm Si-lenses. The
packaged transmitter module radiates -5 dBm into free space,
the maximum conversion gain of the receiver is -7.9 dB, and
its minimum SSB noise gure is 30.3 dB. These characteristics
provide a proof-of-concept that FMCW radar system operating
in the unlicensed band above 300 GHz can be efciently
realized in low-cost SiGe HBT technology. The micrographs
of the monolithically integrated SiGe HBT chips as well as a
lens-packeged TX module are shown in Fig. 3.
A 240 GHz monostatic circular polarized SiGe FMCW
radar system based on a transceiver chip with a single on-chip
antenna was presented in [26]. The radar transceiver front-end
is implemented in a low-cost 0.13-m SiGe HBT technology
version with cutoff frequencies fT /fmax of 300/450 GHz. The
transmit block comprises a wideband x16 frequency multiplier
chain, a 3-stage PA, while the receive block consists of an

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Table of Contents

Frequency
Tripler

PA

Frequency
Doubler

On-Chip
Single-ended
Slot Antenna

(a)

IQ-Mixe

Freq. Mult. Chain

Transmitter

Diff. Branchl.
Coupler

Frequency
Tripler
LO-in

PA

Frequency
Tripler

PA

TX-PA

DC-Bias

(b)

LNA

PA

LO-PA

Frequency
Tripler

LO-in

15 GHz
Active Balun

(a)

On-Chip
Subharmonic
Differential Folded
Mixer
Dipole Antenna

D
S

(b)
Pwr.
Supply

Receiver

4.5mmSi-lens

LO-IN
DC-Bias

(c)

Differential
I/Q-Outputs

Pwr.
Supply

18 GHz Input

TX module

SiGe
chip

On-chip
Antenna

Diff.
Quadr.IF-OUT

Bonding
Wires

PCB
Si-lens

Fig. 3. (a) Micrograph of the monolithically integrated 2.1 0.45-mm

0.32 THz TX chip, and (b) of the 2.3 0.45-mm 0.32 THz subharmonic
quadrature RX chip. (c) Lens-integrated TX module with SiGe HBT TX chip
mounted on the back-side of the Si-lens.

LNA, a fundamental quadrature down-conversion mixer, and

a 3-stage PA to drive the mixer. A differential branch line coupler, and a differential dual polarized on-chip antenna complete
the transceiver architecture. The use of a single antenna in the
circular polarized radar transceiver leads to compact size and
high sensitivity. The measured peak radiated power from the
4.5-mm Si-lens equipped radar module is +3 dBm (EIRP) at
236 GHz. The operational bandwidth of the radar transceiver is
60 GHz around the center frequency of 240 GHz. After system
calibration a range resolution of 3.65 mm was achieved, which
is only 21% above the theoretical limit.
Figure 4 shows the micrograph of the circular polarized
radar transceiver chip. A quadrature excitation of the feeds,
exploiting a branch-line coupler, results in circular polarized
radiation. The implemented conguration forms a Left Hand
Circular Polarized antenna for the transmitted signal. The
polarization of the reected signal from the target is therefore
changed to Right Hand Circular Polarized. The two received
portions of signal power from the orthogonal polarization
antenna ports are combined at the LNA input through the
quadrature hybrid coupler.
VII. A NTENNA DESIGN AND PACKAGING
A key feature at THz frequencies is that antennas get smaller
and may be implemented on-chip in a cost-efcient way, thus,
eliminating the need for additional external components such
as expensive waveguides. Highly integrated chip sets may be
then simply wire-bonded on low-cost boards (see Fig. 5). Ideal
on-chip antennas should fulll numerous challenging requirements, possibly including: wide operation bandwidth in terms
of input match and radiation pattern quality, highest possible
radiation efciency on a bulk silicon substrate, low mutual

Fig. 4. (a) Micrograph of the monolithically integrated 2.4 1.2-mm2

240 GHz radar transceiver chip implemented in SiGe technology; (b) PCB
with radar transceiver SiGe HBT chip mounted on the back-side of a 4.5 mmsilicon lens.

coupling for array arrangements, layout fully compatible with

complex silicon design rules, appropriate gain to compensate
the inuence of a high path loss, and Gaussian-like radiation
patterns if applied in the quasi-optical systems [27]. All of
them being a persistent problem for on-substrate antennas,
has become one of the main motivations for the use of the
lens-coupled on-chip planar antennas.
A set of broadband linearly polarized ring antennas illuminating silicon lenses through the chip backside has been
developed to work with a variety of FET- and HBT-based
square-law detectors, and harmonic oscillator and multiplierchain based power source components [8][10], [24], [28]
[30] (see Fig. 6). Depending on the connected circuitry and
the required additional functionality, the ultimate antenna
geometry may vary but it basically shares some common
features. It consists of 2-wire semi-rings connected along the
center feed and is driven differentially by detector devices in
its center or fed from a harmonic source located aside. The
center feed of the antenna is non-uniformly tapered using stepwise approximation or even non-monotonic shapes altogether
with the appropriate ring width to provide the required input
impedance characteristics to the frequency-dependent intrinsic
transistor properties operating close to or even beyond its cutoff frequency.
VIII. S UMMARY AND CONCLUSION
This paper presented recent developments on transmitter
and receiver circuit in advanced SiGe technologies. All circuits were fully integrated including on-chip antennas and no
external passives such as wave-guides or horn antennas were
required which demonstrates their low-cost potential for future
THz applications.
ACKNOWLEDGEMENTS
The author would like to thank the European Heads of
Research Councils (EuroHORCs) and the European Science

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Table of Contents

Fig. 5. The PCB-assembled lens-antenna integrated RX circuit at 820 GHz

as an example of a low-cost THz hardware solution [31].

Fig. 6. An example of a lens-coupled on-chip ring antenna designed to operate

with a broadband HBT THz power detector.

Foundation for partial funding of this work through an European Young Investigator Award. This work was also partially
funded by the European Commission through the project
DOTFIVE (no. 216110) and DOTSEVEN (no. 316755).
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Silicon Wireless Systems for 60-GHz Consumer and Infrastructure

Applications
Alex Tomkins, Alan Poon, Eric Juntunen, Ahmed El-Gabaly, Grigori Temkine, Yat-Loong To, Craig
Farnsworth, Arash Tabibiazar, Mohammad Fakharzadeh, Saman Jafarlou, Hatem Tawfik, Brad Lynch,
Mihai Tazlauanu, and Ronald Glibbery.
Peraso Technologies Inc., Toronto, Ontario, M5J 2L7, Canada

I. INTRODUCTION
The unlicensed 60-GHz band offers unprecedented access
to uninterrupted spectrum that is on the cusp of being fully
utilized for a range of applications by both start-ups and
established communication companies. Many potential
applications exist, encompassing both consumer and
enterprise applications, with most distilling down to the
requirement for high data-rate and low-latency wireless
links.
The adoption of the Wireless Gigabit Alliance (WiGig)
specification by the Wi-Fi Alliance as part of the nextgeneration Wi-Fi protocol, IEEE 802.11ad-2012[1], was a
major step forward for the industry. It showed its readiness
to move forward in a unified manner and avoid the potential
fragmentation that can occur without a widely accepted
industry standard.
Furthermore, the anticipated adoption of 60-GHz
technology into the consumer space will help drive down
costs across the entire mm-Wave implementation space,
especially when, as we propose, WiGig derived solutions
are leveraged into the backhaul and infrastructure space.

transceiver and 40-nm CMOS-based baseband chip.

Together, the chipset supports the IEEE 802.11ad protocol
including the 4 channel frequencies (58.32, 60.48, 62.64,
and 64.8 GHz) and modulation and coding schemes (MCS)
up to QPSK at 2.5 Gb/s (MCS9) and 16-QAM at 4.62 Gb/s
(MCS12). Furthermore, the upcoming transceiver revision
enhances the transceiver performance and offers additional
features.
To support multiple markets, the chipset is combined with
a range of packaging solutions to provide the optimal
interface and performance for the given application. For
consumer electronics and other highly integrated markets, a
transceiver package with integrated transmit and receive
antennas is available, each offering approximately 8 dBi
2
gain within a 7 x 7 mm area. For backhaul and
infrastructure applications, dedicated transmit and receive
waveguide modules have been developed that provide a
standard WR-15 interface and less than 1 dB insertion loss
at 60 GHz, all in a cost-effective and volume
2
manufacturable form-factor. The modules are 25 x 40 mm
and utilize a 30-pin system-level interface.
B. System Performance Expectations
25
PRS1021 (LOS)
PRS1025 (LOS)
PRS1021 (NLOS)
PRS1025 (NLOS)

20
Link Range (m)

Abstract A silicon-based 60-GHz chipset is described that

addresses both consumer and infrastructure-backhaul
requirements.
An antenna-integrated packaged solution
includes a WiGig compliant transceiver and > 8dBi gain
antennas. Low-loss wave-guide modules are also shown that
integrate the same transceiver with a < 1dB loss WR-15 waveguide transition. A fully WiGig compliant baseband IC is
described integrating a USB 3.0 interface and a full analog
front-end interface to a radio transceiver. Finally, the nextgeneration transceiver IC is described that features enhanced
output power, > +16 dBm, and newly optimized fast-locking
AGC operation.

15
10
5
0
0

II. SYSTEM SOLUTION

WiGig PHY Datarate (Gbps)

Figure 1: Plot of modeled link range for the antenna-in-package

radio as a function of the WiGig PHY data-rate at sensitivity.
Measured points are shown as triangle markers.

A. Overview
Peraso has developed a range of solutions to address
multiple markets, all built around common silicon, and
differentiated with a range of packaging and module
solutions. The chipset contains a 130-nm SiGe-based radio

978-1-4799-3622-9/14/$31.00 2014 IEEE

System models have been developed to guide the

development of the various solutions. Using standard
channel propagation models, IC-specific performance

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Table of Contents

metrics and known sensitivities for various modulation and

coding schemes, estimated link-distances were calculated
for various data-rates.
The data-rates, as shown in Figure 1, are the effective
physical layer (PHY) data-rates, which include the LDPC
error-correction coding overhead, but exclude any higherlevel protocol overhead. The sensitivity, as per the
802.11ad specification, is defined at a 1% frame-error rate
(FER). For the antenna-integrated packaged solution,
results are shown for both a line-of-sight (LOS) model and a
none-line-of-sight model (NLOS), which consists of a tworeflection path. Results are shown for both the current
generation silicon, the PRS1021, and the next-generation
transceiver, the PRS1025. More details are provided for
these two designs in Sections II and III.
Limited measurement results are currently available for
the full system under LOS conditions, and are shown by
symbols in the figure. These results were obtained using a
packaged radio to packaged radio link in conjunction with a
reference baseband system based on the Agilent 81199A
Wideband Waveform Center, rather than the Peraso
baseband chip to isolate the RF-performance. The results
align well with the model over low to moderate data-rates
(up to 2.5 Gb/s) but fall off at 4.6 Gb/s, where the model
overestimates performance. Investigations are on-going for
an explanation.
1000

PRS1021 (24 dBi)

PRS1025 (24 dBi)
PRS1021 (38 dBi)
PRS1025 (38 dBi)

Link Range (m)

800
600
400

this model will extend the longer distance links by almost 2

times.
Here, the model predicts greater than 1 Gb/s links over
distances of approximately 200 m when using a more
compact 24 dBi gain antenna, and about 700 m when
configured with 38 dBi antennas.
Measurements of the current system have been carried
out to just beyond 140 m using 24 dBi horn-antennas, where
data-rates beyond 1 Gb/s at the application layer have been
achieved (including all driver and protocol implementation
overhead) and further testing is on-going.
II. SYSTEM COMPONENTS
A. Radio Transceiver
Built using a 130-nm SiGe:C BiCMOS technology, the
transceiver[2] implements direct-conversion transmit and
receive architectures with a fundamental-frequency PLL
and integrated crystal oscillator. An integrated bandgap and
multiple LDOs provide stable and robust biasing and
power-supplies, and multiple programmable GPIOs and a 4wire SPI interface ensure fast and robust control over all
operational features.
The receiver delivers > 70 dB of gain, a dynamic range
control of about 50 dB and a noise-figure of around 6 dB.
The transmitter offers an 8-dBm OP1db and a 20-dB
programmable gain-range. TX EVMs less than -21 dB are
achieved across the first 3 WiGig channels, as shown in
th
Figure3, with some degradation then observed into the 4
channel due to PLL phase-noise limitation.
These
limitations, and more, are being addressed in a nextgeneration transceiver IC.
Ch. 1

200

Ch. 2

0
0

WiGig PHY Datarate (Gbps)

Figure 2: Plot of modeled infrastructure link range as a function

of the WiGig PHY data-rate. Preliminary measured data-points
are shown as triangle markers.

Ch. 3

Backhaul and infrastructure links, as shown in Figure 2,

will implement more aggressive antenna schemes (here
showing 24- and 38-dBi gains respectively) and will thus
achieve much higher link distances. However, with longer
link distances also comes a much larger impact from oxygen
absorption (as high as 16 dB/km) and the possibility for
degraded link conditions due to humidity and rain-fall.
Furthermore, infrastructure links demand a much higher
level of reliability than a consumer link, thus our model
assumes an additional 3 dB of margin and effective frameerror rates better than 0.1%. Ignoring water and humidity in

174

WiGig
EVM
Channel (dB)
1
-22.13
2
-22.23
3
-21.15

Figure 3: Plots of measured constellations for WiGig channels 1-3

and the corresponding transmitter EVMs for each case (table,
right). Additionally, a die photo of the radio transceiver is shown
at the bottom-right.

Table of Contents

B. WiGig Baseband IC

D. WR-15 TX/RX Waveguide Module

Falcon-B WiGig Baseband

UMAC Peripherals
GPIO, SPI, UART,
PWR, LSADC, I2C

USB 2.0/3.0
USB
PHY

Device/
Host

MAC

PHY

Upper MAC CCM

WiGig PHY Tx
Path

640K

Upper MAC CPU

MAC/PHY IF
and GCMP

AFE
DAC
DAC

PLL

Packet Buffer + Shared

Memory

PCIe Gen2 1x
PHY

EP/RC

LMAC Peripherals
GPIO, SPI, UART

416K

Figure 6: WR-15 waveguide module and the associated RX (left)

and TX (right) high-frequency substrate SiPs.

Additional 128K

ADC
Packet
Processor

Lower
MAC CPU

Packet
Processor
RAM
64K

Lower
MAC RAM

WiGig PHY
Rx Path

ADC

192K

Figure 4: Block diagram and package photo of the 802.11adcompliant baseband IC.

The baseband IC, shown in Figure 4, is a fully-integrated

802.11ad baseband including MAC and PHY that
implements a USB 3.0 interface on the host-side, and a full
analog front-end interface to a radio transceiver, including
high-speed ADCs and DACs. The sampling rates are 3.52
and 2.64 GS/s for the DAC and ADC respectively, and both
are 6-bit resolution. Two integrated RISC CPUs and on-die
memory perform all control and management functions,
including upper and lower MAC functions as well as radiocontrol and data flow-control. The IC is implemented in a
2
40-nm CMOS technology, and uses a 7x7 mm BGA
package.

Backhaul and fixed infrastructure links demand much

higher performance than consumer applications in terms of
both link distance and reliability. To achieve these
requirements, high-performance wave-guide based antennas
are often specified, so dedicated RX (left) and TX (right)
modules have been designed to interface with these devices
and are shown in Figure 6.
With an integrated low-loss waveguide transition (<1 dB
insertion loss across the 60-GHz band) and the integration
of a majority of the necessary support components, this
system-in-package (SiP) utilizes a 30-pin connector to
interface with a baseband modem, either a WiGig compliant
baseband, or a custom backhaul modem.
E. Fully Integrated 802.11ad Compliant USB 3.0
Dongle

C. Antenna-Integrated Package

Figure 5: The 7 x7 mm2 antenna-integrated package (left) and the

associated radiation pattern (right).

For cost-sensitive and space-constrained mobile

applications, a low-loss organic substrate-derived package
was developed for the transceiver. The package is a 7x7
2
mm BGA with 0.5-mm pitch balls. The antenna pattern has
been designed to provide a uniform peak gain of 8 dBi
across all WiGig channels in the upper half-plane, and the
half-power beamwidth is greater than 90.

175

Figure 7: Fully integrated 802.11ad-compliant USB 3.0 dongle

Both the transceiver and baseband ICs have been

integrated together in a USB-3 compatible dongle that
integrates a fully functional WiGig/802.11ad compliant
system. Testing is on-going, but already, User Datagram
Protocol (UDP) data-rates beyond 1.2 Gb/s have been
achieved, including all application-layer and driver
overhead within both Windows and Linux.

Table of Contents

III. NEXT-GENERATION TRANSCEIVER

The next-generation transceiver design is currently under
fabrication and has been designed to significantly augment
the existing transceiver in a few major areas: frequency
coverage and phase-noise, transmitter linearity, receiver
automatic
gain-control
(AGC),
and
system
integration/testability/calibration. This is being done with
minimal increase in cost or area.
A. Transmitter Architecture

symbol-rate recovery block in the baseband, as well as AGC

functionality in the receiver. To ensure that the baseband
symbol-rate recovery and other timing compensation is not
impaired, the AGC in the receiver should settle not only
before the CEF, but also before the end of the STF.
To achieve the required wide-dynamic range of operation
(in excess of -78 dBm to -33 dBm) and rapid convergence,
the revised AGC implements a multi-stage variable gain
architecture with parallel power sensing feedback. The
variable gain is implemented digitally with fine control at
baseband, with <1 dB gain-step size, and more coarsely at
RF, with larger programmable step sizes and about 25 dB of
additional dynamic range.

Figure 8: The re-designed transmitter architecture.

The transmitter features a multi-stage variable-gain PA

designed to achieve an OP1dB beyond +16 dBm across the
60-GHz band. The revised lineup is designed to address a
wide-range of output power targets and input signal ranges
using high-linearity I/Q mixers and wide-dynamic range,
digitally-stepped attenuators. To ensure robust operation,
DC offset-cancellation DACs and I/Q amplitude and phase
compensation circuits have been implemented.
B. Receiver Gain Control
Preamble ~ 1.9s
STF
1.2s

CEF
0.65s

Header
0.6s

Payload
N x 0.3s

Figure 10: Example waveforms from simulation of the receiver

AGC, with a variety of input packet waveforms (top) and the
corresponding outputs (bottom).

A rapid gain acquisition is achieved in about 300 ns to

within 6 dB of the final value, and the final gain, within +/1dB of the target, is progressively converged towards over
the next 1 s, before the end of the STF. Examples of the
simulated AGC convergence are shown in Figure 10.

...
VII. CONCLUSION

Figure 9: Basic representation of the 802.11ad SC packet

structure

The 802.11ad standard[1] uses a packetized structure

wherein the actual data content of the packet, the payload, is
preceded by a preamble and a header which contain critical
information about the data to follow.
Figure 9 shows the basic structure of an 802.11ad singlecarrier (SC) packet. The header contains, among other
things, the MCS level for the payload and its length. The
preamble contains a short training field (STF) and a channel
estimation field (CEF). The CEF is a critical field for the
baseband to receive in order to ensure that the rest of the
payload can be properly decoded and thus requires the RFportion of the receiver to have suitably conditioned the
signal, mainly the amplitude and distortion levels, prior to
the beginning of this field. The STF period of the preamble
offers a repeating signal patterns (Golay complementary
sequences) that are used to drive, among other things, a

176

A family of consumer and infrastructure products have

been presented that utilize the unlicensed 60-GHz frequency
band and the WiGig/802.11ad standard.
Continued
development and optimization of the existing radio and
baseband performance is ongoing through improvements to
the MAC and system driver software. Furthermore, the
next-generation transceiver design is under manufacturing
and is expected to provide significant improvements to
system performance with little to no cost or area penalty.
REFERENCES
[1] IEEE Standard for Information technology, 802.11ad-2012,
December 2012.
[1] E. Juntunen, A. Tomkins, A. Poon, J. Pham, A. El-Gabaly, M.
Fakharzadeh, H. Tawfik, Y. To, M. Tazlauanu, B. Lynch, and
R. Glibbery, A Compact Antenna-In-Package 60-GHz SiGe
BiCMOS Radio, RFIC 2014, June 2014

Table of Contents

An Active Double-Balanced Down-Conversion Mixer in InP/Si

BiCMOS Operating from 70-110 GHz
Jamin J. McCue1, Matthew Casto1,2, James C. Li3, Paul Watson2, and Waleed Khalil1
1

The Electroscience Lab, The Ohio State University, Columbus, OH, 43210, USA
The Air Force Research Laboratory, 2241 Avionics Circle, WPAFB, OH 45433, USA
3
HRL Laboratories, LLC, Malibu, CA 90265, USA

semiconductors and CMOS has been proposed and

demonstrated for mixed-signal circuits [6], and more
recently for W Band LNAs [7]. This work quantifies the
performance of InP/Si BiCMOS, in comparison with other
silicon technologies, for the development of W-Band
down-conversion mixers.

Abstract In this paper, a double-balanced Gilbert cell

down-conversion mixer is demonstrated from 70-110 GHz.
The wide bandwidth and high frequency are enabled by the
HRL InP/Si BiCMOS process. With an fT of 300 GHz, the
available 0.25 m InP HBTs are used in the signal path while
the 90nm CMOS devices are used for biasing and gain
adjustment. The fully differential circuit is implemented
using two on-chip Marchand baluns feeding both the LO and
RF ports. An IF buffer follows the mixer to improve
matching and signal quality for testing. After de-embedding
the balun and IF buffer, the mixer core achieves a peak
conversion gain of 13 dB, a minimum DSB NF of 10 dB, and
an OP1dB of -2 dBm while consuming 5 mA from a 3.3 V
supply.
Index Terms W-Band circuits, mm-wave mixer, doublebalanced mixer, Marchand balun, heterogeneous integration.

II. INP/SI BICMOS INTEGRATION

HRL has developed an intimate heterogeneous
integration technology vertically integrating its 250 nm
InP DHBTs with the IBM 90 nm RF-CMOS technology.
The interconnect via between the CMOS tier and the InP
2
2
tier features a 11 m size, a 2x2 m total footprint, and
5m pitch with negligible parasitics. The integration starts
with a fabricated, unfinished CMOS wafer and a fully
grown epitaxial InP HBT wafer. The CMOS wafer has full
thickness and has been stopped at the planarized metal
layer. Then the InP DHBT expitaxial layers are transferred
from their growth substrate to a temporary handle wafer,
and subsequently bonded to the CMOS wafer. Once
bonded, the temporary handle wafer is removed and
subsequent InP DHBT and heterogeneous interconnect
processing starts. Additional details concerning fabrication
and processing can be found in [8, 9].
The semiconductor technologies used for this paper
have several features that enable RFIC design. The 90nm
IBM RF-CMOS technology features 1.8/2.5/3.3 V FETs,
two backend MIMCAPs, and 8 levels of copper
interconnect. The 250 nm HRL InP DHBT technology
features a peak 300 GHz fT/fMAX, 4.5 V off-state
breakdown, integrated thermal via, and 2 levels of gold
interconnect. Fig. 1 (a) shows a cross-section of the InP/Si
BiCMOS technology. VIA01 serves as the via between
the last CMOS copper metal layer and the first InP gold
metal layer while TVIA serves as the integrated thermal
via. Fig. 1 (b) shows a SEM image of a heterogeneously
integrated 250 nm InP DHBT.

I. INTRODUCTION
The W Band, between 75 GHz and 110 GHz, is an
emerging application space on several fronts including
radar [1, 2], imaging [3], and high speed communications
[4]. A critical receiver component found in systems
developed for such applications is a down-conversion
mixer whose function is to accurately translate signals to
lower frequencies for processing. For many applications,
direct conversion or low-IF receivers are attractive for
lowering complexity and cost. Direct conversion
receivers, however, are especially susceptible to
deleterious effects due to flicker (1/f) noise, DC offset,
LO-to-RF leakage, IQ mismatch, and both even- and oddorder intermodulation distortion [5]. In order to combat
these effects, well-balanced mixers utilizing bipolar
devices are often utilized. In addition, with highly-scaled
technologies operating at W Band frequencies, process
variations can degrade performance necessitating some
form of integrated assessment and tuning capability [2].
Taking these factors into consideration, BiCMOS
technologies become very attractive for W Band
applications requiring down-conversion.
Until recently, research has been focused on the
demonstration of CMOS and SiGe BiCMOS technologies
[1-6]. In order to move beyond the performance of siliconbased technologies, while still providing high levels of
integration and control, heterogeneous integration of III-V

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Table of Contents

the frequencies of interest while th

he current commutation
stage is sized for on/off switching speed.
s
By designing for
these two qualities, the mixer gain is
i maximized while the
noise contribution of the LO traansistors is held to a
minimum.
To save power and facilitate biaasing, the available 90
nm CMOS transistors are used as current sources in the
t current of the mixer
design. Transistor M1 sets the DC tail
while M2-M5 provide base currentt biasing for the bipolar
devices. Transistors M2-M5 are imp
plemented as thick gate
devices to avoid breakdown in thee high voltage domain;
VBias2 and VBias3 are created by mirroring a single offchip current reference.

(b)

(a)

Fig. 1. (a) Crooss-section of the

complete HRL InP/Si BiCMOS
BEOL stack. (bb) Cross-sectional
SEM image of a fabricated InP/Si
BiCMOS chip sshowing a DHBT,
heterogeneous via (VIA01), 8
layers of coppper metal, and a
single layer of goold metal.

B. IF Buffer
The IF buffer, depicted in Fig. 2 and detailed in Fig. 3,
is composed of two emitter folllower stages and one
differential gain stage. The first em
mitter follower isolates
the mixer core. Additionally, due to
o the high fT of the InP
devices, small shunt capacitances are added in the first
stage to filter the upper mixing prroduct. Given the large
difference between the upper ( LO + RF) and lower ( LO - RF)
mixing products, these small capaccitors have little effect
on the IF bandwidth (0.6-7 GHz).

III. CIRCUIT DESIGN

The circuit diagram for the integrated W Band mixer is

shown in Fig. 2 with the mixer core emphhasized. Two onchip baluns generate the differential RF and LO signals
necessary for the balanced design. After ddown-conversion,
an AC coupled IF buffer isolates the mixxer core from the
testing infrastructure and matches to 50
.

Fig. 3.

IF buffer schematic.

The differential gain stage is inserted primarily for noise

testing and output signal quality. Since a nominal gain of
10 dB is expected from the mixer core,
c
the added gain of
the buffer desensitizes the circuit to
o off-chip noise sources
which introduce measurement errorr. The gain stage is also
AC coupled to independently adjustt gain and set biasing.
The final emitter follower stagee serves to match the
buffer output to 50 . A buffer drop
pout is included on-chip
for de-embedding the mixer core fro
om the buffer.

Fig. 2. Schematic of the active W-Band mixxer core along with

the LO and RF inputs and the differential IF ouutput.

A. Mixer Core

The mixer core is composed of bipoolar InP devices

which are used for both the transconductannce stage and the
current commutation stage. Due to theirr high fT, which
improves switching speed and bandw
width, and high
breakdown voltage, which improves llinearity without
degeneration, the InP devices are ideallyy suited for high
speed mixing applications.
In sizing the InP devices, only eigght options are
available: two emitter widths (0.25, 0.500 m) with four
emitter lengths each (1, 2, 3, 4 m). Froom among these,
the transconductance stage is sized for tthe highest gm at

IV. BALUN DESGIN

For testing the fully differentiall mixer at W Band, a

single ended to balanced conversiion is needed. An onchip, broadside coupled Marchan
nd balun (Fig . 4) is
implemented for its wide bandwid
dth [10] and small size
[11]: a result of the quarter wave naature of the structure.

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Table of Contents

LO power across frequency. After de-embedding the

losses of the balun, shown in Section IV, the gain of the
mixer + buffer is shown in Fig. 7 (a). For these
measurements, the mixer gain saturated at an LO power of
~1 dBm presented to the mixer core. At frequencies above
104 GHz, the W Band multiplier was unable to supply this
LO power to the mixer core resulting in lower gain.

Fig. 4.

A 3D view of the on-chip Marchand balun.

A balun dropout is used to characterize its loss and its

amplitude and phase imbalance. Given testing limitations
at the W Band, multiple 2-port measurements were taken
instead of a single 3-port measurement.
The dropout return loss and insertion loss are shown in
Fig. 5 (a) while the amplitude and phase errors are shown
in Fig. 5 (b). With no matching network, the balun return
loss is < -10 dB from 83-110 GHz. The structure also
exhibits amplitude and phase errors of < 1 dB and < 5,
respectively, with an insertion loss of ~ 8.5 dB.

Fig. 6.

Test setup measuring conversion gain.

The Noise Figure (NF) measurements were taken

identically to those of gain, with the exception of a
Quinstar QNS-FB15LW W Band noise source used as the
RF input. Given the frequency difference between the IF
and RF signals, a low frequency noise source was used for
calibration as discussed in [18]. After de-embedding the
test setup and balun losses [19], the NF for the mixer +
buffer was calculated and is shown in Fig. 7 (a).
The buffer gain and NF were measured separately in a
dropout circuit. De-embedding the gain and NF of the
buffer lowers the overall gain by 9.3 dB and improved the
measured mixer NF by ~1 dB. The calculated gain and NF
of the mixer core are also depicted in Fig. 7 (a).

Fig. 5. (a) Measurement of the balun dropout return and

insertion loss. (b) The amplitude and phase error of the balun.

When fully integrated into a system, the mixer core may

have either differential or single-ended LO and RF signals
available. For this reason, the mixer core is evaluated
seperately from the balun. To do this, the measured balun
loss is used to assess the gain and NF of the mixer core in
Section V.
V. MEASUREMENT RESULTS
Fig. 7. (a) Measured conversion gain and DSB NF with and
without the IF buffer. (b) Measured return loss and isolation.

Testing of the W-Band mixer was performed on wafer

using GSG and GSGSG probes. Conversion gain
measurements were taken with an Agilent E8361C PNA
with N5260A extenders used as an RF source, a Quinstar
QMM-923510040 multiplier driven by an Agilent
E8257D signal generator used as an LO, and an Agilent
4448A PSA used to record the mixer + buffer output
power. This test setup is shown in Fig. 6.
An Agilent W8486A power meter was used to calibrate
both the output power of the RF source for conversion
gain calculations, and the LO source, ensuring constant

The isolation and matching of the RF and LO ports were

measured using the Agilent PNA. Figure 7 (b) shows the
LO return loss below -10 dB from 74-110 GHz and below
-8 dB from 71.5-110 GHz. Additionally, the RF return
loss is below -9 dB from 75.5-110 GHz. The matching
bandwidths of the balun are improved over that of the
dropout because of an additional matching network placed
between the input baluns and the mixer core. The

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Table of Contents

TABLE I
W-BAND MIXER COMPARISON
Reference

Technology

Gain (dB)

[12]

65 nm CMOS

4 6*

[13]
[13]
[15]
[16]
[17]
[17]
This Work

130 nm SiGe
BiCMOS
65 nm CMOS
130 nm SiGe
BiCMOS
180 nm SiGe
BiCMOS
130 nm SiGe
BiCMOS
130 nm SiGe
BiCMOS
250 nm InP,
90nm CMOS

NF (dB)

-1.5

8 10*
DSB
17.4 19.5*
SSB
10 13

20 26*

12 14*

17.2 11.6*

12.5 14.0*
10
5
5 13
(14 22)

15.0 16.5*
SSB
11.0 13.4
SSB
16.6 17.7
SSB
10.0 12.7
(11 14) DSB

BW (GHz)

Output P1dB
(dBm)

Power
(mW)

LO-RF Isolation
(dB)

74 98

~0

~ 50

18

75 110

2 -5

92.4

> 30*

76 77

-14.5

21

73 81

-2

67

68 82

3.4

118.8

> 40*

70 80

3.9

81

89 97

3.3

81

-2 -3

16.5
(50.1)

> 40*

70110

* Includes Balun Loss Includes IF Buffer/Amplifier

[3] Derham, T, et al., "Active MMW Imaging System using the

Frequency-Encoding Technique," KJMW 2007, Nov. 2007.
[4] A. Jebril, et al., Perspectives of W-band for Space
Communications, 2007 IEEE Aerospace Conf. Mar. 2007.
[5] J. Laskar, et al., Modern Receiver Front Ends, WileyInterscience, 2004.
[6] S. Raman, et al., The DARPA COSMOS program: The
Convergence of InP and Silicon CMOS Technologies for
High-Performance Mixed-Signal, IPRM Conf., Jun. 2010.
[7] P. Watson, et al., A Wide-Bandwidth W-band LNA in
InP/Si BiCMOS Technology, IEEE IMS, June 2014.
[8] J.C. Li, et al., Heterogeneous wafer-scale integration of
250nm, 300GHz InP DHBTs with a 130nm RF-CMOS
technology, IEEE IEDM, Dec. 2008.
[9] J. C. Li, et al., 100 GHz+ Gain-Bandwidth differential
amplifiers in a wafer scale heterogeneously integrated
technology using 250 nm InP DHBTs and 130 nm CMOS,
IEEE JSSC, Oct. 2009.
[10] Chen, A.C.; Anh-Vu Pham; Leoni, R.E., III, "Development
of low-loss broad-band planar baluns using multilayered
organic thin films," TMTT, IEEE, Nov. 2005
[11] Hwann-Kaeo Chiou, et al., "Low-Loss and Broadband
Asymmetric Broadside-Coupled Balun for Mixer Design in
0.18-m CMOS Technology," TMTT, IEEE, April 2008
[12] Khanpour, M., et al., "A Wideband W-Band Receiver
Front-End in 65-nm CMOS," JSSC, IEEE, Aug. 2008
[13] Kim, J.; Kornegay, et al., "W-band double-balanced downconversion mixer with marchand baluns in silicongermanium technology," Electronics Letters, July 2009
[14] Ning Zhang, et al., "W-Band Active Down-Conversion
Mixer in Bulk CMOS," Microwave and Wireless
Components Letters, IEEE, Feb. 2009
[15] Powell, J., et al., "SiGe Receiver Front Ends for MillimeterWave Passive Imaging," TMTT, IEEE, Nov. 2008
[16] Chen, et al., "A 68-82 GHz integrated wideband linear
receiver using 0.18 m SiGe BiCMOS," RFIC, May 2010
[17] Reynolds, S.K.; Powell, J.D., "77 and 94-GHz
Downconversion Mixers in SiGe BiCMOS,". ASSCC,
IEEE, Nov. 2006
[18] Noise Figure Measurements of Frequency Converting
Devices, Agilent Application Note 1487.
[19] Noise Figure Measurement Accuracy: The Y-Factor
Method,
Agilent
Application
Note
57-2

measured isolation of the mixer, including balun loss, is

greater than 40 dB across the band.
The output P1dB of the mixer + buffer was measured at
-2 dBm. This performance is without any degeneration or
feedback techniques typically used to increase linearity.
Table I summarizes the performance of W-Band Gilbert
cell mixers and compares them with the presented InP/Si
mixer. The tested circuit is shown (Fig. 8) and occupies an
area of 1.3 mm x 0.8 mm including input baluns and pads.

Fig. 8.

Chip photograph of the active W-Band mixer

VI. CONCLUSION
A wide-band, double-balanced down-conversion mixer
is designed in the HRL InP/Si BiCMOS process. An onchip W Band balun enables the fully differential structure.
The mixer operates from 70-110 GHz with a peak gain of
13 dB and a minimum DSB NF of 10 dB after buffer deembedding. The power usage of the mixer core is 16.5
mW from a 3.3 V supply.
REFERENCES
[1] H. Essen, et al., A Versatile, Miniaturized High
Performance W-band Radar, GeMiC. Dig, Mar. 2009.
[2] O. Inac, et al., A 90-100 GHz Phased-Array
Transmit/Receive Silicon RFIC Module with Built-In SelfTest, IEEE TMTT, Oct. 2013.

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GaN Technology for E, W and G-band Applications

A Margomenos1, A. Kurdoghlian1, M. Micovic1, K. Shinohara1, D.F. Brown1, A. L. Corrion1, H. P.
Moyer1, S. Burnham1, D. C. Regan1, R. M. Grabar1, C. McGuire1, M. D. Wetzel1, R. Bowen1, P.S. Chen1,
1
1
1
2
1
H.Y Tai , A. Schmitz , H. Fung , A. Fung , D. H. Chow
1
2

HRL Laboratories, LLC, 3011 Malibu Canyon Road, Malibu CA 90265, USA

Jet Propulsion Laboratories, California Institute of Technology 4800 Oak Grove Drive, Pasadena, CA 91109, USA

Abstract Highly scaled GaN T-gate technology offers

devices with high ft/fMAX, and low minimum noise figure while
still maintaining high breakdown voltage and high linearity
typical for GaN technology. In this paper we report an E-band
GaN power amplifier (PA) with output power (Pout) of 1.3 W at
power added efficiency (PAE) of 27% and a 65-110 GHz ultrawideband low noise amplifier (LNA). We also report the first Gband GaN amplifier capable of producing output power density
of 296mW/mm at 180 GHz. All these components were realized
with a 40 nm T-gate process (ft= 200 GHz, fMAX= 400 GHz, Vbrk >
40V) which can enable the next generation of transmitter and
receiver components that meet or exceed performance reported
by competing device technologies while maintaining > 5x higher
breakdown voltage, higher linearity, dynamic range and RF
survivability.
Index Terms Gallium nitride, low-noise amplifiers,
millimeter wave integrated circuits, millimeter wave transistors,
power amplifiers.

Fig. 1. Positioning map of GaN W-band amplifiers [3-12].

performance metrics are becoming comparable to competing

InP, GaAs, and SiGe technologies while at the same time
maintaining > 5x higher breakdown voltage. This not only
offers millimeter-wave power amplifiers but it also enables a
variety of other integrated circuits (low noise amplifiers,
mixers, switches, phase shifters, transmitter/receiver modules
etc) operating at lower junction temperatures, with wider
dynamic range that eliminate the need for front-end limiter.
This is of particular importance because it increases the
insertion opportunities and offers economies of scope (the
same GaN technology can be used to cover a wide range of

I. INTRODUCTION
Millimeter-wave (30-300 GHz) circuits are used in a
variety of applications including licensed communication links
at Ka, Q, V, E and W-bands, short-range high resolution
radars, imaging, radio astronomy, remote sensing and test
equipment. These circuits are currently realized with a variety
of device technologies: CMOS, SiGe BiCMOS, GaAs, InP etc
and it is typical that different device technologies are used for
different applications, especially at higher frequencies.
Recent improvements in GaN HEMT devices grown on
SiC substrates have allowed the demonstration of a variety of
next generation millimeter-wave transmitter and receiver
circuits. GaN device technology, with its wider band-gap,
increased saturated electron velocity, higher breakdown
voltage and higher thermal conductivity substrate leads to
circuits with high output power density, high efficiency, high
linearity and wide operational bandwidth. At the system level,
these component improvements offer increases in operational
range, reduction in aperture size requirement, lower power
consumption, wider operational bandwidth, higher data
throughputs, higher spectral efficiency waveform transmission
and reception, lower cost thermal management, increased
robustness and immunity to co-site or hostile jamming.
These advantages are becoming more pronounced as we
move to more aggressively scaled technologies and in
particular T-gate device topologies. Such configurations offer
high ft/fMAX, low minimum noise figure (Fmin) and contact
resistance and operate at lower drain voltage compared to field
plate devices. Furthermore, the aforementioned device

978-1-4799-3622-9/14/$31.00 2014 IEEE

Table 1. HRLs GaN T-gate device performance metrics

Quantities
Gate Length (nm)
fT (GHz)
fMAX (GHz)
Vbrk (V)
Fmin (dB) at 50 GHz

T2
150
90
220
50
2

T3
40
200
400
>40
1.2

T4A
20
329
558
17
0.8

operational frequencies and circuit applications) therefore

making the technology more easily accessible and eventually
more affordable by moving the industry quicker along the
experience curve.
As an example, Fig. 1 summarizes recent W-band T-gate
GaN amplifiers. At these frequencies, T-gate configurations
offer high Pout, wide bandwidth and high PAE but it critical to
point out that both scaling and low contact resistance are
critical in achieving this performance. Such amplifiers will
enable the next generation of high data rate communication
systems, phased array radars and active imagers. There is

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particular interest in the 71-76 GHz, 81-86 GHz and 90-96

GHz bands for high data rate point-to-point wireless links. The

amplifier. All these circuits use HRLs highly scaled GaN T3

process [2] (40 nm, ft=200 GHz, fMAX=400 GHz, Fmin= 1.2 dB at
50 GHz, and Vbrk>40V). The presented circuits show that
highly scaled GaN technologies can meet or exceed RF
performance of competing MMIC technologies, while at the
same time maintaining > 5x higher breakdown voltage and
higher linearity.

Fig. 2. Scanning electron images of three generations of GaN Tgate devices [1-3].

E-band range (71-76 GHz and 81-86 GHz) offers 10 GHz of

bandwidth which in conjunction with low-order modulation
schemes can yield >1 Gbit/sec data rates in the 1-3 mile range.
E-band is a very appealing frequency range for high data rate
communication systems due to the relatively low atmospheric
absorption, potential for high data rates and long distance
transmissions even under deteriorated conditions. Due to the
small wavelength the sizes of the antennas are small, and the
transmitted beams narrow, making E-band ideal for secure,
interference immune links using compact antenna apertures.

Fig. 4. Measured small signal gain of GaN T3 E-band power

amplifier at Vds=12V.

Fig. 3. Output power of various T2 E- and W-band GaN

power amplifiers [4,10,11].

The main performance bottleneck of such systems is the GaAs

power amplifiers used in the transmitter. Their power,
linearity and bandwidth limit the achievable range and data
rates of these links. Moreover, it forces the system
manufacturers to use different transmitter power amplifiers for
each frequency range (71-76 GHz, 81-86 GHz, 90-96 GHz).
The incorporation of GaN technology with its higher output
power, linearity and efficiency will enable the next generation
of wireless point-to-point radios with over 3x improvement in
range and over 5x improvement in data rates by enabling
higher spectral efficiency modulation schemes. In addition to
that, GaN technology can offer complete solutions where a
single transmitter module can cover the entire E and W-bands.
In this paper we are presenting the first reported E-band
GaN power amplifier showing world record PAE of 27% at
1.3W of Pout, an ultra-wideband E- and W-band LNA covering
65-110 GHz and the first reported G-band GaN power

Fig. 5. Large signal performance of T3 E-band power amplifier.

II. DEVICE TECHNOLOGY AND FABRICATION PROCESS

During the last decade, our group has presented GaN
circuits at various frequency bands. In [9] we reported the first
GaN W-band PA with Pout of 316 mW, which evolved into a
PA with Pout of 842 mW at 88 GHz and an associated PAE of
14.8% [12]. Both of these reports utilized our initial first
generation mm-wave device technology. More recently [3]
we have reported our second generation GaN mm-wave
device technology (T2) that increased both the Pout and the
PAE of W-band PAs at 2.1W and 19% respectively [10]. The
epitaxial
layer
structure
consisted
of
an

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GaN process (T4). The device performance is summarized in

Table 1. Fig. 2 shows scanning electron micrographs of all
three GaN device technologies.
III. CIRCUITS USING 150NM GAN TECHNOLOGY
By using our baseline 150nm (T2) GaN technology we have
demonstrated a wide variety of transmitter and receiver
components. Among these we have demonstrated wideband
W-band amplifiers, high power E- and W-band amplifiers
[4,10,11], a class-E X-band PAs [13], a Q-band LNA [14] and
a 3-40 GHz doubly-balanced mixer [15]. Fig. 3 summarizes
the measured Pout of the various E- and W-band GaN
amplifiers realized by HRL using the T2 process. The
technology offers both high power PAs covering 71-76 GHz,
81-86 GHz, and 90-96 GHz as well as a wideband (70-105
GHz) amplifier design.

Fig. 6. Measured response of 5-stage GaN LNA.

Al0.25Ga0.75N/GaN/Al0.04Ga0.96N double-heterojunction, grown by

MBE.
The AlGaN buffer layer improves the device
performance by suppressing short-channel effects. Reduced
parasitic resistance was achieved by partially etching through
the AlGaN barrier, followed by MBE regrowth of n+ GaN (ND
19
-3
= 7.5 x 10 cm ) on the ohmic regions using SiO2 as a
regrowth mask, such that the n+ GaN makes a lateral contact
directly to the 2DEG. With this process, contact resistance
(total resistance between the ohmic metal and the 2DEG) was
reduced to 0.2 ohm-mm. This is a 50% reduction compared to
our previous ohmic process. This yields devices with onresistance of 1.1 -mm. For MMIC fabrication the SiC substrate

III. CIRCUITS USING 40NM GAN TECHNOLOGY

We have also demonstrated a variety of E and W-band
receiver and transmitter circuits by utilizing T3 GaN
technology. The first example is an 81-86 GHz 3-stage power
amplifier shown in Fig. 4. The first stage uses a single 4x37.5
m device which drives a pair of 4x37.5 m devices. The
final stage is comprised by 4 combined 4x50 m devices. This
provides a total output gate periphery of 800 m. The high
ft/fMAX and gain/stage offered by T3 is critical in realizing Wband amplifiers with such gate peripheries. The small signal
measured at Vds=12V showed gain over 20 dB from 79-95
GHz and good input and output impedance match across that
band. Fig. 5 shows the large signal performance at 83 GHz.
Measured Pout was 1.37W at PAE of 27%.
The second example is a 5-stage reactively matched LNA.
The first four stages are 4x25m devices while the final stage
is a 2x37.5 m device for increased linearity. All stages
incorporate source inductive feedback. The circuit is

Fig. 7. Large signal performance of 5-stage T3 LNA.

is thinned down to 50m. Through substrate vias are used for

backside source grounding to reduce parasitic source
inductance. Table 1 summarizes the device performance of
HRLs baseline T2 process. With the same process we have
demonstrated wideband W-band amplifiers, high power Eband amplifiers [11] and class-E X-band PAs [13]. More
recently, under DARPA funding [2], HRL has developed a
40nm GaN process (T3) which utilizes both lateral and
vertical scaling in order to achieve fT=200 GHz, fmax=400 GHz,
Fmin= 1.2 dB at 50 GHz, and still maintain high breakdown
viltage (Vbrk>40V). In 2013 [1] HRL presented our latest 20nm

Fig. 8 Measured small signal gain of G-band T3 amplifier.

implemented in microstrip line topology and 2.5D

electromagnetic simulator was used to simulate all passive
networks. Fig.6 presents the measured small signal data at
Vds=8V. The gain is over 25 dB from 65-110 GHz and input
and output match are better than -7 dB and -5 dB respectively.

183

Table of Contents

This corresponds to a gain/stage of >5 dB up to 110 GHz.

The simulated NF is between 2.3-3.2 dB across the band. The
chip size is 3 mm x 1.3 mm. State of the art W-band LNAs
offer comparable small signal performance [16]. In order to
evaluate the linearity of the amplifier we tested it under large
signal at 100 GHz. Fig. 9 presents the measured P-1dB (14
dBm) and Psat (16 dBm) for the 5-stage LNA. Comparable
wideband W-band GaAs HEMTs have typical P-1dB of 0 dBm.

of the contracting agency. This work was partially sponsored

by the Defense Advanced Research Projects Agency
(DARPA) Nitride Electronic NeXt-Generation Technology
(NEXT) program under Contract No. HR0011-09-C-0126,
program manager Dr. Daniel Green and upon work supported
by the Air Force Research Labs (AFRL) and DARPA under
Contract No FA8750-12-C-0263. The views and conclusions
contained in this document are those of the authors and should
not be interpreted as representing the official policies, either
expressly or implied, of the Defense Advanced Research
Projects Agency or the U.S. Government. Approved for public
release; Distribution unlimited. Part of this research was
carried out at the Jet Propulsion Laboratory, California
Institute of Technology, under a contract with the National
Aeronautics and Space Administration.

IV. G-BAND GAN POWER AMPLIFIER

Due to its high fMAX, T3 technology can also be used for

REFERENCES
[1] K. Shinohara et al, Scaling of GaN HEMTs and Schottky
Diodes for Submillimeter-Wave MMIC Applications, IEEE
Trans. on Electron Devices, vol. 60, issue 10, pp. 2982-2996,
2013.
[2] K. Shinohara et al, 220 GHz fT and 400 GHz fmax in 40-nm
GaN DH-HEMTs with Regrown Ohmic, IEEE IEDM 2010.
[3] D.F. Brown et al, W-band Power Performance of AlGaN/GaN
DHFET with Regrown n+ GaN Ohmic Contacts by MBE,
IEEE EDM 2011.
[4] G74-PA, G84-PA, G94-PA, BAL-WPA, www.mmics.hrl.com.
[5] A. Brown et al, W-band GaN Power Amplifier MMIC IEEE
IMS 2011.
[6] Y. Nakasha et al, E-band 85-mW Oscillator and 1.3-W
Amplifier ICs using 0.12-m GaN HEMTs for Millimeter-wave
Tranceivers, IEEE CSICS 2010.
[7] M. Van-Heijningen et al, W-band Power Amplifier MMIC with
400 mW Output Power in 0.1 m AlGaN/GaN Technology,
EuMA 2012.
[8] J. Schellenberg et al, W-band, Broadband 2W GaN MMIC,
IEEE IMS 2013.
[9] M. Micovic et al, GaN HFET for W-band Power
Applications, IEEE IEDM 2006.
[10] M. Micovic et al, 92-96 GHz GaN Power Amplifiers, IEEE
IMS 2012.
[11] A. Margomenos et al, 70-105 GHz Wideband GaN Power
Amplifiers, European Microwave Integrated Circuits
Conference 2012.
[12] M. Micovic et al, W-Band GaN MMIC with 842mW Output
Power at 88 GHz, IEEE IMS 2010.
[13] A. Margomenos et al, X-band Highly Efficient GAN PA
Utilizing Built-In Electroformed Heat Sinks Advanced Thermal
Management, IEEE IMS 2013.
[14] H.P. Moyer et al, Q-band GaN LNA Using a 0.15m T-gate
Process, IEEE CSICS 2008.
[15] J. Kang et al, Ultra-wideband, High-dynamic Range, Low Loss
GaN HEMT Mixer, Electronics Letters, vol.4, iss.4, 2014.
[16] X.B. Mei et al, A W-band InGaAs/InAlAs/InP HEMT LNA
MMIC with 2.5 dB Noise Figure and 19.4 dB Gain at 94 GHz,
Indium Phosphide and Related Materials Conference 2008.
[17] J. Langst et al, Balanced Medium Power Amplifier MMIC
from 200 to 270 GHz, IEEE IRMMW-THz 2-13.
[18] V. Radisic et al, 220-GHz Solid-State Power Amplifier
Modules, IEEE Journal of Solid State circuits, vol. 47, no. 10,
October 2012.

Fig. 9. Large signal performance of T3 amplifier at 180 GHz.

realizing G-band amplifiers. Fig. 8 shows the small signal

performance and circuit layout of a single stage G-band
amplifier biased at Vds=10V. The amplifier is comprised of a
single 4x20m device and has 4.5 dB of gain and good match
between 180-200 GHz. Fig. 9 summarizes the large signal
performance at 180 GHz. The amplifier showed output power
density of 296 mW/mm and PAE of 3.5% at 180 GHz, when
biased at Vds=8V. This is >3x higher than the state of the art
reported InP HEMT power density at G-band [17-18]. This is
the first reported G-band GaN amplifier.
V. CONCLUSION
In this work we presented E, W and G-band GaN circuits
realized with highly scaled T-gate technologies (150 and 40
nm). The technology offers high fT/fmax, low Fmin, and high
breakdown voltage enable high power, high efficiency, robust,
highly linear, and high dynamic range circuits that can meet or
exceed RF performance of competing, state of the art, device
technologies.
ACKNOWLEDGEMENT
This material is based upon work partially supported by
the Office of Naval Research under Contract No. N00014-12C-0050 monitored by Dr. Paul Maki and N00014-12-C-0088
monitored by Dr. Peter Graig. Any opinions, findings and
conclusions or recommendation expressed in this material are
those of the author(s) and do not necessarily reflect the views

184

Table of Contents

An evaluation of extraction methods for the emitter

resistance for InP DHBTs
T. Nardmann1, J. Krause1, M. Schroter1,2
1

Chair for Electron Devices and Integrated Circuits, Technical University Dresden, 01062 Germany
2
ECE Dept., UC San Diego, La Jolla, CA 92093, USA

Abstract - The emitter series resistance is a very important parameter for bipolar transistors since it can have a significant impact on
both the DC and high-frequency characteristics of transistors. Its
accurate determination is quite difficult due to the complicated emitter material stack and the lack of suitable test structures. Thus,
extraction methods that rely on transistor terminal characteristics
must be used instead.
In this paper, the accuracy of several widely used extraction methods for the emitter resistance has been investigated for three different type I InP DHBT technologies by applying the methods to both
measured and simulated data. Since for the latter the emitter resistance is exactly known, it allows a reliable evaluation of the accuracy
and the applicability of a method.
Index Terms - Parameter extraction, Emitter resistance, IndiumPhosphide HBT, Compact modeling.

I INTRODUCTION
InP HBTs are among the fastest transistors manufactured today
and well suited for mm-wave circuits and systems [1, 2].
However, compact modeling in the area of III-V devices lags
behind that of comparable technologies which has been an
obstacle for effective deployment of InP HBTs (e.g. [3]). Various
attempts to improve compact models document the increasing
demand for accurate modeling (e.g. [4, 5]). Recently, the wellknown compact model HICUM [6] has been successfully applied
to InP DHBTs [7, 8]. Most notably, the scaling of model
parameters with transistor geometry was found to be quite good.
However, the lack of adequate extraction routines has been an
obstacle to efficient compact model parameter extraction. The
superposition of the impact of different physical effects on the
transistor characteristics with different dependence on geometry,
temperature or frequency greatly complicate the parameter
extraction. Being able to isolate single parameters and the
corresponding elements of the equivalent circuit not only allows
for a more simple and physics-based extraction avoiding to lump
different effects together, but also enables a further analysis of
the transistor properties limiting high-frequency operation. Thus,
it would be of great benefit for the overall extraction and analysis
procedure if every element could be determined reliably and
independently.
The emitter series resistance becomes relevant in the mediumto high-current region or at high frequencies and is often difficult
to separate from other effects, most notably the reverse Early
effect and the self-heating of the device. Several methods exist
that attempt to determine the emitter resistance from DC or lowfrequency [9-19] as well as from the high-frequency [20, 21]
terminal quantities. So far, most methods have been applied to
978-1-4799-3622-9/14/$31.00 2014 IEEE

185

Si-BJTs or SiGe-HBTs [22]. The unique properties of InP

DHBTs may lead to differences in their usefulness and precision.
Typically, a method or its improvement is proposed and
applied to measured data of a single or few transistors. The
results are then compared to those from another method, also
obtained from measured data, leaving the question about the
accuracy of the results completely open. However, there exists a
very simple way of evaluating the absolute accuracy of parameter
extraction methods in general by simply applying them to
characteristics generated by a compact model or, in some
instants, also by device simulation. In both cases, the target
parameter is exactly or at least (for device simulation) very well
known.
In this publication, various methods for extracting the emitter
series resistance are applied to data from both compact model
and measurement. Using the compact model generated data
allows not only to establish the absolute error of a method but
also to investigate the cause of errors and the impact of various
other effects. This way conclusions can be drawn as to the
applicability of an extraction method to particular (including
future) technologies. Note that models can also be operated in
bias regions in which the actual transistor would cease to
function. In this paper, 14 InP HBTs with different geometries
from three different fabrication sources have been investigated
for the comparison. Section II specifies the devices used. Section
III briefly describes the methods evaluated and shows their
application to compact model data. Section IV contains the
corresponding experimental results.
II INVESTIGATED DEVICES AND TECHNOLOGIES
The investigated technologies and transistors are a GCS
process with AE0 = 0.8*(3, 5, 10) m as well as AE0 = (0.5, 0.8,
1, 1.5, 2)*15 m from two different process runs, both with
(fT, fmax) = (300, 250) GHz, a Teledyne process with
AE0 = 0.5*(3, 5, 10) m with (fT, fmax) = (300, 450) GHz and an
(fT,
FhG IAF process with AE0 = 0.7*(2, 4, 12) m with
fmax) = (300, 260) GHz. Devices marked in bold indicate
availability of a compact model. For the GCS transistors, both
geometry scalable HICUM/L2 parameters were extracted using
suitable test structures on a special test chip [8] and a HICUM/L0
model was created based on single-transistor extraction methods
[7]. All data for the rE related investigation were generated and
measured, respectively, at a chuck temperature of T0=300 K and
a frequency of 10 GHz (where applicable).

Table of Contents

III EXTRACTION METHODS AND EVALUATION

extraction methods to model-generated data, and Table 1 lists the

relative mean square error w.r.t. the known value of rE in the
compact model. This is the most suitable way for assessing the
accuracy, since no error sources apart from method
approximations exist.

The figures shown in this paper contain the data for a transistor
with AE0 = 0.8x15 m from [8].
An often-used method for the rE extraction is the gm-method
[9]. It is based on the deviation of the measured transconductance
gm from an estimated internal low-injection transconductance
gm = IC/(nFVT). Corrections for (known) values of the base
resistance and current gain have been used here. Fig. 1a shows an
example of the linear extrapolation of the gm data towards its
limit at infinite current. A correction for self-heating has been
published in [10], but taking gm from Re(Y21) is more precise and
partially eliminates the influence of self-heating, making the
correction in [10] unnecessary.
The Z-Parameter method was originally proposed in [11]. It
is based on the assumption that the junction and parasitic
capacitances can be neglected at sufficiently low frequencies and
high current densities. Under these conditions, the extrapolation
of Re(Z12) towards infinite IC yields the emitter resistance (cf.
Fig. 1b).
The H-Parameter method in [12] is based on a reformulation
of the gm-method by peeling off the impact of other equivalent
circuit elements from measured small-signal parameters.
Variations of the method that perform a further deembedding
of parasitic elements and attempt to correct for self-heating are
also available [13]. Since the latter sometimes improve and
sometimes deteriorate the extraction accuracy, they have not
been evaluated here explicitly.
The ideal IB method [14] has been widely applied to Si-based
transistors. It relies on the deviation of the base current IB from
its ideal characteristic extracted at low current densities, where
self-heating and the influence of series resistances are negligible.
The results of this method, when applied to measurements or
models of InP devices, were so bad though that they have not
been included in this paper. The method cannot be recommended
at all for InP devices. The reason for this is the behavior of the
base current, which at most shows only a very small ideal
region at comparatively high bias and self-heating.
The open-collector method [15], when applied to III/V
devices with their semi-insulating substrate in the variant of the
floating substrate node, relies on the relationship between
VCE(IE) at IC = IS = 0. When the collector current is forced to 0,
the CE voltage variation with IE includes, among others, the
voltage drop over rE.
The simultaneous method in [16] and T method in[17] rely
on an iterative simultaneous extraction of the thermal and emitter
resistance. They require the temperature dependence of IB to be
known. The method in [16] uses the voltage drop over rE during
a Gummel measurement calculated from an extrapolated ideal IB.
The method proposed in [17] uses VCE0 = IErE, which results
from the intercept of the linear extrapolation of the data with the
CE voltage axis (i.e. at T = T-T0 = 0). Fig. 3 shows examples
for both methods.
The impact ionization method [18] is often used for Si-based
transistors. However, the application of this method to InP HBTs
is impractical due to the onset of impact ionization at too high
voltages that risk destroying the device. Hence, this method will
not be considered further.
Fig. 4 shows the result of applying the above mentioned

(b)

(a)

1/f
Fig. 1: Application example: (a) gm method and (b) Z-parameter method.
(a)

(b)

Fig. 2: Application example: (a) H-Parameter method and its variations;

(b) open-collector method.
(b)

(a)

rE

Fig. 3: Application example: (a) simultaneous method and (b) T method.

186

GCS bE0 = 0.8m

TD

IAF
0.7x4

GCS , lE0 = 15m

23

25

24

-2

-50

-295

-19

-29

12

-80

51

ZPara
(corr.)

34
(31)

43
(34)

48
(35)

71
(34)

85
(33)

38
(30)

35
(28)

34
(27)

8
(8)

20
(20)

HPara

46

49

47

36

22

23

18

15

-2

-25

Simul

-1

-8

-22

-16

-20

-26

-13

17

32

43

63

74

23

34

41

-64

38

0.8x10

92

-250

0.8x5

78

-154

0.8x3

59

-107

2x15

51

-24

1.5x15

40

OpenC

1x15

gm

0.8x15

AE0
(m)

0.5x15

Tech

0.5x10

Table 1:Relative error (in %) of extraction method w.r.t. model value.

Table of Contents

The simultaneous method in [16] is the most precise one,

with an average relative error of only 11.4%. Its main
disadvantage is the required knowledge of the temperature
dependence of IB, which must be extracted with high precision.
The determination of the extraction region may occasionally be
difficult and can have a strong influence on the result.
The T method in [17] seems to be a less precise variant of
the simultaneous extraction, but the extraction region
determination is comparatively easy and robust. Also, the
extraction of Rth is usually very accurate with this method.

From both Table 1 and Fig. 4, it is clear that no perfect method

exists. The methods vary significantly in their absolute values,
but at least some agree on a general trend for rE. Only the ZParameter method shows consistently a larger value.
(a)

(b)

IV EXPERIMENTAL RESULTS

(c)

Fig. 5 shows the results of the application of extraction

methods to measured data. Extraction regions, where necessary,
were chosen according to the description of the appropriate
region in the corresponding publication.

(d)

(a)

Fig. 4: Results of the extraction methods applied to compact model data;

(a) GCS lE0 = 15 m, (b) GCS bE0 = 0.8 m, (c) IAF and (d)
Teledyne. The legend in (b) applies to all figures. The dashed line
in (c) and (d) indicates the model value.

(c)

The gm-method is not very well suited for InP DHBTs. Most
importantly, the correction by rB/f is often relevant due to the
comparatively low f. A further error source is the change of f
with bias and the fact that self-heating is not originally
compensated for. Finally, self-heating impacts the method even
when gm is taken from Re(Y21) due to the dependence of gmi on
T. The average relative error for this method is 41.2%.
The open-collector method fails completely for some
geometries and yields only moderately accurate results otherwise
with an average relative error of 38.2%. More detailed
investigations reveal that the main reason for the failure of this
method is its susceptibility to self-heating due to the typically
high thermal resistance values.
The Z-Parameter method also shows some deviations. A closer
examination of the equivalent circuit reveals that, even in the
limit of infinite IC, the term Re(Z12) is not equal to rE. The
correction proposed in [19] has been applied to the extraction
method and was found to improve the agreement with the model
value. The disadvantage of the correction is that it requires prior
knowledge about some equivalent circuit elements. The average
relative error is 41.6% without and 28% with correction.
The H-Parameter method in [12] shows the third best
average results with an average error of 30% and gives at least
reasonable starting values for further optimization in all cases.
An advantage is the unambiguous extraction region given by the
minimum value of the rE curve over bias. For measured data,
however, it may be impossible to find that minimum without
destroying the device.

(b)

(d)

Fig. 5: Results of the extraction methods applied to measured data. (a)

GCS lE0 = 15 m, (b) GCS bE0 = 0.8 m, (c) IAF and (d) Teledyne.
The legend in (b) applies to all figures.

The gm-method yields the same trends for model and

measurement, i.e. theory and practice agree well in this case.
The open-collector method proves unreliable, as expected
from the model-generated values and theory. Most often, the
results do not even show the correct trend with geometry.
The Z-Parameter method yields values very similar to those
for the model. No correction was applied, since not all necessary
values are known for all devices. Since the method tends to
overestimate the rE value, a correction would further improve the
result.
Similar to the gm-method on which it is based, the
H-Parameter method yields almost the same results when
applied to model and measurement.
As shown in Fig. 6, both the Z- and H-Parameter method are
weakly frequency dependent already in the range of 1 to 6 GHz,
more so for higher frequencies as the assumptions they are based
187

Table of Contents

on become invalid. The simulations in Fig. 6(b) indicate a similar

sensitivity to the selected frequency (but in opposite direction)
for both methods, while from measured data it appears that the
H-parameter method has a significantly larger dependence than
the Z-parameter method. In particular, the measured rE curve
shows a visible slope even at very low frequencies.
Finally, the two simultaneous methods suffer from the nonideal behavior of IB that is typical for III-V HBTs, which makes
the exact determination of the temperature dependence difficult
and impacts the precision of these methods. Where IB(T) is very
well described, however, the methods yield results in good
agreement with the corresponding compact model value.
(a)

VII REFERENCES
[1] M. Rodwell et al.,, "InP Bipolar ICs: Scaling Roadmaps, Frequency Limits,
Manufacturable Technologies," Proc. IEEE, vol. 96, no. 2, pp. 271-286, 2008.
[2] T. Kazior et al., Integration of III-V transistors and Si CMOS on silicon
substrates: A path to adaptable, reconfigurable, high performance circuits,
Proc. GomacTech, Orlando, pp. 23-26, 2011.
[3] H. Zirath, private communication, 2012.
[4] M. Iwamoto et al., "Large-signal HBT model with improved collector transit
time formulation for GaAs and InP technologies," IEEE Microwave
Symposium.Digest,, Philadelphia, PA, pp. 635-638, 2003.
[5] S. Nedeljkovic et al., "A Custom III-V Heterojunction Bipolar Transistor
Model-Discussion of the features of a custom III-V heterojunction bipolar
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(b)

[6] M. Schroter and A. Chakravorty, Compact hierarchical modeling of bipolar

transistors with HICUM, World Scientific, Singapore, 2010.
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Fig. 6: Frequency dependence of the extracted rE for the Z- and Hparameter method: (a) Experimental and (b) simulation results for
a transistor with AE0 = 0.8x15 m.

[11] S. Maas et al., Intermodulation in Heterojunction Bipolar Transistors, IEEE

Trans. Microw. Theory Tech., vol. 40, no. 3, pp. 442-448, 1992.
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2009.

V SUMMARY AND CONCLUSIONS

Seven different methods for extracting the emitter series
resistance rE of HBTs have been evaluated. The methods were
applied to fourteen transistors from three different foundries and
laboratories. The accuracy of the methods was assessed by
applying them to compact model generated data with known
values for rE.
Based on this study, two methods stand out. The first one is the
simultaneous method, which gives the by far most accurate
results when compared to the model and should be used when the
base current temperature behavior is well known and conforms to
the model. The second is the Z-Parameter method, which
provides accurate values for rE when a correction term is applied.
Which method is most preferable depends also somewhat on the
exact properties of the technology. Additionally, it has been
shown that the open-collector method, which is still used for
extracting rE of III-V HBTs (e.g. [23]) does not yield reliable
results at all and should not be employed.
These results should help improve the compact modeling of
InP DHBTs and thus aid in the development and deployment of
this promising mm-wave technology.

[13] C. Raya et al., Improving Parasitic Emitter Resistance Determination

Methods for Advanced SiGe:C HBT transistors, Proc. IEEEBipolar Circuits
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VI ACKNOWLEDGMENTS
The authors would like to thank Global Communication
Semiconductors (GCS), the Fraunhofer IAF and Teledyne
Scientific for their support and wafer fabrication. This work is
partially supported by the DFG Collaborative Research Center
912 Highly Adaptive Energy-Efficient Computing.

[21] T. Nakadai and K. Hashimoto, Measuring the Base Resistance of Bipolar

Transistors, Proc. IEEE Bipolar Circuits and Technology Meeting,
Minneapolis, MN, p. 200-203, 1991.
[22] J. Krause, M. Schrter, An evaluation of methods for determining the emitter
resistance of SiGe HBTs, to be published
[23] S. V. Cherepko, Improved Large-Signal Model and Model Extraction
Procedure for InGaP/GaAs HBTs under High-Current Operations, IEEE
Microwave Symposium.Digest,Vol. 2, pp. 671 - 674, 2001.

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Table of Contents

The Impact of Electro-Thermal Coupling on HBT Power Amplifiers

Matthew T. Ozalas
Keysight Technologies, Santa Rosa, CA
Abstract Thermal issues pose significant challenges for
todays RF power amplifier designs. Recently, layout-based
electro-thermal simulation tools have become widely
available across the industry. While these tools are most
commonly used for device-level reliability and lifetime
verification, electro-thermal simulation can also enable
engineers to gain new insight into the performance effects
that are brought on by cross-circuit thermal coupling in RF
power amplifiers. This paper describes the use of electrothermal simulation to understand, predict, and account for
cross-circuit thermal coupling in a commercial HBT power
amplifier. Specifically, electro-thermal analysis is used to
analyze how thermal coupling impacts gain compression and
low frequency memory effects.
Index Terms Electrothermal effects, heterojunction
bipolar transistors, memory effect, power amplifiers (PAs),
thermal analysis, Wireless LAN.

thermal resistance, leads to the concept of a thermal time

constant ( TH ). The thermal time constant therefore
describes the amount of time it takes to heat up a specified
volume of material to 63.2% of the steady state
temperature value.
Although the thermal response of a material is
distributed in nature, it can be approximated using several
thermal time constants associated with different
volumetric heat transfer mechanisms: for example, it may
be practical to model different time constants related to
heat spread at a device metal layer, an IC or wafer
substrate, and an external packaging material [2].
II. ELECTRO-THERMAL SIMULATION
The Keysight Heatwave Thermal Simulator [3],
integrated as part of Keysights Advanced Design System
[5], is used for this work to analyze the thermal
performance of a multi-stage power amplifier topology.
This electro-thermal simulator couples together a circuit
simulator with a layout-based thermal simulator and
iterates until a self-consistent electrical and thermal
solution is reached. To get the thermal solution, the
thermal conductivity and volumetric heat capacity for
each material in a cross-sectional stack-up must be
provided along with the material parameters and
dimensions so a full 3D model can be constructed.
In addition to steady-state junction-temperature based
reliability analysis, electro-thermal simulation enables
design engineers to analyze cross-circuit thermal
interactions which may impact the fundamental
performance of an amplifier. In the next section, two
commonly encountered circuit-level thermal performance
effects relevant to commercial power amplifier design are
analyzed and illustrated using electro-thermal simulation.
In both cases, the non-ideal performance of the amplifier
is caused by the difference in temperature between a
voltage reference device used to bias the circuit and a
bigger power device used to provide large-signal RF gain.

I. INTRODUCTION
In power amplifier circuits, excess DC and RF power
which is not transmitted to the load network is dissipated
as heat inside of the active device. To characterize the
extent to which dissipated power causes a temperature rise
in an active device, a thermal resistance (RTH) is defined
which converts dissipated power to temperature.
However, there are some additional complexities that
arise. First, thermal resistance is based on thermal
conductivity (), which is temperature dependent, so this
causes the thermal resistance factor to vary with
temperature. Second, the thermal resistance contains a
spreading term which describes how the heat spreads
laterally though the device and substrate [1].

TDEV = TAMB + RTH * PDISS

RTH =

L (W + 2t SUB )
1
,
ln E E
2 ( LE WE ) WE ( LE + 2t SUB )

(1)
LE > W E

(2)

The substrate spreading term in the thermal resistance

equation, shown in (2) for a rectangular emitter geometry,
implies that for closely coupled devices, heating can occur
by both self-heating, described above, and mutual heating
caused by heat spread from other nearby devices.
Because heat transfer does not happen instantaneously,
it is necessary to also consider the time it takes to heat up
a volume of material as part of the thermal network. This
is accomplished through the addition of a thermal
capacitance term (CTH), which, when combined with the

978-1-4799-3622-9/14/$31.00 2014 IEEE

III. POWER AMPLIFIER DESIGN CONSIDERATIONS

A. Circuit Topology and Analysis
To illustrate the performance effects of electro-thermal
coupling at the circuit level, a power amplifier was

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temperature of the mirror device, assuming that the

temperature of the RF amplifier device is held constant:
dI OUT dVbe MIR
dI OUT
=
*
dTMIR
dTMIR
dVbe MIR

dI OUT dVbeMIR
=
dTMIR
dTMIR

designed for a 2.4 GHz WLAN 802.11b/g application

using an HBT process provided by WIN Semiconductor.
Since bipolar devices have finite base current, it is
impractical to use a textbook current mirror bias topology
rather a standard HBT bias topology is used for this
work, shown in Fig 1. This bias topology relies on a
mirror device to set a Vbe-based reference voltage and a
helper device to source the corresponding base current
into the much larger multi-finger RF array [4].
This particular circuit topology is used to maintain
constant bias impedance regardless of RF drive, which
causes the DC current provided by the network to increase
with RF input power. This effect is useful for power
amplifier design because it allows for much lower DC
current at backed off RF powers while still providing a flat
gain response at higher power levels. This is due to gain
expansion which is triggered by the bias networks
response to an increase in DC current through the power
device resulting from a rectified RF input signal.
It is straightforward to analyze how this circuit is
sensitive to temperature differences between the RF
amplifier device and the bias device. From Fig. 1, an
expression for the output current in relation to the baseemitter voltage of the mirror device can be derived as:

dVbeMIR
mV .
1.1 D
dTMIR
C

I OUT

I OUT = I S [ RF ] e

(4)

TRF .
TMIR

(9)

In Fig 1, Iref is often implemented externally in a

CMOS control IC, and this current is ambient-temperature
compensated using a PTAT (Proportional to Absolute
Temperature) reference to flatten the static gain
characteristics of the PA due to the devices beta drop
over temperature. For high efficiency and small size, the
current through the HBT mirror device is designed to be
as low as possible. This means that the mirror device will
have a much lower current density than the RF amplifier
device, resulting in lower relative power dissipation and
less self-heating in the mirror device due to Rth. In this
example, Pdiss for each Qmir device was 5 mW, while
Pdiss for each Qrf device was 16.5 mW. Because of this
difference, the self-heating effects in Qmir are minimized
and the temperature of this device might instead be
dominated locally by mutual heating from the RF
amplifier device, Qrf. This means the relative placement
of the mirror-based reference device can impact the bias
current through the RF amplifier changing both the shape
of the gain compression curve and also the manifestation
of thermally induced memory effects.

Vbe MIR r [ RF ]
VT [ RF ] ( r [ RF ] + Rb )

(8)

If Qmir is hotter than Qrf, then VbeMIR will decrease,

causing a decrease in output current according to (7),(8).
For constant Iref, which implies a stable ambient
temperature for the module, (4) can be generalized to
show that the output current is proportional to the ratio of
temperature between Qrf and Qmir:

(3)

Rb I OUT
ln
VT [ RF ] 1 +
= Vbe MIR
r [ RF ] I S [ RF ]

VbeMIR *r [ RF ]

I S r [ RF ]
VT [ RF ] ( r [ RF ] +Rb )

(7)
e
VT [ RF ] ( r [ RF ] + Rb)

Since the diode voltage VbeMIR is proportional to the

2
intrinsic carrier concentration ni , the diode voltage
exhibits a strong CTAT (Complementary to Absolute
Temperature) characteristic. For this particular transistor,
the temperature dependence of VbeMIR was extracted at a
constant Iref with a value of approximately -1.1mV/C,
which is fairly typical for these types of HBT devices:

Fig. 1. Bias topology for WLAN RF Power Amplifier used to

maintain constant bias impedance for a variable RF drive level

VRb + VbeRF = VbeMIR

(6)

(5)

B. Layout and Experimental Simulation Approach

Referring to (5), Is represents the reverse saturation

current of the base-emitter diode of Qrf which is
proportional to the emitter area. It is also straightforward
to derive the dependence of the output current on the

To test the sensitivity of the circuit to physical layout,

two different IC layouts were created from an identical

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Fig. 2. Schematic of the full, three-stage HBT PA for WLAN

Fig. 4. Composite AM-AM and AM

M-PM response (top), and
resulting output spectral power (bottom
m) for the 3 stage WLAN
PA comparing self-heating and electro-tthermal simulations

Fig.3. Schematically identical layouts with ouutlined bias circuits

thermally coupled (left), decoupled (right) to the power device.
The decoupled case is slightly hotter overall, aas implied by (1,9).

input of the power amplifier to obsserve both hysteresis in

the gain curves that occurs at the riising and falling edges,
and the thermal drop that occurs during
d
the pulse as the
amplifier is heating up due to the ch
hange in beta.
The preceding analysis showed
d that the temperature
differences between the reference device
d
and the amplifier
device lead to changes in bias current
c
which impacts
steady state performance; now, the concept is extended to
pled bias configuration
show how a tight thermally-coup
can be used to minimize memory efffects, shown in Fig 5.
To isolate the thermal effects from other memory
sources such as bias network, the pulse was set up at a
very low frequency relative to the modulation frequency.
mpossible to include a
In many cases, it is difficult or im
complex thermal network in a statiic device model (many
models only include one or two th
hermal poles), so in the
case of a simplified thermal netwo
ork, the model will not
react in a transient manner at low
w frequency timescales.
This is illustrated in Fig. 6, which sh
hows the beta drop that
occurs in the device due to the therm
mal time constant when
simulated with a pulsed bias forr a static self-heating
device model verses a full electro-th
hermal simulation.
For the full amplifier, a simu
ulation was set up to
stimulate the PA with a pulsed inpu
ut signal, and hysteresis
in the gain response was plotted
d for the upramp and
downramp conditions of the pulsse. As expected, the
electro-thermal simulation resultss do show additional
hysterisis for the thermally decoupled bias case, indicating
that there is a higher degree of mem
mory effects when there
is less thermal coupling between th
he bias network and RF
amplifier device.

schematic, which is a full WLAN PA, shoown in Figs. 2, 3.

In one case, the bias devices were ttightly thermally
coupled to the RF devices, in the otheer case, the bias
devices were thermally decoupled from thhe RF devices to
see the effects that different amounts of tthermal coupling
would have on the overall circuit perform
mance. Electrothermal simulation was run for both casees and compared
to a simulation which considered only thhe self-heating of
each device individually through static thermal network
included in the ADS-HBT (AHBT) devicee model.
As predicted by the preceding analyysis, the electrothermal simulation shows that the temperaature coupling of
the bias device to the RF amplifier array impacts the gain
and phase response of the overall amplifieer, causing lower
RF gain and a less desirable sooft compression
characteristic which degrades the adjacennt channel output
spectrum when subjected to 802.11g moodulation. Both
effects are due to the bias current offseet as a result of
additional thermal coupling between the bias device and
the amplifier. The simple self-heating siimulation clearly
represents the perfectly temperature-decooupled bias case,
which is not possible to replicate in a pracctical IC layout.
C. Thermally Induced Memory Effects
A circuit-envelope electro-thermal simuulation was done
on the two different IC layouts in Fig. 3 too show the extent
to which the temperature difference betweeen Qmir and Qrf
contributes to memory effects. To quantiify the difference
in memory effects, a pulsed RF signal wass applied to the

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Fig. 5. Visualizing dynamic memory effects ddue to temperature

mismatch between devices when subjected to aan RF power burst.

Fig. 8. Simulated hysteresis in AM-AM

M response due to power
burst, three different cases normalized for
f relative comparison.

IV. CONCLUSIO
ON
Accounting for cross-circuit theermal coupling can be
critical in RF power amplifier design
d
to achieve flat
compression characteristics and min
nimize memory effects.
In this work, electro-thermal sim
mulation was used to
illustrate the extent to which cross-circuit thermal
coupling impacted the gain compression, output spectrum,
y used WLAN HBT PA
and gain hysteresis for a commonly
topology. Self-heating results werre compared to electrothermal results for two schematicallly identical IC layouts
with different degrees of thermal co
oupling between critical
devices. This showed that depend
ding on layout, crosscircuit coupling caused the gain of the PA to drop by 1-2
de by 0.5-1 dB at low
dB, the output spectrum to degrad
powers, and hysteresis to appear on
n the order of 0.2-0.45
dB relative to zero for the static selff-heating case.

Fig. 6. Transient response showing beta drop due to self-heating

of a single device stimulated with a transiennt bias pulse, for a
static self-heating device model vs. electro-tthermal simulation
(done separately across different time scaales with implied
envelope highlighted). The static model hhas a single-timeconstant thermal network while the electro-tthermal simulation
has a more complex thermal response duue to the thermal
simulator solving the heat equation in the full 33-D structure.

ACKNOWLEDGMENT

Thanks to Pete Zampardi at RFMD

D for technical guidance
and WIN Semiconductor for provid
ding PDKs and models.
REFERENCES
S

[1] P. Zampardi, A Study of New Base Pushout Effects in

P
dissertation, Dept.
Modern Bipolar Transistors, Ph.D.
Elect. Eng., UCLA, Los Angeles,,C
CA, 1997.
[2] M. Busani, R. Menozzi, M. Bo
orgarino, and F. Fantini,
Dynamic Thermal Characterizaation and Modeling of
Packaged AlGaAs/GaAs HBTs, IEEE Trans. Components
pp. 352-359, June 2000.
& Packaging Tech., vol. 23 no. 2 ,p
[3] R. Gillon, P. Joris, H. Oprin
ns, B. Vandevelde, A.
Srinivasan, and R. Chandra Practtical Chip-centric electrothermal simulations THERMIN
NIC, ISBN 978-1-42443365-0 , pp. 220-223, Sept 2008.
hip-centric electro-thermal
[4] C. Lin, and Y. Hsu Practical Ch
simulations IEEE GaAs and Otther Semiconductor App.
Symposium., pp. 489-492, Oct 2005.
m ADS 2014
[5] Keysight Advanced Design System

Fig. 7. Transient electro-thermal simulatioon results showing

the temperature rise of Qrf and Qmir due tto an input power
pulse, for thermally decoupled and thermally ccoupled layouts.

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Analysis of the Influence of Layout and Technology Parameters on

the Thermal Impedance of GaAs HBT/BiFET Using a HighlyEfficient Tool
A. Magnani1, V. dAlessandro1, L. Codecasa2, P. J. Zampardi3, B. Moser3, and N. Rinaldi1
1

Department of Electrical Engineering and Information Technology, University Federico II, via Claudio 21,
80125 Naples, Italy. Phone: +39-081-7683145.
2
Department of Electronics, Information, and Bioengineering, Politecnico di Milano, 20133 Milan, Italy.
3
RF Micro Devices, Inc., 7628 30700 Russell Ranch Road, Westlake Village, CA 91362, USA (P. J.
Zampardi), and 7628 Thorndike Rd. Greensboro, NC 27409-9421, USA (B. Moser).
behavior of the devices even though its importance for
linearity considerations has been shown in some works [3][5].
In this work, we take advantage of our highly-efficient
thermal tool that allows drastically reducing the CPU time
and memory storage compared to standard numerical
programs. The tool is adopted to evaluate the influence of the
key layout and technology parameters on the thermal
impedance of state-of-the-art GaAs HBTs. It is shown that
simulation results can allow device designers to better
understand and face the trade-off between electrical and
thermal performance.

Abstract This work is focused on the analysis of the

dynamic thermal behavior of advanced GaAs HBTs, with
particular emphasis on BiFET technologies, where pHEMTs are
integrated below the conventional bipolar device. A novel
highly-efficient tool is employed to determine the influence on
the thermal impedance of the key layout and technology
features, namely, size of the emitter and base-collector mesa,
pHEMT layers, and metallization architecture. The tool relies
on the multi-point moment matching algorithm, and allows
CPU time and memory storage much lower than those required
by commercially-available numerical software packages.
Index Terms Heterojunction bipolar transistors, multipoint moment matching, numerical simulations, thermal
impedance, thermal resistance.

II. DEVICES UNDER TEST

I. INTRODUCTION

The devices under test (DUTs) are single-finger HBTs

manufactured by RFMD with BiFET and HBT-only
processes [1]. In BiFET devices, the additional pHEMT
layers (that include an InGaP etch-stop and InGaAs channel)
are located beneath the HBT, as shown in Fig. 1, while in the
HBT-only counterparts they are absent. It is worth noting that
materials constituting pHEMT layers suffer from low thermal
conductivity compared to GaAs. Both transistor categories
are mesa isolated. The DUTs are contacted using two
different styles, one involving first metal (0.74 m Au), and
another first metal with top metal (TM, 2.74 m Au).

While GaAs heterojunction bipolar transistors (HBTs)

have been the technology of choice for handset power
applications since the mid 1990s [1], more advanced
processes include the co-integration of FET devices. Adding
pHEMT devices (forming a BiFET process) enables power
amplifiers with highly functional bias circuits and
implementation of RF switching functions, such as stage bypassing and mode select, on a single die. At the same time,
designs have been pushed to be smaller (increasing the power
density) and meet more stringent linearity requirements,
where the dynamic thermal behavior becomes more relevant.
As a result, it is important to (1) understand how process
choices (such as layer structures and device geometries)
affect the dynamic thermal performance of the transistors and
(2) provide guidance to device and modeling engineers on
which transistor features impact such a performance.
Most studies for GaAs HBTs have been limited to the
analysis of the impact of metallization or special processes on
the thermal resistance. Scaling of the thermal resistance based
on device geometry, a necessity for compact model
generation, has received attention for Si [2] but not for GaAs.
Prior works on GaAs have always used the emitter area for
scaling; however, none of them has discussed the thermal
impedance which fully characterize the dynamic thermal

978-1-4799-3622-9/14/$31.00 2014 IEEE

WE
GaAs base

LE

emitter

GaAs collector

heat
source

B-E
junction

GaAs subcollector
pHEMT layers
GaAs substrate
TB=300 K

Fig. 1. Cross-section of a BiFET HBT under test evidencing the

effective emitter width WE and length LE, as well as the heat source
geometry.

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Table of Contents

III. SIMULATION APPROACH

H

3D data input

Heat conduction within the DUTs is cumbersome to

metrical structure.
describe because of their complex 3-D geom
A standard approach using finite elementt analysis (FEM)
results in a mesh consisting of millions of elements with
grossly different dimensions; moreover, seecond- or higherorder FEM elements are needed to acchieve acceptable
simulation accuracy, thus introducing millions of degrees of
freedom in the FEM model. The reesulting transient
simulations would require many hours of C
CPU time and tens
of GBs of memory storage, even for simple cases (e.g., the
evaluation of the thermal response to a poweer step).
To alleviate this computational burden, w
we used the highlyefficient tool described in the flowchart repoorted in Fig. 2 and
denoted as FANTASTIC (FAst Novel T
Thermal Analysis
Simulation Tool for Integrated Circuits) [6]]. As can be seen,
the input is a tetrahedral mesh representiing the structure,
which can be imported from any softwaare with meshing
capabilities. From this mesh, the mass matriix M, the stiffness
matrix K, and the power density vector g oof a second-order
FEM model are efficiently constructed. Thhese data are used
to generate a dynamic compact thermal model (DCTM)
through an enhanced formulation of the muulti-point moment
matching (MPMM) algorithm of Codecassa et al. [7], [8].
Using this approach, a small number m of poositive real values
1>2>>m of the complex frequencyy are analytically
determined [9] as a function of the relativee error allowed by
the DCTM. The FEM model in the coomplex frequency
domain is then solved for each of these ffrequency values.
Thus, the equations
(1)
( i M + K ) v i = g

Mesh
Materials
Boundary conditions
FEM discrretization

Multi Point
Frequencies estimation
Moment Matching Moment soolver
Compact model

SPICE nettlist
Full 3D tem
mperature maps

Fig. 2. Schematic flowchart of the proposeed MPMM-based tool.

Fig. 1 shows that the thickness of the heat source is equal

med to be fully depleted)
to that of the collector (which is assum
while the horizontal size is slightly lower than the emitter
d
by applying a
one. The thermal impedance ZTH is determined
unity power step at the time t=0, and averaging the evaluated
n of the emitter onto the
temperature field over the projection
base-emitter junction; the thermal resistance RTH is the
steady-state value of ZTH. Widely acccepted literature values
were employed for the materiall parameters (thermal
conductivity k, mass density , and sp
pecific heat c), including
binary and ternary alloys (e.g., [10
0], [11]); in particular,
k=0.4410-4 W/mK, =5.3210-15 Kg/m3, c=322 J/KgK
were chosen for GaAs. A commerccial FEM program was
used to generate the 3-D mesh for eaach device; the top-view
of the mesh corresponding to the WELE=23.5 m2 BiFET
DUT is illustrated in Fig. 3. The num
mber of tetrahedra for an
HBT spans from 106 (for the shorrtest-emitter devices) to
1.5106 (for the longest). A ZTH com
mputation by using a fine
discretization for the time axis was found
f
to require 20 mins
(only to generate the DCTM the acctual simulation lasts 1 s)
and 1 GB RAM on a PC with a i7-3820QM (quad core)
2.70 GHz CPU and 32 GB RAM; conversely,
c
more than 8
hours and approximately 10 GB RAM
R
are needed when
resorting to a traditional FEM solver.

are solved for vi, with i=1, , m. This is efffectively achieved

by adopting a conjugate-gradient iterative ssolver with proper
Choleski incomplete preconditioning, annd by using an
estimate determined from the solutions tto already-solved
equations as an initial guess for the solution to each system of
equations (1). The CPU time and m
memory storage
requirements of the MPMM tool are prim
marily due to the
solutions to (1), and can be an order of maggnitude lower than
those of a conventional FEM model. Veectors vi are then
elaborated for determining the space used too project the FEM
model and generate the DCTM, which is rrepresented by an
equivalent SPICE-like RC thermal circuuit with a small
number m of RC pairs [6]. As a result, trannsient simulations
can be performed at low computationaal cost for any
dissipated power waveform of practiccal interest. For
example, the thermal response to a pow
wer step usually
involves less than 1 s of CPU time and neegligible memory
storage. In a post-processing stage, usiing the transient
solution of the DCTM, the whole space-tim
me distribution of
the temperature and heat flux can be alsoo computed, thus
allowing an in-depth investigation of the heat propagation
within the device.

(a)

(b)

Fig. 3. (a) Top-view of the mesh correspo

onding to the BiFET device
with WELE=23.5 m2, and (b) magniffication of the mesa region,
as obtained by a commercial FEM simulat
ator.

IV. RESULTS AND DISSCUSSION

Fig. 4 shows good matching betweeen the experimental RTH
values extracted by resorting to thee procedure in [12] and
those computed by FANTASTIC forr BiFET transistors with
WE=2 m as a function of LE.

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as computed by the FANTASTIC post-processing. The heat

propagation analyzed through the observation of various
temperature maps taken at time instants between A and B
can be described as follows. At point A the heat is still mostly
confined within the mesa; afterward, it follows two paths to
reach the backside metal (assumed to be an ideal thermal
ground); in particular,
the downward heat flow crosses the pHEMT layers and
the GaAs substrate;
the upward heat spreads into the whole metallization
(including the pads), and then enters the substrate through
a thin SiN layer on which the pads are sitting; this means
that a parasitic thermal shunt effect takes place, which
contributes to mitigate the junction temperature.
At point B, the temperature field is close to the steady-state
conditions. It can be seen that the mesa is still much hotter
than the surrounding regions.
Fig. 7 compares the ZTH of BiFET DUTs with alternative
variants, namely, HBT-only devices without pHEMT layers,
TM structures, and BiFET with base-collector mesa reduced
in width and length (in particular, the top mesa layer is
shrunk by 1.7 and 1.3 m along WE and LE, respectively), the
geometry of the heat source being held fixed. An inspection
of the curves reveals that (1) in BiFET HBTs the heat
flowing to the backside hits the pHEMT layers after 0.1 s;
(2) after that time, the impedance for the HBT-only DUTs
can be reviewed as a downward-shifted version of the BiFET
one. In particular, RTH reduces by 5.5-6.5% regardless of the
emitter length; (3) as far as TM transistors are concerned, it
was found that RTH decreases by 7-9% in comparison to the
BiFET counterparts, thanks to the improved metal path for
the upward heat; (4) merely shrinking the base-collector mesa
increases RTH by about 7% for the short-emitter device, with
little impact on the longer one.
The above analyses confirm that FANTASTIC can provide
simple guidance on what device feature the ZTH should scale
with. In particular, the size of the base-collector mesa gives
rise to a fundamental trade-off between thermal and electrical
performance; for example, undercutting the mesa [13]
reduces the base-collector capacitance, but leads to an
increase in ZTH that can offset the electrical benefit. Important
information is gained on the thermal performance sensitivity
to emitter size and heat source geometry.

Thermal resistance RTH [K/W]

3000
experimental
simulated

2500
2000
1500
1000
W E=2 m

500
0

10

15

20

25

30

35

40

45

Emitter length LE [m]

Fig. 4. Simulated (open squares) and experimental (filled) thermal

resistance RTH vs. emitter length LE for devices sharing WE=2 m.

Fig. 5 shows ZTH vs. time of BiFET HBTs with WE=2 m

and various LE; a comparison with a few curves obtained for
WE=1.6 m transistors evidences that the thermal
performance degradation induced by the smaller mesa and
heat source is exacerbated for shorter emitters. The figure
also illustrates that an unacceptable inaccuracy arises when
describing ZTH with a single RC pair; by making use of an inhouse identification routine, it was found that a good
representation can be obtained by using at least 7-8 pairs.
Thermal impedance ZTH [K/W]

3500
3000
2500

W E=2 m
W E=1.6 m

LE=3.5 m

LE=6.5 m

2000
1500

LE=10.5 m
LE=20.5 m

1000

LE=30.5 m

500

LE=40.5 m

0
10-1110-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1

Time [s]

Fig. 5. Simulated thermal impedance ZTH vs. time for transistors

with WE=2 m and various lengths LE (solid lines), along with the
curves corresponding to WE=1.6 m devices with LE=3.5 and
40.5 m (dashed). Also shown for the case LE=3.5 m is the ZTH
that would be obtained by using a single-pole representation with an
optimized thermal capacitance (dot-dashed), and a Foster network
with 7 RC pairs (dotted). Symbols indicated with A and B identify
the operating points at which the temperature maps shown in Fig. 6
are taken.

V. CONCLUSION
In this paper, the dynamic thermal behavior of state-of-theart GaAs HBTs has been analyzed by means of an advanced
tool relying on the multi-point moment matching approach,
which requires CPU time and memory storage drastically
lower than those corresponding to widely-used commercial
programs. The impact of various layout and technology
parameters has been quantified, namely, emitter size, basecollector mesa, pHEMT layers, and metallization style. In
addition, a clear insight into the heat propagation within the

Fig. 6 depicts the distribution of the temperature rise over

ambient normalized to the dissipated power (i.e., the ZTH
field) for the active region of the 23.5 m2 HBT at the time
instants A and B indicated in Fig. 5, corresponding to 0.1 s
and 1 ms after the application of the power step, respectively,

195

Table of Contents

transistor structure has been given through the analysis of

temperature maps captured in a post-processing stage. It is
concluded that the proposed tool can be successfully used to
support the device designer in dealing with the critical tradeoff between thermal and electrical performance.

REFERENCES
[1]
[2]

[3]
[4]

[5]

B
[6]

[7]
Fig. 6. Field of the temperature rise above ambient normalized to the
dissipated power [K/W] over a section vertically crossing the center
of the heat source, as determined by FANTASTIC for the BiFET
device with WELE=23.5 m2 at the operating points A and B
indicated in Fig. 5.

[8]

Thermal impedance ZTH [K/W]

3500

2500

BiFET
HBT-only
TM
shrunk mesa

2000

LE=3.5 m

3000

[9]
[10]

1500

[11]

LE=20.5 m

[12]

1000
500

W E=2 m

[13]

0
10-1110-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1

Time [s]

Fig. 7. Simulated evolution of the thermal impedance ZTH for

devices with WE=2 m and emitter lengths LE=3.5 and 20.5 m:
comparison between BiFET transistors (solid lines), devices without
pHEMT layers (dashed), TM HBTs (dotted), and DUTs with shrunk
base-collector mesa (dot-dashed).

196

M. Fresina, Trends in GaAs HBTs for wireless and RF, in

Proc. IEEE BCTM, 2011, pp. 150153.
D. J. Walkey, T. J. Smy, D. Marchesan, H. Tran, and M.
Schrter, A scalable thermal model for trench isolated bipolar
devices, Solid-State Electronics, vol. 44, no. 8, pp. 1373
1379, 2000.
http://www.home.agilent.com/upload/cmc_upload/All/6Feb20
14Webcast.pdf
K. Lu, P. M. McIntosh, C. M. Snowden, and R. D. Pollard,
Low-frequency dispersion and its influence on the
intermodulation performance of AlGaAs/GaAs HBTs, in
Proc. IEEE MTT-S Digest, 1996, pp. 13731376.
N. G. Constantin, K. H. Kwok, H. Shao, C. Cismaru, and P. J.
Zampardi, Formulations and a computer-aided test method
for the estimation of IMD levels in an envelope feedback RFIC
power amplifier, IEEE Trans. Computer-Aided Design of
Integrated Circuits and Systems, vol. 31, no. 12, pp. 1881
1893, 2012.
L. Codecasa, V. dAlessandro, A. Magnani, N. Rinaldi, and P.
J. Zampardi, FAst Novel Thermal Analysis Simulation Tool
for Integrated Circuits (FANTASTIC), in Proc. IEEE
THERMINIC, 2014.
L. Codecasa, D. DAmore, and P. Maffezzoni, Compact
modeling of electrical devices for electrothermal analysis,
IEEE Trans. Circuits and Systems I: Fund. Theory and
Applications, vol. 50, no. 4, pp. 465476, 2003.
L. Codecasa, D. DAmore, P. Maffezzoni, and W. Batty,
Analytical multipoint moment matching reduction of
distributed thermal networks, IEEE Trans. Components and
Packaging Technologies, vol. 27, no. 1, pp. 8795, 2004.
L. Codecasa, D. DAmore, and P. Maffezzoni, Parameters for
multipoint moment matching reduction of discretized thermal
networks, in Proc. THERMINIC, 2002, pp. 151154.
R. Anholt, HBT thermal element design using an electrothermal simulator, Solid-State Electronics, vol. 42, no. 5, pp.
857864, 1998.
V. Palankovski and R. Quay, Analysis and simulation of
heterostructure devices, Springer, 2004.
D. E. Dawson, A. K. Gupta, and M. L. Salib, CW
measurements of HBT thermal resistance, IEEE Trans.
Electron Devices, vol. 39, no. 10, pp. 22352239, 1992.
W. Liu, D. Hill, H.-F. Chau, J. Sweder, T. Nagle, and J.
Delaney, Laterally etched undercut (LEU) technique to
reduce base-collector capacitances in heterojunction bipolar
transistors, in Proc. IEEE GaAs IC Symposium, 1995, pp.
167170.

Table of Contents

Evaluation and Modeling of Voltage Stress-Induced Hot Carrier

Effects in High-Speed SiGe HBTs
Grazia Sassoa, Cristell Maneuxb, Josef Boeckc, Vincenzo dAlessandroa, Klaus Aufingerc,
Thomas Zimmerb, and Niccol Rinaldia
a

Department of Electrical Engineering and Information Technology, University of Naples Federico II,
Via Claudio 21, 80125, Naples, Italy, grazia.sasso@unina.it
b
IMS, University of Bordeaux, Bordeaux, France c Infineon Technologies AG, Neubiberg, Germany

Abstract

Hot-carrier degradation analysis and

modeling of 240/380 GHz fT/fMAX SiGe HBTs are addressed.
A proper stress bias setup is proposed, suitable for the
evaluation of RF performance during stress interruption.
The impact of stress conditions, lateral scaling and device
layout is discussed. An analytical model is proposed, which
predicts base current degradation, including its dependence
upon stress voltage, stress duration, and emitter geometry,
and contributes to understand the physical background of
the phenomena.
Index Terms Degradation models, hot carrier effects,
reliability, reverse EB stress, RF devices, SiGe HBT.

analytical formulation is introduced, which is suited to

predict the amount of base current degradation for
different emitter geometries as a function of stress
condition and duration. Besides, a stress bias setup is
proposed to determine the RF performance during stress
breaks.
II. TECHNOLOGY AND EXPERIMENTAL PROCEDURE
Measurements were performed on SiGe:C NPN HBTs
manufactured by Infineon Technologies. HBTs feature
peak cut-off and oscillation frequencies fT/fMAX of 240/380
GHz [5]. Table I summarizes the stressed devices with
their effective emitter area AE and applied stress voltage
VEB-stress. Single and parallel connected (N=1-9) HBTs
with several combinations of emitter width/length WE/LE
were available, which allowed the analysis of different
lateral scaling levels. In addition to HBTs with single
contacts for emitter, base, and collector (BEC
configuration), one device with two base contacts (BEBC)
was examined. The stressed and unstressed measurements
were conducted on wafer at a temperature of 300 K. Most
of the samples were stressed at VEB-stress=3.5 V. This
condition, rather extreme and very far from the usual
device biasing, accelerates the degradation, thereby
allowing the estimation of the time-to-failure (TTF) of
device and of integrated-circuit fabrication technology
within a reasonable measurement time. In order to
examine the AC performance reliability as well, RF
devices with ground-signal-ground (GSG) pads
configuration were tested with a proper setup.
Two different reverse-bias stressing methods are
traditionally used for reverse EB stress, namely, opencollector (OC) and forward collector (FC) stress, in which
the collector terminal is left open (or shorted to the base
TABLE I. HBTS LAYOUT AND STRESS BIAS

I. INTRODUCTION
Silicon-germanium (SiGe) heterojunction bipolar
transistors (HBTs) experienced a huge improvement in
speed and noise performance thanks to device shrinking
[1], thus becoming the most promising competitors of
compound semiconductor devices for millimeter wave
applications [2]. Unfortunately, this comes at the cost of
higher electric fields and current densities, which may
cause performance degradation if not appropriately
accounted for in the device design [3]. In BiCMOS
circuits where bipolar transistors and CMOS gates are
frequently interfaced, HBTs can be subject to a reverse
base-emitter bias when CMOS transistors are switched
during circuit operation. The reverse bias stress can entail
a performance degradation due to damage induced by hot
carriers. Degradation might in turn jeopardize speed and
long-time reliability of the circuit and put restrictions on
both transistor and circuit design [4]. Hot carrier damage
is typically categorized into reverse emitter-base (EB)
stress, forward stress, and mixed-mode (MM) stress.
Much effort has been made to investigate the responses of
SiGe HBTs under stress conditions [3]. However,
available studies on state-of-the-art HBTs mainly focus on
MM stress effects; moreover, when reverse EB stress is
addressed, it is achieved by standard techniques that do
not allow a correct monitoring of the RF performance
during stress.
The aim of this work is to contribute to the current
understanding by reporting a detailed investigation of the
degradation induced on the DC and RF performance of
SiGe HBTs by the reverse EB stress. In addition, an

978-1-4799-3622-9/14/$31.00 2014 IEEE

AE=Nx(WExLE) [m2]
9x(0.13x0.93)
9x(0.15x0.93)
3x(0.13x2.73)
3x(0.13x2.73)
1x(0.13x9.93)
1x(0.23x9.93)

197

Configuration
BEC
BEC
BEC
BEBC
BEC
BEC

VEB-stress [V]
3.5
3.5
3.5
3.5
2.5
3.0

VCB [V]
3.5
2.0
3.5
3.5
2.5
3.0

Table of Contents

employed instrumentation. On the other hand, during

experiments the stress is periodically interrupted for
monitoring any changes in device characteristics, and
therefore the OC stress technique would require to move
RF probes during test, thus affecting the RF measurements
accuracy. Here we propose an alternative approach, in
which the stress voltage VEB-stress is applied at the BE
junction with VCE=0 (i.e., VEB=VCB>0). This bias
condition was verified to be equivalent to the OC stress
bias, since the collector current is negligible during stress,
and an uncontrolled forward biasing of the substratecollector junction is avoided. Moreover, it allows the
monitoring of the RF performance during stress
interruptions without any mechanical movement in the
experimental setup. The validity of the method was
proved by comparing stress conditions and degradation
effects for two HBTs with similar sizes stressed at VEBstress=3.5 V with VCE=0 (i.e., VCB=3.5 V) and VCB=2 V,
respectively. When VCE=0 V, IC is negligible (7 A) and
the stress current is IE-stress=-(IB+IC)-IB=120 A, mainly
due to BBT effects. However, when VCB is reduced (i.e.,
VC<0) in the attempt to reach the condition VCB=0 V, the
resulting (negative) IC strongly increases (-68 mA), due to
the forward biasing of the substrate-collector junction.
Nevertheless, the current contributing to the stress is
unchanged in the two instances, as demonstrated by the
comparison of the degradation effects as a function of the
stress duration t depicted in Fig. 1. The slight discrepancy
in the DC and RF degradation between the two devices
can be ascribed to the small difference in their aspect ratio.

VBC=0) and forward biased (VBC>0), respectively [4].

Damage is caused by hot holes, created by band-to-band
tunneling (BBT) in the base-emitter junction during OC
stressing, and by hot holes and electrons, injected from the
collector into the base, in FC stressing. Once accelerated
by the high electric field between emitter and extrinsic
base, hot carriers generate interface traps at the Si/SiO2
interface, and lead to an increase in the recombination
component of the base current IB, resulting in degradation
of the current gain =IC/IB while the collector current IC
remains unchanged. Moreover, if energetic enough, hot
carriers surmount the Si/SiO2 barrier giving rise to an
increase in fixed oxide charge density and oxide trap
charge density. However, standard reverse EB stress
methods are not exploitable when AC measurements are
to be performed. Since in the GSG RF configuration the
emitter is usually shorted to substrate and grounded
VE=VS=0, the VBC0 bias condition combined to VEB>0
causes an uncontrolled forward biasing of the substratecollector junction and entails the current compliance of the

Base current degradation IB(t) [A]

10

2.0

9x(0.13x0.93) - VEB-stress=3.5 V, VCB=2.0V

9x(0.15x0.93) - VEB-stress=VCB=3.5 V

1.5

-7

IB(VBE=0.7 V)

10

1.0

IB(VBE=0.5 V)
0.5
-8

10

fT
1

10

100

Stress time t [s]

0.0
1000

Decrease of maximum cut-off frequency fT [%]

-6

III. DEGRADATION RESULTS AND MODELING

The effect of the reverse EB stress is firstly illustrated in
Fig. 2, which shows the degradation in gain measured at
VBE=0.7 V and VCE=1.2 V under 3.5 V reverse stress vs.
stress duration. Fig. 2 also depicts corresponding stress
current densities JE, revealing a slight increase during a
stress test of an HBT at a given VEB-stress. This small
increase in the stress current may be due to trap-assisted
tunneling (TAT) rather than to BBT. The base current
increment IB(t)=IB(t)-IB(0) as a function of the stress time
is depicted in Fig. 3 with its corresponding ideality factor
nR extracted by using IB(t)=ISR(t)exp[(qVBE)/(nRkT)].
The excess base current to emitter perimeter PE ratio is
almost comparable for different devices, suggesting that
the interface traps generated by the stress are mostly
located along the perimeter of the emitter, as expected.
The ideality factor extracted around VBE=0.7 V slightly
exceeds two and mildly decreases with stress time. This
could be explained assuming that a Shockley-Read-Hall
(SRH) recombination mechanism via midgap traps in the
BE junction is responsible for the observed leakage,

Fig. 1. Base current (left) and maximum cut-off frequency (right)

degradation at VCE=1.2 V as a function of the stress duration for
two geometries stressed at VEB-stress=3.5 V with VCB= 2.0 V (dashed
lines) and VCB= 3.5 V (full lines).
2x10

9x(0.13x0.93) - BEC
3x(0.13x2.73) - BEC
3x(0.13x2.73) - BEBC

90
JE-stress

80

10
70

VEB-stress=3.5 V
10

100

Stress time t [s]

60
1

-4

-4

Stress current density JE-stress [A/m ]

Current gain decrease [%]

100

1000

Fig. 2. Current gain reduction at VBE=0.7 V and VCE=1.2 V (left)

and stress current density (right) vs. stress time for several
geometries under stress condition of VEB-stress=3.5 V.

198

Table of Contents

Base current degradation IB(t) [A]

linear dependence S=VEB-stress/5 was derived to account

for variation of the surface potential with VEB-stress. Thus,
the model obtained by combining (1) and (2) describes the
degradation due to generation of interface traps and
includes, additionally, the generation of charge in the

10

VEB-stress=3.5 V

9x(0.13x0.93) - BEC
9x(0.15x0.93) - BEC
3x(0.13x2.73) - BEC
3x(0.13x2.73) - BEBC

-6

I B

Excess base current ideality factor nR

whereas nR values extracted at different VBE values after

1000s of stress and depicted in Fig. 4 indicate the
existence of tunneling, perhaps through inherent trap
states around the emitter perimeter (TAT), which
dominates at very low injection levels [4]. Fig. 4 also
depicts a Gummel plot before and after 1000s of stress. In
the high bias region, IB shows no change and the highinjection is not affected by degradation; the collector
current IC is unchanged. Besides currents, also opencollector and open-emitter breakdown voltages (BVCEO
and BVCBO) were monitored during tests and verified to
follow the same variation rate as IB and IC, respectively,
that is, BVCBO was unaffected by stress. AC performance
was determined as well during experiments; junction
capacitances, AC current gain H21, fT and fMAX were
extracted from the scattering parameters S. Despite the
very high stress condition applied, no significant variation
was detected for RF parameters (with the exception of
low-frequency values of H21, which follow the
degradation of DC performance), as can be seen from
Fig. 1 and Fig. 5. Degradation effects reported in Figs. 2-4
refer to two DUTs differing only in the contact layout
configuration and HBTs with comparable total AE but
different number of transistors N. These figures confirm
that the two base contact BEBC device has the same
amount of degradation of the single contacts BEC device,
being the differences simply ascribable to the
experimental scattering data, and no influence of the
number of transistors was detected.
Next, a new empirical formulation is proposed to model
the base current degradation as a function of stress
duration and stress voltage. First, the model proposed in
[6] for a given stress condition was modified to include
the dependence upon the emitter perimeter PE, leading to

3
10

10

-7

VBE=0.7 V

nR

-8

10

2
1000

100

Stress time t [s]

Fig. 3. Excess base current (left) and its ideality factor (right)
measured at VBE=0.7 V and VCE=1.2 V vs. stress time for several
geometries under stress condition of VEB-stress=3.5 V.
10

10

-3

10

-6

10
1.0

-9

Before stress (t=0s)

After stress (t=1000s)

tstress = 1000 s

3.2

Collector and base current IC ,IB [A]

Excess base current ideality factor nR

3.4

IC

3.0
2.8

IB

2.6
9x(0.13x0.93) - BEC
9x(0.15x0.93) - BEC
3x(0.13x2.73) - BEC
3x(0.13x2.73) - BEBC

2.4
2.2
0.5

0.6

0.7

0.8

Base-emitter voltage VBE

0.9

Fig. 4. Excess base current ideality factor extracted after 1000s of

VEB-stress=3.5 V for several geometries (left) and collector and base
current before and after 1000s of VEB-stress=3.5 V for the HBT
9x(0.13x0.93) (right) vs. VBE measured at VCE=1.2 V.

t
q VBE
I B ( t ) = PE ISRP exp
(1)
.
nR k T
t0
At a fixed VBE and VEB-stress, a unique value of nR has been
considered for all the DUTs, obtained as the mean value
over various devices (see Fig. 4), and single values of the
stress time power factor and of ISRP were extracted for
all the stressed HBTs. Afterwards, the model was
extended to include the dependence upon VEB-stress. The
ISRP pre-exponential factor accounts for the dependence on
VBE-stress as well, and can be written as
q S
ISRP = ISRP0 exp
(2)
,
k T
where S is the variation of the surface potential induced
by the charge trapped in the oxide [7]. Using the
experimental results obtained at VEB-stress= 2.5 and 3.0 V
and outlined in Table I, the stress time power factor was
extracted as a function of stress voltage and the simple

21
3x(0.13x2.73) - BEBC

15

AC current gain |H21| [dB]

|S21|

17

13

15

11

13
11
9

Scattering parameter |S21| [dB]

|H21|

19

9
Before stress (t=0s)
After stress (t=1000s)
1E8

1E9

Frequency f [Hz]

VEB-stress=3.5 V
1E10

Fig. 5. Magnitude of AC current gain and S21 of a SiGe HBT

measured at VBE=0.88 V and VCE=1.2 V before and after 1000s of
VEB-stress=3.5 V as a function of frequency.

199

Table of Contents

Base current degradation IB(t) [A]

10

-5

VBE=0.7 V
VBE=0.8 V
-6

10

-7

10

Base current degradation IB(t) [A]

3x(0.23x2.73) - BEC

-8

10

Base current degradation IB(t) [A]

model was completed to embed the evaluation voltage VBE

into ISRP0 as ISRP0=Aexp[-(qVBE)/(2kT)]. Model results
are compared to experimental data in Fig. 6 for three
devices with different aspect ratios and stress conditions
under different bias conditions. Data depicted in Fig. 6b
and Fig. 6c span over a wider stress total duration
(10000s), being the applied stress voltages milder. The
comparison indicates that the proposed unified model can
be used to describe base current degradation due to reverse
EB stress over stress duration for different geometries and
under different reverse stress conditions.

(a)

VEB-stress=3.5 V

VBE=0.6 V

10

10

100

1000

Stress time t [s]

IV. CONCLUSION

-5

VBE=0.5 V

10

-6

10

-7

10

-8

10

-9

10

VBE=0.5 V

(b)

VEB-stress=3.0 V

Hot carrier induced degradation in SiGe HBTs with

different emitter geometries has been studied. A novel
stress bias setup has been proposed, which allows the
monitoring of the RF performance during stress. By
combining the dependence upon stress duration, emitter
perimeter, and stress and bias conditions, a model
predicting the base current degradation amount for
different geometries and helping understand the physical
beneath the phenomena has been derived.

VBE=0.6 V
VBE=0.7 V
VBE=0.8 V

1x(0.23x9.93) - BEC

-10

10

-5

10

-6

10

-7

10

-8

10

-9

10

VBE=0.5 V

100

Stress time t [s]

1000

ACKNOWLEDGMENT

10000

The authors wish to acknowledge the DOTSEVEN

(316755) project supported by the European Commission
through the Seventh Framework Program (FP7) for
Research and Technology Development.

(c)

VEB-stress=2.5 V

VBE=0.6 V
VBE=0.7 V

10

-10

10

-11

VBE=0.8 V

REFERENCES
[1] J. D. Cressler, A retrospective on the SiGe HBT: What we
do know, what we don't know, and what we would like to
know better, Proc. IEEE SiRF, pp. 81-83, January 2013.
[2] http://www.dotseven.eu.
[3] J. D. Cressler, Emerging SiGe HBT Reliability Issues for
Mixed-Signal Circuit Applications, IEEE Trans. on Device
and Materials Reliability, vol. 4, no. 2, pp. 222-236, June
2004.
[4] L. Vendrame, P. Pavan, G. Corva, A. Nardi, A. Neviani,
and E. Zanoni, Degradation mechanisms in polysilicon
emitter bipolar junction transistors for digital applications,
Microelectronics Reliability, vol. 40, no. 2, pp. 207-230,
February 2000.
[5] P. Chevalier, T.F. Meister, B. Heinemann, S. Van
Huylenbroeck, W. Liebl, A. Fox, A. Sibaja-Hernandez, and
A. Chantre, Towards THz SiGe HBTs, Proc. IEEE
BCTM, pp. 57-65, October 2011.
[6] M. Ruat, N. Revil, G. Pananakakis, and G. Ghibaudo,
Unified Analysis of Degraded Base Current in SiGe:C
HBTs after Reverse and Forward Reliability Stress, Proc.
IEEE BCTM, pp. 1-4, October 2006.
[7] F. Maugain, C. Papadas, G. Ghibaudo, N. Gambetta, and P.
Mortini, On the degradation features of poly-emitter n-p-n
BJTs after hot carrier injection, Proc. IEEE Reliability
Physics Symp., pp. 266-270, April 1995.

1x(0.13x9.93) - BEC
10

100

Stress time t [s]

1000

10000

Fig. 6. Comparison between analytical model (lines) and

experimental data (symbols) of excess base current at several VBE
values for three different geometries stressed at (a) VEB-stress=3.5 V,
(b) VEB-stress=3.0 V, and (c) VEB-stress=2.5 V.

oxide for all the geometries. It provides a complete

description for IB and helps understand the physical
background, evidencing that, when a low stress bias is
applied, the dominant mechanism of degradation at short
stress duration is the creation of interface traps; after a
certain amount of injected stress charge (i.e., stress time)
which depends on the voltage stress, the dominant
mechanism of degradation is the creation of charge in the
oxide. When the stress voltage increases, the creation of
charge in the oxide starts to dominate earlier. Finally, the

200

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Miniaturization of Ka-band High Power Amplifier by 0.15 m GaN MMIC Technology

Kris (Keon-Shik) Kong, Ming-Yih Kao, and Sabyasachi Nayak
TriQuint Semiconductor Texas
500 West Renner Rd, Richardson, TX 75080 (email) kris.kong@tqs.com
Abstract
We demonstrate a compact and efficient Kaband high power amplifier with output power of
34.5dBm at 30 GHz by using 0.15 m GaN
technology. This paper reports record compact area
of 2.38 mm^2 in a Ka-band high power amplifier
(HPA) class. We employed 0.15 m GaN process on
50m thick SiC substrate technology to achieve high
output power with high efficiency and compact
design. The advantage of a GaN PA in commercial
millimeter-wave market is illustrated by comparing it
to similar GaAs power amplifiers.
Introduction
We have recently witnessed the development
of GaN device technology demonstrating record
power and efficiency at millimeter wave frequency
[1, 2]. The low cost of MMIC HPA is critical in the
millimeter-wave commercial markets such as PTP
and satellite communications. The cost of a GaN
wafer is currently much higher than a GaAs wafer.
Therefore, we have to achieve a significant reduction
of a chip size in order to utilize GaN device
technology into the high frequency commercial
market. As a result, the design topology and
selection of FET cells become very critical for a
compact design. This paper presents HPA MMIC in
a smallest reported GaN footprint of less than 2.5
mm^2 for producing ~ 34.5 dBm output power at 30
GHz. The advantage of GaN PA is demonstrated by
comparing it to similar GaAs PAs that have been
previously developed and published [3-7].

Fig.1 Transfer curve of a 0.15m x 50m GaN FET

at Vd = 10V
Design of Compact GaN MMIC PA
We selected the design topology and approach to take
a full advantage of higher output power density of
GaN device. The individual FET size at the output
stage of MMIC power amplifier is critical since it
affects not only the output power but also chip size.
Since the high power amplifier has a stacked FET
cells at the output stage, the vertical dimension of
MMIC PA is determined by the specified output
power and the number of FET cells to be combined.
GaN device technology provides high power density
and efficiency so that the less number of combined
FET cells is required at the output stage. TriQuints
50 m substrate technology also provides compact
layout of FET cell due to implementation of slotted
vias.
Figure 2 shows the photograph of 3 stage GaN
MMIC HPA MMIC, whose size is 2.38 mm^2. We
selected a proper matching topology adequate for a
reduction of chip size and shunt capacitors over vias
instead of open-stubs. There are couplings between
elements due to compact layout and extensive EMsimulation has been done in the design process. The
complexity of circuit has been reduced tremendously
since the number of combined FET cells was reduced
when it is compared to GaAs PAs. Figure 3 shows
the configuration of a 3 stage power amplifier.
The optimum load is determined based on load-pull
measurements. The output matching network was

Device Technology and Characteristics

The 0.15m gate length GaN Ka-band power
amplifier MMICs were fabricated on 50m thick SiC
substrate with an AlGaN/GaN epitaxial layer and
slotted via holes. As shown in Fig. 1, typical
measured DC characteristics at Vd = 10V of these
50m wide 0.15m GaN FETs are Imax ~ 1.17A/mm,
gm, max 400mS/mm and Vp ~ - 3.0V. Gate-drain
breakdown voltages exceed 60V at Igd = 1mA/mm.
When device was tuned for efficiency, the measured
load pull results at 30GHz for a 8 x 50m unit FET
cell demonstrates 3 W/mm output power density with
associated gain of > 9dB and power added efficiency
(PAE) of > 50% at Vd = 20V, Id=100 mA/mm.

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designed to transform 50 ohm to the optimum load of

FETs at the output stage. The gate impedance of the
FET at each stage is matched to the optimum load for
the FET of a previous stage in consideration of output
power, small signal response, and, power margin.
The input matching network was designed to match
the gate impedance of a FET at 1st stage to 50 ohm at
the input port.

Figure 4. Photograph of fixtured MMIC HPA

Figure 2. Photograph of 34.5 dBm MMIC HPA
(Chip Area: 2.38 mm^2)

Figure 5 shows the small signal responses of the

fixtured HPA MMICs. The small signal response
shows the broad-band gain of > 24dB covering 29
34.5 GHz. The output power of a fixtured MMIC
HPA is shown in Figure 6. The output power (Psat)
of HPA is above 34.5 dBm at 29-31 GHz.

Figure 3. Configuration of 3W PA
Measured MMIC Results
The circuit was biased at IdQ=155 mA and
Vdq=20V. The fixtured HPA is shown in Figure 4.
The MMIC HPA is mounted on a 40 mil carrier plate
and TFNs are used for providing contact points for
RF probe and DC bias. The reference planes are the
input and output ports after calibrating out lines on
TFNs by using a TRL calibration technique.
Figure 5. Small signal responses of a fixtured
compact MMIC PA.

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Table 1 shows the comparison of performance and

chip size for GaAs and GaN Ka-band HPA family
that has been reported. This paper reports the highest
power density per chip area (mW/mm^2) in Ka-band
HPA class. Figure 7 illustrates the advantage of GaN
device technology compared to GaAs in terms of
achieving a compact HPA for millimeter-wave
commercial markets.

Figure 6. Frequency vs. Psat of a compact GaN

MMIC PA

Table 1. Comparison of Ka-band HPA MMICs for Output Power per Chip Area
Reference

Frequency

Psat (dBm)

Chip Area

(GHz)

at 30 GHz

(mm^2)

Device Technolgy

Psat/mm^2
(mW/mm^2)

This Work

27 - 33 GHz

34.5

2.38

GaN

1184

[2]

27-31

36.75

4.75

GaN

995

[3]

27-31

35.8

12.88

GaAs

295

[4]

29-31

36.5

14.89

GaAs

300

[5]

26-32

36.2

8.63

GaAs

483

[6]

28-31

36.3

16.2

GaAs

265

[7]

27-33

33.5

6.16

GaAs

364

[8]

28-31

37.8

5.64

GaN

1068

Figure 7. Advantage of GaN Technology for Commercial Ka-band PAs

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Conclusion
We presented a compact Ka-band GaN MMIC high
power amplifier with the benchmark result achieving
highest power density per a chip area (mW/mm^2)
among the reported MMIC HPAs. The reported GaN
PA achieved the output power of 34.5 dBm at 30
GHz in a chip size of 2.38mm^2. The design
employed 0.15 m GaN process on 50m thick SiC
substrate technology to achieve high output power
and compact design. We demonstrated the advantage
of GaN device technology by developing a low cost
compact MMIC HPA for millimeter-wave
commercial market.

[7] S. Chen et.al., A Balanced 2 Watt Compact

PHEMT Power Amplifier MMIC for Ka-band
Applications, 2002 IEEE MTT-S Int Microwave
Symp. Dig., vol 2, pp. 847-850, June 2002.
[8] C. Campbell, et al., High Efficiency Ka-Band
Gallium Nitride Power Amplifier MMICs, 2013
COMCAS.

Acknowledgement
Authors would like to express appreciation to
Oleh Krutko, James Nelson, Dan Green, Shuoqi
Chen, Chuck Campbell, Maureen Kalinski, and Doug
Reep for their support and encouragement on this
work.

Reference
[1] C. Campbell, et al., A K-Band 5W Doherty
Amplifier MMIC Utilizing 0.15m GaN on SiC
HEMT Technology, 2012 CSIC.
[2] C. Campbell, et al., High Efficiency Ka-band
Power Amplifier MMICs Fabricated with 0.15m
GaN on SiC HEMT Process, 2012 IMS.
[3] K. Kong, et al., A Compact 30 GHz MMIC High
Power Amplifier (3W CW) in Chip and Packaged
Form, 2002 GaAs IC Symposium Digest, 37-39.
[4] J.J. Komiak, et al., Fully Monolithic 4 Watt High
Efficiency Ka-Band Power Amplifier, 1999
IEEE MTT-S Digest, 947-950.
[5] K. Kong, et al., Ka-Band MMIC High Power
Amplifier (4W at 30 GHz) with Record Compact
Size, 27th 2005 IEEE GaAs IC Symp., pp. 232235.
[6] F.Y. Colomb, et.al., 2 and 4 Watt ka-band GaAs
PHEMT Power Amplifier MMICs, 2002 IEEE
MTT-S Int. Microwave Symp. Dig., vol. 2, pp.
843-846, June 2002.

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X-Ku wide-bandwidth GaN HEMT MMIC Amplifier

with Small Deviation of Output Power and PAE
Yoshitaka Niida, Yoichi Kamada, Toshihiro Ohki, Shiro Ozaki, Kozo Makiyama, Naoya Okamoto,
Masaru Sato, Satoshi Masuda, and Keiji Watanabe
FUJITSU LABORATORIES LTD., Atsugi, Kanagawa, 243-0197, Japan
niida.yoshitaka@jp.fujitsu.com
Abstract A new design methodology was proposed to
obtain wide-bandwidth and flat-group-delay reactivematching GaN HEMT MMIC amplifiers. Frequency
dependence of the optimal source and load impedance of a
GaN HEMT are derived as polynomial equations and
matching circuits are designed by small signal simulation
without the use of large-signal transistor model and largesignal simulation. Fabricated GaN HEMT MMIC amplifiers,
which show a small deviation of Pout and PAE in the range of
8-18 GHz, prove that our methodology is suitable for the
design of a wide-bandwidth MMIC amplifier.
Index Terms GaN, MMICs, HEMTs, Power Amplifiers.

(a)

Frequency- dependent 2-Port

Network


Large-Signal
Transistor Model

Small-Signal
Matching Circuit

Z = 50

(b)
Z = ZL*(f)

I. INTRODUCTION

Small-Signal
Frequency-dependent Port

The recent expansion of high-speed and large-volume

communication requires power amplifiers with high
frequency, high efficiency, wide bandwidth, and flat group
delay. Gallium nitride (GaN) is a prospective material
because of its high breakdown voltages, originating in the
wide band gap of 3.4 eV. Intrinsic polarization and piezo
polarization enable the generation of high-density and highmobility two-dimensional electron gas at the AlGaN/GaN
hetero-interface and the fabrication of a high-electronmobility transistor (HEMT) with low on-resistance [1].
Several studies have discussed wide-bandwidth GaN
HEMT monolithic microwave integrated circuit (MMIC)
distributed amplifiers (DA) [2]-[6]. Although a DA has an
advantage of wide bandwidth characteristics, it typically
exhibits low gain and low PAE.
A reactive matching amplifier (RMA), on the other hand,
realizes higher gain and higher PAE because a RMA
consists of lossless components.
The challenge for a RMA is to design matching circuits
with the optimal source and load impedance of the
transistor within the entire range of the desired frequency.
This challenge corresponds to the difficulty of achieving
impedance matching in a wide frequency range. The
accuracy of the matching circuits is affected by the accuracy
of the large-signal model of the transistor and the
convergence performance of a circuit simulator.
In this study, a new design methodology was proposed to

978-1-4799-3622-9/14/$31.00 2014 IEEE

ZL = ZL(f)

Frequency- dependent 2-Port

Network


Small-Signal
Matching Circuit

Z = 50

Fig. 1. Schematic of an output matching circuit. (a)

Conventional design method: A large-signal transistor model and
large-signal simulation. (b) Our proposed method: A smallsignal simulation.

obtain impedance matching circuits of MMIC amplifiers

without the use of a large-signal transistor model and largesignal simulation. We obtain the frequency-dependent
source and load impedance of the unit transistor from loadpull measurements and derive polynomial equations for the
optimal source and load impedance. Then, we design
impedance matching circuits that S21 of the input matching
circuit and the output matching circuit have maximum at
each frequency at the same time with small-signal
simulation. One-stage GaN HEMT MMIC amplifier
fabricated using this method exhibits small deviation of
output power and PAE in the wide bandwidth of 8-18 GHz.
This result proves that our method is suitable for the design
of a wide-bandwidth MMIC amplifier with small deviation
of output power and PAE.
II. GAN MMIC AMPLIFIER CIRCUIT DESIGN TECHNOLOGY
Figure 1 shows the concept of a conventional output
matching circuit and our design method for an output
matching circuit. In the design of power amplifiers, a largesignal transistor model and large-signal simulation are

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required to simulate the source and load impedance of the

transistor in large-signal operations. However, the accurate
extraction of the large-signal nonlinear transistor parameter
and convergence of the large-signal simulation are difficult.
Moreover, large-signal simulations take time to design
optimum matching circuits.
The concept of the proposed design method is described
in Fig. 1(b). We regard the large-signal model of the
transistor as a frequency-dependent small-signal port. The
impedance of the small-signal port serves as a large-signal
impedance of the transistor. This downgrade of the largesignal transistor model to a frequency-dependent smallsignal port facilitates the design of impedance-matching
circuits without a large-signal transistor model and largesignal simulation.
We derived the equation for frequency-dependent optimal
load impedance of the unit transistor from load-pull
measurements. Table I shows the optimal load impedance
of the unit transistor that corresponds to the maximum PAE
at each frequency. We fit these data using a polynomial
equation and determine the frequency-dependent load
impedance as

Polynomial Line ZL(f)

ZL @ 18.0 GHz

ZL @ 8.0 GHz
ZL @ 12.0 GHz

Fig. 2. Frequency dependence of the load impedance of the

unit transistor (black dots) and calculated polynomial line (red
line) from 8 to 18 GHz.
Vd

ZL*(f)
L

High pass

Low pass

Fig. 3. Circuit topology of the output matching circuit of our

MMIC amplifier

Z L ( f ) = (0.57 f 2 18 f + 160)
+ j * (0.048 f 2 4.8 f + 110),
(1)
where f is the frequency in GHz. In Fig.2, black dots
represent the optimal load impedance of the unit transistor
at each frequency and the red line represents the polynomial
equation obtained from (1). Similarly, the frequencydependent source impedance ZS(f) is obtained.
We set the impedance of the input port of the output
matching circuit as frequency-dependent impedance ZL(f)
and optimize the length of the stubs and capacitance to
ensure that each S21 of the output circuit attains a maximum
value in the desired frequency range.
The designed circuit topology of the MMIC amplifier is
shown in Fig. 3. We utilize open stub, short stub, and series
capacitors. The circuit is comprised of high-pass and lowpass matching network to obtain small group delay over
entire frequency band.

Source

Gate
SiN

Drain

n-GaN
n-AlGaN
GaN
S.I. -SiC

Fig. 4.

Schematic of the cross-section of our GaN HEMT.

Fig. 5. Chip photograph of the fabricated MMIC amplifier.

2
The chip size is 3.6 2.9 mm .

TABLE I
OPTIMAL LOAD IMPEDANCE THAT CORRESPONDS TO THE
MAXIMUM PAE OF THE UNIT TRANSISTOR BIASED AT V =
30 V.

III. DEVICE FABRICATION AND MEASUREMENT RESULTS

We fabricated MMIC amplifiers using 0.25 m
AlGaN/GaN HEMT technology. Figure 4 shows a
schematic of the cross section of our GaN HEMT. An ntype doped GaN cap layer was epitaxially grown on the
GaN HEMTs to control the surface charge on the GaN
HEMT and to suppress the instability that corresponds to
the large-signal current collapse and gm dispersion [7].
Figure 5 shows a photograph of the MMIC amplifier. The

Frequency (GHz)
8
10
12
14
16
18

Z = 50
C

ZL ()
57.8 + j*72.5
31.1 + j*73.1
28.0 + j*57.7
25.3 + j*50.4
18.8 + j*46.7
20.4 + j*40.1

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Table of Contents

15

S11, S22, S21 (dB)

10

MMIC amplifier was mounted on a copper plate with

AuSn.
The measurement result of the S-parameter at Vds = 30 V
is shown in Fig. 6. The S-parameter shows the flat
characteristics of S21 and the maximum S21 is 8.5 dB at 9
GHz. Figure 7 shows the characteristics of the group delay.
The group delay between 10 and 18 GHz is within 38 ps.
Figure 8 shows the characteristics of Pout, gain, and PAE
as a function of Pin at 14 GHz. The maximum Pout and
maximum PAE are 32.7 dBm and 32.8 %, respectively. The
frequency dependence of PAE and Pout where Pin was set at
26 dBm is shown in Fig. 9. The Pout shows flat
characteristics against the frequency in the desired
frequency range of 8-18 GHz. The maximum and minimum
Pout in the desired frequency range are 32.7 dBm and 30.8
dBm, respectively. A PAE of 35 % is attained at f = 16
GHz.
To evaluate the flatness of the MMIC amplifier, deviation
of the Pout and deviation of the PAE are defined as DP and
DPAE as,
Pout , max Pout , min
DP =
100
(%),
( 2)
( Pout , max + Pout , min ) / 2

S21

5
0
S22

-5
-10
S11

-15
-20
0

10
Frequency (GHz)

15

20

Fig. 6. Measured S21, S11 and S22 of the MMIC amplifier, biased
at 30 V.

Group Delay (ps)

250
200
150
100
50
0
8

Fig. 7.

10

12
14
Frequency (GHz)

16

18

PAEmax PAEmin
100
(%),
(3)
( PAEmax + PAEmin ) / 2
where Pout,max and Pout,min correspond to the maximum Pout and
the minimum Pout, respectively, (in watt) and PAEmax and
PAEmin correspond to the maximum PAE and minimum
PAE, respectively, in the desired frequency range. The
deviation of Pout and the PAE of our MMIC amplifier are
43 % and 35 %, respectively. The deviation of Pout and
deviation of the PAE as indicated in previous studies about
X-Ku band GaN MMIC amplifier are listed in Table II.
Figure 10 shows a chart of the correlation between the
deviation of Pout and deviation of the PAE obtained from
RAM-type GaAs and GaN MMIC amplifier. Our MMIC
amplifier reveals the smallest combination of deviation of
Pout and the PAE compared to previously mentioned studies.
This result proves that our proposed design method is
suitable for the design of a wide-bandwidth MMIC
amplifier with small deviation of output power and PAE.
DPAE =

Measured group delay of the MMIC amplifier.

Pout (dB), Gain (dB),

PAE (%)

35
30

Pout

25

PAE

20
15

Gain

10
5
0
0

10

15
Pin (dBm)

20

25

30

Fig. 8. Pin-Pout characteristics of Pout, gain and PAE of the

MMIC amplifier, biased at 30 V

Pout (dB), PAE (%)

40
35

Pout

IV. CONCLUSION

30

We fabricate a reactive-matching-amplifier-type widebandwidth GaN HEMT MMIC amplifier without a largesignal transistor model and large-signal simulation. We
derived a frequency-dependent load impedance of the GaN
HEMT from load-pull measurements at each frequency and
designed a matching circuit using small-signal simulation.
The GaN HEMT MMIC amplifier that we fabricated yields
minimal deviation of Pout and PAE and flat group delay,

PAE
25
20
8

10

12
14
Frequency (GHz)

16

18

Fig. 9. Frequency-dependent PAE and Pout of the MMIC

amplifier, biased at Vd = 30 V. Pin is fixed at 21 dBm.

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TABLE II
COMPARISON OF X-KU BAND GAN HEMT MMIC AMPLIFIER.
Ref.
[2]
[3]
[4]
[5]
[6]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
This work

Freq. (GHz)
4-18
1.5-17
6-18
2-20
8-42
8-15
6-18
8-14
6-18
6-18
6-18
6-18
6-20
8-18

Relative band width (%)

127
168
100
164
136
61
100
54
100
100
100
100
108
77

Type
DA
DA
DA
DA
DA
RMA
RMA
RMA
RMA
RMA
RMA
RMA
RMA
RMA

Deviation of PAE (%)

140
120
100
80
60
40
This work

0
0

50
100
Deviation of Pout (%)

Ave. PAE (%)

26
29
18
22
5
37
28
41
25
19
19
17
10
29

DP (%)
56
62
30
115
32
64
62
45
61
60
42
93
125
43

DPAE (%)
38
69
51
147
59
72
66
44
88
64
53
88
141
35

MMICs in microstrip technology, IEEE MTT-S Int.

Microwave Symp. Dig., 2012.
[7] T. Kikkawa, M. Nagahara, T. Kimura, S. Yokokawa, S. Kato,
M. Yokoyama, Y. Tateno, K. Horino, K. Domen, Y.
Yamaguchi, N. Hara, and K. Joshin, A 36 W CW
AlGaN/GaN-power HEMT using surface-charge-controlled
structure, IEEE MTT-S Int. Microwave Symp. Dig., pp.
18151818, 2002.
[8] F. Ali, M. Salib, and A. Gupta, A 1-watt X-Ku band HBT
MMIC amplifier with 50 % peak power-added efficiency,
IEEE Microwave and Guided Wave Letters, vol. 3, no. 8, pp.
271272, 1993.
[9] M. Salib, A. Gupta, F. Ali, and D. Dawson, A 1.8 W, 6-18
GHz HBT MMIC power amplifier with 10 dB gain and 37 %
peak power-added efficiency, IEEE Microwave and Guided
Wave Letters, vol. 3, no. 9, pp. 325326, 1993.
[10] M. Cardullo, C. Page, D. Teeter, and A. Platzker, High
efficiency X-Ku band MMIC power amplifiers, IEEE
Microwave and Millimeter-Wave Monolithic Circuits
Symposium, pp. 163166, 1996.
[11] J. Komiak, W. Kong, and K. Nichols, High efficiency
wideband 6 to 18 GHz PHEMT power amplifier MMIC,
IEEE MTT-S Int. Microwave Symp. Dig., vol. 2, pp. 905907,
2002.
[12] G. Mouginot, Z. Ouarch, B. Lefebvre, S. Heckmann, J.
Lhortolary, D. Baglieri, D. Floriot, M. Camiade, H. Blanck,
M. Le Pipec, D. Mesnager, and P. Le Helleye, Three stage
6-18 GHz high gain and high power amplifier based on GaN
technology, IEEE MTT-S Int. Microwave Symp. Dig., pp.
13921395, 2010.
[13] E. Kuwata, K. Yamanaka, H. Koyama, Y. Kamo, T.
Kirikoshi, M. Nakayama, and Y. Hirano, C-Ku band ultra
broadband GaN MMIC amplifier with 20 W output power,
Asia-Pacific Microwave Conference Proceedings, pp. 1558
1561, 2011.
[14] U. Schmid, H. Sledzik, P. Schuh, J. Schroth, M. Oppermann,
P. Bruckner, F. van Raay, R. Quay, and M. SeelmannEggebert, Ultra-wideband GaN MMIC chip set and high
power amplifier module for multi-function defense AESA
applications, IEEE Trans. Microwave Theory & Tech., vol.
61, no. 8, pp. 30433051, 2013.
[15] P. Dennler, R. Quay, and O. Ambacher, Novel semireactively-matched multistage broadband power amplifier
architecture for monolithic ICs in GaN technology, IEEE
MTT-S Int. Microwave Symp. Dig., 2013.

160

20

Ave. Pout (dBm)

36
41
41
42
26
30
33
35
38
39
42
40
34
32

150

Fig. 10. Chart showing the correlation between the deviation

of Pout and the deviation of the PAE obtained from RAM-type
GaAs and GaN MMIC amplifier.

which proves that our design method is suitable for the

design of a wide-bandwidth MMIC amplifier.
REFERENCES
[1] U. K. Mishra, L. Shen, T. Kazior, and Y.-F. Wu, GaNBased RF Power Devices and Amplifiers, Proc. IEEE, vol.
96, no. 2, pp. 287305, 2008.
[2] D. Meharry, R. Lender, K. Chu, L. Gunter, and K. Beech,
Multi-watt wideband MMICs in GaN and GaAs, IEEE
MTT-S Int. Microwave Symp. Dig., pp. 631634, 2007.
[3] C. Campbell, T. Lee, V. Williams, M.-Y. Kao, H.-Q. Tserng,
and P. Saunier, A wideband power amplifier MMIC
utilizing GaN on SiC HEMT technology, IEEE Compound
Semiconductor Integrated Circuits Symp., 2008.
[4] S. Masuda, A. Akasegawa, T. Ohki, K. Makiyama, N.
Okamoto, K. Imanishi, T. Kikkawa, and H. Shigematsu,
Over 10 W C-Ku band GaN MMIC non-uniform distributed
power amplifier with broadband couplers, IEEE MTT-S Int.
Microwave Symp. Dig., pp. 13881391, 2010.
[5] J. Komiak, K. Chu, and P. Chao, Decade bandwidth 2 to 20
GHz GaN HEMT power amplifier MMICs in DFP and no
FP technology, IEEE MTT-S Int. Microwave Symp. Dig.,
2011.
[6] P. Dennler, D. Schwantuschke, R. Quay, and O. Ambacher,
8-42 GHz GaN non-uniform distributed power amplifier

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A 6-12 GHz Push-Pull GaN Amplifier for Low

Harmonic Drive Applications
Michael Roberg and Bumjin Kim
TriQuint - Infrastructure and Defense Products
Richardson, Texas 75080, Email: michael.roberg@tqs.com

AbstractThis paper presents a fully integrated 6-12 GHz GaN

MMIC push-pull amplifier for low harmonic drive applications.
A folded Marchand balun is used to perform the unbalancedbalanced and balanced-unbalanced transformations. The threestage push-pull amplifier provides in excess of 28 dB of small
signal gain at a quiescent bias point of 25 V, 200 mA. The
minimum saturated output power across the 6-12 GHz bandwidth
is 32.3 dBm. The worst case second harmonic level under a
saturated operating condition is -40 dBc, demonstrating the
capability of the push-pull amplifier to suppress the even order
harmonics, especially when the second harmonic is within the
amplifier bandwidth.

I. I NTRODUCTION
Power amplifier (PA) output power and efficiency is dictated
by the fundamental and harmonic impedances presented to the
intrinsic output terminal of the amplifying device [1]. These
impedances are responsible for shaping the intrinsic drain
waveforms which determine the dissipated power within the
device as well as the fundamental and harmonic output power.
Often, it is assumed that the impedances interact only with the
device nonlinearity to shape the intrinsic waveforms. However,
this assumption is invalid in the case where the device is driven
with both fundamental and harmonic power. This situation
arises in the case where a wide band (> octave bandwidth)
amplifier is used as the driver stage of a wide band PA. The
input harmonic power can significantly impact the PA output
power and efficiency. Either degradation or enhancement of
the PA performance may be observed based on the level of
the input harmonic power as well as the time alignment to
the fundamental drive frequency. In order to ensure consistent
PA performance over a wide range of applications, the input
harmonic power to the PA must be reduced to a relative level
such that its impact is negligible.
A push-pull amplifier is a well known solution when drive
power with low even-order harmonic levels is required. For
applications requiring only an octave of bandwidth, a reactively matched push-pull amplifier is an excellent solution.
The second harmonic is inherently suppressed by the push
pull operation while the third harmonic is suppressed due
to the bandwidth of the matching networks internal to the
baluns. A significant challenge for a MMIC push-pull PA is
in the design of a low loss balun with sufficient magnitude
and phase balance to suppress the second harmonic. Some
examples of push-pull amplifiers within or near the 6-12 GHz

Fig. 1. Push-pull amplifier photograph. The die size is 3194 m x 2603 m.

The drains of all three stages are tied together on chip. The gates of stages 1
and 2 are tied together with the stage 3 gate being separate, allowing further
DC bias optimization for various applications.

band are published in [2] (hybrid implementation) and [3]

(MMIC implementation).
This paper presents a fully integrated 6-12 GHz GaN MMIC
push-pull amplifier for low harmonic drive applications. A
folded Marchand balun is used to perform the unbalancedbalanced and balanced-unbalanced transformations. The threestage push-pull amplifier provides in excess of 28 dB of small
signal gain at a quiescent bias point of 25 V, 200 mA. The minimum saturated output power across the 6-12 GHz bandwidth
is 32.3 dBm. The worst case second harmonic level under a
saturated operating condition is -40 dBc, demonstrating the
capability of the push-pull amplifier to suppress the even order
harmonics, especially when the second harmonic is within the
amplifier bandwidth.
II. P ROCESS T ECHNOLOGY & D EVICE S ELECTION
The AlGaN/GaN HEMT devices were fabricated on 100 mm
SiC wafers in TQGaN25 high volume manufacturing technology. The transistors have 4 m source to drain spacing and
are mesa isolated. Ohmic contacts are formed and exhibit a
typical contact resistance less than 0.25 mm. The 0.25 m

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T-gate with an integrated field plate is defined using e-beam

lithography. A source connected second field plate is fabricated
over the gate and channel to reduce the high electric field
on drain side and improve the performance of the transistors.
Wafers are backside thinned down to 100 m. The 60 m via
holes are used to provide grounding to the backside. The
backside of the wafers are plated with gold to form the MMIC
ground plane.
Typical DC characteristics of the transistors are Imax =
1.05 A/mm, gm,max = 340 mS/mm and a -3.3 V pinch-off
voltage at Vds = 10 V . Device breakdown voltages measured
at Igd = 1 mA/mm and Vgs = 6 V are typically 170 V.
The typical power density of a four finger, 100 m gate width
transistor biased at Vd = 40 V, Id = 100 mA/mm in a PAE
tuned condition is 5.5 W/mm at 10 GHz. The power gain and
PAE of the transistors at the PAE tuned conditions are 15 dB
and 60%, respectively.

Fig. 2. Folded Marchand balun implementation and connectivity. The central

conductor is magenta while output conductors are dark blue. The yellow and
light blue conductors correspond to RF probe ground pads. The 6 m thick
center and output conductors are 10.6 m and 25.6 m wide, respectively. The
spacing between the center and output conductors is 12 m.

III. C IRCUIT D ESIGN

The first step in the push-pull amplifier design was the
design of the balun. Given both the bandwidth of the application and the desire to be fully integrated within a single
MMIC, a planar Marchand balun was selected [4]. The balun
is folded and uses multiple conductors in order to minimize the
occupied space [5]. Fig. 2 shows the topside connectivity of
the balun. The central /2 conductor (magenta) edge couples
with the outer two /4 conductors (blue) which are connected
using air bridges. The balun was designed such that all ports
are terminated in 50 . The balun was optimized initially using
a coupled line model in Microwave Office with final optimizations being performed using AXIEM. The optimization
procedure involved minimizing loss and magnitude imbalance
while maintaining as close to a 180 phase shift between
the output ports as possible. Additionally, return loss was
maximized.
Following balun design, the internal PAs were designed
under the assumption of push-pull operation. Fig. 3 shows
the basic schematic of the push-pull amplifier implementation.
Effectively, the push-pull amplifier consists of two identical
PAs whose inputs come from a balun and whose outputs
are combined by the same balun. The individual PAs were
optimized to achieve high gain with greater than 1 W saturated
output power. Three stages of gain were selected in order
to achieve high gain for driver amplifier applications. The
sizes of the first, second and third stage devices are 4x25m,
4x50m and 8x50m, respectively. The drains of all stages
are tied together to simplify DC biasing. The gates of stages
one and two are tied together as well, with the stage three gate
being separated to allow further quiescent point optimization
if desired.
IV. M EASURED R ESULTS
Fig. 4 shows a photograph of a balun test structure. This
structure is identical to the balun in the MMIC PA, except for
the terminations on the balanced ports. The balanced ports of
the test structure are terminated in 50 thin film resistors to

Fig. 3.

Push-pull amplifier schematic and connectivity.

Fig. 4.
Photograph of the balun test structure. The balanced ports are
terminated in 50 TaN resistors to grounding vias to approximate matched
terminations.

ground. To measure the input match of the balun test structure,

a 1-port calibration was performed and S11 of the unbalanced
port is measured. In order to measure one arm of the balun,
the 50 resistor to ground on the corresponding balanced port
was cut with a laser. There are three main drawbacks of this
technique: 1) only one arm of a balun test structure can be
measured, 2) this implementation requires Ground-Signal or
Signal-Ground probing which isnt as accurate as GroundSignal-Ground probing and 3) loading the balun with 50
resistors to grounding vias doesnt exactly capture the way
the balun is used in the MMIC PA. Reticle space was not
available for a back-to-back balun test structure.
Fig. 5 shows measured versus modeled S-parameters for
one arm of the balun test structure. The measurements show
the structure has better than 13 dB return loss in the 612 GHz band. The S21 of the structure varies between 3.8 dB

210

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Table of Contents

Fig. 5.

Measured versus modeled S11 and S21 of the balun test structure.

Fig. 7. CW output power and PAE with Pin = 13 dBm, measured in

250 MHz steps.

Fig. 6. Measured versus modeled magnitude and phase imbalance of the

balun test structure.

and 4.7 dB, indicating that the dissipative loss of the test
structure is between 0.8 and 1.7 dB. Fig. 6 shows the measured
versus modeled magnitude and phase imbalance of the balun
test structure. The measured magnitude imbalance is between
0.25 dB in the 6-12 GHz band while the phase difference
between the balanced ports is within 2 of 180 . While
this structure is not the ideal test structure for the balun,
the measurements do indicate that the balun is performing
reasonably well.
Fig. 1 shows a photograph of the push-pull MMIC PA. The
PA is epoxied to a CuMo carrier plate. The RF launches
are 10-mil GSG TFNs which bond to the chip using two
1-mil bondwires. The reference plane of all measurements
corresponds to the location where the bondwires attach to the
TFNs. The MMIC DC pads are bonded to 1000 pF capacitors
for the initial off-chip bypassing, with larger capacitance being
placed near the supplies during testing. All measurements

were taken with the backside of the carrier plate at ambient

temperature (no thermal control was applied). The quiescent
DC bias point of the amplifier for all measurements is 25 V,
200 mA. The amplifier must be biased from both top and
bottom given there is no DC connectivity between the upper
and lower internal amplifiers.
Fig. 7 shows the measured PA output power and PAE versus
frequency under a fixed CW drive of 13 dBm. The peak output
power of 34.3 dBm occurs at 7.5 GHz with an associated PAE
of 26 %. The power bandwidth of the PA extends from just
above 5 GHz to past 13 GHz. At 12 GHz, the minimum power
and PAE of 32.3 dBm and 16.7 % occur. The degradation of
power and PAE as frequency increases is attributed to the
increase in the loss of the balun as depicted in Fig. 5.
Fig. 8 shows output power, PAE and gain versus input
power at 9 GHz (mid-band) while Fig. 9 shows the associated
AM/PM distortion. The 3 dB compression point occurs at an
input power of approximately 5 dBm. At 3 dB compression,
the output power and PAE are 30.8 dBm and 18.1 %, respectively with an AM/PM distortion of 5.25 . Peak PAE of
23.6 % occurs at approximately 12 dBm input power with an
associated output power and AM/PM distortion of 33.2 dBm
add 9 , respectively.
Fig. 10 shows the measured scattering parameters versus
frequency. The gain varies between 27.7 dB and 32.4 dB in the
6-12 GHz band. The in-band input return loss of the amplifier
is greater than 12.7 dB while the output return loss is greater
than 7.8 dB. For much of the band, the output return loss is
greater than 13 dB.
As previously mentioned, the second harmonic output level
of the amplifier is an important parameter when driving a
larger PA. Fig. 11 shows the second harmonic output level of
the amplifier versus input power. At 6 GHz, when the second
harmonic is still in-band, the second harmonic is less than
-40 dBc when the amplifier is fully saturated. This level of
second harmonic is sufficient to not alter the performance of

211

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Table of Contents

Fig. 8. 9 GHz Output power, PAE and gain versus Pin , measured in 1 dB
input power steps.

Fig. 11. Second harmonic rejection versus Pin , measured in 1 dB input

power steps.

a wide band reactively matched amplifier. By 12 GHz, the

second harmonic is reduced to nearly -70 dBc. The second
harmonic rejection of the amplifier proves the baluns are
working properly and the active devices are being consistently
fabricated.
V. C ONCLUSION

Fig. 9. 9 GHz AM/PM distortion versus Pin , measured in 1 dB input power

steps.

A 6-12 GHz push-pull GaN amplifier for low harmonic

drive applications has been presented that achieves greater
than 32.3 dBm output power with less than -40 dBc second
harmonic. The compact folded Marchand balun design allows
the realization of a compact, fully integrated 6-12 GHz pushpull amplifier. Measurements of the balun test structure and
the push-pull PA indicate the balun is performing as designed.
The measured level of second harmonic is sufficient to not alter
the performance of a wide band reactively matched PA when
this amplifier is used as the driver stage.
R EFERENCES
[1] M. Roberg and Z. Popovic, Analysis of High-Efficiency Power Amplifiers With Arbitrary Output Harmonic Terminations, Microwave Theory
and Techniques, IEEE Transactions on, vol. 59, no. 8, pp. 20372048,
Aug 2011.
[2] A. Stameroff, H. Ta, A.-V. Pham, and R. Leoni, Wide-Bandwidth
Power-Combining and Inverse Class-F GaN Power Amplifier at X-Band,
Microwave Theory and Techniques, IEEE Transactions on, vol. 61, no. 3,
pp. 12911300, March 2013.
[3] H. Wang, C. Sideris, and A. Hajimiri, A 5.2-to-13GHz class-AB CMOS
power amplifier with a 25.2dBm peak output power at 21.6% PAE, in
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010
IEEE International, Feb 2010, pp. 4445.
[4] C.-S. Lin, P.-S. Wu, M.-C. Yeh, J.-S. Fu, H.-Y. Chang, K.-Y. Lin, and
H. Wang, Analysis of Multiconductor Coupled-Line Marchand Baluns
for Miniature MMIC Design, Microwave Theory and Techniques, IEEE
Transactions on, vol. 55, no. 6, pp. 11901199, June 2007.
[5] C. Montiel, Folded Marchand Balun Design and Validation Using
Sonnet, in 28th Annual Review of Progress in Applied Computational
Electromagnetics, April 2012, pp. 680685.

Fig. 10.

Scattering parameters versus frequency.

212

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Investigation of various envelope complexity linearity under

modulated stimulus using a new envelope formulation approach

F.L. Ogboi, P.J. Tasker, M. Akmal, J. Lees, J. Benedikt, *S. Bensmida, *K. Morris, *M. Beach, *J.
McGeehan

Centre for High Frequency Engineering, Cardiff University, Cardiff, United Kingdom
Centre for Communications Research, University of Bristol, Bristol, United Kingdom

Ogboifl2@cardiff.ac.uk
Abstract In [1] a new formulation for quantifying the
linearizing baseband voltage signal, injected at the output
bias port, to linearize a device behavior was introduced. A
key feature of this approach is that since it is formulated in
the envelope domain the number of linearization coefficient
required is independent of the envelope shape, complexity.
This property is validated by performing baseband
linearization investigations on a 10W Cree GaN HEMT
device. Modulated signals with increasing complexity 3, 5,
and 9-tone modulated stimulus, at 1.5dB of compression,
were utilized. In all cases just two-linearization coefficients
needed to be determined in order to compute the output
baseband signal envelope necessary.
Intermodulation
distortion was reduced to around -50dBc, a value very close
to the dynamic range limit of the measurement system.
Index Terms Distortion, envelope, modulation,
waveform engineering, power amplifiers.

impedances requirements, and hence increasing number of

variables to control.

Fig. 1. 2-tone system

I. INTRODUCTION
The linearity behavior of wireless communications
systems are usually performance degraded by in-band
intermodulation distortion products, namely third and fifth
order terms, generated in the active devices used such as
transistors (DUT). This is largely due to the non-linear
behavior of the DUT as a result of its physics,
environment, and connected circuits in its response to both
previously and presently applied stimulus. A number of
approaches and publications [4, 8] have been suggested
and used to suppress/eliminate these with considerable
success. In our earlier work [5], baseband investigation
focused on engineering the output baseband impedance
environment. Such solutions involved presenting constant
broadband baseband impedances, targeted at specific IMD
components contained in the baseband IMD envelope.
Such solution proved successful for signals with a small
number of tones and limited IMD components like the 2tone case, shown in Fig. 1.
However, as the number of tones in the modulation
scale up, 9-tone case is shown in Fig. 2, so does the
number of baseband and IMD components with each
component resulting in an increasing number of

978-1-4799-3622-9/14/$31.00 2014 IEEE

Fig. 2. 9-tone system

The alternative approach introduced in [1], however
involves computing the output baseband signal envelope
, , when targeting the suppression/elimination of the
carrier IMD components, using the following equation;
,

(1)

The advantage of this approach is that it has only a few

to control and the number is independent of
variables,
the RF input envelope shape, ,
. Hence, predicting
no increased complexity in the iterative process for
determining the optimum linearizing output baseband
voltage when moving from the simple 3-tone to the
complex 9-tone is expected. This paper validates this
envelope complexity insensitivity.

213

Table of Contents

II. MEASUREMENT SYSTEM

M

The drain and gate bias voltages of +28V and -2.08V

nt drain current of
were used, giving a quiescen
approximately 12% IDSS, for each modulation type. The
o
was considered
load condition, although not quite optimal,
sufficiently close for this investigatiion.

To investigate this concept, the basebaand measurement

system described in [1], and shown in F
Fig. 3, capable of
measuring multiple-complex modulateed voltage and
current waveforms while engineeringg and injecting
intelligent baseband voltage signals into the device, was
utilized. For this investigation, a 75W, 10KHz-250MHz
wideband baseband amplifier from Ampplifier Research
Model 75A250, was used to engineeer the injected
baseband voltage. The advantage of thiis is that we are
able to precisely engineer and absolutely control the
baseband components associated with thhis system. The
modulated RF time domain terminal volltage and current
waveforms were also captured by thhe measurement
system. Hence, it was possible to m
measure all the
necessary dynamic voltage and current ennvelope behavior
at baseband, RF and harmonic frequenciess.
This measurement system was vector calibrated to the
device package plane using a custom buiilt 50 TRL test
fixture, over, precisely 50MHz basebandd bandwidth and
100MHz RF bandwidth, for each of the first three
harmonics. Stimuli with increasing coomplexities were
measured, using equally spaced tones onn a 0.5MHz grid.
Using this tone spacing of 0.5MHz, peak tto average power
ratio (PAPR) for the 3-tone, 5-tone and 9--tone are 4.77dB,
6.99dB and 9.54dB respectively.
T
The fundamental
excitation was centered at 2GHz, while ddelivering a peak
envelope power (PEP) of approximately 38dBm for each
of the modulation type. The input signall was adjusted in
each case to maintain approximately 1.55dB compression
and an approximately constant input ennvelope dynamic
voltage swing. The transistor, a 10W Crree GaN HEMT,
was biased in class AB, with RF funddamental and all
harmonic frequencies terminated into a paassive 50 .

III. LINEARIZATION INVE

ESTIGATION
The transistor inherent non-lineearity is observed and
measured using the baseband short circuit condition. The
RF fundamental dynamic envelopee transfer characteristic
and the input voltage output curren
nt envelopes measured
are shown below for the various env
velope complexities.
A. Observed transistor inherent non
n-linearity
Results achieved are shown in Fiig. 4, Fig. 5 and Fig. 6,
for the 3-tone, 5-tone and 9-tonee stimuli. They show
considerable distortion produced
d, as evident in the
observed compressed dynamicc envelope transfer
characteristics.
500

10.35V
300

6
200

389.2mA
4

100
2

[3-tone S/C]

Output Current[mA]

450

Output Current[mA]

Input Voltage[V]

10

0
0.5

350
300
250

Dynamic Transfer
Characteristics
10.35V, 389.2mA

200
150
100
50

0
0.0

[3-tone S/C]

400

1.0

Time[ns]

1.5

2.0x10

-6

5
6
7
8
9
Input
Voltage[V]

10

11

12

Fig. 4, Measured 3-tone fundamental RF input voltage/output current

envelopes and the determined, measured, 3-to
one RF fundamental dynamic
envelope transfer characteristic for the basebaand short circuit condition.
500

386.56mA

300

10.3V
6

200

[5-tone - SC]
4

100
2

Output Current[mA]

450

Output Current[mA]

Input Voltage[V]

10

400

[5-tone - SC]

350
300
250
200

Dynamic Transfer
Characteristics
10.3V, 386.56mA

150
100
50

0
0.0

0.5

1.0

Time[ns]

1.5

2.0x10

-6

3
4
Input

5
6
7
8
Voltage
[V]

10

11

12

Fig. 5, Measured 5-tone fundamental RF input voltage/output current

envelopes and the determined, measured, 5-to
one RF fundamental dynamic
envelope transfer characteristic for the basebaand short circuit condition.
500

382.96mA
300

10.31V
6

200

[9-tone - SC]

100
2

Output Current[mA]

450

Output Current[mA]

Input Voltage[V]

10

400
350

[9-tone - SC]

300
250
200

Dynamic Transfer
Characteristics
10.31V, 382.96mA

150
100
50

0
0.0

0.5

1.0

Time[ns]

1.5

2.0x10

-6

0
0

3
4
Input

5
6
7
8
Voltage
[V]

10

11

12

Fig. 6, Measured 9-tone fundamental RF input voltage/output current

envelopes and the determined, measured, 9-to
one RF fundamental dynamic
envelope transfer characteristic for the basebaand short circuit condition.
Fig. 3. Baseband waveform engineering and modulaated RF measurement
system (LSNA).

Note that the observed dynam

mic envelope transfer
characteristic can be modeled as folllows:

214

Table of Contents

(2)

dynamic envelope transfer characteristic can be achieved using an

optimized output baseband injection signal..

where represents the linear gain of the system,

quantifies the level of third order intermodulation
distortion (IMD), quantifies the level of fifth order
intermodulation distortion (IMD), and so on, up to the
desired maximum order m. In this case distortion up to
fifth order is observed; hence only three terms in (2) are
required. Note the insensitivity of these envelope transfer
characteristic to the varying stimulus modulation
complexity.

It is important to note, that in all cases, independent of

signal complexity, the determination of the optimized
output baseband signal necessary to achieve this linear
performance required the determination of just two
linearization coefficients, and . In fact the values of
these components was also insensitive to varying stimulus
modulation complexity.

t .

IV. ENVELOPE INDEPENDENCE

B. Applying Baseband Linearization

More traditionally this performance improvement is

presented and observed in terms of the elimination of
spectral regrowth.

The formulation, being demonstrated in this paper, and

detailed in [1] was now used to engineer the required
output baseband stimulus to linearize the transistors
dynamic RF transfer characteristic. In this case just two
coefficients, and , need to be optimized to compute
the necessary output baseband linearizing stimulus using
equation (1). Fig. 7, Fig. 8 and Fig. 9, show the linearized
performance achieved. In all cases the device has been
successfully linearized. The dynamic envelope transfer
characteristics now becoming a straight line through the
origin.

Pout[dBm]

Output Power
IM5= - 15.974dBm

-40

[3-tone - SC]

-60

300
6

[3-tone LINEAR]

200

4
2

100

400

[3-tone LINEAR]

350

0.5

1.0

1.5

Time[ns]

Dynamic Transfer
Characteristics
10.35V, 453.33mA

200
150
100

2.0x10

5
6
7
8
9
Input
Voltage[V]

10

11

12

Fig. 7, Measured 3-tone fundamental RF input voltage/output current

envelopes confirming that a linear, measured, 3-tone RF fundamental
dynamic envelope transfer characteristic can be achieved using an
optimized output baseband injection signal.

300

[5-tone - LINEAR]

200

100

400

[5-tone - LINEAR]

350

0.5

1.0

Time[ns]

1.5

Dynamic Transfer
Characteristics
10.32V, 464.1mA

150
100

-6

2.0x10

3
4
Input

5
6
7
8
Voltage
[V]

10

11

12

10.35V

300

[9-tone - LINEAR]

200

100

Output Current[mA]

Input Voltage[V]

Output Current[mA]

0
0.0

0.5

1.0

Time[ns]

1.5

-6

2.0x10

2.00

Frequency[GHz]

2.01

Output Power
IM3= 2.699dBm

2.02x10

(a)

400

[9-tone - LINEAR]

300
250

Dynamic Transfer
Characteristics
10.35V, 475.65mA

200
150
100
0
0

3
4
Input

5
6
7
8
Voltage
[V]

10

11

Input Power
P1=9.4758dBm

-20

[5-tone - SC]
1.98

350

Output Power
P1=22.841dBm

Output Power
IM5= - 17.472dBm

-60

50
0

1.99

-40

450
400

[3 - tone - LINEAR]

20

500

475.65mA

-40

200

Fig. 8, Measured 5-tone fundamental RF input voltage/output current

envelopes confirming that a linear, measured, 5-tone RF fundamental
dynamic envelope transfer characteristic can be achieved using an
optimized output baseband injection signal.
10

Input Power
P1=14.029dBm

250

0
0.0

300

50
0

2.02x10

(b)
Fig. 10, Measured 3-tone Spectrum before (a) and after (b) applying
baseband linearization.

Pout[dBm]

10.32V

Output Power
IM5= - 16.994dBm

-20

1.98

450

Output Current[mA]

400

-60

500

464.1mA

Output Current[mA]

Input Voltage[V]

10

2.01

Output Power
P1=27.906dBm

250

-6

2.00

Frequency[GHz]

Output Power
IM3= - 15.736dBm

20

300

50
0.0

1.99

(a)

450

Pout[dBm]

400

Output Current[mA]

Input Voltage[V]

453.33mA

500

Output Current[mA]

10.35V

Input Power
P1=14.059dBm

-20

1.98
10

Output Power
P1=27.183dBm

Output Power
IM3= 5.6307dBm

20

12

Fig. 9, Measured 9-tone fundamental RF input voltage/output current

envelopes confirming that a linear, measured, 9-tone RF fundamental

215

1.99

2.00

Frequency[GHz]

2.01

2.02x10

Table of Contents

Output Power
IM3= - 15.274dBm

Pout[dBm]

20

of linearization coefficients are independent of the

complexity of the modulated signal. This property was
validated with modulated signals of increasing complexity
of 3, 5, and 9-tones. In each case a 10W Cree GaN
HEMT device was driven 1.5dB into compression
generating non-linear behavior up to 5th order system.
Irrespective of the signal complexity the device was
successfully linearized using just two-linearization
coefficients. Distortion was reduced to around -50dBc a
value very close to the dynamic range of the measurement
system. More work is now planned to use this approach
on a real communication signal.

Output Power
P1=23.701dBm

Output Power
IM5= - 19.615dBm

Input Power
P1=9.5799dBm

-20

-40

[5 - tone - LINEAR]

-60

1.98

1.99

2.00

Frequency[GHz]

2.01

2.02x10

(b)
Fig. 11, Measured 5-tone Spectrum before (a) and after (b) applying
baseband linearization.

Output Power
IM3= - 2.4727dBm

Pout[dBm]

20

-20

Output Power
IM5= - 27.227dBm

-40

Output Power
P1=17.831dBm

ACKNOWLEDGMENT

Input Power
P1=4.5037dBm

This work is supported by EPSRC (grant

EP/F033702/1). We also thank CREE for supplying
devices and specifically Simon Wood, Ryan Baker and
Ray Pengelly.

[9 - tone - SC]

-60

1.98

1.99

2.00

Frequency[GHz]

2.01

2.02x10

(a)

REFERENCES

Pout[dBm]

20

Output Power
P1=18.8dBm

Output Power
IM3= - 31.966dBm

-20

[1]

Input Power
P1=4.517dBm

Output Power
IM5= - 25.233dBm

-40

-60

[2]

[9 - tone - LINEAR]
1.98

1.99

2.00

Frequency[GHz]

2.01

2.02x10

[3]

(b)
Fig. 12, Measured 9-tone Spectrum before (a) and after (b) applying
baseband linearization.

[4]

Fig. 10, Fig. 11 and Fig. 12 show the spectral performance

improvements achieved in the case of 3-tone, 5-tone and
9-tone stimulus respectively as a result of linearizing the
envelope transfer characteristic.
In all cases a very similar level of improvement is
observed. Spectral regrowth, distortion, in all cases is
simultaneously reduced to a level around -50dBc, a value
we believed is limited more by the dynamic range of the
measurement system than the ability of the optimized
baseband enveloped derived signal to linearize, and
eliminated the AM/AM distortion.

[5]

[6]

[7]

VII. CONCLUSION
[8]

The linearization of the transistor dynamic transfer

characteristic via the injection of a correctly formulated
baseband signals at the output bias port has been
demonstrated. Since the formulation for this signal is
defined in the envelope domain it ensures that the number

216

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Table of Contents

W-band GaN Receiver Components Utilizing Highly Scaled, Next

Generation GaN Device Technology
A Margomenos, A. Kurdoghlian, M. Micovic, K. Shinohara, H. Moyer, D. C. Regan, R. M. Grabar, C.
McGuire, M. D. Wetzel, D. H. Chow
HRL Laboratories, LLC, 3011 Malibu Canyon Road, Malibu CA 90265
Abstract We report the first W-band GaN receiver
components using a next generation, highly scaled GaN device
technology. This technology (40nm, fT= 220 GHz, fmax= 400 GHz,
Vbrk > 40V) enables receiver components that meet or exceed
performance reported by competing device technologies while
maintaining > 5x higher breakdown voltage, higher linearity,
dynamic range and RF survivability. This paper includes results
for a 4 and a 5 stage low noise amplifier (LNA) (gain over 5
dB/stage at 110 GHz), a single-pole single-throw (SPST) and a
single-pole double-throw (SPDT) switch with loss of 0.9 dB and
1.3 dB respectively and a reflective type phase shifter.
Index Terms Gallium nitride, low-noise amplifiers,
millimeter wave transistors, phase shifters, switches.
Fig. 2. Measured S-parameters of W-band SPST GaN switch.

I. INTRODUCTION

highly scaled GaN process [2] (GaN T3 process: 40 nm,

fT=220 GHz, fmax=400 GHz, Fmin= 1.2 dB at 50 GHz, and
Vbrk>40V). The presented circuits show that with highly scaled
GaN technology one can meet or exceed RF performance of
competing MMIC technologies, while at the same time
maintaining > 5x higher breakdown voltage and higher
linearity. For example Fig. 1 shows the measured gain and NF

GaNs intrinsic material properties and high thermal

conductivity SiC substrate enable amplifiers that have
significantly higher output power (Pout) and power density
compared to competing technologies. Therefore, up to now,
power amplifiers have been the typical GaN circuit. However,
during the last few years highly scaled GaN device
technologies have been developed and demonstrated [1].
These devices, offer fT, fmax, and minimum noise figure (Fmin)
values comparable to competing InP, GaAs and SiGe
technologies while at the same time maintain > 5x higher
breakdown voltage. Therefore, such highly scaled GaN
technologies can enable the next generation ultra-linear,
receiver components with wide dynamic range that eliminate
the need for front-end limiters. In this paper we are presenting

Fig. 3. Measured S-parameters of W-band SPDT GaN switch.

of a GaN T3 single-stage amplifier (6x75m device) biased at

Vds=4V. The amplifier shows NF less than 1.5 dB up to 40
GHz and gain of 15 dB at 10 GHz.
II. DEVICE TECHNOLOGY AND FABRICATION PROCESS
Fig. 1. Measured NF and gain of GaN T3 6x75m single-stage
amplifier at Vds=4V, Ids==126mA.

During the last decade, our group has presented GaN MMIC
at various frequency bands. In [3] we reported the first GaN
W-band PA with Pout of 316 mW, which evolved into a PA

the first reported W-band GaN receiver components using our

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with Pout of 2.1 W at 94 GHz and an associated PAE of 19%

[4]. The latter uses our baseline GaN T2 device technology
(150nm, fT=90 GHz, fmax=220 GHz). With the same process we
have demonstrated wideband W-band amplifiers, high power
E-band amplifiers [5] and class-E X-band PAs [6]. The GaN
MMIC discussed in this paper utilized the GaN T3 device
technology described in [2].

Fig. 6. Measured phase response of 2-bit GaN phase shifter

showing all 4 states and rms phase error.

Fig. 3 where an 80-100 GHz bandwidth is demonstrated. The

SPDT switch has 1.3 to 1.7 dB loss, return loss better than 10
dB and isolation better than 9 dB across the band. The chip
size is 0.68 mm x 1.1 mm. In both circuits the switches were
biased at -10 V (On state) and +2V (Off state). The reported
insertion loss compares favorably with state of the art E and
W-band SPDT switches [7,8]. The isolation can be improved
by using inductive sections to cancel the capacitive loading of
the GaN device in its off-state and by using a series-shunt
topology on each arm. In order to demonstrate the high
linearity of the switch, we tested the SPDT under large signal
at 94 GHz. The results are presented in Fig. 4 where no gain
compression is observed up to input power of 24 dBm with a
control bias of -5V. It is expected that the P-1dB of the SPDT
switch will be in excess of 27 dBm and can be further
increased with a more negative control voltage.

Fig. 4. Large signal performance of SPDT switch at 94 GHz

showing no gain compression up to 24 dBm of input power.

Fig. 5. Measured S-parameters of 2-bit GaN phase shifter

showing insertion and return loss of all 4 states.

III. W-BAND RECEIVER COMPONENTS

The first presented circuit is a SPST switch which uses a
4x25m GaN device in shunt configuration. Fig.2 presents the
measured response. The switch has an operational bandwidth
of 60-110 GHz with insertion loss between 0.9 dB to 1.4 dB
loss, isolation and return loss better than 9 dB across that
band. The chip size is 0.68 mm x 0.8 mm. By using the same
shunt topology, a SPDT switch was fabricated and tested. The
SPDT switch is based on /4 microstrip lines with shunt
inductors at the output. Measured results are summarized in

Fig. 7. Large signal performance of 22.5 phase shifter bit at 94

GHz showing no gain compression up to 24 dBm of input
power.

The third circuit is a reflective type phase shifter which

utilizes a 3dB Lange coupler and two reflective loads that
provide the appropriate phase delay. We designed a 2-bit
phase shifter by cascading a 22.5 and a 45 phase delay bit.
Both bits were designed using GaN switches in a shunt

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configuration, which were biased at -7V (On state) and +2 V

(Off state). The combination of the device parasitics along
with shunt and series transmission lines provided the
appropriate phase delay for each bit and compensated for the
output capacitance of the device. Fig. 5 and 6 show the
measured S-parameters and phase delay for all 4 states (0,
22.5, 45 and 67.5) as well as a schematic of the circuit. The
rms phase error is less than 5 from 78-89 GHz with a
minimum at 83 GHz. Average insertion loss for the 4 states is
2.9 dB 0.5 dB and return loss is less than 10 dB from 60-110
GHz. In order to evaluate the linearity of the phase shifter, we
tested a 22.5 drop-out at 94 GHz. The results are presented in
Figure 7, where 0 dB compression is observed up to 24 dBm
of input power.

In addition to the 2-bit phase shifter, we tested 90 and 180

single bit phase-shifter cells. For these bits we followed a
series topology for the reflective load (GaN device is series to
ground). The measured results are summarized in Fig. 8 and 9
respectively. Due to model inaccuracies both shunt single-bits
were centered at 74 GHz with a 70-78 GHz bandwith (<10
phase error). Both bits showed good return loss and insertion
loss between 1.8-2.8 dB and 2.1-4.6 dB respectively. Each
single bit occupies an area of 1 mm x 0.85 mm, which is
dominated by the Lange coupler. These results are comparable
with previously reported W-band reflective GaAs HEMT
phase shifters [9,10].

Fig. 10. Measured response of 4-stage GaN LNA.

The fourth circuit is a 4-stage reactively matched LNA.

Each stage is comprised of a 2x25m device with source
inductive feedback. The circuit is implemented in microstrip
line topology. All passive elements input, output and interstage matching as well as gate and drain biasing networks
were simulated with Sonnet including higher order harmonics.

Fig. 8. Measured amplitude and phase response of 90 single

bit phase shifter.

Fig. 11. Large signal performance of 4-stage GaN LNA.

Fig. 10 presents the measured small signal of the amplifier at 8

V Vds and Id of 110 mA/mm. The gain is over 20 dB from
70-110 GHz and input and output match are between -13 dB
and -3 dB across the band. This corresponds to a gain/stage of

Fig. 9. Measured amplitude and phase response of 180 single bit

phase shifter.

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will be presented at the conference.

V. CONCLUSION
In this work we presented the first reported W-band GaN
receiver components utilizing a next generation, highly scaled
GaN device technology. The high fT/fmax, low Fmin, and high
breakdown voltage enable for the first time robust, highly
linear, high dynamic range receiver components that can meet
or exceed RF performance of competing, state of the art,
device technologies. All the presented circuits demonstrated
small signal performance comparable or better than state of
the art W-band receiver components using competing MMIC
technologies. The biggest advantage of highly scaled GaN
device technology is that it can meet these performance goals
and still maintain a >40 V breakdown voltage which increases
the RF survivability, the linearity and the dynamic range of
the receiver components.

Fig. 12. Measured response of 5-stage GaN LNA.

>5 dB up to 110 GHz. The simulated NF is between 1.8-2.4

dB across the band. The chip size is 2 mm x 1.3 mm. In order
to evaluate the linearity of the amplifier we tested it under
large signal. Fig. 11 presents the measured P-1dB (11-12 dBm)
and saturated power (Psat) (13.5-14 dBm) for the 4-stage LNA.
Comparable wideband GaAs HEMTs have typical P-1dB of 0
dBm.
The fifth and final circuit is a 5-stage reactively matched
LNA. The first four stages are 4x25m devices while the final
one is a 2x37.5 m device for increased linearity. All stages
incorporate source inductive feedback. The circuit is
implemented in microstrip line topology and Sonnet was used
to simulate all passive networks. Fig. 12 presents the
measured small signal data at 8 V Vds and 110 mA/mm. The
gain is over 25 dB from 65-110 GHz and input and output
match are better than -7 dB and -5 dB respectively. This
corresponds to a gain/stage of >5 dB up to 110 GHz. The
simulated NF is between 2.3-3.2 dB across the band. The
chips size is 3 mm x 1.3 mm. State of the art W-band LNAs
offer comparable performance [11,12]. In order to evaluate the
linearity of the amplifier we tested it under large signal at 100
GHz. Fig. 13 presents the measured P-1dB (14 dBm) and Psat
(16 dBm) for the 5-stage LNA. Measured NF for both LNAs

ACKNOWLEDGEMENT
This material is based upon work supported by the Office
of Naval Research under Contract No. N00014-12-C-0050.
Any opinions, findings and conclusions or recommendation
expressed in this material are those of the author(s) and do not
necessarily reflect the views of the contracting agency.
REFERENCES
[1] K. Shinohara et al, Scaling of GaN HEMTs and Schottky
Diodes for Submillimeter-Wave MMIC Applications, IEEE
Trans. on Electron Devices, vol. 60, issue 10, pp. 2982-2996,
2013.
[2] K. Shinohara et al, 220 GHz fT and 400 GHz fmax in 40-nm
GaN DH-HEMTs with Regrown Ohmic, IEEE IEDM 2010.
[3] M. Micovic et al, GaN HFET for W-band Power
Applications, IEEE IEDM 2006.
[4] M. Micovic et al, 92-96 GHz GaN Power Amplifiers, IEEE
IMS 2012.
[5] A. Margomenos et al, 70-105 GHz Wideband GaN Power
Amplifiers, European Microwave Integrated Circuits
Conference 2012.
[6] A. Margomenos et al, X-band Highly Efficient GAN PA
Utilizing Built-In Electroformed Heat Sinks Advanced Thermal
Management, IEEE IMS 2013.
[7] J. May et al, Design and Characterization of SiGe RFIC for
Passive Millimeter-Wave Imaging, IEEE Trans. of MTT, vol.
58, no. 5, pp. 1420-1430, May 2010.
[8] I. Kallfass et al, Multiple-Throw Millimeter-Wave FET
Switches from 60 -120 GHz, European Microwave Integrated
Circuits Conference 2008.
[9] S. E. Shih et al, A W-band 4-bit Phase Shifter in Multi-layer
Scalable Array Systems, IEEE CSICS 2007.
[10] S. Y. Kim et al, A 4-bit Passive Phase Shifter for Automotive
Radar Applications in 0.13 m CMOS, IEEE CSICS 2009.
[11] X.B. Mei et al, A W-band InGaAs/InAlAs/InP HEMT LNA
MMIC with 2.5 dB Noise Figure and 19.4 dB Gain at 94 GHz,
Indium Phosphide and Related Materials Conference 2008.
[12] J. Alvarado et al, W-band SiGe LNA Using Unilateral Gain
Peaking, IEEE IMS 2008.

Fig. 13. Large signal performance of 5-stage GaN LNA.

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Ka band chip-set for Electronically Steerable Antennas

Rmy Leblanc, Noelia Santos Ibeas, Ahmed Gasmi, Jol Moron
OMMIC SAS, 2 rue du Moulin, 94453 Limeil Brvannes France
Tel: +33 145106724, r.leblanc@ommic.com
Abstract This paper presents a Ka band chipset
dedicated to electronically steerable antenna systems. The
first MMIC of the chipset is a multifunction chip including
several amplifier stages, digitally controlled attenuator and
phase shifter, a complex Transmit/Receive switching scheme
and a Serial Input to Parallel Output digital circuit. The
second MMIC includes a Low Noise amplifier, a Power
amplifier and a Transmit/Receive switching circuitry. Both
circuits present state of the art performances at frequencies
above 30 GHz and allow together a huge reduction of system
complexity. The circuits are fabricated using P-HEMT
processes validated for Space use. Various possible
architectures together with design issues and test results will
be presented.
Index Terms Analog-digital integrated circuits, HEMT,
Monolithic integrated circuits, Phased arrays, Phase shifters,
Attenuators.

II. KA BAND CHIPSET DESIGN

More recently, an increasing need for such
multifunction chips in several parts of the Ka band
(between 26 and 40 GHz) has been identified.
In this frequency range and for such multifunction
chips, the processes are pushed to their limits and designs
have to take into account various coupling and interface
effects. In addition, the reduced distance between the
radiating elements due to smaller wave length has a strong
impact on the maximum allowed MMIC width, which
may be forced to be kept at around 3mm, adding
constraints to MMIC architecture.
The Ka Band OMMIC chip sets are composed of:

I. INTRODUCTION

Electronically steerable antennas are now used in many

applications, such as military systems, earth observation
equipment, radio astronomy and mobile radio. These
antennas use a matrix of independently parameterized
radiating elements to form a directed beam. The
orientation and quality of the beam is obtained by the use
of digitally controlled phase shifters and attenuators
embedded in each radiating element.
To keep a good quality signal in both transmission and
reception modes, low noise and power amplifiers have to
be added, together with convenient switches to select the
operation mode and Serial Input to Parallel Output (SIPO)
digital circuits to control the overall system.
In the past years, OMMIC has developed a range of
multifunction chips including all these parts in a single
MMIC (Core-Chip). This strategy induces a drastic
reduction of the system complexity, size and cost.
Thanks to state of the art and well controlled space
evaluated E/D PHEMT processes, OMMIC is able to
design and produce in volume such circuits including in
the same MMIC digital SIPO and analogue functions in C,
X and Ku bands, maintaining, in spite of the internal
losses of the attenuators, phase shifters and switches, noise
level as low as 2.5dB and power levels as high as 20 dBm
or more. [1]-[7]

978-1-4799-3622-9/14/$31.00 2014 IEEE

one Transmit/Receive chip (T/R chip) including a

power amplifier, a low noise amplifier and a low loss
switch system
one multifunction chip including SIPO, switches,
amplifiers, phase shifter and attenuator (Core-Chip)

The two chips of each chipset are designed to work

together and can be used in Transmit (Tx) or Receive (Rx)
mode by controlling the switch configuration.
A. T/R chip
The T/R chip is placed between the antenna and the
Core-Chip to enhance noise in Receive mode and output
power in Transmit mode.
The T/R chip includes a Low Noise Amplifier (LNA) in
one direction and a Power Amplifier (PA) in the other
direction, linked with SPDT switches. Two different
configurations are possible:

3 port configuration, where only one switch is used,

placed on the antenna side, that is at the LNA input
and the PA output
2 port configuration, where another switch is placed
on the other side

In both cases, the losses of the first switch have the

highest impact on the performances, increasing noise and

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decreasing output power by 1 to 2 dB. To avoid

oscillation, the isolation of the switches has to be high and
this tends to increase the series losses.
The SPDT switch circuit must be as simple as possible
for minimum loss to have low noise figure (NF) for the
receive mode and high output power (P3dB) for the
transmit mode. In the other hand, the isolation must be
maintained to avoid interaction between PA output and
LNA input. For the TR chip, we have considered two
topologies of switches:
1-Quarter Wave Length switch
2-Low loss switches with short transmission line
resonating with the off-state capacitance to enhance
isolation.
For this T/R chip, we have used the Resonating switch
to have good trade-off between the electrical performances
and small size of the chip. The PHEMT size of the output
switch in Transmit mode is optimized to handle the output
power of the Power Amplifier.
The switch control also drives the biasing of the LNA
and of the PA which are switched-off when not in use.
This reduces the global DC consumption and enhances
loop stability.

TR Chip
Figure 1: Lay out example of

a Ka band T/R chip

B. Core Chip
The Core-Chip main use is to create the phase shift and
the attenuation required to set the antenna orientation, but
it must also have good enough Noise, RF Power and Gain
to be used with the T/R chip without degradation. In
addition, it contains a digital circuit converting the 10 bit
serial input signal (Clock, Data and Latch Enable) to the
parallel output required to drive the Attenuator, the Phase
Shifter and the switches.

The last stages of the output Power amplifier are formed

by several transistors combined to provide the required
gain and output power, and to decrease the self-heating
effect. The amplifier electrical performance is highly
dependent on the internal temperature of the various
devices and by the thermal properties of the solder or glue
used to mount the amplifier. The topology, in spite of the
small size, has been optimized to keep the channel
temperature below the maximum rating (150C).

The choice of the Core-Chip architecture is driven by

several considerations, the most restrictive one being
usually the MMIC size due to antenna wavelength pitch
and implementation constraints. If this one is not critical, a
structure similar to the T/R chip with one complete Rx
chain, one complete Tx chain and one or two SPDT
switches is the most easy to implement. But this structure
requires the use of two attenuators and two phase shifters,
increasing MMIC size and complexity. Alternative
architectures have thus been designed, where some circuit
elements are common to the Rx and Tx chains, at the cost
of more complex switch configuration.

We have used for this T/R chip the OMMIC space

validated (listed in European Space Agency Preferred
Parts, EPPL) 130 nm gate length D01PH process. Thanks
to its double 2D electron-gas and low ohmic contact
resistance, this Pseudomorphic HEMT process presents a
100 GHz h21 frequency cut-off, a 630 mW/mm saturated
output power and a 1 dB noise figure at 30 GHz.
This process is fully documented with Design Manual
and Process design kits for several commercially available
simulation packages.

Depending on overall system specifications and on T/R

chip performances in terms of Noise figure and Output
power, several trade-off are possible for the Core Chip.
One or two of the passive components - phase shifter
and/or attenuator - may be placed at the input of the
circuit, being common to the Tx and Rx chains, and thus
reducing the MMIC size. Otherwise they should be
doubled and placed in the middle of each chain. This
increases significantly the final size, but allows adjusting
Tx and Rx RMS errors separately, which may be helpful if
a coupling is still present. And obviously, another way of
reducing the size is by reducing the number of
amplification stages, but this affects the gain and may
jeopardize the global noise and output power.

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On the other hand, if the Core Chip is supposed to work

alone, NF and P1dB become critical again. In that case,
there are two main options: using a double chain structure
with two complete chains connected by switches or using
a single chain structure where all the elements are
common to both modes. In the first case, the Core Chip
would achieve the best possible performances with only
one drawback: MMIC size. As this is usually a critical
requirement, the single chain structure would be the only
left option, but this architecture, in Ka band, presents an
unavoidable coupling due to the required loops in the path,
and thus the RMS errors are degraded.

III. TEST RESULTS

A summary of the Chip-Set measured performances in
the above 30 GHz range is given below. These values
include the Tx/Rx switch losses.

Measured value
@32-34 GHz
24.8 dBm
30 dB
3.3 dB
30 dB
10 bits
3
0.5 dB

Parameter
Tx P3dB
Tx Gain
Rx NF
Rx Gain
SIPO
Phase rms
Attenuation rms
DC consumption Tx
mode
DC consumption Rx
mode

Finally, another point to take into account is the number

of ports. In the case of the double chain, the difference
between two or three ports is only one switch which is
removed, incrementing the gain a little bit. But, a special
attention should be paid to stability if the 3-port Core Chip
is connected to the 3-port T/R chip, since a very high gain
loop may appear if all the passive elements are placed
outside of the chains.

2.5 W
0.6 W

Table 1: Global Chip-Set performance summary

We have used for the various versions of the Core Chip

the OMMIC space validated (ESA EPPL) 180 nm gate
length ED02AH process. This Pseudomorphic HEMT
process presents a 60 GHz h21 frequency cut-off, a
350 mW/mm saturated output power and a 1.2 dB noise
figure at 30 GHz. In addition, its Enhancement mode /
Depletion mode (E/D) capability makes possible
multifunction chips mixing analog millimeter wave
functions with high density digital functions such as 10,
12 or 26 bit SIPO.
This process is fully documented with Design Manual
and Process design kits for several commercially available
simulation packages and dedicated verification tools have
been developed to cope with very complex analog/digital
30 GHz chip.

Examples of measured phase rms, attenuation rms,

noise, and P3dB performances are shown on Figures 3 to
7 below.
Measured Phase rms value
10

Phase rms ()

9
8
7
6
5
4
3
2
1
0
32.0

32.2

32.4

32.6

32.8

33.0

33.2

33.4

33.6

33.8

34.0

Freq (GHz)

Figure 3: Example of Core chip phase rms measurement

Measured Attenuation rms

Attenuation rms (dB)

5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
32.0

32.2

32.4

32.6

32.8

33.0

33.2

33.4

33.6

33.8

Freq (GHz)

Figure 4: Example of Core chip attenuation rms measurement

Core Chip
Figure 2: Lay out example of
a Ka band Core-Chip

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with 30 dB gain, 25dBm P3dB and 3.5dB NF MMICs in

this frequency range is reported.

measured Gain (Tx mode)

30
29

Gain (dB)

28
27
26
25
24

ACKNOWLEDGMENT
Pr Ernesto Limiti from University Roma Tor Vergata was
involved in the early phases of this study and performed
designs of T/R chips at other frequencies.
The authors are grateful to the OMMIC fabrication and
test teams for their outstanding work.

23
22
21
20
32

32.2

32.4

32.6

32.8

33

33.2

33.4

33.6

33.8

34

Freq (GHz)

Figure 5: Example of TR chip Gain measurement

REFERENCES

P3dB Tx mode measurement

26

[1] R. Giordani, M. Amici, A. Barigelli, F. Conti, M. Del

Marro, M. Feudale, M. Imparato, A. Suriani, Highly
Integrated and Solderless LTCC Based C-Band T/R
Module, 2010 European Microwave Conference,
Proceedings, pp. 902-905.
[2] G. Langgartner, R. Baggen, S. Vaccaro, D. Smith,
Dedicated GaAs Core Chip for Mobile Satellite Ku-Band
Front Ends, 2010 ESA Conference.
[3] F.E. van Vliet, M. van Wanum., A.W. Roodnat, M.
Alfredson, Fully-integrated Wideband TTD Core Chip
with Serial Control, 2003 GAAS Applications Symposium
Digest, pp. 89-92.
[4] F. Robert, R. Leblanc, J. Moron, A. Gasmi, N. Santos and
M. Rocchi, E/D GaAs PHEMT Core Chips for
Electronically Steerable Antennas, Microwave Journal,
Nov.2012, pp. 98-106
[5] R. Leblanc, J. Moron, A. Gasmi, N. Santos, M. Rocchi,
Analogue/Digital
GaAs
PHEMT
corechips
for
electronically steerable antennas, IMS 2012 WFF
Advances in reconfigurable RF systems and materials
[6] Ciccognani W., Ferrari M., Ghione G., Limiti E., Longhi
P.E., Pirola M., Quaglia R., A Compact High Performance
XBand Core-Chip with on Board Serial-to-Parallel
Conversion, Proceedings of the 40th European Microwave
Conference
[7] Vaccaro S., Llorens del Rio D., Snchez R.T., Baggen R.,
Low cost phased array for mobile Ku-band satellite
terminal, 2010 Proceedings of the Fourth European
Conference on Antennas and Propagation
[8] Dong-Woo Kang, Jeong-Geun Kim, Byung-Wook Min,
Gabriel M. Rebeiz, Single and Four-Element Ka-Band
Transmit/Receive Phased-Array Silicon RFICs With 5-bit
Amplitude and Phase Control, IEEE Transactions On
Microwave Theory And Techniques, Vol. 57, No. 12,
December 2009, pp 3534-3543

P3dB (dBm)

25
24
23
22
21
20
32

32.2

32.4

32.6

32.8

33

33.2

33.4

33.6

33.8

34

33.8

34

Freq (GHz)

Figure 6: Example of TR chip P3dB measurement

Measured Noise figure (Rx mode)
5
4.5
4

NF (dB)

3.5
3
2.5
2
1.5
1
0.5
0
32

32.2

32.4

32.6

32.8

33

33.2

33.4

33.6

Freq (GHz)

Figure 7: Example of TR chip noise measurement

VII. CONCLUSION
Using Pseudomorphic HEMT processes merging E/D
capabilities with very good noise and power
performances, OMMIC has designed, fabricated and
measured state of the art Ka band multifunction chips to
enhance steerable antenna systems while reducing their
size and their cost. To our knowledge, this is the first time
such a chipset including digital SIPO and analog functions

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12.5 THz Fco GeTe Inline Phase-Change Switch

Technology for Reconfigurable RF and
Switching Applications
Nabil El-Hinnawy, Pavel Borodulin, Evan B. Jones, Brian P. Wagner, Matthew R. King, John S.
Mason, Jr., James Bain, Jeyanandh Paramesh, T.E. Schlesinger, Robert S. Howell, Michael J. Lee, and
Robert M. Young
geometry to optimize the complex electro-thermal actuation
mechanism, significant performance improvements have since
been realized and fabricated into state-of-the art RF circuits.
II. DEVICE FABRICATION

AbstractImprovements to the GeTe inline phase-change

switch (IPCS) technology have resulted in a record-performing
radio-frequency (RF) switch. An ON-state resistance of 0.9
(0.027 mm) with an OFF-state capacitance and resistance of
14.1 fF and 30 k, respectively, were measured, resulting in a
calculated switch cutoff frequency (Fco) of 12.5 THz. This
represents the highest reported Fco achieved with chalcogenide
switches to date. The threshold voltage (Vth) for these devices was
measured at 3V and the measured third-order intercept point
(TOI) was 72 dBm. Single-pole, single-throw (SPST) switches
were fabricated, with a measured insertion loss less than 0.15 dB
in the ON-state, and 15dB isolation in the OFF-state at 18 GHz.
Single-pole, double-throw (SPDT) switches were fabricated using
a complete backside process with through-substrate vias, with a
measured insertion loss 0.25 dB, and 35dB isolation.

Operation of digital PCM devices has been extensively

documented [2]-[4], with some via-style phase-change
switches being used for RF applications [7]. Operation of
IPCS devices has also been described elsewhere [5], [8], with
switch geometry variations being reported as well [9], [10]. A
schematic cross-section is shown in Fig. 1(a). Fabrication
begins with a dielectric material (substrate insulator) being
thermally grown on the surface of the substrate. A SiC
substrate is used with a SiO2 as the substrate insulator. Next, a
NiCrSi thin-film resistor (TFR) is patterned using a liftoff
technique. A plasma enhanced CVD (PECVD) Si3N4 dielectric
barrier material is then deposited. Contact openings in the
dielectric barrier are dry etched, followed by a liftoff of
sputtered GeTe. Deposition is done in a Perkin Elmer
production deposition tool, and a similar procedure was used
to optimize the DC magnetron sputtering parameters of GeTe
as done in [11]. Contact and interconnect metallization
composed of Ti/Au is then patterned via liftoff, followed by
deposition of an additional PECVD Si3N4 dielectric
passivation with dry etched openings. A second level Au
interconnect metallization is then plated to decrease line
resistance and allow the formation of air bridges. The wafer is
then thinned, and through-substrate vias are dry etched using
an inductively-coupled plasma process, before a backside
ground plane is Au-plated, establishing ground vias to the
front side of the wafer. The plated interconnect metallization
and backside processing represent a traditional III-V process
flow, and demonstrate the ability of the IPCS devices to be
integrated with either a silicon or III-V process flow.

Index Termsgermanium telluride (GeTe), inline phasechange switch (IPCS), TOI, IP3, RF switch, SPDT, chalcogenide

I. INTRODUCTION

HASE-CHANGE

materials (PCMs) have been used in optical

data storage, such as rewritable CDs, based on
Ovshinskys discovery of the change in optical properties with
change in structure in phase-change chalcogenides [1]. More
recently, they have been used in digital non-volatile memory
devices, taking advantage of the electrical resistance change to
improve memory density and switching speed over flash
memory devices [2]-[4].
The first demonstration of a functional chalcogenide RF
inline phase-change switch (IPCS) was recently reported by
El-Hinnawy et al. [5]. This device employed an initial design
intended to demonstrate the ability to quench chalcogenide
PCM in the amorphous state utilizing an integrated,
electrically isolated thin-film heater in a horizontal
configuration. While only intended to demonstrate the concept
for functionality, this design nonetheless achieved an Fco
(defined as 1/(2RonCoff)) of 1.0 THz, which outperforms
FETs in frequency performance [6]. By altering device

III. RESULTS
A. Material & Device Characterization
Germanium telluride is used as the PCM in this device, as it
possesses the lowest crystalline state resistivity relative to
other chalcogenides typically used as PCMs [12]. The
measured recrystallization temperature for the optimized film
was 185C, with a measured resistivity of 3.6x10-6 m.

N. El-Hinnawy, P. Borodulin, E. Jones, B. Wagner, M. King, J. Mason, R.

Howell, M. Lee, and R. Young are with Northrop Grumman Electronic
Systems, Linthicum, MD 21090 USA (e-mail: nabil.elhinnawy@ngc.com).
N. El-Hinnawy, J. Bain, J. Paramesh are with the Carnegie Mellon
University, Pittsburgh, PA 15213, USA
P. Borodulin, T.E. Schlesinger are with the Johns Hopkins University,
Baltimore, MD 21218, USA
978-1-4799-3622-9/14/$31.00 2014 IEEE

225

Passivation
Contact Metalization
Phase Change Material
Dielectric Barrier
Thin Film Resistor
Substrate Insulator
Substrate

Using the fabrication process described, various layouts of

the IPCS were fabricated with PCS lengths ranging from 0.9
to 2.5-m, PCS widths ranging from 10 to 30-m, and TFR
widths ranging from 0.5 to 2.5-m. Fig. 1(b) shows a
fabricated single-pole, single-throw (SPST) switch utilizing a
microstrip design, with a magnified view of the IPCS area. All
devices are pulsed with an HP8114A pulse generator, utilizing
a 10-ns rise and fall time. Fig. 2 shows an IPCS device cycled
for 100 pulses, using alternating ON and OFF pulses. A 100-ns
voltage pulse was used to set the device in the OFF-state, and a
1500-ns voltage pulse was used to set the switch in the ONstate. The switch had an initial ON-resistance of 1.2 , but
stabilized to 0.9 after 5 cycles.

-0.1

-30

Measured
Modeled

-0.4
-0.5

Measured
Modeled

-40

10
20
30
40
0
10
20
30
40
Freq. (GHz)
Freq. (GHz)
Fig. 3. Measured and modeled (left) insertion loss (ON-state transmission) and
(right) isolation (OFF-state transmission) for a 12.5 THz SPST IPCS with 0.9um
PCS length and 30um PCS width.

IPCS
LENGTH
0.9um
0.9um
0.9um

TFR
WIDTH
0.9um
1.3um
1.7um

TABLE I
GETE IPCS MEASURED RESULTS
IPCS
RON
ROFF
VTH
WIDTH
()
(k)
(V)
30um
0.90
26.9
2.09
30um
0.92
31.5
2.72
30um
0.91
35.3
3.31

COFF
(fF)
14.1
16.5
18.2

FCO
(THz)
12.5
10.5
9.6

measured isolation with the TFR contact pads floating

(disconnected from the pulse generator). This is done
intentionally, as the connection of the TFR pads to an
unknown load can lead to inconsistent and incorrect
extractions of the OFF-capacitance on 2-port structures. Fig. 4
shows the switch response when the TFR pads are shorted to
ground. The isolation of the 2-port IPCS SPST with a
grounded TFR is significantly higher, due to reduced
capacitive coupling through the TFR. The energy that
normally couples from port 1 to port 2 through the TFR is
partially reflected and partially dissipated in the TFR,
increasing the overall isolation at the expense of some
increased insertion loss. This could potentially lead to a false
assumption in the cutoff frequency and improper evaluations
of the switch, as the lower isolation at port-2 (due to the shunt
element) decreases the perceived extracted OFF-capacitance by
more than 110%, as seen in Table II.
C. RF Circuit Results
Fig. 5 shows a measured SPDT switch with a microstrip
design in comparison to other switch technologies from 0-18
GHz [13]-[17]. Fig. 5(a) shows the insertion loss measuring
TABLE II
MEASURED IPCS DEVICES WITH FLOATING & GROUNDED TFR CONTACTS
TFR
IPCS
TFR
IPCS
RON
COFF
FCO
CONTACTS LENGTH WIDTH WIDTH
()
(fF)
(THz)
Floating
0.9um
0.9um
20um
1.41
15.2
7.5
Grounded
0.9um
0.9um
20um
1.40
7.2
15.8

105
104
103

-0.2

-10

Transmission (dB)

IPCS Resistance ()

-20

-0.3

B. RF & DC Results
Table I lists the device dimensions, measured ON and OFF
resistance, threshold voltage (Vth), OFF-capacitance, and
calculated cutoff frequency (Fco) for 3 different IPCS
configurations. It is observed that the OFF-capacitance
increases with increasing TFR width, which is consistent with
RF simulations. This increase in OFF-capacitance is due to the
parasitic
capacitance
between
the
interconnect
metallization/GeTe and the TFR. As reported in previous
publications, the cutoff frequency (Fco) is used as the figure of
merit, which is defined as the ratio of off-impedance to onimpedance: 1/(2RonCoff). By optimizing device geometry
and pulse parameters to minimize Ron and Coff, an Fco of 12.5
THz was achieved. This represents the highest reported value
for chalcogenide switches to date. Fig. 3 shows the measured
and modeled insertion loss and isolation for the 12.5 THz
switch. The insertion loss measured less than 0.25dB from 040 GHz, and measured 0.15dB at 18 GHz. The third-order
intercept (IP3) for all 3 devices measured 72 dBm in the ONstate. The measured isolation was 15 dB at 18 GHz, primarily
attributed to the parasitic capacitance through the TFR. The
OFF-capacitance for these devices was extracted from the

-20

-0.4

102
101

-30

-0.6
Floating
Grounded

-0.8

1
0

-10

-0.2

Transmission (dB)

30m
a)
b)
Fig. 1. a) schematic cross-section of the IPCS fabrication process b) optical
view of fabricated IPCS SPST using a microstrip design, with a close-up of
the IPCS switch area

Transmission (dB)

Transmission (dB)

Table of Contents

-1

-40
-50

Floating
Grounded

0
5
10
15
20
5
10 15 20
Freq. (GHz)
Freq. (GHz)
Fig. 4. Measured a) insertion loss (ON-state transmission) and b) isolation
(OFF-state transmission) for the two different heater configurations. It is worth
noting the two measured switches were 20um in IPCS width, as opposed to the
switches in Table I that were 30um wide
0

20

40
60
80
100
Pulse Number
Fig. 2. Measured resistance of the 12.5 THz IPCS device as a function of
pulse number, using alternating ON and OFF pulses for 100 pulses. A 100-ns
pulse was used to set the device in the OFF-state, and a 1500-ns pulse was
used to set the switch in the ON-state

226

Table of Contents

less than 0.3dB from 0-18GHz, and Fig. 5(b) shows the
isolation measuring greater than 35dB across the band [18].

Northrop Grumman Electronic Sy

ystems for their continued
support and helpful discussions.
This work was sponsored in paart by Defense Advanced
Research Projects Agency Microsy
ystems Technology Office
(MTO) under the Radio Frequency Field Programmable Gate
PA Order No. W705/00,
Array (RF-FPGA) program (ARP
Program Code: 2720 Issued by DARPA/CMO under Contract
No. HR0011-12-C-0095). The view
ws expressed are those of
the authors and do not reflect the offficial policy or position of
the Department of Defense or the U.S.
U Government. This is in
accordance with DoDI 5230.29, Jan
nuary 8, 2009. This content
has been approved for public releasee, distribution unlimited.

IV. CONCLUSION
GeTe-based IPCS
Advances in the fabrication and design of G
switches have decreased the Ron and Coff to 0.9 (0.027
mm) and 14.1 fF, respectively. This resuults in an Fco of
12.5THz for an SPST switch, which reepresents a 10x
improvement over first generation IPCS devices. These
T RF switch that
devices have been integrated into an SPDT
measures less than 0.25dB insertion loss froom 0-18GHz, and
greater than 35dB of isolation across the same band,
demonstrating the ability to fabricate noon-volatile IPCS
MMICs such as SPDTs, tunable filters, phaase shifters, time
delay units, and multi-port switch matricees. Future work,
already in progress, focuses on improvedd processes and
materials to decrease RF losses and power cconsumption, and
further increase the threshold voltage.

REFERENCE
ES
[1]
[2]
[3]

ACKNOWLEDGMENT

[4]

The authors would like to thank Dr. Willliam Chappell of

Purdue University and DARPA, Dr. Andrew Christiansen with
the Navy for their guidance and direction, annd the entire staff
at the Advanced Technologies Laboratoories (ATL) of

[5]

[6]
[7]
[8]

[9]
[10]
[11]
a)

[12]
[13]
[14]
[15]
[16]
[17]
[18]

b)
Fig. 5. Measured a) insertion loss (ON-state transmissiion) and b) isolation
(OFF-state transmission) for the fabricated SPDT switch, with comparisons to
other technologies [13]-[17]

227

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witching phenomena in disordered
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o. 20, pp. 1450-1453, 1968.
S. Raoux et al., Phase change materialls, MRS Bulletin, vol. 37, no. 2,
pp. 118-123, Feb. 2012.
G. Burr et al., Phase change memory technology,
t
J. Vac. Sci. Technol.
B, vol. 28, no. 2, pp. 223-262, Apr. 2010
M. Nardone et al., Electrical conductio
on in chalcogenide glasses of
phase change memory, J. Appl. Phys., vol. 112, no. 7, pp. 071101,
2012.
N. El-Hinnawy et al., A Four-Terminaal, Inline, Chalcogenide PhaseChange RF Switch Using an Independeent Resistive Heater for Thermal
Actuation, IEEE Electron Device Lett., Vol. 34, no. 10, pp. 1313-1315,
2013
R. Wolf et al., Highly Resistive Substrrate CMOS and SOI for Wireless
Front-End Switch Applications, CS ManTech
Ma
Conference, May 16th19th, 2011. Palm Springs, CA.
C-Y Wen et al., A Phase-Change Via-Reconfigurable CMOS LC
VCO, IEEE Trans. Electron Devices, vol.
v 60, no. 12, pp. 3979-3988,
2013
N. El-Hinnawy et al., A 7.3 THz Cut-O
Off Frequency, Inline,
Chalcogenide Phase-Change RF Switch
h Using an Independent Resistive
Heater for Thermal Actuation, 2013 IE
EEE Compound Semiconductor
Integrated Circuit Symposium Digest (C
CSICS), pp. 1-4, 2013
A. Crunteanu et al., Out-of-Plane and Inline RF Switches based on
Ge2Sb2Te5 Phase-Change Material, 2014 IEEE MTT-S International
Microwave Symposium Digest, pp. 1-4, 2014
M. Wang, Y. Shim, M. Rais-Zadeh, A Low-Loss Directly Heated TwoPort RF Phase Change Switch, IEEE Electron
E
Device Lett., Vol. 35, no.
4, pp. 491-493, 2014
M. King et al., Development of Cap-Free Sputtered GeTe Films for
Inline Phase Change Switch (IPCS) Bassed RF Circuits, Journal of
Vacuum Science and Technology B, voll. 32, no. 4, pp. 041204, 2014.
S. Raoux et al., Phase transitions in Gee-Te phase change materials
studied by time-resolved x-ray diffraction, Appl. Phys. Lett., vol. 95,
pp. 143118, 2009
C. F. Campbell and D. C. Dumka, Wid
deband high power GaN on SiC
SPDT switch MMICs, IEEE MTT-S In
nternational Microwave
Symposium Digest, pp.145-148, 2010
Fabricated to a Northrop Grumman Electronic Systems design by a
commercial GaAs foundry.
M. Parlak and J. F. Buckwalter, A 2.5--dB insertion loss, DC-60 GHz
CMOS SPDT switch in 45-nm SOI, Compound
C
Semiconductor IC
Symposium (CSICS), 2011
SPDT, High Power, RF-MEMS Switch
h, DC to 40 GHz, MSW220HP
product datasheet, Radant MEMS,
http://www.radantmems.com/radantmem
ms/products.html
T. Boles et al., AlGaAs PIN diode mullti-octave, mmW switches, 2011
IEEE International Conference on Micrrowaves, Communications,
Antennas and Electronics Systems (COM
MCAS), pp.1-5.
N. El-Hinnawy et al., Low-loss latchin
ng microwave switch using
thermally pulsed non-volatile chalcogen
nide phase change materials,
Applied Physics Letters, vol. 105, no. 01, pp. 013501, 2014

Table of Contents

Low Loss, High Performance 1-18 GHz SPDT Based on the Novel
Super-Lattice Castellated Field Effect Transistor (SLCFET)
Robert S. Howell, Eric J. Stewart, Ron Freitag, Justin Parke, Bettina Nechay, Harlan Cramer,
Matthew King, Shalini Gupta, Jeff Hartman, Pavel Borodulin, Megan Snook, Ishan Wathuthanthri,
Parrish Ralston, Karen Renaldo, H. George Henry
Northrop Grumman Corporation (Electronic Systems), Linthicum, Maryland, 21090, USA
(410) 993-5094, rs.howell@ngc.com
maintaining approximately the same OFF capacitance of a
conventional HEMT, allowing for a dramatic
improvement in RF switch performance. Figure 1 shows a
representational cross-sectional view of a SLCFET that
depicts this super-lattice epitaxial structure in conjunction
with the castellated gate structure.
While a super-lattice structure has been employed to
make optoelectronic semiconductor devices [8], microcoolers [9] or as a means of reducing contact or access
resistance to a HEMT [10, 11], the use of a super-lattice in
a FET has been limited by the inability to fully turn OFF
the stacked paralleled current channels formed by the
super-lattice [12, 13], due to the screening effect the top
channels have on the bottom channels.
Using a
castellated 3D gate structure [14] (so named for their
resemblance to the crenellations on top of a medieval
castles walls) that pinches from the sides of the 2DEG
layers permits the field effect gate action to be used to
control each of the 2DEG layers formed by the superlattice. This allows the super-lattice castellated field effect
transistor (SLCFET) to take full advantage of its structure
as a high performance RF switch. This novel transistor has
been used to build broadband (1-18 GHz) single pole
double throw (SPDT) RF switches, demonstrating the
great potential of this new type of transistor topology for
high performance RF switch applications.

Abstract A low loss, high isolation, broadband RF

switch has been developed using a novel type of field effect
transistor structure that exploits the use of a super-lattice
structure in combination with a three dimensional,
castellated gate to achieve excellent RF switch performance.
Using an AlGaN/GaN super-lattice epitaxial layer, this SuperLattice Castellated Field Effect Transistor (SLCFET) was
used to build 1-18 GHz SPDT RF switches. Measured
insertion loss of the SPDT at 10 GHz was -0.4 dB, with -35
dB of isolation and -23 dB of return loss, along with a
measured linearity OIP3 value 62 dBm and a P0.1dB of 34
dBm.
Index Terms Field effect MMIC, Monolithic Microwave
Integrated Circuit (MMIC), Switches, Wideband.

I. INTRODUCTION
High performance RF switch components are vital for
the successful implementation of a variety of system
architectures, spanning the application space from phased
array radars and multi-function sensors to the wireless
components of mobile phones and consumer electronics.
While both the PiN diode [1] and RF MEMS [2]
technologies report very low loss and high isolation
relative to conventional FET switching technologies, the
low power consumption, less demanding control biasing
networks and fast switching capabilities offered by FET
RF switches remains attractive [3]. However, FET based
RF switches, including Si CMOS [4], GaAs pHEMT [5],
or InP [6] and GaN HEMTs [7] based technologies have
reported substantially higher insertion losses than the PiN
diode and RF MEMS technologies. An optimal RF switch
would achieve the superior insertion loss and isolation
performance of PiN diodes and RF MEMS with the many
attractive features of FET RF switches.
With that goal in mind, Northrop Grumman has
invented a novel field effect transistor structure, based on
a super-lattice epitaxial layer combined with a three
dimensional, castellated gate structure to achieve record
performance for FET based switch MMICs. The superlattice creates multiple current channels in parallel
between the source and drain of the device, lowering ON
resistance and the resulting RF switch insertion loss, while

978-1-4799-3622-9/14/$31.00 2014 IEEE

Source
Drain

Source
Gate

Gate

Drain

Figure 1: Representational close-up cross-section of the

SLCFET transistor structure, with close up SEM
micrographs of a 2 finger SLCFET showing the 3D gate.

228

Table of Contents

II. DEVICE/CIRCUIT FABRICATION PROCESS

III. WIDEBAND SPDT DESIGN AND PERFORMANCE

The SPDT switches reported below have been

fabricated with the baseline SLCFET process developed
by Northrop Grumman Electronic Systems. This process
is based on an AlGaN/GaN super-lattice epitaxial layer
grown using MOCVD on 100 mm diameter semiinsulating SiC wafers. The mask layers use a combination
of I-line stepper and electron beam lithography processes,
resulting in a direct written 0.25 m gate process. Passive
components provide full MMIC capabilities. Plasma
enhanced chemical vapor deposition (PECVD) SiN films
are used for both device passivation and for MIM
capacitor formation. NiCrSi is used for thin film resistor
formation, while the MMIC interconnects and matching
networks includes both Au electroplated transmission
lines and air bridges. The backside processing includes
thinning the SiC substrates to a thickness of 100 m,
followed by backside vias and an electroplated Au
metallization. The baseline SLCFET devices used in these
SPDTs exhibited a Vpinch = -8V, while their RF switch
figure of merit (FCO = 1/2RONCOFF) was measured as 1.2
THz, with an RON = 0.65 Ohm-mm and a COFF of 0.21 pFmm. This figure of merit for the SLCFET compares
favorably with state of the art FET switch technologies, as
shown in Figure 2.

The wideband 1-18 GHz SPDT switch design was based

on a linear, scalable small signal model based on
measurements from two finger FET transistors. ON and
OFF state version of the model were created from Sparameter measurements at different gate bias conditions.
In order to maximize bandwidth of the design, a seriesshunt SPDT topology was implemented, with a design
oriented around minimizing insertion loss while
maintaining a high (better than -25 dB) of isolation. Due
to the lack of a large signal model for this switch
technology at the time of the design, no attempt was made
with this design to optimize for high power handling,
though the wide bandgap nature of the underlying
AlGaN/GaN super-lattice and high current handling
capabilities give this technology an inherent advantage for
high power switching applications. A micrograph of a
representative fabricated SPDT switch, with a footprint of
1.4 mm x 1.3 mm is shown in Figure 3. The SPDT was
designed with an incorporated Line-Reflect-Line (LRL)
structure, to facilitate calibration and S-parameter
measurements. The resulting reference plane is located at
the juncture between the LRL feeds at each port and the
narrower microstrip transmission line inductors that form
the matching networks for each port. The inductors and
FET capacitances form low pass filter structures at each
RF port that minimize the insertion loss and maximize the
bandwidth associated with the resulting series-shunt SPDT
switch circuit topology.
SLCFET
SPDT
1.4x1.3 mm2

Figure 3: Micrograph of a representative SLCFET

1-18 GHz Series-Shunt SPDT MMIC.

Figure 2: RF Switch Cut-off Frequency Figure of Merit

for various FET technologies reported in the literature,
versus their respective ON resistances. The SLCFET
compares favorably to competing FET RF switch
technologies, approaching the FOM of PiN diodes and RF
MEMS. The measured SLCFET data points represent
both the baseline SLCFET design used in the reported
SPDT, as well data from a refined SLCFET device design
with lower RON that was not used in this SPDT design.

Measured small signal insertion loss, isolation and

return loss performance of this SPDT are shown in Figure
4, with a comparison to the modeled performance of the
circuit. Insertion loss ranges from -0.2 dB at the low end
of the band (2 GHz), to -0.4 dB of insertion loss at 10
GHz and -0.6 dB at 18 GHz. Measured isolation is -57 dB
at 2 GHz, -35 dB at 10 GHz and -26 dB at 18 GHz.

229

Table of Contents

Measured return loss is -32 dB at 2 GHz, -23 dB at 10

GHz and -19 dB at 18 GHz. The simulated insertion loss
and isolation for this SLCFET SPDT is a good fit with the
experimental data, with the only significant deviance
occurring with a somewhat higher measured isolation at
lower frequencies than the simulated SPDT model
predicts.

respectively. The input power was increased to the 40

dBm power limit of the testing signal generator without
damage to the SPDT being evaluated.
The linearity of the SPDT was evaluated using 2 tone
measurements around 10 GHz, with the tones located at
10 GHz +/- 0.3 MHz and 10 GHz +/- 5kHz. As Figure 6
shows, the 3rd order intermodulation products increased by
the expected 3:1 ratio. For both the +/- 0.3 MHz and +/- 5
kHz tone separations, the extrapolated third order intercept
point for the OIP3 occurs at 62 dBm.

Figure 4: Measured and modeled performance of a

representative SLCFET 1-18 GHz Series-Shunt SPDT
MMIC. Control voltages used for these measurements
were 0V for ON switches and -10V for OFF switches.
Figure 6: Measured SLCFET SPDT 3rd order intercept at
10 GHz, comparing 3:1 increase in power of 3rd order
terms against the 1:1 slope of Pin vs Pout, with an OIP3
value of 62 dBm.

The power handling and linearity of a representative

SLCFET SPDT was evaluated at 10 GHz. Figure 5 shows
the measured insertion loss as a function of the input
power at 10 GHz, for control voltages of -14V, -19V and 24V. The measured P0.1dB compression points were 31
dBm, 33 dBm and 34 dBm and measured P1dB
compression points were 34 dBm, 36 dBm and 36 dBm

Table I compared these reported SLCFET SPDT results

with SPDT results for similar frequency ranges of
differing technology bases. As this brief technology
survey indicates, the SLCFET based SPDT technology
provides a performance level with a FET that has
previously only been achieved with PiN diodes and RF
MEMS.
IV. CONCLUSION
Northrop Grumman has developed a novel transistor
topology, the SLCFET, with significantly improved RF
switch performance compared to conventional FET RF
switch performance. Using a series-shunt design, 1-18
GHz SPDTs have been fabricated exhibiting low loss,
high isolation in combination with high linearity and high
power handling.
ACKNOWLEDGMENT
The authors gratefully acknowledge R. Chris Clarke,
Harvey Nathanson and Bill Hopwood for their guidance in
developing the SLCFET technology.

Figure 5: Measured insertion loss at 10 GHz as a function

of input power, with 0V for ON switches and -14V, -19V
and -24V for the OFF switches in the series-shunt
SLCFET SPDT.

230

Table of Contents

TABLE I
BRIEF SURVEY OF SPDT SWITCHES OF VARYING TECHNOLOGIES WITH SIMILAR BANDWIDTHS

36
> 42
15

IIP3 or
OIP3
(dBm)
62
NR
NR

Chip
Size
2
(mm )
1.8
1.9
1.8

Control
Voltage
Swing (V)
14
40
1.8

NR

32

NR

2.52

47

NR

NR

NR

NR

3.5
1.9
1.2

23
29
33

NR
15
23

12.5
10
7.1

27
20
18.2

0.44
1.4
0.26

5V &
10
mA/diode
1
0.95
2.1

0.45

35

20

44

NR

170

Reference

SPDT
Technology

Frequency
(GHz)

IL (dB)
@18 GHz

Iso (dB)
@18 GHz

RL (dB)
@18 GHz

P1dB
(dBm)

This work
7
15

SLCFET
GaN HEMT
GaAs
mHEMT
GaAs
pHEMT
GaAs PiN

DC-18
DC-18
DC-35

0.6
1.5
1.7

30
25
27

19
12
NR

DC-20

1.3

42

DC-70

0.41

ABCS
SiGe HBT
45 nm SOI
CMOS
RF MEMS

DC-40
8-40
DC-60
DC-20

5
1

16
17
4
18

NR = Not reported

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5321-5325, 2003.
[11] T. Palacios, A. Chini, D. Buttari, S. Heikman, A.
Chakraborty, S. Keller, S. DenBaars and U. Mishra, Use of
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Trans. Elec. Dev., v. 53, no. 3, pp. 562-565, 2006.
[12] N.H. Sheng, C.P. Lee, R.T. Chen, D.L. Miller and S.J. Lee,
Multiple-channel GaAs/AlGaAs High Electron Mobility
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[13] D.K. Arch, M. Shur, J.K. Abrokwah and R.R. Daniels,
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Tang, R.M. Proie, RF MEMS switches for wide I/O data
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[1] T. Boles, J. Brogle, D. Hoag, and Curcio, AlGaAs PiN

diode multi-octave, mmW switches, COMCAS 2011, pp.
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RF MEMS metal-contact switches for DC-20 GHz
applications, 2011 IEEE MTT-S International Microwave
Symposium Digest, pp. 1-4, 2011.
[3] D. Gotch, "A Review of Technological Advances in Solidstate Switches-In-depth look at the technological advances
in solid-state switches, from discrete and monolithic PIN
diode switches to GaAs PIN and FET." Microwave Journal
v. 50, no. 11, pp. 24-36, 2007.
[4] M. Parlak and J.F. Buckwalter, A 2.5 dB insertion loss, DC60 GHz CMOS SPDT switch in 45-nm SOI, 2011 CSICS,
pp. 1-4, 2011.
[5] Q. Xiao, G. Samiotes, T. Galluccio and B. Rizzi, A high
performance DC-20 GHz SPDT switch in a low cost plastic
QFN package, Proc. 39th European Microwave
Conference, pp. 1673-1676, 2009.
[6] H. Kamitsuna, Y. Yamane, M. Tokumitsu, H. Sugahara and
M. Muraguchi, Low-power InP-HEMT switch ICs
Integrating 2x2 switches for 10 Gb/s systems, IEEE J.
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[7] C. Campbell and D. Dumka, Wideband high power GaN on
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High conductivity modulation doped AlGaN/GaN multiple

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1700 pixels per inch (PPI) Passive-Matrix Micro-LED Display

Powered by ASIC
Wing Cheung Chong*, Wai Keung Cho, Zhao Jun Liu, Chu Hong Wanga and Kei May Lau
Department of Electronic and Computer Engineering,
Hong Kong University of Science and Technology, Clear Water Bay, Hong Kong
a

3C Limited, 481 Castle Peak Road, Kowloon, Hong Kong

*Email: eeeddie@ust.hk, Phone: +852 2358 8843

Abstract We report the first 1700 pixels per inch (PPI)

passive-matrix blue light-emitting diodes on silicon (LEDoS)
micro-displays. By flip-chip bonding a micro-LED array onto
an ASIC display driver, we successfully fabricated a 0.19inch display with a resolution of 256 x 192, the highest ever
reported in LED-based micro-display. In addition, the
LEDoS micro-display can deliver brightness as high as
1300 mcd/m2 and render images in 6-bit grayscale. The
remarkable performance suggests the tremendous potential
of LEDoS micro-displays for portable display applications
which require high performance, small size and low power
consumption.
Index Terms Passive-matrix, light-emitting diodes on
Silicon (LEDoS), micro-display, micro-LED array, ASIC,
high resolution, flip-chip.

from the p-electrode line, leading to numerous dead pixels

in the display. Similar issues also appear in active-matrix
InGaN micro-display in which the LED array was bonded
onto the silicon side by high-density indium bumps [8]. To
improve the integrity of LED-based micro-displays, an
alternative bonding scheme which can reduce the solder
bump density is of paramount importance.
In this paper, we report, to our best knowledge, the first
1700 pixels per inch (PPI) blue passive-matrix lightemitting diodes on silicon (LEDoS) micro-displays
powered by ASIC with 6-bit grayscale, as shown in
Fig. 1. This is realized by flip-chip bonding of a microLED array onto a CMOS-based ASIC display driver. The
LEDoS micro-display consists of 256 x 192 pixels within
a display area of 0.19 inch in diagonal. In our design, all
passive-matrix interconnects are implemented on the LED
side, in sharp contrast to previous reports in which the
interconnects were done on the driver side [7]. With this
special architecture, all the solder bumps can be relocated
to the peripheral areas of the micro-LED array where the
bumps can be bigger and more spread out. At the same
time, only 448 bumps are needed for our display with
almost 50000 pixels. The huge reduction in bump density
significantly improves the bonding reliability. This novel
passive-matrix display design and bump arrangement
make high resolution and high-yield LEDoS micro-display
achievable for a variety of applications.

I. INTRODUCTION
LED micro-display has received attention recently
because of its great potential to augment other existing
micro-display technologies in the market [1]-[8]. Unlike
liquid crystal display (LCD), liquid crystal on silicon
(LCoS), and digital light processor (DLP), LED microdisplay is a self-emissive device which can generate bright
images efficiently without external light sources and lossy
optical components. While organic LED (OLED) is an
attractive alternative for micro-display applications,
semiconductor-based LED is more advantageous in terms
of brightness, lifetime, thermal stability and robustness in
extreme conditions. Development of inorganic LED
micro-displays is thus highly desirable.
Despite all the attractive advantages, it is challenging to
achieve high-resolution inorganic LED micro-displays
with high pixel yield. An et al. demonstrated a passivematrix micro-LED array structure by flip-chip bonding of
a gallium nitride (GaN) micro-LED array on a silicon
submount with common p-electrode stripes [7]. In their
design, each pixel in the micro-LED array is connected to
the common p-electrode stripes via an individual solder
bump. Due to the large thermal mismatch between GaN
and silicon, severe bonding failures occur in the closely
spaced bumps. Many pixels are physically disconnected

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Fig. 1. Passive-matrix LEDoS micro-display wire-bonded on

a flex cable.

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Table of Contents

II. MICRO-LED ARRAY FABRICATION

p-electrode stripes. The final structure of the passivematrix micro-LED array is illustrated in Fig. 2(e). The pelectrode stripes were defined on top of the transparent
resist and connected to all the pixels in the same row.

The blue passive-matrix micro-LED arrays were

fabricated on blue epi-wafers with peak wavelength
2
460 nm, respectively. The chip size was 5.1 x 4.5 mm
2
with a display area of 3.8 x 2.9 mm , consisting of 256 x
192 pixels. The fabrication process of micro-LED arrays
is shown in Fig. 2.

III. ASIC ARCHITECTURE

Fig. 3. Block diagram of the ASIC display driver for driving

the passive-matrix micro-LED array.

Fig. 2. Schematic of passive-matrix micro-LED array in each

processing step. (a) Formation of isolation trenches;
(b) Patterning of pixels and evaporation of p-type ohmic
contacts; (c) N-electrode stripes definition; (d) Patterning of
transparent polyimide; (e) P-electrode stripes definition.

LED pixels of the micro-LED array in the same column

share a common electrode of the n-type GaN. Thus it is
necessary to isolate all column stripes of micro-LED array.
This is realized by creating isolation trenches via dry
etching of GaN down to the sapphire substrate (Fig. 2(a)).
Individual pixels were defined by standard photolithography. The photoresist pixel patterns were then
transferred to GaN by dry etching down to the n-type GaN
layer. After that, tin-doped indium oxide (ITO) was
selectively deposited on top of the pixels to form p-type
ohmic contacts, as shown in Fig. 2(b). Ohmic
characteristic was achieved after rapid thermal annealing.
As shown in Fig. 2(c), n-electrode stripes were defined on
the n-type GaN layer. Passivation and isolation were done
by conformal coating of a thick photo-patternable
transparent polyimide over the whole epi-wafers, as
shown in Fig. 2(d). Contact holes were opened later to
expose the p-type ohmic contacts for subsequent wiring of

233

ASIC display drivers were fabricated at SMIC with

0.18 m CMOS technology. Fig. 3 shows the architecture
of the ASIC driver. The data processing unit reads data
and control signals from an external microcontroller and
writes the data into the RAM. The pulse frequency
modulation (PFM) generator then reads the data from the
RAM in sequence and generates 256 PFM driving signals
to the 256 columns of the micro-LED array through the
data driver. Finally, data driver and scan driver power the
passive-matrix micro-LED array by giving enough control
voltage to turn pixels on and off.

Fig. 4

Timing diagram of PFM signals generated by ASIC.

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Fig. 4 shows the waveforms of different gray levels

generated by the ASIC display driver. Symbol f is the
frame rate. The pulse frequency of each pixel depends on
its grayscale. The PFM generator can create 6-bit
grayscale to provide more satisfactory display quality. The
whole system operates at 48 MHz and can display 16
frames per second at maximum.

IV. INDIUM BUMPING AND FLIP-CHIP PROCESS

Indium is used as a medium to electrically connect all
electrode pads between the ASIC display driver and
micro-LED array. As shown in Fig. 7(a), indium plates
were deposited and formed on electrode pads of the
micro-LED array by thermal evaporation and lift-off
process. To form ball-shaped indium as shown in Fig.
7(b), the micro-LED array with indium plates were put
into a reflow furnace at 220C for 1 minutes in a formic
acid ambient. After the indium bumping process, the
micro-LED array was flip-chip bonded onto the ASIC
display driver to form passive-matrix LEDoS microdisplays as shown in Fig. 7(c). The alignment accuracy of
the flip-chip bonder is 1m.

Fig. 5. Schematic of interconnects between ASIC display

driver and micro-LED array.

Fig. 5 displays the schematic of interconnects between

the ASIC display driver and micro-LED array. In this
passive-matrix driving scheme, the LEDs on the same
column are driven at different times. Data driver provides
256 PFM signals and the scan driver selects each row in
sequence by providing high voltage (>3V) to LED pixels
in the same row through the p-electrode stripes. Top views
of ASIC display driver and micro-LED array are shown in
Fig. 6. A total 448 electrode pads were allocated near the
periphery of the micro-LED array for flip-chip bonding.

Fig. 7. Microscopic images of micro-LED array with

(a) indium plates; (b) indium balls after reflow; (c) pressed
indium after flip-chip bonding onto the ASIC display driver.

V. RESULTS
The brightness of blue LEDoS micro-displays was
measured by a Spectrascan colorimeter. The maximum
brightness of the LEDoS micro-displays was measured to
2
be 1300 mcd/m , at an average injection current of 20mA
to the passive-matrix micro-LED array. The total power
consumption of the micro-display is only 0.6W. The
operating temperature of the LEDoS micro-display ranges
from -55 to 125 C, tested in Votsch thermal cycling
chamber, demonstrating the robustness in harsh
environment.
Fig. 8 shows the display quality of the blue LEDoS
micro-displays. Images can be clearly rendered in the
LEDoS micro-display. Advantages of 1700 PPI and 6-bit
grayscale make the display more powerful in high

Fig. 6. Top views of ASIC display driver (left) and 256 x 192
micro-LED array (right) before flip-chip bonding.

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Fig. 8.

Source files (top) and its corresponding display images (bottom) shown in the blue LEDoS Micro-displays.

resolution image reconstruction. It demonstrated that the

proposed passive-matrix LEDoS micro-display has
tremendous potentials for portable display applications
which require high performance, small size and low power
consumption.

REFERENCES
[1] Z. J. Liu, K. M. Wong, C. W. Keung, C. W. Tang, and
K. M. Lau, Monolithic LED microdisplay on active matrix
substrate using flip-chip technology, IEEE J. Sel. Topics.
Quantum Electron., vol. 15, no. 4, pp. 1298-1302,
July/August 2009.
[2] C. W. Jeon, H. W. Choi, and M. D. Dawson, Fabrication
of matrix-addressable InGaN-based microdisplays of high
array density, IEEE Photon. Technol. Lett., vol. 15,
no. 11, pp. 1516-1518, November 2003.
[3] C. W. Jeon, H. W. Choi, E. Gu, and M. D. Dawson, Highdensity matrix-addressable AlInGaN-based 368-nm
microarray light-emitting diodes, IEEE Photon. Technol.
Lett., vol. 16, no. 11, pp. 2421-2423, November 2004.
[4] W. C. Chong, K. M. Wong, Z. J. Liu, and K. M. Lau, A
novel full-color 3LED projection system using R-G-B light
emitting diodes on silicon (LEDoS) micro-displays, in SID
Symp. Dig. Tech. Papers, vol. 44, issue. 1, pp. 838-841,
June 2013.
[5] Z. J. Liu, W. C. Wong, K. M. Wong, and K. M. Lau, 360
ppi flip-chip mounted active matrix addressable light
emitting diode on silicon (LEDoS) micro-displays, J. Disp.
Technol., vol. 9, no. 8, August 2013.
[6] C. W. Sun, C. H. Chao, H. Y. Chen, Y. H. Chiu, W. Y. Yeh,
M. H. Wu, H. H. Yeh, and C. C. Liang, Development of
Micro-Pixellated GaN LED Array Micro-Display System,
in SID Symp. Dig. Tech. Papers, vol. 42, issue. 1, pp. 10421045, June 2011.
[7] C. C. An, M. H. Wu, Y. W. Huang, T. H. Chen, C. H. Chao,
and W. Y. Yeh, Study of flip chip assembly of high
th
density micro-LED array, in 6 Int. Microsyst., Packag.,
Assembly, Circuits Technol. Conf. (IMPACT), pp. 336-338,
October 2011.
[8] J. Day, J. Li, Y. C. Lie, C. Bradford, J. Y. Lin, and
H. X. Jiang, III-Nitride full-scale high-resolution
microdisplays, Appl. Phys. Lett,. 99, 031116, 2011.

VI. CONCLUSION
1700 PPI passive-matrix blue light-emitting diodes on
silicon (LEDoS) micro-displays were fabricated by flipchip bonding of micro-LED array onto ASIC display
driver chips. Outstanding performance of LEDoS microdisplays demonstrated that the novel passive-matrix
design and bump arrangement can make high resolution
and high-yield LEDoS micro-display achievable for a
variety of applications.
ACKNOWLEDGMENT
This work was supported in part by a grant from the
Research Grants Council (RGC) of the Hong Kong
Special Administrative Government (HKSAR) under the
heme-based Research Scheme (T23-612/12-R). The
authors want to thank the HKUST Nanoelectronics
Fabrication Facility (NFF), Electronic Packaging
Laboratory (EPACK), Suzhou Institute of Nano-tech and
Nano-bionics (SINANO), Chinese Academy of Science,
Prof. Anthony H.W. Choi, and Prof. Chun-Sing Lee for
their facilitation and EPISTAR Corporation for the epiwafers. Special thanks to Dr. K. W. Ng and R. Q. Zhu for
useful discussions.

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Programmable Active Clock Spine for 100Gb/200Gb Coherent

Optical Receiver Chip in 32nm CMOS
Naim Ben-Hamida, Christopher Kurowski, Robert Gibbins, Junxian Weng, Ted Wong, John Lindsay, Harvey Mah,
Sadok Aouini, Andrew McCarthy
Ciena Corporation, Ottawa, Ontario, K2H 8E9, Canada, DA-Integrated, Ottawa, Ontario, K2S 1E6, Canada
E-mail:nbenhami@ciena.com
elements require testing, but the overall ATPG-based SCAN
test methodology could not be adversely affected.
Rather than synthesizing one large clock tree from a single
point, the clock is distributed over a transmission line with
minimal delay to multiple points (drops) throughout the ASIC
and then synthesizes smaller clock trees starting from each of
these drops, Figures 1, 2. The method for distributing the
source clock to multiple points is defined as a clock spine. As
shown in Figure 2, the clock spine is composed of a fractional
PLL for clock generation, a transmission line, and an AllDigital DLL (ADDLL) for clock alignment. Figure 1 shows a
picture of the coherent receiver; the various clock spines are
the yellow traces and dots on top of the digital core in blue.

Abstract This paper describes an active clock

distribution network for a 100G/200G coherent optical
receiver. The chip has more than 1 billion transistors
implemented in 32nm CMOS bulk technology with 11
metal layers. The active clock spines enabled a low-skew,
low jitter, and low power clock distribution solution. In
addition, a debug-friendly clocking environment provides
easy observability, testing, and reconfiguration features;
hence, enabling rapid time to market.

KeywordsClock generation; DLL; DFT

I. INTRODUCTION
Global IP traffic is predicted to increase by 23% per year
between 2012 and 2017 [1]. This growing demand, together
with a minimum transmission cost imperative, have spurred the
development of optical transmission technologies designed to
make most efficient use of available spectrum. Electric field
modulation and coherent detection are chief among these. They
rely heavily on digital signal processing (DSP) and require
conversion between analog and digital domains [2]. Cost
reduction drives designs to the largest practical symbol rate
with optimum power performance tradeoff, as determined by
electro-optic and CMOS technologies. These flexible optical
transceivers are software-programmable allowing various
transmission schemes or modulation formats, data rates, FEC
protocols, and number of subcarriers to be configured. This
allows best use of the available channel bandwidth. For
example, capacity might be traded for reach based on
modifying the amount of information placed on a carrier. Such
flexible transceivers are also referred to as software-defined
optics (SDO). DACs, ADCs, DSP, and FEC are at the heart of
flexible transceivers. Clock generation and distribution agility
is one of the key enabling features for the coherent receiver
ASIC used in the SDO and is the focus of this paper, Fig 1.
This paper is organized as follows: Section II presents the
clock spine architecture and its major building blocks. Section
III describes how DFT is implemented within the spine.
Section IV shows the experimental results and compares the
presented clock spine to other published clock distribution
techniques with some concluding remarks.

A. Clock generation
The source of the spine is a high speed programmable clock
(1.2GHz to 2.5GHz), generated from a fractionally
programmable PLL. The PLL uses Dual LC tank VCOs
covering a frequency range from 14.4GHz to 18.9GHz. The
programmability of the frequency is produced by two
programmable dividers, one on the feedback path while the
other is on the clock output. The produced frequency ranges
from 52MHz to 393MHz while the target range is 150MHz312.5MHz. The output produced by the PLL is a pair of
differential quadrature clocks at 8 times the target frequency.
A low speed clock is embedded in the high speed quadrature
clock for the purpose of synchronizing the divide-down
counters across all drops.

II. CLOCK SPINE ARCHITECTURE

The clock spine provides the ability to align clock trees of
different depth, and/or shift clocks in relation to each other. It
also provides a solid test strategy because not only did the new

978-1-4799-3622-9/14/$31.00 2014 IEEE

Fig. 1. Image of the Coherent Rx chip layout, showing the active clocks
spine as yellow traces and dots on top of the blue digital core

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time horizontal clock spines provide 42 clock tree synthesis

points both above and below each spine.

Fig. 4. Transmission line layout

Fig. 2. Clock spine top level block diagram

B. Clock distribution
Figure 3 shows the clock generation and transmission line
based distribution. The transmission lines are micro-strip
lines.
Fig. 5. Transmission line insertion loss and return loss

C. All-Digital DLL
At each drop, a digital delay lock loop (DLL) actively
aligns the clock and removes the insertion, Figure 6. The
purpose of such a system is to reduce the amount of uncertainty
in the placement of final clock edges and therefore easing the
task of meeting timing requirements during the design phase.

Fig. 3. Clock generation and distribution

The spine clocks are sent over two differential transmission

lines. The transmission line uses the top AP layer (M11) over
M10, M9 with 4um width and 2um gap. The distance between
differential pairs is 16um and 14.1um to bump, as depicted in
Figure 4. The transmission line has a differential impendence
of 67 Ohms, a propagation delay of 7.5ps/mm, and 1.85dB loss
per 9mm at 1.6GHz, Figure 5. The transmission line drivers are
powered from the digital core supply and their strength is
digitally adjustable through programmable current sources. As
shown in Figures 2,3, a clock source within the macro is
distributed vertically using a clock spine. Two balanced-in-

Fig. 6. ADDLL block diagram

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ADDLL drops are interposed between the traditionally

synthesized clock trees (which can be of different insertion
delay) and the clock spines. The ADDLL drops are used to
align tree end clocks across all the synthesized clock trees to
within +/-5ps, Figure 6. For the purpose of staggering the
clocks and improving timing handoff margin, the reference
clock is also adjustable over a full clock cycle in 10ps steps.
The ADDLL bandwidth is programmable up to 500 kHz
through a digitally controlled integrating (Ki) loop allowing
faster tracking, Figure 7.
Fig. 10. Phase rotator DAC linearity. I & Q currents as a function of time
where a ramp is applied to the DAC input code.

Fig. 7. Digital filter

Fig. 11. 6-bit DAC mismatch simulation, LSB=4.6uA and Sigma=0.586uA

Each ADDLL receives a 1.6GHz differential CML clock

and a gapped clock. The 1.6GHz clock is divided down by 8
using a Johnson counter to produce 16 phases. The phase
interpolator (PI) interpolates between two adjacent phases in
10ps steps and generates an offset clock. The interpolation is
done by changing the weighting factors for I and Q
components of the analog mixer, Figure 8.

The phase detection is performed with a Bang-Bang phase

detector. It produces a 3 bit output used to decode an early,
late and on time states, Figure 12. The speed up of the
acquisition time is obtained by increasing the phase stepping
size based on the phase detector output. The phase detector
meta-stability is mitigated by multiple retime stages and error
detection. If a metastable condition is detected, the phase error
will be discarded. The low-pass digital filter consists of a 16bit accumulator that takes a phase error signal from the decode
block with the 3-bits KI input. The 3-bits KI input controls the
scaling of the error and directly affects the lock time and
bandwidth of the DLL, Figure 7. The accumulator output is
decimated by 16 to meet the analog interpolator DAC settling
time requirement of 20MHz or less. A maximum change of the
decimated accumulator value is limited to +/-3 steps, if the
difference between the new accumulator value and the
previous one is more than +/-3 steps the accumulator is
considered corrupted and is reversed back to the previous
accumulator value. The filter can be disabled so that the
accumulator output can be held constant or to allow the
firmware to control the accumulator value and adjust the
CMOS clock tree phase via input increment decrement pins.

Fig. 8. Phase Interpolator schematic

The step size of the resulting output clock phase is

controlled by the custom DAC which is linearized to produce
the required 10ps resolutions, Figure 9-11.

Fig. 12. Bang-Bang phase detecor with metastability detector

Fig. 9. Phase interpolator schematic

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chip to another, it is nearly impossible to balance the clock tree

using standard clock trees. The clock spine allowed the
reduction of the clock insertion delay from 6ns to ~1ns leading
to 6 time reduction of OCV (over corner and voltage) variation.
It also allowed improved timing handoff margin; reduced
timing closure cycle, and power reduction by clock staggering.
The clock spine enabled built-in diagnostic and self-test for
clock quality and skew assessment, Figure13. Standard stuck at
and TDF test were enabled through the insertion of a testergenerated low speed clock as a gap in the high speed clock
transmitted over the transmission line. The clock spine is fully
integrated in the digital flow and uses digital core supply.

III. DFT INSERTION

The spine analog delay elements introduced into the clock
tree drops do not fit with the traditional SCAN clock test
scheme which needs a mix of low-speed, at-speed, and dropped
clock pulses. To circumvent this, a low-frequency-only SCAN
clock supplied by the ATE tester is multiplexed with the onchip produced mission mode clock source to produce the
overall SCAN clock. DFT controls are broadcast to all DLL
blocks simultaneously allowing both parallel and serial modes.
Manual and automatic timing control modes are also supported
during SCAN mode.

The following novel methodology was developed:

The SCAN clock is embedded in the high frequency (8X
mission rate) spine transmission line gapped mission
mode clock
The low frequency SCAN clock is regenerated in each
drop point with a local divider placed after the analog
delay element; the gapped clock provides observability to
ensures that all SCAN dividers are synchronized with the
tester SCAN clock;
The SCAN clock dividers are part of the clock tree path
and their delay is nullified as part of the feedback process;
An intelligent multiplexor [5] selects between the base
regenerated SCAN clock, the mission mode clock for
TDF loads, or no clock (dead cycles); all under ATPG
control. Also, during special cycles the feedback loop
correction logic holds its current state;
Only two extra chip I/Os (low-frequency or DC) are
needed.

Table 1: De-skew comparison between different techniques

Authors

Clock
zones

Skew
before

Skew
after

Step size

GeannopoulosISSCC-98

60ps

15ps

12ps

Rusu
ISSCC-00

30

110ps

28ps

8ps

Kurd

47

64ps

16ps

8ps

Stinson
ISSCC-01

23

60ps

7ps

7ps

This work

42

500ps

10ps

10ps

Furthermore, for debug purposes, the reference and feedback

clocks are captured using a built-in sample scope. This
provides a convenient way to debug inter-domain speed paths,
Figure 13.
IV. EXPERIMENTAL RESULTS AND CONCLUSION
The active spine provided a clock to a 130 Million-gates
coherent receiver chip. The chip size is 17.5mm x 18.5mm
packaged in 42.5mm x 42.5mm MCM organic package. The
area occupied by the clock spine is around 2% of the total area
and the power is in the order of 3% of the total power. The
power number compares very well with the 7% clock spine
power consumption for microprocessors [4]. Table 1 shows a
comparison between de-skew techniques. Given the uneven
density of the logic in our chip, the skew between clocks
without a clock spine is an order of magnitude higher than the
one achieved by the active spine [3][4]. The results showed
that all the ADDLL drops are aligned within 1 phase step,
Figure 13.

Fig. 13. Sample scope of the DLL clocks and Scan/TDF clocks

REFERENCES
[1]

[2]

[3]

We presented a transmission line-based clock spine with

tunable active clock tree. The tuning is enabled by fully digital
DLLs with zero clock tree depth and programmable clock
phase with a resolution of 6ps to 12ps steps. The clock domain
was divided into 42 segments with zero clock tree depth. Due
to the difference in the density of the logic from one area of the

[4]

[5]

239

Cisco Visual Networking Index: Forecast and Methodology, 2012-2017

(http://www.cisco.com/en/US/solutions/collateral/ns341/ns525/ns537/ns
705/ns827/white_paper_c11-481360.pdf).
Y. M. Greshishchev, J. Aguirre, M. Besson, R. Gibbins, C. Falt, P.
Flemke, N. Ben-Hamida, D. Pollex, P. Schvan, and S.-C. Wang., A
40GS/s 6b ADC in 65nm CMOS, in IEEE Int. Solid-State Circuits
Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, 2010, pp. 390391.
S. Kurd, Microprocessor Clocking Architecture, in IEEE Int. SolidState Circuits Conf. (ISSCC) FORUM, San Francisco, CA, 2013..
Simon Tam et al, Clock Generation and distribution of a dual Core
Xeon Processor with 16MB L3 cache, in IEEE Int. Solid-State Circuits
Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, 2006.
R. Press et al., Easily Implement PLL Clock Switching for At-Speed
Test, Chip Design Magazine, Feb./Mar. 2006.

Table of Contents

A 7-8 GHz serrodyne modulator in SiGe for MIMO signal generation

Johan C. J. G. Withagen , A. J. Annema , B. Nauta , F. E. van Vliet

University of Twente, Enschede, 7500 AE, Netherlands, +31 53 486 2644, j.c.j.g.withagen@utwente.nl

TNO, The Hague, 2509 JG, The Netherlands, +31 88 86 61 058, frank.vanvliet@tno.nl

AbstractAn 8-bit 360 sawtooth modulated phase shifter is

used to apply very small frequency offsets to RF signals between 7
and 8 GHz. Offsets between 6 Hz and 10MHz can be obtained.
Such frequency offsets can be used to generate orthogonal signals,
which are required in e.g. MIMO applications. Each undesired
frequency component is suppressed to below -30 dBc. The phase
modulator is realized in a 250 nm SiGe BICMOS technology.
Index TermsPhase Modulation, Radar, BICMOS intgrated
ciruits, MIMO

I. I NTRODUCTION
Multiple Input Multiple Output (MIMO) radar transceivers
[1], [2] require the generation of orthogonal signals. Orthogonality can be achieved by generating unique small frequency
offsets at every array element. The simplified radar concept
in Fig. 1 contains element-level waveform control, in this
case a time-dependent frequency translation fN (t) in the
RF domain. Mixers can perform this function, but would
generate many harmonics and inter-modulation products near
the carrier, since fN fLO . Another issue of mixers is LO
leakage to the output signal. In contrast, using a linear phase
shift to change the frequency does not produce images and
harmonics in band. It also minimizes LO leakage. In this paper
a circuit is presented that can accomplish frequency shifts,
based on linear phase shifting [3] which is suitable for this
task.
II. C ONCEPT
Modulating the phase (t) of a sinusoid linearly in time (i.e.
(t) = k t), translates the angular frequency of this sinusoid
by k:
vout (t) = V sin(in t + (t)) = V sin((in + k)t).

(1)

The resulting angular frequency out of the output signal is

then a shifted version of the input frequency, out = in + k.
As phase is periodic in 360 , a linearly increasing phase is
equivalent to a sawtooth-shaped phase with a 360 amplitude;
this latter is used in this paper. By replacing (t) = k t by
any continuous function, any frequency translation or chirp,
linear and non linear, can be generated. To obtain the phase
shift, 1st order All Pass Filters (APFs) are used, each with the
following transfer function [4]:
H(j) = 2

1 j 0
1

1
=
1 + j 0
1 + j 0

(2)

The amplitude and phase transfer of these APFs are given by:

Fig. 1: Simplified time-multiplexed N-element MIMO pulsed radar

array, with per-element waveform control, fN (t).
|H(j)| = 1 , H(j) = 2 arctan

(3)

The phase shift range of such APFs is theoretically 180 ;

in practical designs less than 180 . To shift 360 at least
3 APFs are needed. For symmetry purposes an interleaved
combination of 4 APFs is used to achieve 360 , requiring 90
tuning range per APF. By adding two cross-bar switches, the
differential structure of the phase shifter can be exploited to
reduce the number of APFs to 2. Together with a polyphase
filter and an output switch, a 360 phase shifter is obtained.
The phase shifter structure is given in Fig. 2. Path A shifts
phase from 0 to 90 and 180 to 270 and Path B shifts
phase from 90 to 180 and 270 to 360 . In Fig. 3 phase
sweeps to get a static frequency translation are plotted versus
time. The output switch switches when the phase of signals
from both APFs are equal, in order to prevent spurs by phase
jumps. This is ensured by a period of time in which both
tune sweeps overlap. The switches are implemented as soft
switches. Combined with summing in the current domain,
this results in the interpolation of phase errors. The crossbar switches switch while the other APF is connected to the
output, thus minimizing its influence on the output.

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Table of Contents

in

out

Fig. 2: Structure of the 360 interleaved phase shifter.

360

Fig. 4: Die photo. Chip measures 1.6mm x 1.6mm.

90

LPF

Input

-1

Output

Invert A
90

,
0
`

Invert B
LPF

Output
switch

Fig. 3: Phase shifter A and B are tuned and used interleaved in time

to create a 360 phase shifter. The blue areas indicate where phase
shifter A and B have the same output phase. The switches Invert
A and Invert B switch when they are not connected to the output
via Output switch.

-1

III. C IRCUIT I MPLEMENTATION

Fig. 5: Circuit implementation of the APF; blue insets represent the

The circuit is implemented in a 0.25 m BICMOS technology

with Si-Ge bipolar hetero junction transistors (HBTs) with a ft
of 180 GHz; a die photograph of the chip is shown in Fig. 4.
At the input a wide band 7-12 GHz polyphase filter is used
to create a differential quadrature signal from the differential
input signal. The four quadrature signals are fed to the two
APFs, see Fig. 2; the architecture of an APF is shown in Fig. 5.
The input signal of the APF drives both its differential pairs.
The leftmost differential pair is biased at twice the bias current
of the rightmost differential pair to achieve a gain ratio of 2:1.
The negative gain in the right hand side part is implemented
by swapping the input signal compared to the left-hand side.

The Low Pass Filter (LPF) is implemented by a gm-C filter

created by the cascode transistors transconductance gm and
by a capacitance C between the cascode transistors emitters.
Tuning the collector current itune + iC,dif f pair of the cascode
transistors, their transconductance is changed and therefore the
m (t)
, is tuned. With (3)
cutoff frequency of the LPF, 0 = gC(t)
this yields

parts described in (2) and shown in the top level overview of the
APF in the top right corner. The red box indicates the capacitance
compensation circuit.

241

241

(t) = 2 arctan

C(t)
.
gm (t)

(4)

Table of Contents

HBTs are used in the APF, whose transconductance gm is

ideally given as
gm (i) =

i(t)
.
Vt

(5)

Here i(t) represents the time dependent collector current

through the device and Vt is the thermal voltage kbqT . The
capacitance in (4) is mainly composed of capacitor C0 and of
the base-emitter junction capacitances of the cascode transistors; the latter are by good approximation linearly dependent
on the collector current: Cbe (iC ) iC . The circuit can
be operated both linearly for small input signals and can use
large signals which essentially utilizes the differential pairs
as current commuting switches. The resulting behavior and
equations are similar. For simplicity reasons, the analyses in
this paper assume linear operation. Then (4) can be rewritten
as:
(t) = 2 arctan

Vt (2 C0 + (itune (t) + itail ))

(6)
itune (t) + itail

which can be rewritten into an equation that describes the

heavily non-linear relation between itune (t) and (t):


Vt 2C0 tan (t)
2
 itail

itune (t) =
(7)
(t)
1 Vt tan 2
Equation (7) shows that the current dependency of the baseemitter capacitance of Q1 , Cbe,Q1 , results in relatively large
required itune (t) ranges, which is to a large extent due to the
current dependency of the Cbe of the cascode transistors. In our
design this dependency is compensated by the circuitry within
the red box in Fig. 5. Here, an extra transistor, Q2 , is added and
connected via its base to the emitter node of the corresponding
cascode transistor. Operating this Q2 at IC,Q2 = Iconstant
IC,Q1 with for example Iconstant = itail , the capacitance C(t)
in (4) becomes:
C1 (t) = 2C0 + (itail + itune (t) + itail itune (t))
= 2C0 + 2itail
Using this, (7) reduces to
itune (t) = Vt C1 tan

(t)
2

(8)


itail

(9)

Many (t) shapes can be constructed, all requiring a different itune (t). To get a constant frequency shift, linear phase
modulation (t) = kt is required resulting in
 
kt
itail
(10)
itune (t) = Vt C1 tan
2
In the actual circuit design, the cascode stage in Fig. 5 is
implemented twice in parallel and is operated as a Gilbert Cell.
This effectively implements the crossbar switches A and B
that provide the 180 phase shift as required for the system in

Fig. 6: Half of the left hand side part of the LPF in Fig. 5: the
impedance seen at the emitter of Q1 is composed of the 1/gm of Q1
together with the reactance due to Cbe,Q1 , Cbe,Q2 and 2C0 which is
itune -independent if i1 + 12 i2 = constant.
Fig. 2. Relatively slow switching is used to suppress switching
spurs. The output switch in Fig. 2 is also implemented as a
slow switching Gilbert Cell. Degenerated bipolar differential
pairs are used to create the itune currents required for both
the cascode circuitry and for the Cbe -compensation circuitry
from externally applied differential vtune voltages.
IV. M EASUREMENTS
The measured (vtune ) behavior of the two APFs in the
inverting and non-inverting state at a signal frequency of 7
GHz is shown in shown in Fig. 7. For this measurement, the
phase shift of the chip was measured using a vector network
analyzer and the tune signals were provided by a 14-bit Digital
Analog Converter (DAC) of which 8 bits are effectively used to
drive the IC. Figure Fig. 7 shows that at 7 GHz the system can
shift a full 360 which allows frequency translation. To create
a fixed frequency translation, f , the (vtune ) characteristic
in Fig. 7 is inverted to get vtune () = vtune (f t) which
voltage was generated by the DAC. For an input signal at 7
GHz and a f = 5.5kHz the resulting phase error across one
sawtooth period is shown in the before calibration curve in
Fig. 8. The phase error, , is used to calibrate the phase
shifter by adapting the vtune as:

 1 
vtune

(11)
vtune =
t
t
The resulting one-pass calibrated phase error is depicted by
the after calibration curve in Fig. 8. The measured spectrum
of the output signal for the calibrated phase shifter, shifting
the 7 GHz input signal by 5.5 kHz, is shown in Fig. 9. A
number of unwanted spurs is visible near the carrier; the
strongest of these is the third harmonic spur at -30.8 dBc.
Three effects are identified as most dominant in spurious
creation: 1) phase-dependent gain of the APF causes amplitude
modulation (AM); 2) switching causes phase jumps as shown
in Fig. 7 and 3) a small second harmonic oscillation remains
in the phase error after calibration. The first mechanism is due
to an inexact gain ratio between the leftmost and the rightmost

242

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Table of Contents

differential pair in the APF; this gain ratio ideally is 2:1. In

the current setup this mechanism results in the -30.8 dBc third
harmonic spurs. The phase jumps are mainly due to insufficient
isolation in the circuit and bond wire inductances which result
in -68 dBc third harmonic spurs according to measurement
and simulation. And finally the second order oscillation in the
phase error produces -76 dBc third harmonic spurs.

notQ
notI
Q
I

Phase shift [degree]

360

270

180

Fig. 9: Measured output spectrum for an input signal of 7 GHz,

translated by 5.5 kHz.

90

TABLE I
C OMPARISON TABLE
0
0.5 0.4

0.3 0.2

0.1

0
0.1
Vtune [V]

0.2

0.3

0.4

Technology
Bandwidth
phase shifter bits
highest spurs

0.5

Fig. 7: All four states of the 360 phase shifter characterized by a

quasi DC sweep.

Measured phase error of phase modulator

before calibration
after calibration

1.5
phase error >degrees@

[6]
MMIC FET
6-18
5
-22

This work
SiGe
7-8
8
-30.8

GHz
dBc

determined by either the control signal programmed in a DAC

or by its sampling frequency. By changing the linear slope
of the phase modulation into e.g. a quadratic one a linear
chirp could be generated. The systems operating frequency
of the current design is lower limited by the polyphase filter
and upper limited by the cutoff frequency of the APFs. The
Spurious Free Dynamic Range (SFDR) is limited by amplitude
modulation. Simulations, using phase measurement data as
shown in Fig. 8, show that suppressing this AM could result
in a 30 dB SFDR improvement.

2.5
2

[5]
wavetubes
8.5-9.5
4
-23.7

1
0.5
0

VII. ACKNOWLEDGEMENTS

0.5
1
1.5
0

SKDVHVKLIW>GHJUHHV@

0

Fig. 8: The phase error before and after calibration of one sawtooth
period stretching 360 averaged 30 times measured with a vector
network analyzer.
V. C OMPARISON WITH OTHER WORK
As the authors are not aware of previous publications of
these type of circuits for MIMO applications and a focus to
translate a small frequency with low spurs, a comparison is
made with phase modulators in Table I.
VI. C ONCLUSIONS
A system that uses linear phase modulation to create a
relatively small continuous frequency translation of an RF
carriers was presented. The frequency shift can accurately be

The authors would like to thank Jasper Velner and Gerard

Wienk for their support during the design process, and Henk
de Vries and Dirk-Jan van den Broek for measurement support. NXP Semiconductors N.V. is acknowledged for donating
silicon and providing models.
R EFERENCES
[1] E. Fishler, A. Haimovich, R. Blum, D. Chizhik, L. Cimini, and R. Valenzuela, Mimo radar: an idea whose time has come, in Radar Conference,
2004. Proceedings of the IEEE, 2004, pp. 7178.
[2] D. Rabideau, Doppler-offset waveforms for mimo radar, in Radar
Conference (RADAR), 2011 IEEE, May 2011, pp. 965970.
[3] E. Rutz and J. Dye, Frequency translation by phase modulation, in
WESCON/57 Conference Record, vol. 1, 1957, pp. 201207.
[4] K. Bult and H. Wallinga, A cmos analog continuous-time delay line
with adaptive delay-time control, Solid-State Circuits, IEEE Journal of,
vol. 23, no. 3, pp. 759766, June 1988.
[5] G. Klein and L. Dubrowsky, The digilator, a new broadband microwave
frequency translator, Microwave Theory and Techniques, IEEE Transactions on, vol. 15, no. 3, pp. 172179, Mar 1967.
[6] S. Mitchell, J. Wachsman, G. Lizama, F. Ali, and A. Adar, A wideband
serrodyne frequency translator, Appl. Microwave, pp. 325330, 1990.

243

243

Table of Contents

A Highly Integrated Chipset for 40 Gbps Wireless D-band

Communication Based on a 250 nm InP DHBT Technology
Sona Carpenter, Zhongxia He, Mingquan Bao*, Herbert Zirath*

Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience, Chalmers

University of Technology, 412 96 Gteborg, Sweden
*

Ericsson Research, Ericsson AB, Gteborg, SE-41756, Sweden

Abstract A highly integrated chipset comprising a

transmitter (TX) and a receiver (RX) chip, based on a 250
nm InP DHBT technology for high data rate D-band (110-170
GHz) wireless communication is described. The chipset is
designed for point-to-point wireless communication for 4G
and 5G mobile communication infrastructure, high data rate
backhaul, low-latency wireless HDTV transmission and >40
Gbps transmission over dielectric waveguide. The measured
RX conversion gain is 26 dB, with a noise figure of 9 dB. The
measured TX conversion gain is 20 dB. A maximum QPSK
data rate of 44 Gbps is demonstrated, which exceeds the
present state-of-the art in the D-band by a factor of 2.
Index Terms InP DHBT, D-band, RX/TX, wireless
communication, BPSK, QPSK.

spectrum efficiency is of the order 1 bit/s/Hz in this case.

We have previously demonstrated an integrated frontend
[3] working at 220 GHz including an on-chip antenna. A
data rate of 12.5 Gbps was demonstrated in lab
environment over a relatively short distance, utilizing a
NRZ pulse train. Wireless communication over a distance
of 10 m with 25 Gbps data rate, was recently
demonstrated at 220 GHz [4] with OOK. 40 Gbps at 240
GHz with BPSK was exhibited in [8]. The presented work
is a demonstration of a chipset intended for use in the Dband for high-data rate communication.
II. DESIGN OF THE D-BAND RX/TX CHIPSET

I. INTRODUCTION
Radio communication at millimeterwave frequencies
such as the 60 GHz ISM-band and the E-band (71-76 and
81-86 GHz) has become an attractive alternative for data
communication as an alternative to optical fiber due to
the smaller installation cost, especially in urban areas.
While the 60 GHz band and E-band has attracted
commercial vendors, leading to products on the market,
commercial low-cost solutions for applications above 100
GHz are still lacking. Taking into possession new
frequency bands in the millimeterwave spectra above 100
GHz thus not only secures increased available bandwidth
for backhauling next generation Radio Networks (RAN)
but also open up the possibilities for small, very compact
backhaul links. Due to the low atmospheric path
attenuation in the 141-148.5 GHz band, multiple Gbps
capacity point-to-point links with km range become
realistic. Taking advantage of the 7.5 GHz wide
bandwidth available, combined with high spectral
efficiency modulation, ultra-high capacity backhaul links
with same reach as conventional links can be utilized. At
the moment the state-of-the-art regarding hop distance at
high bit rate for point-to-point links, is represented by
NTT [1]. NTT have demonstrated a hop length of 5.8 km
at a bit rate of 10 Gbps using On-Off Keying (OOK) at
120 GHz. The occupied bandwidth is 17 GHz. NTT has
also recently demonstrated 20 Gbps using QPSK [2],[7]
in laboratory environment at the same frequency. The

978-1-4799-3622-9/14/$31.00 2014 IEEE

The RFIC technology chosen for this project is a 250

I
-I

LO

X3
Multiplier

Quadrature
Phase shifter

PA

Output

Q
-Q

Fig. 1 Block diagram of the 110-170 GHz I-Q direct

modulation transmitter.
I
-I

LO

X3
Multiplier

Quadrature
Phase shifter

LNA

Input

Q
-Q

Fig. 2 Block diagram of the 110-170 GHz I-Q direct

demodulation receiver

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Table of Contents

nm InP DHBT process from Teledyne Scientific, utilizing

double hetero junction bipolar transistors (DHBT) having
a maximum oscillation frequency of 650 GHz. This
process has a 4 dielectric/metal layers backend for
transmission line and passive components, allowing very
dense analog and digital designs on the same chip.
The TX is a direct modulation transmitter, where two
double balanced (I and Q) mixer are pumped by a
frequency tripler multiplier for output frequency from 110
GHz to 170 GHz, a three stage power amplifier is used at
the output to increase the transmitted power of the RF
signal, see Fig. 1. The RX is a direct I-Q receiver and
consists of a low noise amplifier, a double balanced I/Q
mixer and a frequency tripler for the LO, as shown in
Fig.2.
Before the complete chip was designed, each circuit was
verified separately. Circuits with their key parameters are
described as follows.

Fig. 3 Photo of the general purpose amplifier

A. Power Amplifier/LNA
A general purpose 3-stage amplifier is used for the RX
and the TX chips. This amplifier achieves experimentally
a saturated output power exceeding 10 dBm and a noise
figure of 9 dB. The design is of lossy match type,
utilizing resistively loaded stubs at the input and output of
each amplifiers stage. Due to this topology it is possible to
achieve a very wide bandwidth with full coverage of the
D-band. The emitter lengths of the transistors are 4, 6, and
10 m respectively. The layout of the amplifier is depicted
in Fig 3. The amplifier has 20 dB gain from 110 to 160
GHz with less than 0.5 dB variation.

Fig. 4 Chip photograph of the IQ modulator

B. I-Q Modulator
Fig. 5 Chip photograph of the tripler

The I/Q modulator is based on a recently published

design [5] and consists of two double balanced Gilbert
mixer cells, an on-chip integrated differential LO coupler
and RF and LO baluns. This configuration offers a high
isolation between all three ports in in a very a compact die
footprint. With a sinusoidal input signal of 1 GHz and 0
dBm LO power, 6 dB conversion gain and more than 22 dB
image rejection ratio (as SSB mixer) is achieved. The LO
to RF isolation is larger than 25 dB up to 135 GHz,
declining to >15 dB at 155 GHz. The chip photograph is
shown in Fig. 4. The chip consumes 78 mW DC power
and can provide up to 3 dBm RF power in saturation. The
active chip area is 560 m 440 m.

Q outputs providing matching to 50. The circuit

consumes 74 mW of DC power. The measured conversion
gain is nominally 14 dB, with a mid-band noise figure of
12 dB. The 3 dB RF bandwidth is from 128 GHz to 150
GHz.
D. LO Frequency tripler
The frequency tripler used in this work is a recently
published [6] two-stage active wideband frequency tripler
having high efficiency (20%), compact design, and 30 dBc
rejection of 1st, 2nd, and 4th harmonic. A photo is shown in
Fig. 5. The tripler consumes 45 mW DC power. As the
output frequency is from 110 GHz to 155 GHz, the output
power varies from 5 dBm to 10 dBm with the input power
of 3 dBm.

C. I-Q Demodulator
The wideband demodulator design is similar to the
modulator, and consists of two double balanced Gilbert
mixer cells, on-chip integrated differential LO coupler and
RF and LO baluns. Emitter followers are included at the I-

E. Design of the TX and RX chips

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Table of Contents

frequency bands. An LO power of 3 dBm was applied to

the multiplier input. The transmitter dissipates total 165
mW of DC power.
B. Receiver measurement results
The receiver is characterized as an image reject downconverter. On-wafer probe measurements have been
performed to characterize in a similar way as the TX. The
measured conversion gain is 264 dB over the frequency
band from 110-166 GHz at an applied LO power of 3 dBm
The DC power dissipation of the receiver is 192 mW.
IV. DATA TRANSMISSION MEASUREMENTS
A. QPSK direct modulation transmitter verification
The direct modulation transmitter is verified as follows: a
dual-channel pulse pattern generator (PPG, Anritsu
MP1800) is used to generate two independent pseudorandom binary sequence (PRBS), which are synchronized
at same data rates. The I and Q input ports of the direct
modulation transmitter are driven differentially by these
two data streams, and the phase of the RF signal is
modulated by these data to form a QPSK modulated
output, the LO signal is fed by an external synthesizer at a
frequency of one-third of fLO. The RF output passes
through a two meter long dielectric waveguide (15 dB
loss) then connected to a D-band passive mixer
(Radiometer Physics SAM-170, conversion loss 26 dB). A
spectrum analyzer is used to measure the spectrum of the
modulated signal. The measured spectrum of a 12 Gbps
QPSK signal centered at 142 GHz is shown in Fig. 7. The
peak-to-peak voltage of the data stream is adjusted while
monitoring the output power of the spectrum. This
experiment shows the transmitter is saturated when the
input data amplitude is larger than 900 mV (single-end
peak-to-peak).

Fig. 6 Photo of the receiver (top) and transmitter

(bottom) MMIC, both chip area is 1.3x 0.9 mm2

Fig. 7 Measured spectrum of a 12-Gbps QPSK

modulated signal at 142 GHz
For both the TX and RX designs, the mixer cells
including the transconductance stages and the switching
quads are densely laid out in the center of the chip in order
to minimize parasitic effects. The LO distribution as well
as the matching networks are all symmetrically laid out
around the mixing cells to maintain amplitude and phase
balance. The chip area of the TX and RX is 1.3x 0.9 mm2.
A chip photograph of the fabricated transmitter is
shown in Fig. 6. The layout was carried out with special
care to preserve the symmetry of the sub-block functions
for optimum amplitude and phase balance.

B. Data transmission verification

High data rate data transmission is verified with the
experimental setup as shown in Fig. 8. The transmitter and
receiver MMICs are probed on wafer on two probe
stations. A two meter D-band dielectric waveguide is used
to feed RF signal from the transmitter to the receiver.
The transmitter and receiver share the common LO
source through a power splitter, the available LO power
for each MMIC is then less than 1 dBm. At the receiver
side, the I- and Q- output port are connected to a LeCroy
10Zi real-time oscilloscope which is used to measure the
eye-diagram. The I output port is connected to a bit error
detector via a low-pass filter (Mini-circuit LPF-7600),
which can perform long-term bit-error rate test. A photo of
the experimental setup in the lab is shown in Fig. 9.

III. EXPERIMENTAL VERIFICATION OF THE RX/TX CHIPSET

A. Transmitter measurement results
The circuit was measured over 110 GHz-165 GHz range
for the RF signals, and from 500 MHz to 20 GHz for the
IF. A conversion gain of 204 dB is achieved over the

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Table of Contents

Transmitter
MMIC
Pulse
Pattern
Generator
(PPG)

I
-I

D-band
dielectric
waveguide
(2meter)

Receiver
MMIC

Q
-Q

mentally. The ddesign is widebband and covers almost

experim
the entiire D-band. Thhe noise figuree of the receiveer is 9 dB
and thee maximum ouutput power off the transmitteer is >10
dBm. D
Data rates up too 44 Gbps wass measured witth QPSK
modulaation. This is the first implementatiion and
demonsstration of a RX/TX chipset for D-band
applicaations, utilizingg an InP DHB
BT-MMIC tecchnology.
The ressult from this cchip-set exceedds the previouss state-ofthe-art QPSK dataraate in D-band, based on InP
P HEMT
MMIC--implementatioons [2], [7], byy a factor of 2.

Error
Detector
I
-I
-Q
Q

oscilloscope

LO
36-57GHz

Fig. 8 Expeerimental setup

p of data transm
mission test

AC
CKNOWLEDGM
MENT
The Swedish Founndation for Strrategic Research (SSF)
and thee Swedish Research Council (VR) and Vinnnova are
acknow
wledged for thhe financial suppport of this w
work. Dr
Jonas H
Hansryd, Thom
mas Emanuelsson, and Yingggang Li at
Ericssoon AB for theeir support, Veessen Vassilevv, Rumen
Kozhuhharov, and B
Bing Zhang aare acknowleddged for
assistannce with meaasurements. T
Thomas Ogesttadh and
Janus Rasmussen aare acknowleddged for loann of the
Anritsuu and LeCroy iinstruments.

Fig. 9 Photo
o of the experimental setup

REFERENCESS
1.

2.

Fig. 10 (a)-(d) Measured eye

e diagram att 36, 40, and 44
4
Gbps data rate
r

3.

The measurred eye diagraams at differen

nt data rates are
a
shown in Fig
g. 10. In Fig. 10(a), the eye diagram at 36
Gbps is preseented, which iss taken with oscilloscope inp
put
bandwidth seet at 20 GHz. The
T measured BER at this daata
rate is less than 10-6. Att 40 Gbps, th
he QPSK sign
nal
der bandwidth
h and to meeasure such eye
e
occupies wid
diagram, the oscilloscope input bandwidth is set at 36
T
GHz. In Fig. 10(b), the measured BER iss below 10-5. The
g. 10(c), this eye
e
eye diagram at 44 Gbps iss shown in Fig
t
suffers from noise and inteer-symbol interrference, and the
ow 10-2. A 6--tap linear eq
qualizer (EQ) is
BER is belo
implemented using the digiital signal-proccessing feature of
ope, the eye diagram
d
after processed
p
by th
his
the oscillosco
EQ is shown in Fig. 10(d), and
a an estimated BER of 10-33 is
given by thee oscilloscope based on thee processed eye
e
diagram. BER
R was measureed with a PRBS
S-11 sequence.

4.

5.

6.

7.

V. CON
NCLUSION
8.

D
RX/T
TX
A direct modulation/deemodulation D-band
ng I-Q input/ou
utput realized in a 250 nm InP
I
chipset havin
DHBT techn
nology has been designeed and verifiied

247

H. Takahashi, T
T. Kosugi, A
A. Hirata, K. Murata,
Suupporting fast and clear video, IEEE M
Microwave
Maagazine, pp. 54-664, Sept. 2012.
H. Takahashi et al,,120 GHz bandd 20 Gbit/s transm
mitter and
recceiver MMIC uusing quadratuure phase shift keying,
Prooceedings of 7th European Microwave IIntegrated
Cirrcuits Conferencce, pp. 313-316, Oct. 2012.
M. Abbasi, S. Gunnnarsson, N. Waadefalk,R. Kozhhuharov, J.
Angelov, I. Kaallfass, A.
Sveedin, S. Chereddnichenko, I. A
Leuuther and H. Zirath, Singlee-chip 220 GH
Hz active
hetterodyne receiveer and transmitteer MMICs with oon-chip
inteegrated antenna, IEEE Trans. Microwave Theory Tech.,
voll. 59, no. 2, pp. 4466-478, 2011.
I. Kallfass, J. Antes, D. Loopez-Diaz, S. Wagner,
A.T
Tessmann and A
A. Leuther, Brooadband active integrated
circcuits for teraherrtz communicatiion, Proceedinggs of 18th
Eurropean Wirelesss Conference, A
April 2012.
S. Carpenter, M. A
Abbasi, and H. Z
Zirath, A 115 -155 GHz
quaadrature up-connverting MMIC
C mixer in InnP DHBT
tecchnology, 20113 European Microwave IIntegrated
Cirrcuits Conferencce (EuMIC), , Occt. 2013, pp. 1133116.
M. Bao, R. Kozzhuharov, H. Z
Zirath, A higgh powereffi
ficiency D-band frequency tripleer MMIC with ggain up to
7 ddB, IEEE Microowave and Wireeless Componennts Letters,
voll. 24, no. 2, pp. 1123-125, Feb. 20014.
T. Kosugi, H. Takaahashi, A. Hirataa, K. Murata, B
Broadband
InP
P MMICs for 1120 GHz wireleess data commuunication,
IEE
EE Radio and Wireless Sympoosium (RWS), ppp. 49-51,
20113.
D.L
Lopez-Diaz, et al, A 240 GHzz quadrature recceiver and
trannsmitter for daata transmission up to 40 Gbitt/s, 2013
Eurropean Microw
wave Conferencce (EuMC), pp. 1411
2013.
14114,

Table of Contents

Characterization of the High Frequency

Performance of 28-nm UTBB FDSOI MOSFETs as
a Function of Backgate Bias
Stefan Shopov, Sorin P. Voinigescu
ECE Department, University of Toronto, Toronto, ON, M5S 3G4, Canada
AbstractThis paper describes for the first time the high
frequency performance characterization of a production 28nm ultra-thin-body-and-BOX (UTBB) fully-depleted (FD) SOI
CMOS technology. The measured gm , fT , and maximum
available gain (M AG) of fully-wired n-channel and p-channel
MOSFETs are reported as a function of gate-source, drainsource, back-gate voltages and drain current density. It is shown
that the back-gate bias can reduce the VGS at which the peak
gm , peak fT and peak M AG occur by up to 400 mV and
can flatten the fT -VGS characteristics, as needed in highly
linear amplifiers. The peak gm /fT values of 1.5mS/m/298GHz
and 0.93mS/m/194GHz, for n-MOSFETs and p-MOSFETs
respectively, match or exceed those of 28-nm LP bulk and 45-nm
SOI MOSFETs with identical layout geometry and metal stack
wiring.
Index TermsSOI MOSFETs, ultra-thin-body, back gate,
cutoff frequency, M AG, transconductance

Q026)(7
'6

'6

S026)(7

'6

'6

%*1

%*3
1

67,

1

QP

67, QP %2;

1:

3

1
67,

6LILOP
%2;

3
67,

3

67,

3:
GHHS1:
3VXEVWUDWH

Fig. 1: Cross-section of the n- and p-channel MOSFETs with backgate wells and deep n-well (not to scale).

I. I NTRODUCTION
As CMOS technology has been scaled to 28-nm and beyond, the analog and high frequency performance of planar
MOSFETs has started to saturate [1], [2]. With its unique
features, reduced capacitive parasitics, and simpler process
and threshold control compared to FinFETs, UTBB FDSOI
CMOS technology is very attractive for high-speed mixed
signal fiber-optics and mm-wave applications [3]. In particular,
as with partially-depleted SOI CMOS [3], in power amplifiers
and optical modulator drivers, the low-breakdown voltage of
the nanoscale MOSFET can be overcome by series stacking
several transistors up to a number limited by the breakdown
voltage of the buried oxide [3]. To the best of our knowledge,
the high frequency performance of the 28-nm FDSOI process
and the impact of the hybrid wells on the high frequency figures of merit (FoM) of transistors has yet to be characterized.
In this paper we report the measured high frequency FoMs of
production n-channel and p-channel 28-nm FDSOI MOSFETs
and monitor their behaviour with back gate bias.
II. FDSOI P ROCESS AND H IGH -F REQUENCY T RANSISTOR
L AYOUT
The 28-nm FDSOI CMOS technology features high-k metal
gate MOSFETs with a minimum gate length of 24 nm fabricated in a 7 nm silicon film [4] placed above a 25 nm buried
oxide (BOX) [5]. The process has a low-k back-end-of-line
(BEOL) with 11 copper layers and Alucap. As illustrated in
Fig. 1, the BOX is selectively removed from the area outside

978-1-4799-3622-9/14/$31.00 2014 IEEE

the active device channel to allow for a contact to be formed

to n-type or p-type wells in the silicon substrate below the
channel. If an n-type well is placed below the n-channel
MOSFET, and a p-type well is inserted below the p-channel
device, both in a deep n-well, the ultra-thin BOX allows for the
threshold voltage of the two device types to be independently
tuned over several tenths of volt. The n- and p-wells act
as second back-gates for the n-MOSFET and p-MOSFET,
respectively. While this feature has already been used in analog
mixed-signal and high-speed digital applications [5], its impact
on the high frequency and small signal figures of merit of the
device is investigated here for the first time. One prevailing
concern is that the well and deep-nwell capacitances may
degrade the high frequency gain.
To conduct the study, high frequency n-channel and pchannel MOSFET test structures were designed with identical
layouts as in the corresponding 28-nm LP bulk CMOS technology and in earlier generations of (SOI) CMOS technologies.
Layouts of the manufactured single-gate contact and doublegate contact MOSFETs are reproduced in Figs. 2 and 3,
respectively. Two 104m and 338m long transmission lines
were also fabricated for S-parameter de-embedding purposes.
The test structure die photograph is shown in Fig. 4.
III. M EASUREMENT R ESULTS
The DC I-V characteristics and the S-parameters of the 3
transistors and transmission lines were measured on wafer up

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Table of Contents

Fig. 5: Normalized output characteristics of 4024nm500nm nMOSFET and p-MOSFET fabricated in 28-nm bulk (dashed lines)
and FDSOI (solid lines) technologies. The back gate is floating in
the case of the FDSOI devices.
Fig. 2: Layout detail of a 24nm MOSFET with 500nm gate fingers
contacted on a single side of the gate.

Fig. 3: Layout detail of a 24nm MOSFET with 780nm gate fingers

contacted on both sides of the gate.

to 70 GHz. (Measurements at D-Band and at G-Band will

be performed in the coming 4 weeks). Following an LRRM
calibration on a commercial impedance standard substrate,
a transmission-line de-embedding step [6] was applied to
remove the pads and interconnect parasitics up to the device
edge, leaving all wiring stack on top of the device proper
in place, up to metal 11 (M 11), to reflect the expected
transistor performance in a mm-wave or high speed circuit.
The measured output characteristics per gate width are plotted
in Fig. 5 for devices with identical layout geometries fabricated
in 28-nm FDSOI and 28-nm LP planar CMOS processes.
The improvement in output conductance and drain current is

Fig. 4: Die microphotograph of the test structure chip occupying

0.5mm1mm.

Fig. 6: Normalized transfer characteristics of of 4024nm500nm

n-MOSFET and p-MOSFET as a function of gate-source voltage and
back-gate voltage (-/+0.5V to +/-6V) at |VDS |=1V.

immediately apparent in the case of the FDSOI MOSFETs.

Fig. 6 reproduces the measured transfer characteristics in
saturation (VDS =+/-1V) for n- and p-channel MOSFETs,
respectively, with 40 gate fingers, each 24nm long and 500nm
wide. The back-gate voltages, VBGN and VBGP , are varied
between -0.5V and +6V (nominal allowed range is -0.3V
to +1.8V) for the n-MOSFET, and between +0.5V and 6V (nominal allowed range +0.3V to -1.8V) for the pMOSFET, respectively. The maximum drain-source current
varies from 0.9mA/m to 1.4mA/m for the n-MOSFET, and
from 0.45mA/m to 0.85mA/m, for the p-MOSFET.
The corresponding normalized transconductance plots are
shown in Fig. 7. It becomes apparent that the peak-gm VGS
can be tuned by more than 400mV while the peak-gm value for
the n-MOSFET decreases from 1.5mS/m to 1.25mS/m, and
from 0.93mS/m to 0.85mS/m in the case of the p-MOSFET.
Note that gm of the n-type device remains larger than 1.2
mS/m for VGS values between 0.2V and 1V, and larger than
0.75mS/m between -0.2V and -1V for the p-MOSFET. In
both devices, the peak gm value decreases slightly as the
bottom channel-oxide interface becomes strongly inverted and
the drain current increases. The n-MOSFET transconductance
is about a factor of 2 smaller than those measured in InP
HEMTs with similar gate lengths [7].
The gm variation with VGS and VBG impacts directly the

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Table of Contents

Fig. 7: Normalized transconductance of 4024nm500nm nMOSFET and p-MOSFET as a function of gate-source voltage and
back-gate voltage (-/+0.5V to +/-6V) at |VDS |=1V.

Fig. 9: Measured M AG at 60 GHz vs. VGS characteristics for

4024nm500nm n-and p-MOSFETs as a function of back-gate
voltage (-/+0.5V to +/-6V) at |VDS |=1V.

Fig. 8: Measured fT vs. VGS characteristics of 4024nm500nm

n-and p-MOSFETs as a function of back-gate voltage (-/+0.5V to
+/-6V) at |VDS |=1V.

Fig. 10: Measured fT

vs. IDS /W characteristics of
4024nm500nm n-ansd p-MOSFETs as a function of backgate voltage (-/+0.5V to +/-6V) at |VDS |=1V.

measured fT characteristics of these devices, illustrated in

Fig. 8. Again, as the back gate voltage applied to the n-well
below the n-channel MOSFET increases, the threshold voltage
decreases, the fT -VGS characteristics are shifted to lower
VGS values, become flatter, and the peak-fT value decreases
slightly by about 15% from 298 GHz to 255 GHz. The same
behaviour is observed for the p-MOSFET, with the peak-fT
value decreasing only slightly from 195 GHz to 185 GHz as
VBGP varies from +0.5V to -6V.
Since all MOSFETs on the test chip are potentially unstable
below 70 GHz, the fM AX could not be extrapolated reliably
at this time. Instead, the M AG measured at 60 GHz is plotted
in Fig. 9. The n-MOSFET exhibits 10.5dB peak power gain
while the p-MOSFET has 8dB peak gain. Both vary less than
1dB when VGS changes from -0.3V to -1V.
The dependence on the drain current density of fT and
M AG is illustrated in Figs. 10 and 11, respectively. Similarly
to the behaviour vs. VGS , the characteristics become flatter
(more linear) as the back gate voltage increases in absolute
value. At the same time, the peak-fT and peak-M AG drain
current densities increase, suggesting that, in power amplifiers,
FDSOI MOSFETs should be biased at large back-gate voltage
to improve linearity and output power density.
Finally, the drain-source voltage variation of fT and M AG
are plotted in Figs. 12 and 13 for single-gate contact and
double-gate contact n-MOSFETs. As expected, the lower gate

resistance of the double-gate device leads to higher M AG

(11.5dB vs. 10.5 dB) but the additional capacitive parasitics
at the gate decrease its fT compared to a single-gate contact
device.
IV. C OMPARISON T O OTHER T ECHNOLOGY N ODES
Figs. 14-15, compare the fT vs. drain current density
characteristics of floating back gate n-channel and p-channel
FDSOI MOSFETs with 28-nm LP bulk MOSFETs and MOSFETs fabricated in older technology nodes. Unlike 28-nm LP

Fig. 11: Measured M AG at 60 GHz vs. IDS /W characteristics for

4024nm500nm n-and p-MOSFETs as a function of back-gate
voltage (-/+0.5V to +/-6V) at |VDS |=1V.

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Table of Contents

Fig. 12: Comparison of the measured fT vs. VDS characteristics of

2624nm780nm and 4024nm500nm n-MOSFETs for a floating
back-gate at VGS =0.7V.
Fig. 15: Measured p-MOSFET fT vs. technology node.

Fig. 13: Comparison of the measured M AG at 60 GHz vs. VDS

characteristics of of 2624nm780nm and 4024nm500nm nMOSFETs for a floating back-gate at VGS =0.7V.

CMOS, FDSOI CMOS demonstrates continued improvement

in both n- and p-channel devices.
V. C ONCLUSION
The high frequency FoMs of a production 28-nm FDSOI
CMOS technology have been measured for the first time. It
is shown that the back-gate voltage can be used to tune the
gate source voltage and current densities at which the peak

gm , peak fT and peak M AG occur, by at least 400mV.

As the back-gate-channel interface becomes more strongly
inverted, the gm , fT and M AG characteristics with VGS
and drain current density become flatter and are shifted to
lower VGS . This behaviour is very useful in linear (power)
amplifiers and large swing drivers. Moreover, the sensitivity
of the gm , fT and M AG to the back-gate voltage could be
used to implement more complex control functions, such as
mixers and modulators, using a single MOSFET, similar to the
double-gate GaAs MESFETs of the 1970s. Comparison with
MOSFETs fabricated with identical layout in 28-nm LP planar
CMOS and earlier CMOS nodes illustrates that the rate of fT
improvement with gate length scaling can continue, albeit at
a reduced rate.
ACKNOWLEDGMENT
The authors would like to acknowledge CMC for funding
and facilitating chip fabrication. Technology discussions with
Andreia Cathelin and Patrick Cogez of STMicroelectronics are
also highly appreciated. Finally, we would like to thank CMC
for CAD tools and Jaro Pristupa for CAD tools support.
R EFERENCES

Fig. 14: Measured n-MOSFET fT vs. technology node.

[1] M.-T.Yang, et al., RF and mixed-signal performances of a low cost 28nm

low-power CMOS technology for wireless system-on-chip applications,
in Symp. on VLSI Technology (VLSIT), June 2011, pp. 4041.
[2] S.Voinigescu, A.Tomkins, E.Dacquay, P.Chevalier, J.Hasch, A.Chantre,
and B.Sautreuil, A Study of SiGe HBT Signal Sources in the 220330GHz Range, IEEE JSSC, vol. 48, no. 9, pp. 20112021, Sept 2013.
[3] A.Balteanu, I.Sarkas, E.Dacquay, A.Tomkins, G.Rebeiz, P.Asbeck, and
S.Voinigescu, A 2-Bit, 24 dBm, Millimeter-Wave SOI CMOS PowerDAC Cell for Watt-Level High-Efficiency, Fully Digital m-ary QAM
Transmitters, IEEE JSSC, vol. 48, no. 5, pp. 11261137, May 2013.
[4] N.Planes, et al., 28nm FDSOI technology platform for high-speed lowvoltage digital applications, in Symp. on VLSI Technology (VLSIT), June
2012, pp. 133134.
[5] S.Le Tual, P.Singh, C.Curis, and P.Dautriche, 22.3 A 20GHz-BW 6b
10GS/s 32mW time-interleaved SAR ADC with Master T amp;H in 28nm
UTBB FDSOI technology, in IEEE ISSCC, Feb 2014, pp. 382383.
[6] A.Mangan, S.Voinigescu, M.-T.Yang, and M.Tazlauanu, De-embedding
transmission line measurements for accurate modeling of IC designs,
IEEE Trans. on Electron Devices,, vol. 53, no. 2, pp. 235241, Feb 2006.
[7] W.Deal, et al., Scaling of InP HEMT Cascode Integrated Circuits to
THz Frequencies, in IEEE CSICS, Oct 2010, pp. 14.

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An 8-bit 140-GHz Power-DAC Cell for IQ

Transmitter Arrays with Antenna Segmentation
Stefan Shopov, Sorin P. Voinigescu
ECE Department, University of Toronto, Toronto, ON, M5S 3G4, Canada

AbstractAn 8-bit power-DAC cell is demonstrated for the

first time at D-band in a production 45-nm SOI CMOS technology. The circuit proves the scalability of the transmitter array
architecture with antenna segmentation from the W-band to the
D-band. The last two stages of the power-DAC cell employ a
novel two-stage common-gate Gilbert-cell topology with seriesstacking to directly modulate a 125144 GHz carrier in phase
and in amplitude. The measured gain, saturated output power,
and PAE of the power-DAC cell are 14.9 dB, 13.2 dBm, and
2.8%, respectively.
Index TermsD-band, mm-wave, power-DAC, Gilbert-cell,
stack, power amplifier, transmitter, SOI, CMOS.

I. I NTRODUCTION
A saturated power-DAC transmitter architecture with IQ
antenna array segmentation has been recently proposed and
demonstrated at 45 GHz [1] and in the W-band [2], [3] in a
production 45-nm SOI CMOS technology. Record power-DAC
output power levels of 24 dBm and 19 dBm were measured at
45 GHz and 86 GHz, respectively. In this paper, we prove
that the unit power-DAC cell of the IQ transmitter array
architecture is scalable to 140 GHz, in the same technology,
while matching the best reported output power for a CMOS PA
in this frequency range [4]. To achieve this performance, novel
common-gate Gilbert-cell topologies with series stacking are
proposed for the large power BPSK and 6-bit ASK modulator
stages at the output of the power-DAC cell.
II. P OWER -DAC A RCHITECTURE
The block diagram of the proposed power-DAC cell is
shown in Fig. 1. The LO signal is first amplified and then
BPSK modulated before it reaches the large power multi-bit
amplitude modulator which forms the output stage. As in [2],
the ASK modulation is applied after the constant-envelope
BPSK modulation to ensure that the output stage is driven
deep into saturation. Unlike [2], the output stage is realized
as a single-quadrant multi-bit segmented Gilbert-cell. The
main advantages of this two-stage power modulator over the
single output stage implementation in [3] are (i) the improved
symmetry between the positive and negative quadrants, which
is critical for the accurate generation of m-ary QAM signals,
and (ii) a simpler and more power efficient output stage with
less interconnect parasitic capacitance.
III. C IRCUIT D ESIGN
A. LO Distribution
The six-stage LO amplifier schematic is shown in Fig. 2
(a). The first stage is a 40nm160.77m single-ended n-

978-1-4799-3622-9/14/$31.00 2014 IEEE

OOK BPSK

n-bit ASK

LO Amplifier
LO

phase

amplitude

modulation

modulation

Tx

Fig. 1: Two-stage power-DAC cell architecture.

MOSFET cascode with inductive degeneration which provides

broadband 50- input matching and performs single-ended to
differential conversion at the transformer load. Unlike the input
stage, which is implemented with regular-VT devices, ultrahigh-VT n-MOSFETs are used in the five common-source
differential stages that follow. Ultra-high-VT devices help to
minimize the interstage matching network losses because they
allow for the direct DC coupling of the five common-source
stages, as in [5], while also maintaining a relatively large
VDS needed for large power gain. The interstage inductive
T-network shown in Fig. 2 (b) absorbs the CGS and CDS of
the ultra-high-VT MOSFETs to form a broadband artificial
transmission-line. Given the broadband nature of the interstage network and the potential for instabilities to occur, the
LO amplifier is stabilized at low frequencies by (i) introducing
drain-to-source resistive feedback in each of the five differential stages and (ii) using low Lp values in Fig. 2 (b) to provide
a high-pass transfer function. A bias current and transistor size
ratio (analog fan-out) of 1.5 is used between stages to ensure
that the signal swing is not limited before it reaches the final
stage of the amplifier. All MOSFETs are biased for maximum
power gain at a current density of 0.3mA/m.
B. Power Modulator
Unlike [2] and [3], the BPSK and ASK power modulator
stages, shown in Fig. 3, are implemented with a commongate Gilbert-cell topology with series-stacking. The LO signal
is applied directly to the source terminals of the segmented
gate Gilbert-cell quad transistors through a transformer. This
is done to increase the bandwidth of the matching network,
since at D-band the common-gate topology has a lower input
quality factor than the topology employed in [3]. Another
advantage of removing the bottom common-source differential
pair from the Gilbert-cell is that it allows standard high-speed
thin-oxide CMOS logic gates to drive the gate segments of the
Gilbert-cell at the highest possible switching speed. The BPSK

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35pH 30pH

100pH:100pH

1V

16x0.77

10x0.77

27pH 27pH

16x0.77
1V

40pH

15pH 15pH

54x0.77
1

34pH

37pH

Ls2

2Lp

1V

1V

40pH

Ls1

36x0.77

24x0.77
1V

44pH
50pH

22pH 22pH

1V
50pH

1350

1350

900

600

400

Ls1

Ls2

ultra-high-VT devices

Fig. 2: Schematic of (a) the D-band LO amplifier and (b) the differential interstage matching T-network.

modulator employs a series-stacked common gate Gilbert-cell

driven by a differential CMOS inverter chain, Fig. 3 (a), while
the 6-bit ASK modulation is implemented by separating the
Gilbert-cell gate fingers in Fig. 3 (b) into six binary weighted
segments in parallel with a 40nm321.54m common-gate
transistor. The width of the common-gate transistor in the ASK
stage corresponds to twice the width of the MOSFET used
for the most significant ASK bit. The six binary-weighted
groupings of gate fingers in the Gilbert-cell of the ASK
modulator are each driven by a separate differential CMOS
inverter chain through the selector shown in Fig. 4. The
selector is realized with transmission-gates whose inputs are
fixed to VBIAS = 0.8V and 0V, respectively. The 8th bit
is employed to simultaneously turn on and off both powermodulator stages as needed for antenna array segmentation
[1].

BPSK

190fF

190fF

190fF

2x38x1.25
45pH:25pH

38x1.25

23pH

47pH

47pH

4x16x0.77

4x12x0.77

4x12x0.77

BPSK
n

n
0

4k

where
bBPSK,high = VBIAS,
bBPSK,low = 0V

9.2k

6.6k

6.6k

190fF

190fF

BIAS
``

32x1.54

190fF

IV. E XPERIMENTAL R ESULTS

2x64x1.54
0

32x1.54

120pH:25pH

16pH
4x36x0.77

4.4V

24pH

24pH

4x24x0.77

65pH:60pH

4x24x0.77
4.4V

The D-band power-DAC cell was fabricated in IBMs 45-nm

SOI CMOS process which features a copper BEOL with 11
metal layers and floating body n-MOSFETs with measured fT
and fM AX of approximately 250 GHz [1]. The die micrograph
of the circuit is shown in Fig. 5 and the total die area, including
pads, occupies 0.9mm1.26mm. A breakout consisting of the
two power-modulator stages was also fabricated and tested
separately.
First, the S-parameters of the entire power-DAC cell and
of the power-modulator breakout were measured at D-band
for all bit settings. The measured S-parameters of the powerDAC cell are shown in Fig. 6. It shows a peak gain of 14.9
dB and a 3-dB bandwidth spanning 19 GHz. The output
return loss remains >20 dB from 134138 GHz and >10 dB
from 125148 GHz for all amplitude and phase bit settings.
The amplitude and phase characteristics vs. digital word are
shown in Fig. 7 (a) and (b), respectively. As a result of the
constant current and constant impedance Gilbert-cell output
stage, S22 remains insensitive to bit settings. At the maximum
ASK setting, the amplitude imbalance and phase error at
135 GHz is 0.4 dB and 2 , respectively. As expected, the
largest phase error corresponds to the lowest ASK setting.
The dynamic range of the 6-bit ASK modulator is >18.4 dB
from 130150 GHz and it improves to 60 dB at 135 GHz
with the OOK bit. These measurements confirm that leakage
from inactive antenna elements would be fully suppressed (by
>50 dB) in an IQ transmitter array. The output power vs.

4k
9.2k

6.6k

6.6k

where i = 1..6,
bi,high = VBIAS,
bi,low = 0V

BIAS

Fig. 3: Schematics of (a) the stacked driver stage used for BPSK
modulation, and (b) the stacked output stage used for 6-bit ASK
modulation.

BIAS
i

Fig. 4: Selector used to modulate the BPSK and ASK bits of the
power-DAC cell.

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900 m

1260 m

OOK

RST
G

BPSK

TIA

TIA

LO amplifier

ASK bit1
G

G
TIA

BPSK stage ASK stage

G
Tx

LO

power-DAC

G
deserializer

G
1.1V
digital

1.0V

G
CLK

ASK bit2-6

G
VBIAS

4.4V

Fig. 5: Die micrograph of the D-band power-DAC cell.

(a)

input power characteristics of the power-modulator breakout

were measured directly with a power sensor by mechanically
varying the input power supplied by a VDI active multiplier
chain. The large-signal measurements shown in Fig. 8 are
referenced to the G-S-G probe tips by accounting for the
setup losses through a two-tier VNA calibration. A maximum
output power of 13.2 dBm with a drain efficiency of 4.4%
are observed at 128 GHz. The output power remains >12.6
dBm from 128138 GHz. The power-modulator exhibits a
peak PAE of 2.8% and an output power of 12.8 dBm at
138 GHz. The dynamic operation of the power-DAC cell was
verified by modulating the data inputs with PRBS sequences
and measuring D-band spectra with a spectrum analyzer and
a 26th harmonic mixer. The BPSK bit, the most significant
ASK bit, and the OOK bit are provided directly at maximum
data rate from off-chip. Due to the limited number of high
speed pads and probe pins, the remaining five ASK bits
are supplied serially and deserialized on-chip. The powerDAC was modulated successfully up to 0.75 Gb/s per digital
lane. Verification at higher data rates is currently limited
by the bandwidth of the harmonic mixer in the test setup.
This limitation will be overcome after the acquisition of a
broadband (>30 GHz) downconverter (expected in the next
couple of months). The measured spectrum of a 138 GHz
carrier modulated by a 0.5 Gb/s PRBS-7 sequence applied on
the BPSK bit and the spectrum of a 138 GHz carrier modulated
by a 0.5 Gb/s PRBS-8 sequence applied simultaneously on the
BPSK bit, on the most significant ASK bit, and on the OOK
bit are shown in Fig. 9 (a) and (b), respectively.
Finally, Table I compares the D-band power-modulator
breakout to previously reported D-band power amplifiers, and
Table II compares the entire power-DAC cell to previously
reported D-band power-DACs.

(b)

Fig. 6: Measured S-parameters of the power-DAC cell for the 128

amplitude and phase states and OOK state.

(a)

V. C ONCLUSION
A power-DAC cell with amplitude and phase modulation
based on a new two-stage power-DAC modulator topology
has been proposed and verified at D-band. It demonstrates an
output power of 13.2 dBm at 128 GHz and >12.6 dBm from
128138 GHz with a peak PAE of 2.8%. Data modulation of
D-band carriers at 0.75 Gbaud with an aggregate data rate of
1.74 Gb/s has also been demonstrated, limited by the current
test setup.

(b)

Fig. 7: Measured (a) magnitude and (b) phase of the power-DAC cell
transfer-characteristics.

254

Table of Contents

Fig. 8: Measured output power vs. input power of the power modulator breakout.

ACKNOWLEDGMENT
This work was funded by the DARPA ELASTx Program
under the supervision of Dr. Dev Palmer, Program Manager.
The authors would like to thank Prof. P.M. Asbeck, Prof. J.
Buckwalter and Prof. G.M. Rebeiz for technical discussions,
Prof. G.M. Rebeiz for equipment loans, CMC for CAD tools,
Integrand for the EMX simulation software, and J. Pristupa
for CAD support.

Fig. 9: Measured spectra with a 138 GHz LO carrier. Power-DAC

cell modulated (a) by a 0.5 Gb/s PRBS-7 sequence on the BPSK bit,
and (b) by a 0.5 Gb/s PRBS-8 sequence applied simultaneously on
the BPSK bit, most significant ASK bit, and OOK bit.

R EFERENCES
[1] A.Balteanu, et al., A 2-Bit, 24 dBm, Millimeter-Wave SOI CMOS
Power-DAC Cell for Watt-Level High-Efficiency, Fully Digital m-ary
QAM Transmitters, IEEE JSSC, vol. 48, no. 5, pp. 11261137, 2013.
[2] A.Balteanu, S.Shopov, and S.Voinigescu, A 2x44Gb/s 110-GHz Wireless Transmitter with Direct Amplitude and Phase Modulation in 45-nm
SOI CMOS, in IEEE CSICS, Oct 2013, pp. 14.
[3] S.Shopov, A.Balteanu, and S.Voinigescu, A 19 dBm, 15 Gbaud, 9 bit
SOI CMOS Power-DAC Cell for High-Order QAM W-Band Transmitters, IEEE JSSC, vol. 49, no. 7, pp. 16531664, July 2014.
[4] Z.-M.Tsai, et al., A 1.2V broadband D-band power amplifier with 13.2dBm output power in standard RF 65-nm CMOS, in IEEE MTT-S IMS,
June 2012, pp. 13.
[5] M.Seo, et al., A 150 GHz Amplifier With 8 dB Gain and + 6 dBm Psat
in Digital 65 nm CMOS Using Dummy-Prefilled Microstrip Lines,
IEEE JSSC, vol. 44, no. 12, pp. 34103421, Dec 2009.

[6] H.-C.Lin and G. M.Rebeiz, A 112-134 GHz SiGe Amplifier with Peak
Output Power of 120 mW, in IEEE RFIC, 2014, pp. 163166.
[7] N.Sarmah, P.Chevalier, and U.Pfeiffer, 160-GHz Power Amplifier Design in Advanced SiGe HBT Technologies With Psat in Excess of 10
dBm, IEEE Trans. on MTT, vol. 61, no. 2, pp. 939947, Feb 2013.
[8] T.Reed, et al., A 180mW InP HBT Power Amplifier MMIC at 214
GHz, in IEEE CSICS, Oct 2013, pp. 14.
[9] N.Deferm and P.Reynaert, A 120 GHz Fully Integrated 10 Gb/s
Short-Range Star-QAM Wireless Transmitter With On-Chip Bondwire
Antenna in 45 nm Low Power CMOS, IEEE JSSC, vol. 49, no. 7, pp.
16061616, July 2014.
[10] Y.Yang, et al., A 155 GHz 20 Gbit/s QPSK Transceiver in 45nm
CMOS, in IEEE RFIC, 2014, pp. 365368.
[11] N.Deferm and P.Reynaert, A 120GHz 10Gb/s phase-modulating transmitter in 65nm LP CMOS, in IEEE ISSCC, Feb 2011, pp. 290292.

TABLE I: Comparison to power amplifier results at D-band and above.

Ref.

Technology

Design

This work
[4]
[6]
[6]
[7]
[8]

45-nm SOI CMOS

65-nm CMOS
90-nm SiGe HBT
90-nm SiGe HBT
130-nm SiGe HBT
250-nm InP HBT

2-stage power-DAC
4-stage single-ended
4-stage single-ended
4-stage 8-way comb.
3-stage differential
3-stage 16-way comb.

Frequency
(GHz)
128150
140
114134
112130
160
214

PSAT
(dBm)
13.2
13.2
13.8
20.8
10
22.6

Peak PAE
(%)
2.8
14.6
11.6
7.6
1.4

Peak Gain
(dB)
9.4
15
20
15
32
22

Supply
(V)
4.4
1.2
1.5
1.5
4
+2.85, -2.35

TABLE II: Comparison to D-band power-DAC/transmitter results.

Ref.

Technology

This work
[2]
[9]
[10]
[11]

45-nm SOI CMOS

45-nm SOI CMOS
45-nm CMOS
45-nm SOI CMOS
65-nm CMOS

Frequency
(GHz)
125144
100113
114.3
155
116

PSAT
(dBm)
13.2
11.7
6
1
-6.5

Peak PAE
(%)
2.8
-

255

Data rate
(Gb/s)
1.74
244
10
20
10

Modulation
64-state ASK + BPSK + OOK
BPSK + OOK
QPSK/8QAM
QPSK
BPSK/QPSK/8QAM

Table of Contents

Advannced Process and Modeling on

600+ GHz Emittter Ledge Type-II GaAsSb/InP DHBT
Huiming Xuu1, Barry Wu2, Ardy Winoto1, and Milton Feng1
1

Department of Electrical and C

Computer Engineering, University of Illinois at Urbana-Champaign,
U
Urbana, IL 61801 USA

High Frequency Technology Ceenter, Agilent Technologies, Inc., 1400 Fountain

n grove Pkwy, Santa
Rosa, CA 95403 USA
capacitances and resistances of the device in order to
achieve higher fMAX [9]. As the em
mitter width of a DHBT
is reduced, the emitter peripheral surface recombination
current will become a more significant part of the total
base current, leading to further reeduction of the current
gain, increased 1/f noise, and degraaded reliability (known
as the emitter size effect) [10, 11]. To mitigate the emitter
size effect, emitter ledge processes have been developed
d a Type-I InGaAs/InP
for an InGaP/GaAs SHBT [12] and
DHBT [13], respectively, demonstrrating improvements in
current gain and reliability. Later, an InGaAsP ledge was
Sb/InP DHBT [14] and
also proposed for a Type-II GaAsS
demonstrated for a 1x10 m2 dev
vice with = 83 and
fT/fMAX = 190/98 GHz [15]. In thiis paper, we developed
an AlInP emitter ledge for a 0.25 m
doping-graded base
Type-II GaAsSb/InP DHBT. The
T
0.25 m device
exhibited = 24 (a 50% improv
vement over a device
without ledge), BVCEO = 6.3V and
a
fT/fMAX = 480/620
GHz. Based on the measured S-parameters,
S
we have
performed small signal equivalen
nt circuit modeling for
600+ GHz Type II DHBTs with
h and without emitter
ledge.

Abstract An AlInP emitter ledgee (EL) has been

developed for a Type-II GaAsSb/InP DHB
BT with dopinggraded base. The AlInP emitter ledge has efffectively reduced
emitter peripheral surface recombination current, thus
improving current gain. A 0.25 x 5 m2 device has
demonstrated maximum current gain = 224, BVCEO = 6.3 V
and fT/fMAX = 480/620 GHz. RF performan
nces of 600+ GHz
Type II DHBTs with and without emitterr ledge have also
been compared.
Index Terms Ledge, GaAsSb, DHBT
T, doping graded,
InP, surface recombination, THz transistor..

I. INTRODUCTION

Compared with Type-I InGaAs/InP D

DHBTs, Type-II
GaAsSb/InP DHBTs have a staggeredd Type-II basecollector band alignment, thus eliminatiing the need to
grade the base-collector junction to avoid current
blocking. Since the first demonstratiion of Type-II
GaAsSb/InP DHBTs in 1996 [1], thhere have been
considerable improvements on the devicces DC and RF
performance [2-7]. In 2005, a Type-II GaA
AsSb/InP DHBT
IC process was developed for RF, microwave and
telecommunications instrumentation [[2]. Lately, a
composition-graded base Type-II GaA
AsSb/InP DHBT
reported fT/fMAX = 428/621 GHz for a 0.22x4.4 m2 device
with = 19 [5]. A doping-gradedd base Type-II
GaAsSb/InP DHBT has also been dem
monstrated with
fT/fMAX = 470/540 GHz and = 19 for a 0.38x5 m2
device [6]. Most recently, a compositiion-graded base
Type-II GaAsSb/InP DHBT reported fM
MAX = 715 GHz
with fT = 429 GHz and = 11 for a 0.3xx4.4 m2 device
with sputtered base metal contact [7]]. For Type-I
InGaAs/InP DHBT, a 0.13x2 m2 deviice has reported
fT/fMAX = 521/1150 GHz with = 17 [8].
For all the above devices with fMAX > 500 GHz, is
relatively low ( 20). This is because iin order to have
high fMAX, the base needs to be heavily doped to reduce
the base resistance. A more heavily dopeed base will lead
to higher base recombination current annd lower current
gain. Lateral scaling is also needed to reduce the

978-1-4799-3622-9/14/$31.00 2014 IEEE

II. LAYER STRUCTURE DESIGN AND

D DEVICE FABRICATION

Fig. 1. (Color Online) The process steps for the formation

of an AlInP emitter ledge in a Type-II GaAsSb/InP
DHBT.

256

Table of Contents

TABLE I
Layer Structure of the Type-II GaAsSb/InP DHBT
Layer

Comment

Materia
al

Thickness ()

Dopant

Lev
vel (cm-3)

Type

12

Cap

InxGa1-xA
As

0.53~1

350

Si

Maximum

N+

11

Cap

InxGa1-xA
As

0.53

100

Si

Maximum

N+

10

Emitter

InP

700

Si

Maximum

N+

Emitter

InP

100

Emitter

InP

200

Emitter

AlxIn1-xP

0.1~0

6
5
4
3
2
1

Base
Collector
Sub-Collector
Sub-Collector
Sub-Collector
Etch Stop
Substrate

GaAsxSb
b1-x
InP
InP
InxGa1-xA
As
InP
InxGa1-xA
As
InP

0.5
0.53
0.53

Si

18

2.0x10
2

Si

17
4.0x10
4

175

Si

17
4.0x10
4

200
1200
500
350
3500
100

C
Si
Si
Si
Si

8.0~
~17.0x1019
2x1016
Maximum
Maximum
Maximum
UID

P+
N
N+
N+
N+

d HCL:H2O (1:1.5) was

the emitter ledge. Secondly, diluted
used to etch away the InP emitterr layer and part of the
AlInP emitter layer. Thirdly, a layeer of 100 nm SiNX was
deposited using PECVD and etch
hed back using RIE to
form a SiNX spacer. Finally, the AlInP
A
layer was etched
away using 0 oC HCL, leaving a thin layer of AlInP
emitter ledge for the passivation of the extrinsic base
a base contact metal.
surface between the emitter mesa and
A SEM image of a device after th
he formation of emitter
ledge is shown in Fig. 2. To have a clear SEM image, the
SiNX protection mask has been rem
moved before SEM. The
thickness and width of the AlInP emitter
e
ledge is around
15 nm and 90 nm, respectively. The
T base metal contact
was formed in a self-aligned processs.

The epitaxial layer structurefor this studdy was grown on

a 3-inch semi-insulating InP substrate by molecular beam
epitaxy (MBE). The layer structure of the device is shown
in Table I. The 20 nm base of the Typee-II GaAsSb/InP
DHBT is formed by GaAs0.5Sb0.5 withh graded carbon
doping. The doping is graded from 1.7 x 1020 cm-3 on the
emitter side to 8.0 x 1019 cm-3 on the ccollector side, to
create a quasi-electric field in the base. The base sheet
resistance is 850 /sq. determinedd from TLM
measurement.

III. DHBT EMITTER SIZE EF

FFECT ANALYSIS

Fig. 3 shows the Gummel and currrent gain plots for (a) a
0.25x5 m2 device without emitter ledge and (b) a 0.25x5
m2 device with a 90 nm ledge. For device (a), there is no
AlInP emitter ledge, and the distance between emitter
mesa and base metal contact is around 40 nm. The device
without ledge has demonstrated maaximum current gain
= 16, with nB = 1.70 and nC = 1.0
02. In comparison, the
device with a 90 nm ledge has demonstrated maximum
current gain = 24. The base and collector ideality
factors are nB = 1.51 and nC = 1.04, respectively. Thus,
the 90 nm ledge has improved thee current gain by 50%
and reduced the base currrent ideality factor,
demonstrating its effectiveness in suppressing
s
the emitter
peripheral surface recombination current. The measured
own voltage (BVCEO) of
common emitter open base breakdo
the device with emitter ledge is aro
ound 6.3 V at JC = 10-2
2
mA/m .
To investigate the emitter sizee effect, we measured
devices with different emitter wid
dths and extracted the

Fig. 2. A SEM image of the device aftter emitter ledge

formation. (To have a clear SEM image, the SiNX spacer
has been removed before SEM.)
Devices with various emitter widths were fabricated
using a triple mesa wet-etch process withh metal contacts
defined by electron beam lithographyy. The detailed
emitter ledge process steps are illustraated in Fig. 1.
Firstly, the emitter mesa was formed by eetching away the
InGaAs contact layer using Citric:H2O2 (110:1) and emitter
metal as the etching mask. The etchinng time of the
InGaAs contact layer was controlled too form a 90 nm
undercut. This undercut will determine thhe final width of

257

Table of Contents

recombination, the current gain cou

uld be as high as 30 for
this material structure.

emitter peripheral surface recombinationn current density

KSURF by plotting base current JC/ as a fu
function of PE/AE
at a given collector current density. The tootal base current
could be written as JC/ = JIN + KSURF PE/AE. Here, JIN is
the intrinsic base current, KSURF is the em
mitter peripheral
surface recombination current density, PE is the emitter
peripheral length, and AE is the emitter arrea. Fig. 4 shows
the JC / vs PE /AE plot at collector currennt density JC of
100 A/m2 for devices with 90 nm leddge and devices
without ledge. For devices without ledgge, the extracted
KSURF is 2.42 A/m and JIN is 5.76 A/
m2. For devices
with 90 nm ledge, the extracted KSURF is 0.52 A/m and
JIN is 5.46 A/m2.

Fig. 5. Emitter peripheral surface recombination current

d
J C.
density KSURF vs collector current density
IV. RF PERFORMA
ANCE

Fig. 3. (Color online) Gummel and curreent gain plots for

(a) a 0.25x4 m2 device without ledge aand (b) a device
with a 90 nm ledge.

Fig. 6. (Color online) A single--pole transfer function

fitting shows fT/fMAX = 480/620 GHz.
G
Inset: fT and fMAX
performance of the device biased
d at VCB = 0.5 V and
varying collector current density lev
vels.
The S-parameters of device with
h a 90 nm emitter ledge
were measured from 0.5 to 50 GHz
G
using an Agilent
8364A network analyzer. The network
n
analyzer was
calibrated using an off-wafer SOL
LT standard calibration
substrate. The probe contact capaciitances and inductances
were de-embedded using on-waafer open and short
standards. Contact pad capacitancces were stripped first
followed by inductances. The referrence planes of the deembedding are the device termin
nals. Fig. 6 shows the
plots of current gain |H21|2 and unillateral power gain U of
a 0.25 x 5 m2 device biased at JC = 6 mA/m2 and VCB =
0.5 V. A single-pole transfer function fitting of |H21|2 and
u
to extrapolate the
U from 1 GHz to 40 GHz was used
cutoff frequencies fT/fMAX = 480/6
620 GHz. The inset of

Fig. 4. (Color online) The JC / vs PE /AE plot at collector

current density JC of 100 A/m2 for devvices with 90 nm
ledge and devices without ledge.
Figure 5 shows the extracted KSURF at vvarious collector
current densities. It is clear that devicces with 90 nm
emitter ledge have reduced emitter peeripheral surface
recombination current density by at least a factor of 4. It
is estimated that without emitter perripheral surface

258

Table of Contents

without emitter ledge, it is determ

mined that the reduction
in fMAX is mainly due to the increease of base resistance.
The base resistance increases for the
t device with 90 nm
emitter ledge because of the inccrease of the distance
between emitter mesa and base metal contact. As the
wn further, the base
device emitter width scales dow
resistances and base-collector cap
pacitances related with
emitter ledge would become more significant,
s
limiting the
device fMAX performance. So, the optimization
o
of emitter
ledge width is needed to achiieve optimum device
performance.

Fig. 6 shows the plot of fT/fMAX performannce of the device

as a function of bias current at VCB = 0.5 V
V.
An equivalent small signal circuit moddel for the device
was extracted from the measured S-param
meters and shown
in Fig. 7. The measured and simulated S-Parameters fit
quite well, as shown in the Smith Chart oof Figure 7. The
simulated cut-off frequencies from the eequivalent small
signal circuit model are fT/fMAX = 480/6630 GHz, which
agree well with the extracted value fr
from single-pole
fitting method.

V. CONCLUSIION

An AlInP emitter ledge has been

b
developed for a
doping-graded base Type-II GaAsS
Sb/InP DHBT. A 0.25 x
5 m2 device with a 90 nm ledgee demonstrated a peak
current gain of 24, which is a 50% improvement
ut ledge. This result
compared to the device withou
demonstrates the effectiveness of the
t AlInP emitter ledge
in reducing the emitter peripheral surface recombination
current. In addition, equivalent circcuit modeling has been
developed to explain the performan
nce difference in fMAX.
Fig. 7. (Color online) Small-signal circuuit model of the
0.25x5 m2 Type-II GaAsSb/InP DHBT
T with a 90 nm
emitter ledge.

REFERENCESS
[1]
[2]

[3]

[4]
[5]

Fig. 8. (Color online) A single-pole trransfer function

fitting shows fT/fMAX = 480/660 GHz. Innset: fT and fMAX
performance of the device biased at VCCB = 0.5 V and
varying collector current density levels.

[6]
[7]
[8]

Fig. 8 shows the plots of current gain |H21|2 and

unilateral power gain U of a 0.25 x 5 m
m2 device without
2
emitter ledge, biased at JC = 6 mA/m aand VCB = 0.5 V.
A single-pole transfer function fitting of |H
H21|2 and U from
1 GHz to 40 GHz was used to extrappolate the cutoff
frequencies fT/fMAX = 480/660 GHz. Com
mparing the two
devices, it is shown that having a 90 nnm emitter ledge
would reduce the device fMAX performaance. Comparing
the small signal models for the two deevices with and

[9]
[10]
[11]
[12]
[13]

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170 GHz SiGe-BiCMOS Loss-Compensated Distributed Amplifier

Paolo Valerio Testa, Guido Belfiore, David Fritsche, Corrado Carta, and Frank Ellinger
Technische Universitt Dresden, Dresden, Saxony, 01187, Germany
E-mail: paolo_valerio.testa@tu-dresden.de
Abstract This paper presents a travelling-wave amplifier
(TWA) for wideband applications implemented in a 0.13 m
SiGe BiCMOS technology (ft = 300 GHz, fmax = 500 GHz).
The gain cell employed in the TWA is designed to
compensate the transmission-line-losses at high frequencies
in order to extend the bandwidth as well as the gain
bandwidth product (GBP). A gain of 10 dB and a 3-dB
bandwidth of 170 GHz are measured for the fabricated
TWA. The chip has a chip area of 0.38 mm2 and a power
consumption of 108 mW. Compared against the state of the
art, the presented design achieves the highest reported GBP
per area and power consumption.
Index Terms Distributed amplifier, BiCMOS integrated
circuits, propagation losses, ultra wideband technology.

II. FREQUENCY LIMITS OF THE TWA

In Fig. 1 the general TWA circuit topology is depicted.
The system consists of several gain elements embedded
between two transmission lines, carrying input and output
signals. The fundamental idea is to embed the input and
output gain cell capacitances within the guiding structures
to realize synthetics transmission lines. These will be
characterized by different propagation constants and
characteristic impedances from the original ones.

I. INTRODUCTION
The performances of wideband amplifiers are important
for several applications at mm-wave frequencies [1,2] such
as radar imaging, optoelectronics, space radiometry, high
frequency trans-ceivers and ultrafast measurement systems.
A popular approach to the design of such amplifiers is to
exploit distributed amplification techniques, as first
proposed by Percival in 1936 [3]. The resulting circuit
family of travelling-wave amplifiers (TWAs) has been
studied extensively and examples of implementation have
been reported in many different technologies: InP HEMT
and DHBT [1], Si CMOS [4,8], SOI CMOS [5], and GaAs
HBT [6]. Additionally TWAs fabricated in SiGe
technology with bandwidth exceeding 100 GHz have been
recently demonstrated [10].
In this work a high performance 0.13 m SiGe
BiCMOS technology (ft = 300GHz, fmax = 500 GHz), is
used to realize a TWA with the aim of improving the gainbandwidth product (GBP) at moderate levels of power
consumption. The main innovation introduced in the
design is a peak in the equivalent transconductance (Gm) of
the amplifier gain cells to compensate the line losses at
high frequency. This is shown to increase the circuit
bandwidth.
The TWAs speed limitations are presented in section
II, then the designed Gm boosted TWA follows in section
III. In section IV measurement results are reported.
Section V summarizes the work and gives a comparison
against the state of the art.

978-1-4799-3622-9/14/$31.00 2014 European Union

Fig. 1.

Travelling-wave amplifier circuit topology.

With adequate design, a signal can propagate in the

input line, be amplified by the gain elements and
transmitted on the output guiding structure at frequencies
up to the cut-off frequency of the synthetic lines [5]:

fc =

1
L'l (C 'l + Cin )

(1)

where L and C are the inductance and capacitance per

unit of length of the real lines, Cin is the input capacitance
of the gain cell and l is the separation between the gain
cells.
In practical TWA implementations, the signal
propagation losses have to be considered. There are two
main types of losses: those arising from the real line, and
those caused by the insertion of the gain cells. The latter
have much more impact on the TWAs behavior than the
former, which can be neglected [5]. Furthermore if the gain
cell is based on a cascode topology, then its output
resistance is much larger than the input one. In most
practical cases, it can be found that the input resistance of
the gain cell is the main loss contributor [5]. Its presence

261

Table of Contents

entails that an electromagnetic wave propagating in the

input line will be attenuated over the length l of e- [1],
where:

= 2 2 f 2Cin2 Rin Z 0

technology and bias conditions (IC = 6 mA, VCE = 1.2 V),

Fig. 3 shows the comparison of the simulated equivalent
gain cell transconductance (Gm) of the gain cell used in
this work, against those of a conventional cascode
amplifier with and without the Le inductor. Since the
amplifier gain is proportional to Gm [5], its positive slope
(trace a in Fig. 2) has been exploited to compensate the
losses (2) and, thus, improve the amplifier bandwidth.
The gain-cell bias points are current controlled through
Rb, while the capacitors C1 and C2 are employed to AC
ground the Q2-Q1 bases. The main supply voltage is
provided externally from the output of the amplifier.
The resistors Rs1, Rs2, and Rs3 ensure the gain cell
stability. While Rs3 stabilizes the output of the amplifier,
Rs1 and Rs2, decoupled from DC through the MOS
capacitors M1-M2, entail the stability of the common bases
stages Q2-Q1[7].

(2)

f is the wave frequency, Rin is the input resistance of the

gain cell, and Z0 is the synthetic line impedance expressed
by:

Z0 =

L'
C
C '+ in
l

(3)

Since increases with quadratic frequency dependence, it

reduces the 3-dB bandwidth of the amplifier to values
smaller than described in (1), and represents the main
frequency limitation in the state-of-art TWAs.
III. CIRCUIT DESIGN
A. Gm-Boosted Gain Cell
The schematic of the designed distributed amplifier is
presented in Fig. 2. This TWA is based on a cascode stage
(Q0-Q1) gain cell, followed by an additional common base
amplifier (Q2).
To improve the frequency response of the TWA (1) (2),
the resistor Re and the capacitor Ce are employed as
negative feedback [1,2]. Furthermore the capacitor Cb
decreases the Cin at expense of slightly lower gain [1,2].
The collector-emitter connections between Q1-Q0 and
Q2-Q1 are realized with bridge shaped metal lines to obtain
controlled parasitic inductances of 12 pH.

Fig. 3. Comparison of the simulated transconductance of the

gain cell used in this work (a), with those of a cascode amplifier
with the series inductor Le (b) and without (c). IC and VCE, are the
same for each transistor (IC = 6 mA, VCE = 1.2 V).

B. Transmission Lines
A view of the coplanar transmission line used to
connect the gain cells is shown in Fig. 4. All the seven
metal layers offered by the process have been used to
realize a transmission line with characteristic impedance
of 100 Ohm. The width of the signal conductor is 2 m,
while the distance to the side walls is 20 m. The ground
conductor of the transmission line is patterned with slots
orthogonal to the direction of propagation. The slot width
is 0.75 m and 0.25 m their relative spacing. The aim is
to force the return current to flow into side walls
increasing the line inductance and reducing the losses [8].
In this way, it is possible to reduce the value of l (3)
required for a Z0 of 50 Ohm. This results in a smaller

Fig. 2. Circuit schematic of the five stage distributed amplifier

presented in this work.

These inductances are represented in Fig. 2 with the

inductors Le. It is known that their presence improve the
cascode amplifiers bandwidth [4]. For the same

262

Table of Contents

active area. The final design value for l is 130 m, while

the number of gain stages is 5. The chip area is 0.38 mm2.
A commercially available electromagnetic CAD tool has
been used to model the transmission lines and the metal
interconnections of the gain cells (Fig. 5).

In Fig. 8 and 9 the comparison between the measured

and simulated return loss are shown: |S11| and |S22| are
below -10 dB over the entire bandwidth of the amplifier.

Fig. 4.
line.

Fig. 6. Chip photograph of the Gm Boosted TWA. The chip

2
area is 0.38 mm (0.85 mm 0.45 m).

A 100 Ohm ground patterned coplanar transmission

20

S-parameters [dB]

10
0
-10
-20
S11 Mes
S22 Mes
S21 Sim
S21 Mes

-30
-40
-50
0

50

100
f [GHz]

150

200

Fig. 7. Measured S-parameters for ICC = 30 mA

VCC = 3.6 V, and comparison with the simulated |S21|.

Fig. 5. Interconnections within the gain cell and between the

gain cell and the input and output TWA lines.

and

IV. CIRCUIT CHARACTERIZATION

S11 Mes
S11 Sim

-5

A microscope photograph of the circuit electrically

contacted with RF probes is shown in Fig. 6. All the
measurements are performed on-chip with wafer probes,
when the circuit is biased at ICC = 30 mA and VCC = 3.6 V.
The pad parasitics have been taken in account during
the design through electromagnetic simulations. For this
reason it is not necessary to de-embedded them from the
measurement results.
A Rohde & Schwarz ZVA 67 vector analyzer is used to
measure the S-parameters. To characterize the ultra-wide
spectrum of amplification, three different measurement
set-ups are employed in the following frequency ranges:
from 200 MHz to 67 GHz, from 90 GHz to 140 GHz, and
from 140 GHz to 220 GHz. Fig. 7 shows the measured Sparameters and the simulated S21. The amplifier provides a
gain of 10 dB from 1 GHz to 170 GHz.

-10
|S11| [dB]

-15
-20
-25
-30
-35
-40
-45
-50
0

50

100
f [GHz]

150

200

Fig. 8. Comparison between simulated (dotted) and measured

(solid) |S11| at ICC = 30 mA and VCC = 3.6 V.

263

Table of Contents

TABLE I
COMPARISON OF PUBLISHED DISTRIBUTED AMPLIFIERS

|S22| [dB]

FoM
N/A
1.10
2.56
9.34
13.8

BW [GHz]
180
120
73
15-110
170

Gain [dB]
5
21
14
24
10

Technology
InP HEMT
InP DBHT
90 nm Si CMOS
0.13 m SiGe
0.13 m SiGe

GBP [GHz]
320
1346
370
1500
537

Area [mm ]
2.1
2.00
1.72
0.65
0.38

PDC [mW]
N/A
610
84
247
108

Ref.
[1]
[9]
[8]
[10]
This work

the research project DAAB, as well as the programs

HAEC (subproject A1) and cfAED (Resilience path).

0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50

S22 Mes
S22 Sim

50

REFERENCES

100
f [GHz]

150

[1] B. Agarwal, A. E. Schmitz, J. J. Brown, M. Matloubian, M.

G. Case, M. L. Lui, and M. J W. Rodwell, 112-GHz, 157GHz, and 180-GHz InP HEMT Traveling-Wave
Amplifiers, IEEE Trans. Microwave Theory & Tech., vol.
46, no. 12, pp. 2553-2559, December 1998.
[2] J. Chen, and A. M. Niknejad, Design and Analysis of a
Stage-Scaled Distributed Power Amplifier, IEEE Trans.
Microwave Theory & Tech., vol. 59, no. 5, pp. 1274-1283,
May 2011.
[3] E. L. Gizton, W. R. Hewlett, J. H. Jasberg, and J. D. Noe,
Distributed Amplification, Proceedings of the I. R. E., pp.
956-960, August 1948.
[4] M. Egels, J. Gaubert, and P. Pannier, Guide line for
standard CMOS traveling wave amplifier design, IEEE
Conference on Microelectronics, ICM 2005, December
2005.
[5] F. Ellinger, 60-GHz SOI CMOS Traveling-Wave
Amplifier With NF Below 3.8 dB From 0.1 to 40 GHz,
IEEE Journal of Solid-State Circuit, vol. 40, no.2, pp. 553558, February 2005.
[6] C. Meliani, M. Rudolph, R. Doerner, and W. Heinrich,
Bandwidth Potential of Cascode HBT-Based TWAs as a
Function of Transistor fmax / fT Ratio, IEEE Trans
Microwave Theory & Tech, vol. 56, no. 56, pp. 1331-1337,
June 2008.
[7] R. L. Schmid, C. T. Coen, S. Shankar, and J. D. Cressler,
Best Practices to Ensure the Stability of SiGe HBT
Cascode Low Noise Amplifiers, Bipolar/BiCMOS Circuits
and Tech. Meeting, pp. 14, October 2012.
[8] A. Arbabian, and A. M. Niknejad, A tapered cascaded
multi-stage distributed amplifier with 370 GHz GBW in
90 nm CMOS, in IEEE RFIC Symp., pp. 5760, April
2008.
[9] V. Hurm, F. Benkhelifa, R. Driad, R. Lsch, R. Makon, H.
Massler, J. Resnweig, M. Schechtweg, and H. Walcher,
InP DHBT-based distributed amplifier for 100 Gbit/s
modulator driver operation, Electronic Letters, vol. 42, no.
12, pp. 705-706, June 2008.
[10] A. Arbabian, and A. M. Niknejad, A Three-Stage
Cascaded Distributed Amplifier with GBW Exceeding
1.5THz, in IEEE RFIC Symp., pp. 211-214, June 2012.

200

Fig. 9. Comparison between simulated (dotted) and measured

(solid) |S22| at ICC = 30 mA and VCC = 3.6 V.

V. CONCLUSIONS
A traveling-wave amplifier has been designed and
fabricated in a 0.13 m SiGe BiCMOS process for
wideband applications. The chip area is 0.38 mm2.
Consuming 30 mA from a 3.6 V voltage supply, the
amplifier provides 10 dB gain over the bandwidth of
170 GHz. Table I presents a comparison with recentlypublished distributed amplifiers. At expenses of chip area
and power consumption PDC, the GBP can be increased
linearly by cascading TWAs. To account for this design
tradeoff and ease the comparison, we define the following
figure of merit:

FoM =

GBP
Area PDC

(5)

The presented design solution achieves the highest GBP

per area and power consumption (FoM).
The performance improvements presented are enabled
by the introduction of a crucial circuit-design innovation:
the compensation at high frequencies of the synthetic line
losses with a frequency-dependent increase of the gain-cell
transconductance.
ACKNOWLEDGMENT
This work has been supported in parts by DFG
(Deutsche Forschungsgemeinschaft), within the frame of

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Table of Contents

Direct Down-conversion 38 GHz GaAs and SiGe Receivers

Ryan M. Clement1,3, Leigh E. Milner2, Emmanuelle R. Convert1, Leonard Hall2, Michael Parker2, MacCrae
G. McCulloch1, Anna Dadello1, Benny Wu1, James T. Harvey1, Anthony E. Parker3,1, Simon J. Mahon1
1

Macom Sydney Design Centre, 157 Walker Street, North Sydney, NSW 2060, Australia
Defence Science and Technology Organisation, West Avenue, Edinburgh, SA 5111, Australia
3
Department of Engineering, Macquarie University, NSW 2109, Australia

up to 190 GHz and Fmax up to 220 GHz. The breakdown

voltages are 1.9 V for collector to emitter and 4.5 V for
collector to base. The process features five thinner and two
thicker metal layers. AWRs Microwave Office was used for
the GaAs design which was fabricated at WIN in Taiwan using
a 0.15 m pHEMT process with two metal layers.

AbstractDirect down-conversion receivers at Ka band in

GaAs and SiGe are measured and analysed with particular
attention to linearity. The GaAs receiver is observed to have the
superior overall linearity although SiGe has the better secondorder behaviour. The linearity is discussed with respect to the
requirements of point-to-point radio and for the first time, to the
authors knowledge, an explanation is established for the effect of
third-order distortion in the LNA on the second-order distortion
from the complete receiver.
KeywordsDirect down-conversion, Receivers,
GaAs, SiGe, Millimetre-wave Intergrated Circuits

Linearity,

I. INTRODUCTION
Fig. 1: GaAs receiver in 4x4 QFN (left) and SiGe (right).

Radios in the millimetre-wave band are under strong price

pressure leading to examination of alternative semiconductor
systems such as SiGe [1-6] to the standard GaAs [7-9] and to
alternate architectures such as direct down-conversion. SiGe
receivers are acknowledged to have lower cost potential in very
large volume manufacturing but poorer noise figure and
linearity. In this paper, we examine the direct down-conversion
of GaAs and SiGe receivers with particular attention paid to
linearity which is measured up to seventh order.

III. MEASURED RESULTS

The measured noise figure of the packaged GaAs receiver
is 3.5 to 4 dB with 15 dB conversion gain compared to a noise
figure of 7.5 to 8 dB for the bare die SiGe receiver with 25 dB
conversion gain.
Direct down-conversion, two-tone measurements of the
receivers were made at 38 GHz over an LO power range of -6
to 6 dBm. The differential IF outputs were combined with
180 degree off-chip hybrids. The GaAs receiver, being an
image-reject design, has both I and Q channels but as the
measured data for the two was similar, we report only the Q
channel for simplicity. The RF input tones were set to 41 and
53 MHz above the nominal 38 GHz RF frequency, e.g. 38.041
and 38.053 GHz, to create wanted IF at 41 and 53 MHz.
Measurements were made at the intermodulation products up to
seventh order with particular care taken to avoid contamination
by instrument non-linearities.
Fig. 2 shows the wanted and intermodulation direct downconversion IF tones (up to seventh-order and 200 MHz) for the
GaAs and SiGe receivers measured at 38 GHz with an LO of
0 dBm and RF input power levels of -30 and -20 dBm per tone
to represent the power control options specified by ETSI. In
this figure, the intermodulation levels are expressed relative to
the wanted tones. The green symbols show the second-order
subtractive intermodulation tone at 12 MHz (IF2 IF1) and the
three second-order additive intermodulation tones at 82 MHz
(2IF1), 94 MHz (IF1 + IF2) and 106 MHz (2IF2). The blue
symbols show the two subtractive and four additive third-order
intermodulation tones, and so on for the fourth, fifth, sixth and
seven-order intermodulation tones subject to the spectrum
analyser noise floor at approximately -120 dBm.

Design and fabrication of the receivers is reviewed in

Section II and a selection of measured data for the parts is
presented in Section III. A discussion occurs in Section IV.
II. DESIGN AND FABRICTAION
Both the GaAs and SiGe receivers (Fig. 1) studied here
were designed for Ka band operation and share a similar
architecture of low noise amplifier (LNA), mixer and LO
multiplier and buffer; however, there are some noteworthy
differences. The GaAs LNA is a single-ended, four-stage
design and the resistive mixer has balanced in-phase and
quadrature channels. The SiGe LNA is a differential cascode
design with transformers used to provide a compact inter-stage
matching network for the differential signal that
simultaneously rejects common mode signals [10]. The
Gilbert-cell mixer has a balanced in-phase channel but no
quadrature channel thus no image-rejection. The gain of the
SiGe receiver is approximately 10 dB higher than the GaAs
circuit due to the use of an active mixer. The LNA gains are
comparable, thus input-referred mixer products referred to the
receiver input are shifted by similar gain factors.
Both designs relied on extensive electromagnetic
simulation to improve simulation accuracy. AWRs Analog
Office was used for the SiGe design which was fabricated on
the IHP SG25H1 process in Germany. It is a high performance
0.25 m BiCMOS technology with carbon doped npn-HBTs, Ft

978-1-4799-3622-9/14/$31.00 2014 IEEE

265

978-1-4799-3622-9/14/$31.00 2014 IEEE

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Table of Contents

20

40

60

80

100

120

140

160

180

the subtractive second-order product at RF2 RF1 = 38.053

38.041 GHz = 12 MHz is removed by the LNAs output
capacitor). Additive odd-order products are also attenuated by
the LNA roll-off (e.g. 2RF2 + RF1 = 238.053 + 38.041 GHz
= 114.147 GHz is above the LNAs gain band).
However, subtractive third-order LNA distortion does
contribute to products such as the subtractive second-order
product at 12 MHz. Consider an LNA excited by tones, 1 and
2, with an output containing the wanted tones and two closein third order tones. This becomes the input for the mixer, Vmi,
2
2
(1)
where C accounts for the normalised third-order distortion. The
receiver output, VIF, may be approximated as
(2)
Substituting (1) into (2) gives
9
2
cos
1
4
9
cos
2
1
4
1
1
cos 2
cos 2
2
2
2
1
cos
cos
1

200

20

0
-10

-20GaAs, IF
-30SiGe, IF

Pout (dBc)

-20

GaAs, 2nd

-40SiGe, 2nd

GaAs, 3rd
SiGe, 3rd
-60GaAs, 4th
SiGe, 4th
-70
SiGe, 5th
-80SiGe, 6th
SiGe, 7th

-40

-50

-60
-80

-90
-100

-100
0

20

40

60

20

40

60

80
100 120 140
Frequency (MHz)
80

100

120

140

160

180

200

160

180

200

20

20
GaAs, IF

0 SiGe, IF

GaAs, 2nd

-20SiGe, 2nd

Pout (dBc)

-20

GaAs, 3rd
SiGe, 3rd
-40GaAs, 4th
SiGe, 4th
GaAs, 5th
-60
SiGe, 5th
GaAs, 6th
-80SiGe, 6th
GaAs, 7th
SiGe, 7th

-40
-60
-80
-100

cos 3

-100
0

20

40

60

80
100 120 140
Frequency (MHz)

160

180

cos 3

200

3
4

cos 2

Fig. 2: Intermodulation carrier-to-distortion levels to seventh order

for GaAs (squares) and SiGe receiver (triangles) graphed with respect
to the wanted direct down-conversion tones of 41 and 53 MHz (red).
Upper graph: RF = -30 dBm/tone. Lower: RF = -20 dBm/tone.

cos
cos

Expressing the intermodulation levels as input-referred,

intercept points (IIP2, IIP3 etc.) and varying the RF tone and
LO levels allows the receivers to be studied in more detail. Fig.
3 plots input-referred intercept points for the GaAs receiver as
a function of LO and RF power for three intermodulation
tones, subtractive IIP2 at 12 MHz, subtractive IIP3 at 29 MHz
and additive IIP3 at 159 MHz. Fig. 4 presents the
corresponding data for the SiGe receiver.
Cutting the measured data of the contour plots, such as Fig.
3 and Fig. 4, at an LO power of 0 dBm allows easier
comparison of the different intermodulation tones of a given
order and their dependence on RF power level. Fig. 5 illustrates
the second-order terms and a function of input RF power and
Fig. 6 illustrates the third-order terms of the two receivers.

4
2

1
3
4

2
3

cos 2
3
6
1
+ (3)
The subtractive and additive even-order and additive oddorder intermodulation terms present at the IF may be
dominated by mixer but the linearity of the LNA is important
as established by (3). This equation also predicts that the
distortion at 1 + 2 will exceed that at 21 and 22 and differ
from that at 1 2 as seen in the measured data Fig. 2 and
Fig. 5.
The GaAs receiver linearity for all second and third order
products is relatively immune to RF input power level (Fig. 5
and Fig. 6), as the amplified signal is small compared to the
extent of the linear, resistive region of the mixing transistors
I-V characteristic. Overall, the SiGe receiver has better secondorder linearity than its GaAs counterpart but it is unclear at this
time if this is due to the underlying linearity of the SiGe HBT
device or the superior baluns that have been fabricated in the
SiGe process with its more generous metal stack. The fourth
and sixth order linearity is similar between the receivers and
hence the even order products require further investigation. For
third and higher odd order products the GaAs receiver is
clearly more linear and the GaAs receiver is more linear
overall.

IV. DISCUSSION
The conversion gain for both receivers is weakly dependent
on the LO level; however, the intermodulation characteristics
of the SiGe receiver (and hence its Gilbert mixer) shows
significant variation with LO level. Presumably the balance of
the mixer is improved with increased LO drive, due to
imperfect balance of the passive baluns, as the transistors are
driven harder into conduction thus a 50/50 duty cycle.
The GaAs and SiGe LNAs have a band-pass frequency
response and hence even order products generated in the LNA
do not significantly pass into the down-converting mixer (e.g.

266

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Table of Contents

Fig. 3: Three GaAs receiver input-referred intercept points as a

function of LO power (PLO) and RF input power (per tone).
Upper: IIP2 for the subtractive second-order product at 12 MHz.
Middle: IIP3 for the subtractive third-order product at 29 MHz
Lower: IIP3 for the additive third-order product at 159 MHz.
Graphs are truncated when the intermodulation products falls below
the spectrum analyser noise floor.

Fig. 4: Three SiGe receiver input-referred intercept points as a

function of LO power (PLO) and RF input power (per tone).
Upper: IIP2 for the subtractive second-order product at 12 MHz.
Middle: IIP3 for the subtractive third-order product at 29 MHz
Lower: IIP3 for the additive third-order product at 159 MHz

267

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Table of Contents

45

40

35

30

25

20

15

60

within the desired signal bandwidth. The inherent balance of

the mixer is important in cancelling even order distortion, be it
intrinsic to the mixer or the by-product of third-order distortion
from the LNA as seen in (3). The SiGe mixer would seem to
have the edge here with well-matched devices in Gilbert
mixers and better baluns possible in a multi-layer metal stack
compared to the limited metal options in some GaAs
environments. However, while this advantage is evident in the
measured data for second-order distortion, the two
semiconductor systems exhibit similar performance for the
fourth and sixth order intermodulation. For odd order distortion
GaAs has the clear advantage and, in the case studied here, this
makes it the most linear overall. It is possible that the 1/f noise
performance of SiGe bipolar transistors will be better than
GaAs pHEMT devices, improving the close-in noise
performance of SiGe receivers, but that is outside the scope of
this present work.

60
GaAs

50

50
SiGe

IIP2 (dBm)

40

82 MHz
12 MHz

30

106 MHz

40
30

94 MHz

20

20

10

10

0
-45

-40

-35
-30
-25
RF Input Power (dBm per Tone)

-20

-15

Fig. 5: IIP2 for all second-order intermodulation terms as a function

of RF input power at PLO = 0 dBm for both receivers. Frequencies
are shown for the SiGe receiver and the same patterns are used for
GaAs.
-45

-40

-35

-30

-25

-20

-15

15

15
GaAs

10

SiGe

IIP3 (dBm)

CONCLUSION

10

The linearity of two representative GaAs and SiGe

receivers has been measured in direct down-conversion mode
at 38 GHz. The SiGe receiver has better second-order
distortion but GaAs is more linear for odd-order
intermodulation and more linear overall. An explanation has
been provided for the impact of LNA third-order distortion on
the second-order distortion of the complete receiver. Finally,
these results have been discussed with reference to the ETSI
requirements for point-to-point radio.

5
0

0
123 & 159 MHz
-5

-5

135 & 147 MHz

-10

-10
29 & 65 MHz

-15

-15
-20

-20
-45

-40

-35
-30
-25
RF Input Power (dBm per Tone)

-20

-15

ACKNOWLEDGMENT

R.G. Mould, S. Hwang and B. Reed for assistance with the

measurements, A.P. Fattorini, D.A. Richardson and M.C.
Heimlich for useful discussions and the ARC for their support.

Fig. 6: IIP3 for all third-order intermodulation terms as a function of

RF input power at PLO = 0 dBm for both receivers. Frequencies are
shown for the SiGe receiver and the same patterns are used for GaAs
which crosses the spectrum analyser noise floor near -30 dBm/tone.

REFERENCES

For heterodyne receivers with intermediate frequencies in

the 2 to 4 GHz range in point-to-point applications, the critical
requirements are noise figure and IIP3, the first driven by
specsmanship and availability in fading environments, the
latter by ETSI requirements for maximum receive levels with
high order quadrature amplitude modulation (QAM).
A 1024 QAM signal degrades when the SINAD is worse
than about 40 dB, this requires an IIP3 greater than 17 ~ 20 dB
above the maximum receive level which is often specified at
-20 dBm. Thus IIP3 values above 0 dBm are generally
specified. The GaAs receiver clearly has an edge here, due to
the use of high linearity cold FET or resistive mixers,
compared to the SiGe receiver. Note also that IIP3 is the sum
of LNA and mixer distortion, as is the case for other odd order
distortion products (5th, 7th etc.), where the products fall close
to the carrier.
Even order distortion is generally not an issue with such
heterodyne receivers, as the classical products fall well away
from the carrier, and can be removed by filtering. For low
values of IF, an even order distortion product (half IF
distortion) can be an issue when the intermediate frequency is
less than twice the receive diplexer bandwidth. A high level
interferer can generate a 2(LO-interferer product) at IF when
the interferer is halfway between the LO and the wanted RF
signal and is not rejected by the input filter.
In direct down-conversion receivers, all odd and even order
distortion products must be considered, as many of them fall

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[8] S.J. Mahon, E. Convert, P.T. Beasly, A. Bessemoulin, et al., Broadband
Integrated Millimetre-wave Up- and Down-converter GaAs MMICs
IEEE Trans. Microw Theory Tech., MTT-54, pp. 2050-2060, May 2006.
[9] E.R.O. Convert, A.P. Fattorini, S.J. Mahon, et al., Packaged, Integrated
32 to 40 GHz Millimeter-Wave Up-Converter, IEEE Compound
Semiconductor IC Symp, Monterey, 3-6 Oct 2010.
[10] L.E. Milner, L.T. Hall and M.E. Parker, Accurate Simulation of the
Frequency Response of Millimetre-Wave SiGe Amplifiers 1st Aust
Microw Symp, Melbourne, 26 - 27 June 2014.

268

268

Table of Contents

Author Index
A
Agonafer, Damena ...................... 41, 57
Akmal, M. ....................................... 213
Al Hadi, R. ...................................... 169
Alestig, G. ......................................... 21
Ambacher, O. .............................. 66, 70
Andersson, Christer M. ................... 157
Annema, A. J. ................................. 240
Aouini, Sadok ................................. 236
Appel, C. ........................................... 86
Asheghi, Mehdi..................... 41, 53, 57
Aufinger, Klaus............................... 197

B
Bain, James ..................................... 225
Bao, Mingquan ............................... 244
Barner, Jeff ..................................... 136
Beach, M......................................... 213
Beam, Edward ................................ 165
Belfiore, Guido ............................... 261
Ben Bakir, B. .................................. 118
Benedikt, J. ..................................... 213
Ben-Hamida, Naim ......................... 236
Bensmida, S. ................................... 213
Berdaguer, P. .................................. 128
Blache, F. ........................................ 128
Blanck, H. ......................................... 13
Bloch, E. ......................................... 124
Boeck, Josef .................................... 197
Bordel, D. ....................................... 118
Borngrber, Johannes........................ 98
Borodulin, Pavel ..................... 225, 228
Bowen, R. ....................................... 181
Bowers, J. E. ................................... 124
Brast, T. ............................................ 90
Brianceau, P. ................................... 118
Brown, D. F. ................................... 181
Burnham, S. .................................... 181

C
Cameron, N. ...................................... 90
Carpenter, Sona............................... 244
Carron, V. ....................................... 118
Carta, Corrado ................................ 261
Casto, Matthew ............................... 177
Chan, Wesley .................................. 106
Chang, Tsu-Hsi ................................... 9
Chao, Greg ...................................... 106
Chen, P. S. ...................................... 181
Chen, Shuoqi .................................. 165
Cho, Wai Keung ............................. 232
Cho, Jungwan ................................... 53
Choi, Yeung Bun ............................ 132
Chong, Wing Cheung ..................... 232

G
Chou, Tso-Min ................................ 165
Chow, D. H. ............................ 181, 217
Clement, Ryan M. ........................... 265
Codecasa, L. .................................... 193
Coldren, L. A. ................................. 124
Collins, Gayle Fran ......................... 136
Convert, Emmanuelle R. ................. 265
Corrion, A. L. .................................. 181
Cramer, Harlan ................................ 228
Cripe, David .................................... 145

D
Dadello, Anna ................................. 265
d'Alessandro, V. ...................... 193, 197
Dama, B. ........................................... 86
Datta, Suman ................................... 110
Debski, Wojciech .............................. 98
Descos, A. ....................................... 118
Dohrman, Carl L. ................................ 9
Duprez, H. ....................................... 118
Dupuy, J.-Y. .................................... 128
Dusseault, Tom ................................. 41
Duval, B. ......................................... 128

E
Edwards, Jennifer .............................. 94
El-Gabaly, Ahmed .......................... 173
El-Hinnawy, Nabil .......................... 225
Elkhouly, Mohamed .......................... 98
Ellinger, Frank ................................ 261
Ereifej, H. .......................................... 90

F
Fager, Christian ............................... 157
Fakharzadeh, Mohammad ............... 173
Farnsworth, Craig............................ 173
Fay, Patrick ..................................... 165
Feng, Milton.............................. 29, 256
Fisher, Jeremy ................................. 136
Floriot, D. .......................................... 13
Francis, Daniel .................................. 53
Frei, Jeff .......................................... 149
Freitag, Ron..................................... 228
Fritsche, David ................................ 261
Fujimori, Ichiro ................................... 1
Fujimura, Yasushi ............................. 82
Fulbert, L. ....................................... 118
Fung, H. .......................................... 181
Fung, A. .......................................... 181

269

Gao, Xiang ...................................... 165

Gasmi, Ahmed ................................. 221
Gering, Joseph ................................. 161
Gibbins, Robert ............................... 236
Gires, Julie......................................... 41
Glibbery, Ronald ............................. 173
Godin, J. .......................................... 128
Golcuk, Faith ..................................... 94
Goodson, Kenneth E.............. 41, 53, 57
Gothoskar, P. ..................................... 86
Grabar, R. M............................ 181, 217
Graham, Samual ................................ 45
Grahn, J. ............................................ 21
Green, Daniel S. .................................. 9
Griffith, Zach ....................... 62, 74, 124
Grzyb, J. .......................................... 169
Gupta, Shalini .................................. 228
Gurbuz, Ozan .................................... 94
Gutierrez-Aitken, Augusto .............. 106

H
Halder, Subrata ................................ 161
Hall, Leonard ................................... 265
Halonen, J.......................................... 21
Hartman, Jeff ................................... 228
Hartmann, Joel .................................... 5
Harvey, James T. ............................. 265
He, Zhongxia ................................... 244
Heinemann, B. ................................. 169
Heller, Eric ........................................ 45
Hennig, Kelly .................................. 106
Henry, H. George ............................ 228
Higham, Eric ................................... 140
Hou, Bin ............................................ 25
Houshmand, Farzad ........................... 57
Howell, Robert S. .................... 225, 228
Hbers, Heinz-Wilhelm..................... 98
Hurm, V............................................. 70

I
Ikagawa, Tomoko .............................. 82
Inac, Ozgur ........................................ 94
Itabashi, Naoki .................................. 82
Iverson, Eric W. ................................ 29

J
Jafarlou, Saman ............................... 173
Johansson, L. ................................... 124
Jones, Evan B. ................................. 225
Jones, Jeff ........................................ 149
Jorge, F. ........................................... 128
Juntunen, Eric .................................. 173

Table of Contents

K
Kagiwada, Reynold......................... 106
Kallfass, Ingmar ................................ 66
Kamada, Yoichi .............................. 205
Kanar, Tumay ................................... 94
Kane, Avinash S. ................................ 9
Kaneshiro, Eric ............................... 106
Kao, Ming-Yih................................ 201
Karandikar, Yogesh ........................ 102
Kendig, Dustin .................................. 45
Ketterson, Andrew .......................... 165
Khalil, Waleed ................................ 177
Kim, Bumjin ................................... 209
Kim, Moon Seok............................. 110
Kimball, Don .................................. 136
King, Matthew ........................ 225, 228
Koch, Stefan ..................................... 66
Konczykowska, A. .......................... 128
Kong, Kris ...................................... 201
Kono, Naoya ..................................... 82
Krause, J. ........................................ 185
Krvavac, Enver ............................... 149
Kuball, M. ......................................... 37
Kurdoghlian, A. ...................... 181, 217
Kuri, M. ............................................ 70
Kurowski, Christopher .................... 236

L
Landt, Don ...................................... 145
Lau, Kei May .................................. 232
Leblanc, Rmy ................................ 221
Lee, Michael J. ................................ 225
Lees, J. ............................................ 213
Leuther, A. .................................. 66, 70
Li, James C. .................................... 177
Li, Xueqing ..................................... 110
Li, Yihu............................................. 33
Lin, Nancy ...................................... 106
Lindsay, John .................................. 236
Ling, Goh Wang ............................... 33
Liu, Zhao Jun .................................. 232
Liu, Huichu ..................................... 110
Lopez, Ken........................................ 41
Lu, M. ............................................. 124
Lynch, Brad .................................... 173

Masuda, Satoshi .............................. 205

McCarthy, Andrew.......................... 236
McCue, Jamin J. .............................. 177
McCulloch, MacCrae G. ................. 265
McGeehan, J. .................................. 213
McGuire, C. ............................ 181, 217
McMacken, John ............................. 161
Menezo, S. ...................................... 118
Merkle, Thomas ................................ 66
Mertens, Samuel D. ......................... 153
Micovic, M.............................. 181, 217
Milner, Leigh E. .............................. 265
Monier, Cedric ................................ 106
Moron, Jol ..................................... 221
Morris, K. ........................................ 213
Moser, B.......................................... 193
Moyer, H. ................................ 181, 217

N
Nakabayashi, Takashi ....................... 82
Nakamura, Eric ............................... 106
Narayanan, Vijaykrishnan ............... 110
Nardmann, T. .................................. 185
Nauta, B. ......................................... 240
Nayak, Sabyasachi .......................... 201
Nechay, Bettina ............................... 228
Neumaier, Philipp ............................. 98
Newman, Eric ................................... 25
Ng, Kwan Ting................................ 132
Niida, Yoshitaka.............................. 205
Nilsson, B.......................................... 21
Nilsson, P. . .................................... 21
Nodjiadjim, V. ................................ 128
Noori, Basim ................................... 149

O
Ogboi, F. L. ..................................... 213
Ogita, Shoichi ................................... 82
Ohki, Toshihiro ............................... 205
Okamoto, Naoya ............................. 205
O'Keefe, M. F.................................... 90
Oki, Aaron....................................... 106
Oyama, Bert .................................... 106
Ozaki, Shiro .................................... 205
Ozalas, Matthew T. ......................... 189

Magnani, A. .................................... 193

Mah, Harvey ................................... 236
Mahon, Simon J. ............................. 265
Maize, Kerry ..................................... 45
Makiyama, Kozo............................. 205
Malz, S. ........................................... 169
Maneux, Cristell ............................. 197
Margomenos, A. ..................... 181, 217
Mason Jr., John S. ........................... 225
Massler, H. ........................................ 70
Massler, Hermann ............................. 66

Palko, James ...................................... 41

Paramesh, Jeyanandh ...................... 225
Park, H. C........................................ 124
Parke, Justin .................................... 228
Parker, Anthony E. .......................... 265
Parker, Michael ............................... 265
Pavlidis, Georges .............................. 45
Pfeiffer, U. R. .................................. 169
Piels, M. .......................................... 124
Pierson, Richard .......................... 62, 74
Pilla, Manyam ................................. 165

270

Pomeroy, J. W. .................................. 37
Poon, Alan ....................................... 173
Poust, Benjamin .............................. 106
Prasad, Ankur .................................. 157

R
Radulescu, Fabian ........................... 136
Ralston, Parrish ............................... 228
Rebeiz, Gabriel M. ............................ 94
Regan, D. C. ............................ 181, 217
Ren, Jun ........................................... 165
Renaldo, Karen ................................ 228
Reyland, John .................................. 145
Riessle, M. ......................................... 70
Riet, M............................................. 128
Rinaldi, Niccol .............................. 197
Rinaldi, N. ....................................... 193
Roberg, Michael .............................. 209
Rodilla, H. ......................................... 21
Rodwell, M. J. W............................. 124
Rowell, Petra ............................... 62, 74

S
Sanchez, L. ...................................... 118
Santiago, Juan G. ............................... 41
Santos Ibeas, Noelia ........................ 221
Sarmah, N. ....................................... 169
Sasso, Grazia ................................... 197
Sato, Masaru .................................... 205
Sato, Ken ......................................... 106
Saunier, Paul.............................. 17, 165
Schlechtweg, M. .......................... 66, 70
Schleeh, J........................................... 21
Schlesinger, T. E. ............................ 225
Schmalz, Klaus .................................. 98
Schmitz, A. ...................................... 181
Schroter, M. ..................................... 185
Scott, Dennis ................................... 106
Seki, Morihiro ................................... 82
Shakouri, Ali ..................................... 45
Shastri, K. .......................................... 86
Sheppard, Scott................................ 136
Shin, Woorim .................................... 94
Shinohara, K. ........................... 181, 217
Shoji, Hajime ..................................... 82
Shopov, Stefan ........................ 248, 252
Sivananthan, A. ............................... 124
Smorchkova, Ioulia ......................... 106
Snook, Megan.................................. 228
Song, Bo .......................................... 165
Splettster, J. ................................... 13
Starski, J. P. ....................................... 21
Statnikov, K..................................... 169
Stewart, Eric J. ................................ 228
Stulz, H.-P. ........................................ 70
Sunder, S. .......................................... 86
Swaminathan, Karthik ..................... 110

Table of Contents

Tabibiazar, Arash ............................ 173

Tai, H. Y. ........................................ 181
Tanaka, Keiji .................................... 82
Tasker, P. J...................................... 213
Tatsumi, Taizo .................................. 82
Tawfik, Hatem ................................ 173
Tazlauanu, Mihai ............................ 173
Temkine, Grigori ............................ 173
Tessmann, A. .............................. 66, 70
Testa, Paolo Valerio........................ 261
Thai, Khanh .................................... 106
Thorsell, Mattias ............................. 157
To, Yat-Loong ................................ 173
Tomkins, Alex ................................ 173
Tserng, Hua-Quen........................... 165

Wadefalk, N. ..................................... 21
Wagner, Brian P. ............................. 225
Wagner, Sandrine .............................. 66
Wagner, S.......................................... 70
Walker, R. G. .................................... 90
Walker, Anders ............................... 145
Wang, Ruoyu .................................... 98
Wang, Chu Hong............................. 232
Wang, Keh Chung ........................... 132
Watanabe, Keiji............................... 205
Wathuthanthri, Ishan ....................... 228
Watson, Paul ................................... 177
Webster, M. ....................................... 86
Weng, Junxian................................. 236
Wetzel, M. D. .......................... 181, 217
Winoto, Ardy .................................. 256
Withagen, Johan C. J. G. ................. 240
Won, Yoonjin ........................ 41, 53, 57
Wong, Ted....................................... 236
Worley, Rick ................................... 136
Wu, Barry........................................ 256
Wu, Benny ...................................... 265

Yamaji, Kazuhiro .............................. 82

Yamazaki, Hiroshi ............................. 78
Yan, Yu ........................................... 102
Yates, Luke........................................ 45
Ye, Peide D. .................................... 114
Yhland, Klas .................................... 157
Young, Robert M............................. 225

U
Uesaka, Katsumi ............................... 82
Uteaga, M. .......................... 62, 74, 124

V
van Vliet, F. E. ................................ 240
Vassilev, Vessen ............................. 102
Voinigescu, Sorin P. ............... 248, 252

X
Xie, Chenggang............................... 145
Xing, Huili Grace ............................ 165
Xiong, Yong-Zhong .......................... 33
Xu, Huiming ................................... 256

271

Z
Zampardi, P. J.................................. 193
Zeng, Xiang ..................................... 106
Zhang, Shuyun .................................. 25
Zhao, Yibing...................................... 25
Zihir, Samet ....................................... 94
Zimmer, Thomas ............................. 197
Zink, M.............................................. 70
Zirath, H. ........................................... 21
Zirath, Herbert ......................... 244, 102