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Layout Design8

This document discusses layout design and diagrams used in integrated circuit design. It describes different types of diagrams including stick diagrams, symbolic diagrams, and layout diagrams. Stick diagrams convey topology and allow for compacting during the layout process. Symbolic diagrams abstract the layout to reduce complexity. Layout diagrams stress ready translation to masks and must follow design rules. The document also discusses design rules including lambda-based rules, as well as design checks including DRC to check for violations and LVS to ensure the layout matches the schematic.

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Sandeep Boyina
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78 views

Layout Design8

This document discusses layout design and diagrams used in integrated circuit design. It describes different types of diagrams including stick diagrams, symbolic diagrams, and layout diagrams. Stick diagrams convey topology and allow for compacting during the layout process. Symbolic diagrams abstract the layout to reduce complexity. Layout diagrams stress ready translation to masks and must follow design rules. The document also discusses design rules including lambda-based rules, as well as design checks including DRC to check for violations and LVS to ensure the layout matches the schematic.

Uploaded by

Sandeep Boyina
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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LAYOUT DESIGN

DIAGRAMS
Few diagrams which can convey both layer
information and topology. They are,

DIAGRAMS
STICK

SYMBOLIC

LAYOUT

MOS LAYERS

N-diffusion
p-diffusion
polysilicon
metal
metal contacts: all the four above layers are
deliberately joined together where the contacts are
formed.
some cases the second metal and second polysilicon
layers are used.

How the transistor is formed?


When thinox and polysilicon cross each othr the transistor is formed.
Thinox region includes n-diffusion , p-diffusion & transistor channel.

P
o
l
y
s
Diffusion
il
i
c
o
n

Transistor
formed

METAL CONTACTS
After the layouts are designed need for interconnecting
appropriate layer is required.where we need metal
contacts by etching the oxide.
Types of metal contacts are,
9
Butting contacts
9
Buried contacts

SYMBOL

Butting contacts
It is used to make when connecting diffusion to
polysilicon
Disadvantage:
* Suffers with reliablity problem
*It requires metal cap
So, not widely used

Buried contacts
It is used to connect poly to metal contacts then metal to
diffusion.
It is widely used
It is more reliable
It does not require metal cap

STICK DIAGRAM
It conveys information that reflects the actual layout topology of a
circuit to the designer. It contains sufficient information to layout the
circuit

STICK CODING
N-type enhancement
N-diffusion

Polysilicon
G

L:W

L:W
S

D
G

Metal 1
N-type depletion

contact

Implant
S

Buried contact

L:W

L:W
G

D
G

STICK CODING
P-diffusion
S

Demarcation line
Vdd or Vss
contact
D

L:W
G

P-type
transistor

L:W
G

p-type

D-line
D

L:W

N-type
npn

Vias and Contacts


2
4

Via
1

1
5

Metal to
1
Active Contact

Metal to
Poly Contact
3

2
2

VDD

In

Dimensionless layout entities


Out Only topology is important
Final layout generated by
compaction program

GND
Stick diagram of inverter

Stick Diagram for inverter


V

DD

Out

In
GND

Stick Diagram for NAND2


V

DD

Out

A
GND

SYMBOLIC DIAGRAM
It is the attempt to abstract the layout in some
manner in order to to reduce the complexity of the
task.
S

G
N-type enh

G
P-type enh

D
G
N-type dep

npn

LAYOUT DIAGRAM
It is the diagram which can stressing the ready
translation into mask Layout form.
This mask layout produced during design will be
compatible with fabrication process.
A set of design rules are setout for layouts.
The rules will produce layouts which will work in practice.

More specifically Layout rules for,


to prevent short circuiting
to prevent opening
to prevent contacts from slipping outside the area
to be contacted

GOAL is,
Simple
constant in time
applicable to many process
standardized among many institution

Layers in 0.25 mm CMOS process

Intra-Layer Design Rules


Same Potential
0
or
6

Well

Different Potential
2

9
Polysilicon
2

10
3
Contact
or Via
Hole

3
2
Select

Metal1

Active
2
2

DESIGN RULES
Due to the complexity of modern VLSI
circuitry designing for testability is mandatory
Designers want design rules to improve the
performance and chip area.
Design rules are often dependent upon both
process equipment and process design.

PURPOSE OF DESIGN RULES


To prevent unworkable constructs
to prevent the unreliable constructs
to prevent hard to implement constructs
i.e; to allow an engineer to layout VLSI circuit
with reasonable assurance that it will work.

Design rules are,


Meta design rules
Mead- conway design rule
Meta design rule:
very first design rules
Disadvantage: not much helpful unless
one knows the process intimately
Mead-conway rule:
characterize the process with a single
scalable parameter called Lambda

What is lamdba?
It is the parameter defined as the half width
of a max-width line (or) as a multiple of
standard deviation of process.
Then what is lambda based rules?
It is process dependent it is defined as the
maximum distance by which a geometrical
feature on any one layer can stay from
another feature due to overetching,
misalignment distortion etc.

Advantage of Mead-conway lambda based


rules:
allows future scaling and makes the layout
portable.
It is suitable for 3 microns to 0.6 microns.
Unit dimension: Minimum line width
scalable design rules: lambda parameter
absolute dimensions (micron rules)

DESIGN CHECKS
Design performs two major checks before
fabrication
1) Design rule check(DRC)
2) Layout Vs schematic(LVS)

Design rule check (DRC)


It is to ensure that nothing has wrong
in the process of assembling the logic
cells and routing.
DRC at two levels,
@ check of the detailed router
@ check of correctness of the library
cells

Check of the detailed router


This is the first level of check in DRC
Principally it is a check of the detailed router
It checks for shorts, violation,design rule
problem between logic cells.

Check of correctness of the


library cells
This is the second level of check in
DRC
This check is at the transistor level
Principally it is a check of correctness
of the library cells
Usually the ASIC vendor performs the
check with their own software

Layout Vs schematic (LVS)


What do you mean by LVS?
It is the check to ensure that what is about to
be committed to silicon is what is really
wanted.
How do you do?
An electrical schematic is extracted from the
layout and compare to the netlist.
So,what happens?
So,it closes a loop between the logical and
physical design process and ensure that both
are same.

Problems of LVS
Transistor level netlist for a large
ASIC forms an enormous graph
Creating a true reference is diffcult

THAN Q

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