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Introduction To VHDL-FPGA

This document discusses VHDL synthesis for implementing digital designs into FPGAs. It covers VHDL as a hardware description language, the VHDL synthesis subset, module structure, simulation and verification with test benches, the synthesis process, and FPGA design flows and boards.

Uploaded by

Cristian Sisterna
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147 views20 pages

Introduction To VHDL-FPGA

This document discusses VHDL synthesis for implementing digital designs into FPGAs. It covers VHDL as a hardware description language, the VHDL synthesis subset, module structure, simulation and verification with test benches, the synthesis process, and FPGA design flows and boards.

Uploaded by

Cristian Sisterna
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VHDL Synthesis for Implementing

Digital Designs into FPGAs

MSc Cristian Sisterna


UNSJ

Introduction

Very High Speed


ICs

Hardware

Description
Language
2
DSDA - 2016

V
H
D
L
C. Sisterna

Hardware Description Language


HDL
(VHDL/Verilog)

FPGA

Xilinx

Altera

ASIC

Lattice

Actel

3
DSDA - 2016

C. Sisterna

Hardware Description Language


High level of abstraction
if(reset=1) then
count <= 0;
elsif(rising_edge(clk)) then
count <= count+1;
end if;

Easy to debug
Parameterized designs

Re-uso
IP Cores (free) available
4
DSDA - 2016

C. Sisterna

What is not VHDL


Verilog o VHDL IS NOT A programming language; IT IS A

HARDWARE DESCRIPTION LENGUAGE

Verilog o VHDL is not (yet) a highly abstract language:


y(n) = 0.75y(n-1) + 0.3x(n) ;
(Simulink/FPGA design flow)

5
DSDA - 2016

C. Sisterna

HDL Synthesis Sub-Set


Used to write code
to simulate the
behavior of a design

VHDL
VHDL
Synthesizable
Used to implement
the design into
hardware (for
instance in FPGA)

6
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C. Sisterna

VHDL Description Examples


x

y
sel

0
1

if(sel=1) then
z <= y;
else
z <= x;
end if;

z <= y when sel=1 else x;


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DSDA - 2016

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VHDL Description Ejemplos


d

clk

if(clk
)then
q <= d;
else
q <= q;
end if;

if(clk
)then
q <= d;
end if;
if(rising_edge(clk))then
q <= d;
end if;

8
DSDA - 2016

C. Sisterna

VHDL Module Structure


ff.vhd

entity

I/O
d

clk

q
architecture

Functionality
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DSDA - 2016

C. Sisterna

VHDL Module Structure


ff.vhd
entity f
ff is
port(
d,clk : in std_logic;
q
: out std_logic);
end ff;

d
clk

architecture test of ff is
begin
process(clk)
begin
if(rising_edge(clk)) then
q <= d;
end if;
end test;

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C. Sisterna

VHDL Code Is it really Works? ?

Test Bench

Stimulus
Signals

Tested
Signals

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C. Sisterna

VHDL Simulation / Verification

12
DSDA - 2016

C. Sisterna

VHDL - Synthesis
VHDL
Code

with tmp select


j <= w when 1000,
x when 0100,
y when 0010,
z when 0001,
'0when others;

Design
Constraints
NET CLOCK PERIOD = 50 ns;

NET LOAD LOC = P

Design
Attributes

Synthesis
Tool

FPGA list of
Components and
Connections

attribute syn_encoding of my_fsm:


type is one-hot;

FPGA Library
of Components
13

Cyclone
Spartan
DSDA - 2016

C. Sisterna

VHDL-FPGA Design Flow

14
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C. Sisterna

Design Implemented in the FPGA

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FPGA Kit DE1-SoC

http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=836&PartNo=1
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C. Sisterna

FPGA Kit DE2-115

http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=502
17

DSDA - 2016

C. Sisterna

FPGA Kit DE0-Nano-SoC Kit

http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=941

18

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C. Sisterna

FPGA Kit DE0-Nano Kit

http://www.terasic.com.tw/cgi-bin/page/archive.pl?CategoryNo=139&No=593
19

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C. Sisterna

FPGA Xilinx V5

20

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C. Sisterna

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