UNIT -1 SYSTEM DESIGN USING PLDs

Programmable Logic Devices

A Programmable Logic Device is an integrated circuit with internal logic
gates and interconnects. These gates can be connected to obtain the
required logic configuration.
The term programmable means changing either hardware or software
configuration of an internal logic and interconnects.
The configuration of the internal logic is done by the user.
PROM, EPROM, PAL, GAL etc. are examples of Programmable Logic
Devices.
Introduction
Programmable Logic Device can be programmed in two ways:
1. Mask programming (in some few cases)
2. Field programming (typical)
1.) Mask programming: programming of device is done in the mask level.
+ good timing performance due to internal connections hardwired during
manufacture
+ cheap at high volume production
- programmed by manufacturer
- development cycle = weeks or months
- not re-programmable
Programming Technologies
Field programming: Programming of device is done by the user. The
programming technologies are of two
types
Permanent type (Non-volatile):
Fuse (normal on) - CLOSE (intact) OPEN (blown)
Anti-fuse (normal off) - just the opposite of a FUSE
EPROM
EEPROM
Nonpermanent type (Volatile):
driving n-MOS pass transistor by SRAM
-When power of device is switched off then the content of SRAM is lost.
1PLA (Programmable Logic Array):
array of AND and OR gates are programmable

 product term sharing: every product term of the AND array can be
connected to the input of any OR gate
unidirectional input/output pins
Basic PLD Concepts
Memory based: Device with fixed AND array and programmable OR array
output of OR gate has fixed connection with input of AND gates
PROM, EPROM and EEPROM are memory based PLD device
3.) PAL/GAL(Programmable Array Logic/ Gate Array Logic):
AND array is programmable and OR array has fix connection with outputs
of AND gates. PAL/GAL devices may have bi-directional I/O pins.
There are three different types of PAL/GAL devices
combinational PAL devices are used for the implementation of logic
function
sequential PAL devices are used for the implementation of sequential
logic (finite state machines)
arithmetic PAL devices sum of product terms may be combined by XOR
gates at the input of the macrocell D flip-flop
Basic PLD Concepts
Additional features of PAL/GAL devices
PAL:
- EPROM - based programming Technology
GAL:
- has array of programmable AND gates and OLMC (Output
Logic Macro Cell)
- EEPROM - based programming Technology
- programmable output polarity
- device can be configured as dedicated input and output mode
A programmable logic array (PLA) is a kind of programmable logic device used
to implement combinational logic circuits. The PLA has a set of programmable
AND gate planes, which link to a set of programmable OR gate planes, which can
then be conditionally complemented to produce an output. This layout allows for a
large number of logic functions to be synthesized in the sum of products (and
sometimes product of sums) canonical forms.

PLA's differ from Programmable Array Logic devices (PALs and GALs) in that
both the AND and OR gate planes are programmable.

One application of a PLA is to implement the control over a datapath. It defines

various states in an instruction set, and produces the next state (by conditional
branching). [e.g. if the machine is in state 2, and will go to state 4 if the instruction
contains an immediate field; then the PLA should define the actions of the control
in state 2, will set the next state to be 4 if the instruction contains an immediate
field, and will define the actions of the control in state 4]. Programmable logic
arrays should correspond to a state diagram for the system.
Other commonly used programmable logic devices are PAL, CPLD and FPGA.
Note that the use of the word "programmable" does not indicate that all PLAs are
field-programmable; in fact many are mask-programmed during manufacture in the
same manner as a mask ROM. This is particularly true of PLAs that are embedded
in more complex and numerous integrated circuits such as microprocessors. PLAs
that can be programmed after manufacture are called FPGA (Field-programmable
gate array), or less frequently FPLA (Field-programmable logic array)..

PROGRAMMABLE ARRAY LOGIC

 A Programmable Array Logic (PAL) is a relatively small FPD that has a

programmable AND-plane followed by a fixed OR-plane.
Many applications do not require that both the AND as well as OR arrays be
programmable.
Programmable links are slower than permanent links owing to the
considerable resistance shown by the fusible material.
Hence another option for the design engineers The AND array can be kept
programmable as in PLA but the
OR array has got no programmability!

Tri-state outputs
gives programmable bi-directional pins
saves the pin-count
Registered outputs
Enables the use of the PAL in finite state
machines
Increases the versatility of the device

PAL

PAL ICs architecture:

Programming is typically performed by design developersat their site, with

no IC masking steps
Largest devices are now 10M gates (10*10^6)
Programmable Array Logic Devices (PALs)
PAL16R8
PAL16R6
PAL16R4

When a single line represents a number of connections it is called a bus.

Output of OR gate is connected with TRISTATE driver and output of AND
gate is used as driver enable for tristate buffer
PAL Ics are available with different individual logic circuit.
Features:
When enable is high,output signal is available at output
When enable is low,output signal is high impedance state
The enable output of driver isprogrammable
AL16R4 - 4 registered outputs
4 outputs not registered
8 dedicated inputs
8 feedback inputsOE,
CLK, Vcc, GND
Typically 8 product terms per OR gate

The top two and bottom two circuits are simple combinational logic circuits
It consists of 4 D flipflops
Each flipflop is loaded on the low to high transition of clock input.
A power up reset function has been incorporated in PAL16RX series Ics to
reset all internal registers to active low after specified time duration.
Designing Circuits with PAL devices is also anautomated process (most of
the cases)
One can use VHDL, Verilog, ABEL(advanced BooleanExpression
Language), PALASM or similar language todo this
If you dont like using CAD tools you have the option
of representing your design as a programming table
But before using a PAL/ and PLD its better to befamiliar with the internal
details of the device so thatone can optimally use a PAL .

Combinational PAL
device, AMD PAL16L8

PAL 16R4

PAL22V10
PAL22V10 is a CMOS flash erasable programmable array logic device.
It is implemented with the sum of product logic architecture and
programmable macro cell.
The programmable macro cell provides capability of defining architecture of
each output.
It has 10 logic section and each logic section has 8 to 16 AND gates.
The top AND gate of each section is independent programmable enable.
It has 12 inputs and 10 programmable inputs/outputs.

Function specification:

Macrocell:
A great amount of architectural flexibility is provided by the userconfigurable macro cell output options.
The macro cell consists of a D-type flip-flop and two select multiplexers.
The D-type flip-flop operates like a standard TTL D-type flip-flop.
The input data is latched on the low-to-high transition of the clock input.
The Q and Q outputs are made available to the output select multiplexer.

Macrocell:

Complex PLD (CPLD)

is combination of multiple PAL or GAL type devices on a single chip
CPLD architectures consists of
- Macrocells
- configurable flip-flop (D, T, JK or SR)
- Output enable/clock select
- Feedback select
CPLD has predictable time delay because of hierarchical inter-connection
easy to route, very fast turnaround
performance independent of netlist
devices is erasable and programmable with non-volatile EPROM or
EEPROM configuration
wide designer acceptance
has more logic density than any classical PLDs device
relatively mature technology, but some innovation still ongoing

Complex PLD device

Altera EP1800

Erasable CPLD
EP1800 is erasable PLD device and has 48 macrocells, 16 dedicated
input pins and 48 I/O pins.
device is divided into four quadrants, each contains 12 macrocells and
has local bus with 24 lines and a local clock
out of 12 microcells, 8 are local macrocells and 4 are global

Macrocells

Local macrocell

Global macrocell

Sequential circuit design considerations

An important topic to consider when designing sequential circuits is the
method to be used. There are several possible methods, including the
excitation table method and design by state equations. Another important
considerations is which type of flip-flop to use in the design: SR, JK, D, or T.
The JK flip-flop is the most versatile and typically yields the simplest circuit
to implement.
If a sequential circuit design is to be implemented using PLDs where the
number of gates required and the type of flip-flop to be used is not of great
concern, it may be advantageous to simply use the simplest design method
rather than the most efficient. The simplest design method is in many cases to
use state equations with D flip-flops. The general form of the state equation for
a D flip-flop is:
Q(t
+1)=D
So the input for each D flip-flop is simply determined by finding an expression for
the next state for that flip-flop.
Example: Design a 4-bit counter using D flip-flops.
A 4-bit counter, also called a modulo-16 counter, counts in the sequence 0, 1,
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 and repeats. The state diagram is
shown in Figure 1 below.

State diagram

Truth table

D(t + 1) = DC + DB + DA + DCBAC(t + 1) = CB + CA + CBAB(t + 1) = BA +

BAA(t + 1) = A
Figure 4: State equations for the 4-bit counter

Combinational circuits using PLDs

Pro(memory cells) along each column are wire-ORed together. In- grammable logic
devices are organized into an AND array tuitively, the programmable elements can
also be placed in and an OR array, with multiple inputs and multiple outputs.the
decoder so they are wired-ANDed together along each col- The AND array maps
the inputs into particular product
umn. These and other variations lead to different building terms; the OR array takes
these product terms together to blocks. Programmable logic array (PLA) and
programmable produce the final expression.

ASM Chart
The Algorithmic State Machine (ASM) method is a method for designing finite
state machines. It is used to represent diagrams of digital integrated circuits. The
ASM diagram is like a state diagram but less formal and thus easier to understand.
An ASM chart is a method of describing the sequential operations of a digital
system.
An ASM chart consists of an interconnection of four types of basic elements: state
names, states, condition checks and conditional outputs. An ASM state, represented
as a rectangle, corresponds to one state of a regular state diagram or finite state
machine. The Moore type outputs are listed inside the box.

State Name
State name: The name of the state is indicated inside the circle and the circle is
placed in the top left corner or the name is placed without the circle.

State box
State box : The output of the state is indicated inside the rectangle box

Decision box
Decision box: A diamond indicates that the stated condition expression is to be
tested and the exit path is to be chosen accordingly. The condition expression
contains one or more inputs to the FSM (Finite State Machine). An ASM condition
check, indicated by a diamond with one input and two outputs (for true and false),
is used to conditionally transfer between two states or between a state and a
conditional output. The decision box contains the stated condition expression to be
tested, the expression contains one or more inputs of the FSM.

Conditional output box

Conditional output box: An oval denotes the output signals that are of Mealy type.
These outputs depend not only on the state but also the inputs to the FSM.
Datapath
Once the desired operation of a circuit has been described using RTL operations,
the datapath components may be derived. Every unique variable that is assigned a
value in the RTL program can be implemented as a register. Depending on the
functional operation performed when assigning a value to a variable, the register
for that variable may be implemented as a straightforward register, a shift register, a
counter, or a register preceded by a combinational logic block. The combinational
logic block associated with a register may implement an adder, subtracter,
multiplexer, or some other type of combinational logic function.

Eg of ASM chart

ASM Architecture:

Controller & Data Processor

A digital system consists of two components
A control algorithm (controller) and
An architecture (data processor)
Separation of the controller operations from the data processing operations
Control operations give commands that direct the data processing
operations to accomplish the desired tasks.
Data processing operations manupulates the data according to
requirements.
A mechanical analogy: Automobile.
Car (data processor): transports people from one location to another.
Driver (controller): gives instructions to car to achieve objective.