VL9252

LOW POWER VLSI DESIGN

Prepared & Presented By
Dr. V. Vaithianathan
Associate Professor, ECE Dept

Course Details
Course Name: Low Power VLSI Design
Course Instructor: Dr. V. Vaithianathan
Associate Professor, ECE Department
Mail:[email protected]
Class: II Sem M.E. Applied Electronics
Grading
Three Continuous Assessment Tests for 20%
End Semester Exam for 80%

Course Contents
Unit I: POWER DISSIPATION IN
CMOS

Hierarchy of Limits of Power

Sources of Power Consumption

Physics of Power Dissipation in CMOS
FET devices

Basic Principle of Low Power Design

Course Contents
Unit II: POWER OPTIMIZATION

Logical Level Power Optimization

Circuit Level Low Power Design

Circuit Techniques for Reducing Power
Consumption in Adders and Multipliers
Design

Course Contents
Unit III: DESIGN OF LOW
POWER CMOS CIRCUITS

Logical Level Power Optimization

Circuit Level Low Power Design

Circuit Techniques for Reducing Power
Consumption in Adders and Multipliers
Design

Course Contents
Unit IV: POWER ESTIMATION

Power Estimation Techniques

Logic Level Power Estimation

Simulation Power Analysis

Probabilistic Power Analysis

Course Contents
Unit V: SYNTHESIS AND
SOFTWARE DESIGN FOR LOW
POWER

Synthesis for Low Power

Behavioral Level Transforms

Software Design for Low Power

References
K.Roy and S.C. Prasad, LOW POWER
CMOS VLSI Circuit Design, Wiley,2000
Chapter 2: Physics of Power
Dissipation in CMOS FET Devices

UNIT I

Chapter 3: Power Estimation

Unit IV

Chapter 4: Synthesis for Low

Power, Behavioral Level Transforms

Unit V

Chapter 8: Software Design for Low Unit V

Power

References
Anantha P. Chandrakasan & Robert W.
Brodersen, Low Power Digital CMOS
Design, KAP, 1995
Chapter 1: Hierarchy of Limits of
UNIT I
Power
Chapter 2: Sources of Power
Consumption

Unit I

References
Gary Yeap, Practical Low Power Digital
VLSI Design, Kluwer,1998
Chapter 1: Basic Principles of Low UNIT I
Power Design
Unit IV
Chapter 2: Simulation Power
Analysis
Chapter 3: Probabilistic Power
Unit IV
Analysis
Chapter 6: Special Techniques
Chapter 8: Advanced Techniques

Unit III
Unit III

References
Dimitrios Soudris, Chirstian Pignet,
Costas Goutis, Designing CMOS Circuits
for Low Power, Kluwer,2002
Chapter 3: Logic Level Power
UNIT II
Optimization
Chapter 4: Circuit Level Low Power Unit II
Design
Chapter 5: Circuit Techniques for
Unit II
Reducing Power Consumption in
Adders and Multipliers

References
Dimitrios Soudris, Chirstian Pignet,
Costas Goutis, Designing CMOS Circuits
for Low Power, Kluwer,2002
Chapter 6: Computer Arithmetic
Unit III
Techniques for Low Power Systems
Chapter 7: Reducing Power
Unit III
Consumption in Memories
Chapter 8: Low Power Clock,
Unit III
Interconnect and Layout Design
Chapter 9: Logic Level Power Estimation Unit IV

Additional References
J.B. Kuo and J.H Lou, Low voltage CMOS
VLSI Circuits, Wiley 1999.
Abdellatif Bellaouar, Mohamed.I. Elmasry,
Low Power Digital VLSI Design,Kluwer,
1995.
James B. Kuo, Shin chia Lin, Low Voltage
SOI CMOS VLSI Devices and Circuits.
John Wiley and sons, inc 2001
N. Nicolici and B. M. Al-Hashimi, PowerConstrained Testing of VLSI Circuits,
Boston: Springer, 2003.
V. G. Oklobdzija, V. M. Stojanovic, D. M.
Markovic and N. Nedovic, Digital System
Clocking: High Performance and LowPower Aspects, Wiley-IEEE, 2005.

Additional References
C. Piguet, Low-Power Electronics Design,
Boca Raton: Florida: CRC Press, 2005.
J. M. Rabaey and M. Pedram, Low Power
Design Methodologies, Boston: Springer,
1996.
S. Roudy, P. K. Wright and J. M. Rabaey,
Energy Scavenging for Wireless Sensor
Networks, Boston: Springer, 2003.
E. Snchez-Sinencio and A. G. Andreaou, LowVoltage/Low-Power Integrated Circuits
and Systems Low-Voltage Mixed-Signal
Circuits, New York: IEEE Press, 1999.
W. A. Serdijn, Low-Voltage Low-Power
Analog Integrated Circuits, Boston:Springer,
1995.

Additional References
G. Verghese and J. M. Rabaey, Low-Energy
FPGAs, Boston: springer, 2001.
K.-S. Yeo and K. Roy, Low-Voltage LowPower Subsystems, McGraw Hill, 2004.
A. Chandrakasan, W. J. Bowhill and F. Fox,
Design of High-Performance
Microprocessor Circuits, New York: IEEE
Press, 2001.
N. H. E. Weste and D. Harris, CMOS VLSI
Design, Third Edition, Reading,
Massachusetts, Addison-Wesley, 2005.
S. M. Kang and Y. Leblebici, CMOS Digital
Integrated Circuits, New York: McGraw-Hill,
1996.

Additional References
J. M. Rabaey, A. Chandrakasan and B. Nikoli,
Digital Integrated Circuits, Second
Edition, Upper Saddle River, New Jersey:
Prentice-Hall, 2003.
M. Pedram and J. M. Rabaey, Power Aware
Design Methodologies, Boston: Springer,
2002.
S. Sheng and R. W. Brodersen, Low-Power
Wireless Communications: A Wideband
CDMA System Design, Boston: Springer,
1998.
E. Larsson, Introduction to Advanced
System-on-Chip Test Design and
Optimization, Springer, 2005.

Why Low Power VLSI Design?

ISSCC, Feb. 2001, Keynote

Patrick P. Gelsinger
Senior Vice President
General Manager
Digital Enterprise Group
INTEL CORP.

Ten years from now, microprocessors will

run at 10GHz to 30GHz and be capable of
processing 1 trillion operations per second
about the same number of calculations that
the world's fastest supercomputer can
perform now.
Unfortunately, if nothing changes these
chips will produce as much heat, for their
proportional size, as a nuclear reactor. . . .

Why Low Power VLSI Design?

Power versus Energy
Power in high performance systems
Heat removal
Peak power - power delivery

Energy in portable systems

Battery life

Active (energy) vs. standby (power)

consumption
Constant throughput vs. burst-mode
computation

Why Low Power VLSI Design?

Power Density: Core Vs Cache

Why Low Power VLSI Design?

Power Density: The Future

Why Low Power VLSI Design?

VLSI Chip Power Density
Suns
Surface

Power Density (W/cm2)

10000

Rocket
Nozzle

1000

Nuclear
Reactor

100
8086

Hot Plate

10 4004
8008 8085
386
286
8080
1
1970

1980

P6
Pentium
486
1990
Year

2000

2010

Why Low Power VLSI Design?

Power Challenge

Why Low Power VLSI Design?

Power Delivery Challenges

Why Low Power VLSI Design?

Increasing Prominence of Portable Systems
Portability: Battery Storage Capacity is the
limiting factor

Why Low Power VLSI Design?

Battery Progress

Factor 4 over the last 10 years!

2X improvements in semiconductors in 18 months

Why Low Power VLSI Design?

Battery Powered Systems Extended
Battery Life and reduce weight and size.
High-Performance Systems
Cost

Package (chip carrier, heat sink, card slots, plenum, )

Power Systems (supplies, distribution, regulators, )
Fans (noise, power, reliability, area, )
Operating cost to customer Energy Star issue.

Reliability
Failure rate increase by 4X for Tj @ 110C vs 70C
Mission critical operation at 100C

Size and Weight Product footprint (office and

desk space)

Why Low Power VLSI Design?

SIA Roadmap for Processors
Year

1999

2002 2005 2008 2011

Feature size (nm)

180

130

100

70

Logic transistors/cm2

6.2M

18M

39M

84M

180M 390M

Clock (GHz)

1.25

2.1

3.5

6.0

10.0

16.9

Chip size (mm2)

340

430

520

620

750

900

Power supply (V)

1.8

1.5

1.2

0.9

0.6

0.5

High-perf. Power
(W)

90

130

160

170

175

183

Battery Power (W)

1.4

2.0

2.4

2.0

2.2

2.4

50

2014
35

Why Low Power VLSI Design?

Motivation for Low Power
Scaling of Si CMOS technology
Higher functionality with smaller chips
Higher performance at lower cost
Portability

New portable compute-intensive applications

Multi-media
Video display and capture
Audio reproduction & capture
Handwriting recognition
Notebook computer
Personal data assistant
Implantable medical electronics

Need for satisfactory battery life span

Why Low Power VLSI Design?

Historical Drivers for Low Power
Design
Pocket calculators
Hearing aids
Implantable pacemakers and cardiac
defibrillators
Portable military equipment for
individual soldiers
Wristwatches
Wireless computing

Why Low Power VLSI Design?

Microprocessor
Feature sizes of transistors keep shrinking
Magnitude of power/unit area keeps growing
Heat removal & cooling is worsening

Example: VDD 5 V

3.3 V

2.5 V

Power dissipation did not reduce plateaued at 30

W
Higher cooling costs for power densities of 50
W/cm2

Example: speech recognition needs a full PCB and

20 W of power to handle a 20,000 word
vocabulary
NiCd batteries only provide 26 W / pound battery weight

Why Low Power VLSI Design?

 Contemporary high
performance
processors consume
heavy power
 Cost associated with
packaging and
cooling such devices
is prohibitive
 Low-power methodology to be used to reduce cost of
packaging and cooling

Why Low Power VLSI Design?

Emergence of portable computing and
communication equipment, such as laptops,
palmtops, cell-phones, etc. Growth rate of
these portable equipment are very high
As these devices are battery operated, battery
life is of primary concern. Unfortunately, the
battery technology has not kept up with the
energy requirement of the portable
equipment.
Commercial success of these products depend
on weight, cost and battery life.
Low power design methodology is very
important to make them commercially viable.
Battery-aware synthesis approaches

Why Low Power VLSI Design?

 Reliability is closely related to power
dissipation Every 10C rise in temperature
roughly doubles the failure rate
Thermal runway
Gate dielectric
Junction diffusion
Electromigration diffusion
Electrical parameter shift
Package related failure
Silicon interconnect fatigue
0
o

100

200

300

C above normal operating temperature

Onset temperatures of various failure mechanism

Why Low Power VLSI Design?

According to an estimate of the U.S.
Environmental Protection Agency (EPA), 80%
of the power consumption by office
equipment are due to computing equipment
and a large part from unused equipment
Power is dissipated mostly in the form of
heat. The cooling techniques, such as AC
transfer the heat to the environment.
To reduce adverse effect on environment
efforts such as EPAs Energy Star program
leading to power management standard for
desktops and laptops has emerged.
Drive towards Green PC

Why Low Power VLSI Design?

IC Design Space

Why Low Power VLSI Design?

Historical figure of merit for VLSI design
performance (circuit speed) and chip
area (circuit density/cost). But
Power dissipation is now an important
metric in VLSI design.
No single major source for power savings across
all design levels Required a new way of
THINKING!!!
Companies lack the basic power-conscious
culture and designers need to be educated in
this respect.

Overall Goal To reduce power dissipations

but maintaining adequate throughput rate.

Why Low Power VLSI Design?

Power in a CMOS Gate
VDD

iDD(t)
Ground

Why Low Power VLSI Design?

Power in a CMOS Gate
Ptotal (01) = CL VDD2 +

tscVDD Ipeak + VDDIleakage

CL

%75

%20

%5

Why Low Power VLSI Design?

Power in a CMOS Gate
Charging current
Due to logic transitions causing logic gates to
charge/discharge load capacitance

Short-Circuit Current
p-tree and n-tree momentarily shorted as logic
gate changes state

Leakage Current
Diode leakages around transistors and n-wells
Increasing 20 times for each new fabrication
technology
Went from insignificant to a dominating factor

Why Low Power VLSI Design?

Dominance of Active Leakage

Why Low Power VLSI Design?

Dominance of Active Leakage

Why Low Power VLSI Design?

Conclusion
Know your enemy: Power
consumption in CMOS
Leakage is here to stay
Power and performance are
tightly coupled and have to be
jointly optimized
Principles of Power Minimization