Scribd
Upload
75 views15 pages

8 Digital

The document discusses digital and analog signals, inputs, digital clock signals, flop triggering, oscillators, clock distribution, master clocks, low skew buffers, and phase locked loops. Specifically, it covers topics such as rising-edge and falling-edge triggered flops, digital crystal oscillators, microprocessor bus clocks, single and double buffer clock trees, series terminated clock distribution, zero delay clocks, PLL clock multipliers, dividers, and synthesizers.

Uploaded by

Eko Sunaryo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
75 views15 pages

8 Digital

The document discusses digital and analog signals, inputs, digital clock signals, flop triggering, oscillators, clock distribution, master clocks, low skew buffers, and phase locked loops. Specifically, it covers topics such as rising-edge and falling-edge triggered flops, digital crystal oscillators, microprocessor bus clocks, single and double buffer clock trees, series terminated clock distribution, zero delay clocks, PLL clock multipliers, dividers, and synthesizers.

Uploaded by

Eko Sunaryo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 15

T EKNI K DI GI T AL

Rapat Kerja I nstruktur


Via Renata, 29 30 November 2005
ANALOG AND DI GI T AL

Digital Measurement Digital Signal Wave

Analog Measurement Analog Signal Wave


SI GNAL
1. Asserted
2. De-asserted
I NPUT S
1. Synchronous
2. Asynchronous
DI GI T AL CLOCK SI GNAL

Digital Clock Signal


FLOP T RI GGERI NG

Raising-Edge T riggered Flop

Falling-Edge T riggered Flop


OSCI LLAT OR

Digital Crystal Oscillator

Oscillator LC pi Power Filter


CLOCK DI ST RI BUT I ON
MAST ER CLOCK

Microprocessor Bus-Clock
CLOCK DI ST RI BUT I ON

Clock Distribution on Base Board and Expansion Board


CLOCK DI ST RI BUT I ON

Low Skew Buffer and Zero Delay Buffer


LOW SKEW BUFFER

Single Buffer Clock T ree

Double Buffer Clock T ree


LOW SKEW BUFFER

Series T erminated Clock Distribution

Single Output Driving T wo Loads


ZERO DELAY BUFFER

Zero Delay Clock


PHASE LOCKED LOOP

PLL Clock Multiplier


Generic Phase Locked Loop

PLL Clock Divider


PLL Clock Synthesizer

You might also like