Verilog, The Next Generation:

Accelleras SystemVerilog
Stuart Sutherland
Sutherland HDL, Inc., Portland, Oregon
[email protected]

Abstract technical subcommittee include experts in simulation

engines, synthesis compilers, verification methodologies,
This paper provides an overview of the proposed Accellera
SystemVerilog standard. SystemVerilog is a blend of C, members of the IEEE Verilog Standards Group, and senior
C++, SUPERLOG and Verilog, which greatly extends the design and verification engineers.
ability to model designs at an abstract architectural level.
The paper also discusses the current status of the proposed 2. Interfaces
standard. Background: Verilog connects one module to another
through module ports. This requires a detailed knowledge
1. Introduction of the intended hardware design, in order to define the
specific ports of each module that makes up the design.
Moore's law is still proving to be true; the designs we are
Early in a design cycle, this detail may not be well
creating keep getting larger and larger at an amazing pace.
established, yet it is difficult to change the port
Hardware design and verification languages need to keep
configurations of a design once the initial module ports
up with the pace of ever increasing design sizes. The IEEE
have been defined. In addition, several modules often have
1364 Verilog-20011,2 standard helps, with many significant many of the same ports, requiring redundant port
enhancements to the Verilog language. But, the IEEE definitions for each module. Every module connected to a
standardization process is slow and cumbersome. It took PCI bus, for example, must have the same ports defined.
four years from the time work was started on Verilog-2001
until the IEEE ratified the standard. By time Verilog-2001 SystemVerilog provides a new, high level of abstraction for
was approved, our design needs were already demanding module connections, called interfaces. An interface is
more from the language. We cannot wait another 4 years defined independent from modules, between the keywords
interface and endinterface. Modules can use an
for the next set of enhancements to the Verilog language.
interface the same as if it were a single port.
To provide Verilog designers with greater capability, at a
faster pace, Accellerathe combined VHDL International In its simplest form, an interface can be considered a
and Open Verilog International organizationshas bundle of wires. All the signals that make up a PCI bus, for
proposed a set of high-level extensions to the Verilog example, can be bundled together as an interface. Using
interfaces makes it possible to begin a design without first
language, known as SystemVerilog3. These extensions establishing all of the interconnections between modules.
provide powerful enhancements to Verilog, These As the details of design become more established, the
extensions provide powerful enhancements to Verilog, specific signals within the interfaces can be easily be
such as C language data types, structures, packed and represented; any changes within the interfaces will be
unpacked arrays, interfaces, assertions, and much more. reflected in all modules using the interfaces, without
Origins of SystemVerilog: SystemVerilog began with having to change each module..
donations of major portions of the SUPERLOG language interface chip_bus; // Define the interface
by Co-design4, and assertions work by Verplex. These wire read_request, read_grant;
donations were made about July, 2001. The Accellera wire [7:0] address, data;
endinterface: chip_bus
HDL+ subcommittee then met an average of twice
monthly to standardize these donations. A major part of module RAM(chip_bus io, //use the interface
input clk);
this standardization effort has been to ensure that //io.read_request references a signal in
SystemVerilog is fully compatible with the IEEE 1364- // the interface
2001 Verilog standard. Members of the Accellera HDL+ endmodule
 module CPU(chip_bus io, input clk); 4. Time unit and precision
...
endmodule Background: In Verilog, time values are specified as a
number, without any time unit. For example:
module top;
forever #5 clock = ~clock;
reg clk = 0;
chip_bus a; //instantiate the interface The Verilog standard does not specify a default unit or time
or time precision (where precision is the maximum number
//connect interface to module instances of decimal points used in time values). The time units and
RAM mem(a, clk);
precision are a property of each module, set by the
CPU cpu(a, clk);
endmodule compiler directive timescale. There is an inherent
danger with compiler directives, however, because they are
SystemVerilog interfaces go beyond just representing dependent on source code order. If there are multiple
bundles or interconnecting signals. An interface can also timescale directives in the source code, the last
include functionality that is shared by each module that directive encountered before a module is elaborated
uses the interface. In addition, an interface can include determines the time units of the module. If a module is not
built-in protocol checking. Shared functionality and preceded by a timescale directive, the time units and
protocol checking is possible because SystemVerilog precision of that module become dependent on the order
interfaces can include parameters, constants, variables, the source code is compiled. This can potentially cause
structures, functions, tasks, initial blocks, always blocks, different simulation runs to have different results.
and continuous assignments. SystemVerilog adds two significant enhancements to
control the time units of time values. First, time values can
3. Global declarations and statements have an explicit unit specified. The unit is one of s, ms, ns,
ps or fs, for seconds down to femtoseconds. The time unit
Background: Verilog does not have a global space, other
is a suffix to the time value, and cannot be preceded by a
than that the names of modules can be referenced from any
white space. For example:
other module, as module instances. Verilog also allows any
forever #5ns clock = ~clock;
number of top-level modules, which creates unrelated
hierarchy trees. Second, SystemVerilog allows the time units and time
precision to be specified with new keywords, timeunit and
SystemVerilog adds an implicit top-level hierarchy, called
timeprecision. These declarations can be specified within
$root. Any declarations or statements outside of a module
any module, or globally, in the $root space. The units and
boundary will be in the $root space. All modules,
precision must be a power of 10, ranging from seconds
anywhere in the design hierarchy, can refer to names
down to femtoseconds.
declared in $root. This allows global variables, functions
and other information to be declared, that are shared by all timeunits 1ns;
timeprecision 10ps;
levels of hierarchy in the design.
reg error _flag; //global variable
5. Abstract data types
function compare (...); //global function Background: Verilog provides hardware-centric net, reg
and variable data types. These types represent 4-state logic
always @(error_flag) //global statement
...
values, and are used to model and verify hardware
behavior at a detailed level. The net data types also have
module test; multiple strength levels and resolution functions for zero or
chip1 u1 (...) multiple drivers of the net.
endmodule
SystemVerilog includes the C language char and int data
module chip1 (...); types, which allows C and C++ code to be directly used in
FSM u2 (...); Verilog models and verification routines. The Verilog PLI
always @(data) is no longer needed to integrate Bus Functional Models,
error_flag = compare(data, expected);
algorithmic models, and C functions. SystemVerilog also
endmodule
adds several new data types to Verilog, which allow
module FSM (...); hardware to modeled at more abstract levels.
... char a 2-state signed variable, that is the same as the
always @(state)
error_flag = compare(state, expected);
C char data type, which may be an 8 bit integer (ASCII)
endmodule or a short int (Unicode).
 int a 2-state signed variable, that is similar to the C 6. Signed and unsigned modifiers
int data type, but is defined to be exactly 32 bits.
Background: By default, the Verilog net and reg data
shortint a 2-state signed variable, that is defined to types are unsigned types, and the integer type is a signed
be exactly 16 bits. type. The Verilog-2001 standard allows the unsigned types
longint a 2-state signed variable, that is defined to to be explicitly declared as signed data types using the
be exactly 64 bits, similar to the C long long type. signed keyword.
byte a 2-state signed variable, that is defined to be SystemVerilog adds the counterpart, the capability to
exactly 8 bits. explicitly declare signed data types to be unsigned, using
bit a 2-state unsigned data type of any vector width, the unsigned keyword. For example:
that can be used in place of the Verilog reg data type. int unsigned j;
logic a 4-state unsigned data type of any vector It should be noted that unsigned is a reserved word in the
width, that can be used in place of either a Verilog net or Verilog language, but is not used by the Verilog standard.
reg data type, but with some restrictions.
shortreal a 2-state single-precision floating point 7. User defined types
variable, that is the same as the C float type.
Background: Verilog does not allow users to define new
void represents no value, and can be specified as the data types.
return value of a function, the same as in C.
SystemVerilog provides a method to define new data types
The SystemVerilog bit and other data types allow using typedef, similar to C. The user-defined type can
modeling designs using 2-state logic, which is much more then be used in declarations the same as with any data type.
efficient for simulation performance. Since the Verilog typedef unsigned int uint;
language does not have a two-state data type, many uint a, b;
simulators have provided the capability as an option to the A user-defined type can be used before it is defined,
simulator. These options are not portable to all simulators, provided it is first identified using an empty typedef.
however, and often have the side effect of forcing 2-state
typedef int48; //full definition is elsewhere
logic in regions of a design where 3-state or 4-state logic is int48 c;
needed. The SystemVerilog bit data type can greatly
improve simulation performance, while still allowing 3-
8. Enumerated types
state or 4-state logic in the regions of a design where
needed. By using a data type with defined behavior instead Background: Verilog does not have enumerated types.
of proprietary simulator options, 2-state models will be Identifiers must be explicitly declared as a net, variable or
portable to all SystemVerilog simulators. parameter, and assigned values.
The SystemVerilog logic data type is more versatile than SystemVerilog allows the creation of enumerated types,
the Verilog net and reg data types, which makes it easier to using a C-like syntax. An enumerated type has one of a set
model hardware at any level of abstraction. The logic of named values. By default, the values increment from an
type can receive a value one of the following ways: initial value of 0, but the initial value can also be explicitly
specified. The enumerated type will have the same vector
Assigned values by any number of procedural
size as the initial value.
assignment statements, replacing the Verilog reg type
enum {red, yellow, green} RGB;
Assigned a value by a single continuous assignment enum {WAIT=2b01, LOAD, DONE} states;
statement, a restricted replacement for the Verilog wire
Using typedef, an enumerated type can be given a name,
Connected to a the output of a single primitive, a allowing the type to be used in many places.
restricted replacement for the Verilog wire type
typedef enum {FALSE=1b0, TRUE} boolean;
Since the logic type can be used in place of either a boolean ready;
Verilog reg or a wire (with restrictions), it allows writing boolean test_complete;
models at a high level of abstraction, and adding details to
the model as the design progresses without having to 9. Structures and unions
change data type declarations. Background: The Verilog HDL does not have structures
The logic data type does not represent strength levels and or unions, which are useful for grouping several
does not have resolution functions for wired logic, which declarations together.
makes the logic type more efficient to simulate and SystemVerilog adds structures and unions. The declaration
synthesize than the Verilog wire type. syntax is similar to C.
 struct { 11. Declarations in unnamed blocks
reg [15:0] opcode;
reg [23:0] addr; Background: Verilog allows variables to be declared in a
} IR; named beginend or forkjoin statement group. These
variables are local to the group, but can be referenced
union {
hierarchically.
int i;
shortreal f; SystemVerilog allows declarations to be made in unnamed
} N; blocks as well as in named blocks. In an unnamed block, a
hierarchical name cannot be used to access the variable.
Fields within a structure or union are referenced using a All variable types, including user-defined types,
period between the variable name and the field name. enumerated types, structures and unions can be declared
IR.opcode = 1; //set the opcode field in IR within a beginend or forkjoin statement group
N.f = 0.0; //set N as floating point value
A structure or union definition can be given a name using 12. Constants
typedef. Background: Verilog has three specific types of constants:
typedef struct { parameter, specparam and localparam.
bit [7:0] opcode;
bit [23:0] addr; SystemVerilog allows any data type to be declared as
} instruction; //named structure type constant, using the const keyword.
const char colon = ":";
instruction IR; //allocate a structure
A structure can be assigned as a whole, using a 13. Redefinable data types
concatenation of values.
SystemVerilog extends the Verilog parameter to include
instruction = {5, 200};
type. This powerful feature allows the data types within a
Structures can be passed to or from a function or task as a module to be redefined for each instance of the module.
whole, and can be passed through module ports. module foo
#(parameter type VAR_TYPE = shortint;)
10. Arrays (input logic [7:0] i, output logic [7:0] o);

Background: Verilog HDL data types can be declared as VAR_TYPE j = 0; /* j is of type shortint
unless redefined */
arrays. The reg and net types can also have a vector width
...
declared. A dimension declared before the object name is endmodule
the vector width dimension. The dimensions declared
after the object name are the array dimensions. module bar;
logic [3:0] i,o;
reg [7:0] r1 [1:256]; //256 8-bit variables
foo #(.VAR_TYPE(int)) u1 (i, o);
SystemVerilog uses different terminology. The term //redefines VAR_TYPE to a type of int
packed array is used to refer to the dimensions declared endmodule
before the object name, instead of vector width. The term
unpacked array is used to refer to the dimensions 14. Module port connections
declared after the object name. Packed arrays can only be Background: Verilog restricts the data types that may be
made of the types: bit, logic, reg, wire, and the other connected to module ports to net types, and the variable
net types. Multiple dimensions can be declared for packed types reg, integer and time.
arrays as well for unpacked arrays.
SystemVerilog removes all restrictions on connections to
bit [7:0] a; //a 1-d packed array
bit b [7:0]; //a 1-d unpacked array
module ports. Any data type can be passed through ports,
bit [0:11] [7:0] c; //a 2-d packed array including reals, arrays and structures.
bit [3:0] [7:0] d [1:10]; /* a 10 element
unpacked array of a packed array, consisting 15. Literal values
of 4 8-bit bytes */
Background: Verilog has several limitations when
Unpacked dimensions are referenced before packed
specifying or assigning literal values.
dimensions. This allows referencing an entire packed array
as a single element. In the last example above, d[1] refers SystemVerilog adds the following enhancements to how
to a single element in the unpacked array. That element is literal values can be specified.
an array of four bytes. All bits of a literal value can be filled with the same value
 using 0, 1, z or x. This allows a vector of any size SystemVerilog adds the ability to explicitly specify when
to filled, without having to explicitly specify the vector each branch of decision statements is unique or requires
size of the literal value. priority evaluation. The keywords unique and priority
bit [63:0] data; can be specified before the if or case keyword. These
data = 1; //set all bits of data to 1 keywords can be used to instruct simulators, synthesis
A string literal can be assigned to an array of characters. compilers, and other tools the specific type of hardware
A null termination is added as in C. If the size differs, it is intended. Tools can use this information to check that the
left justified, as in C. if or case statement properly models the desired logic.
char foo [0:12] = hello world\n;
For example, if a decision statement is qualified as unique,
simulators can issue a warning message if an unexpected
Several special string characters have been added:
case value is found.
\v for vertical tab
bit[2:0] a;
\f for form feed
\a for bell unique if ((a==0) || (a==1)) y = in1;
\x02 for a hex number representing an ASCII character else if (a == 2) y = in2;
else if (a == 4) y = in3;
Arrays can be assigned literal values, using a syntax //values 3,5,6,7 will cause a warning
similar to C initializers, except that the replicate operator
is also allowed. The number of nested of braces must priority if (a[2:1]==0) y = in1 //a is 0 or 1
exactly match the number of dimensions (unlike C). else if (a[2] == 0) y = in2; //a is 2 or 3
else y = in3; //a is any other value
int n[1:2][1:3] = { {0,1,2}, {3{4}} };
unique case(a)
16. Type casting 0, 1: y = in1;
2: y = in2;
Background: The Verilog language does not have the 4: y = in3;
ability to cast values to a different data type. endcase //values 3,5,6,7 will cause a warning
SystemVerilog adds the ability to change the type of a
priority casez(a)
value to a using a cast operation, represented by <type>. 2'b00?: y = in1; // a is 0 or 1
The cast can be to any type, including user-defined types. 2'b0??: y = in2; //a is 2 or 3;
int(2.0 * 3.0) //cast result to int default: y = in3; //a is any other value
mytype(foo) //cast foo to the type of mytype endcase

A value can also be cast to a different vector size by

specifying a decimal number before the cast operation. 19. Bottom testing loop
17( x - 2) //cast the operation to 17 bits Background: Verilog has the for, while and repeat
The signedness of a value can also be cast. loops, all of which test to execute the loop at the beginning
of the loop.
signed'(x) //cast x to a signed value
SystemVerilog adds a dowhile loop, which tests the loop
17. Operators condition at the end of executing code in the loop.
Background: Verilog does not have the C language ++, --
or the C increment and decrement assignment operators.
20. Jump statements
SystemVerilog adds several new operators: Background: The C language provides several means to
jump to a new statement in execution flow: return,
++ and -- increment and decrement operators break, continue and goto. Verilog does not have any of
+=, -=, *=, /=, %=, &=, ^=, |=, <<=, >>=, <<<= and >>>= these statements, and instead provides the ability to jump
assignment operators to the end of a statement group using the disable
statement. Using disable to carry out the functionality of
18. Unique and priority decision statements break and continue requires adding block names, and can
Background: The Verilog ifelse and case statements create code that is non intuitive.
can be a source of mismatches between RTL simulation SystemVerilog adds the C break and continue
and how synthesis interprets an RTL model, if strict coding keywords, which do not require the use of block names,
styles are not followed. The synthesis full_case and and a return keyword, which can be used to exit a task or
parallel_case pragmas can lead to further mismatches function at any point.
if improperly used. break exits a loop, as in C
 continue skips to the end of a loop, as in C Expressions in event controls: Verilog allows expressions
return expression exits a function to be used in an @ event control list. For example:
return exits a task or void function always @( (a * b) )
always @(memory[address])
SystemVerilog does not include the C goto statement.
In first example, should the event control trigger when the
21. Block names and statement labels operands change, or only if the result of the operation
Background: Verilog allows a beginend or forkjoin changes? In second example, should the event control trig-
ger when the address to the memory changes, or only if the
statement block to be named, by specifying the name after
value in the selected memory address changes? The IEEE
the begin or fork keyword. The name represents the
Verilog standard allows simulators to optimize differently
entire statement block. when the @ event control contains an expression. This can
SystemVerilog allows a matching block name to be lead to different behavior in different simulators, and a
specified after the block end or join keyword. This can mismatch in simulation and synthesis results.
help document which end or join is associated with SystemVerilog adds a changed keyword, which is used as
which begin or fork when there are long blocks or nested a modifier in the event control list. The @(changed
blocks. The name at the end of the block is optional, and expression) explicitly defines that the event control only
must match the name at the beginning of the block. triggers on a change of the result of the expression.
begin: foo //block name is after the begin always @(changed (a*b) )
... always @(changed memory[address])
fork: bar //nested block with a name
... Assignments in event controls: Verilog does not allow an
join: bar //name must be the same assignment to made within an event control.
...
end: foo //name must be same as block name SystemVerilog allows assignment expressions to be used in
an event control. The event control is only sensitive to
SystemVerilog also allows individual statements to labeled,
changes on the right side of the assignment.
as in C. A statement label is placed before the statement,
always @( (y = a * b) )
and is used to identify just that statement.
initial begin
test1: read_enable = 0; 23. New procedures
... Background: Verilog uses the always procedure to
test2: for (i=0; i<=255; i++)
represent RTL models of sequential logic, combinational
...
end logic and latched logic. Synthesis and other software tools
must infer the intent of the always procedure from the
22. Event control enhancements context of the @ event control at the beginning of the
procedure (the sensitivity list) and the statements within
Background: Verilog uses the @ token to control the procedure. This inference can lead to mismatches in
execution flow based on specific events. simulation and synthesis results.
SystemVerilog enhances the @ event control. SystemVerilog adds three new procedures to explicitly
Conditional event control: One common usage of @ is to indicate the intent of the logic:
infer latch behavior with an enable input. The following always_ff the procedure should represent sequential
example illustrates a common style for modeling a latch: logic
always @(data or en) //RTL latch model
always_comb the procedure should represent
if (en) y <= data;
combinational logic
This coding style can be inefficient for simulation, because
always_latch the procedure should represent
even when the enable input is not asserted, the event
latched logic
control will trigger on every change of the data input.
For example:
SystemVerilog adds an iff condition that can be specified
always_comb @(a or b or sel) begin
in event controls. The iff condition must be true in order
if (sel) y = a;
for the control to trigger. By moving the enable decision else y = b;
into the event control, the control will only trigger when end
the latch output can change. Software tools can examine the event control sensitivity
always @(a or en iff en==1) list and procedure contents to ensure that the functionality
y <= a;
matches the type of procedure. For example, a tool can
check that an always_comb procedure is sensitive to all Return from any point: Verilog returns from a task or
external values read within the procedure, makes function when the execution reaches the endtask or
assignments to the same variables for every branch of endfunction keyword. The return value of a function is
logic, and that branches covers every possible condition. If the last value assigned to the name of the function.
any of these conditions are not true, then a software tool SystemVerilog adds a return keyword, as discussed in
can report that the procedure does not properly model section 20 of this paper. Using this keyword, a task or
combinational logic. function can be exited at any point.
Multiple statements: Verilog requires that a task or
24. Dynamic processes function have a single statement or statement block.
Background: Verilog provides a form of static concurrent Multiple statements must be grouped into a single begin
processes using forkjoin. Each branch of a fork is a end or forkjoin block.
separate, parallel process. Execution of any statements SystemVerilog removes the restriction of a single statement
which follow the forkjoin will not be executed until or block. Therefore, multiple statements can be listed in a
every process in the group has completed. task or function without using beginend or forkjoin.
initial Statements that are not grouped will execute sequentially,
begin
as if within a beginend. It also legal to create a task or
fork
send_packet_task(1,255,0); function definition with no statements.
send_packet_task(7,128,5); Void functions: The Verilog language requires that a
watch_result_task(1,255,0); function have a return value, and that function calls receive
watch_result_task(7,128,5);
join //all tasks must complete to get here
the return value.
end SystemVerilog adds a void data type, which can be
SystemVerilog adds a new, dynamic process, using the specified as the return type of a function. Void functions
process keyword. This forks off a process, and then can be called the same as a Verilog task, without receiving
continues execution without waiting for the process to a return value. The difference between a void function and
complete. The process does not block the flow of execution a task is that functions have several restrictions, such as no
of statements within the procedure or task. This allows time controls.
multi-threaded processes to be modeled. Function inputs and outputs: The Verilog standard
initial requires that a function have at least one input, and that
begin functions can only have inputs.
process send_packet_task(1,255,0);
process send_packet_task(7,128,5); SystemVerilog removes these restrictions. Functions can
process watch_result_task(1,255,0); have any number of inputs, outputs and inouts, including
process watch_result_task(7,128,5); none.
end //all processes run in parallel
26. Continuos assignment enhancements
25. Task and function enhancements
Background: In Verilog, the left hand side of a continuous
SystemVerilog adds several enhancements to the Verilog assignment can only be a net data type, such as wire. The
task and function constructs. continuous assignment is considered a driver of the net.
Static and automatic storage: By default all storage Nets can have any number of drivers.
within a Verilog task or function is static. Verilog-2001 SystemVerilog allows any variable data type except reg to
allows tasks and functions to be declared as automatic, be used on the left hand side of a continuous assignment.
making all storage within the task or function automatic. Unlike nets, however, all other data types are restricted to
With SystemVerilog: being driven by a single continuous assignment. It is illegal
Specific data within a static task or function can be to mix continuous assignments and procedural assignments
explicitly declared as automatic. Data declared as (including initial assignments) for the same variable.
automatic has the lifetime of the call or block, and is
initialized on each entry to the task or function call. 27. $bits system function
Specific data within an automatic task or function can be Background: Verilog does not have an equivalent to the C
explicitly declared as static. Data declared to be static sizeof function.
in an automatic task or function has a static lifetime but a SystemVerilog adds a new $bits built-in system function.
scope local to the block. This function returns the number of hardware bits required
to hold a value (a 4-state value requires one hardware bit, approved, Accellera plans to donate SystemVerilog to the
even though it might require multiple bits to store within IEEE 1364 Verilog Standards Group, for incorporation into
simulation). This function can also be used to determine a future version of the IEEE 1364 Verilog standard.
the number of bits represented by a structure.
32. Future plans for SystemVerilog
28. define enhancements The first generation of SystemVerilog as presented in this
SystemVerilog enhances the capabilities of the define paper is not the end of the roadit is the beginning.
compiler directive to support strings as macro arguments. Accellera will continue to review the needs of Verilog
The macro text string can include an isolated quote, which design and verification. New features will be added to the
must be preceded by a back tick ( `" ), which allows macro SystemVerilog standard as they become well defined.
arguments to be included in strings. The macro text can These extensions will also be donated to the IEEE 1364
include a backslash ( \ ) at the end of a line to show Verilog Standards Group.
continuation on the next line. If the macro text string is to
contain a backslash, the backslash should be enclosed in 33. Conclusion
back ticks ( `\` ), so that it will not be treated as the start SystemVerilog provides a major set of extensions to the
of a Verilog escaped identifier. The macro text string can Verilog-2001 standard. These extensions allow modeling
also include a double back tick ( `` ), which allows and verifying very large designs more easily and with less
identifiers to be constructed from arguments. These coding. By taking a proactive role in extending the Verilog
enhancements make the `define directive much more language, Accellera is providing a standard that can be
versatile. For example, the `include directive can be implemented by simulator and synthesis companies
followed by a macro name instead of a literal string. quickly, without waiting for the protracted IEEE
`define f1 "../project_top/opcode_defines" standardization process. It is fully expected that the IEEE
`include `f1
Verilog standards group will adopt the SystemVerilog
extensions as part of the next generation of the IEEE 1364
29. State machine modeling Verilog standard.
The Accellera HDL+ committee defining the
SystemVerilog standard is currently evaluating additional 34. References
constructs that will allow modeling complex state
[1] IEEE Std. 1364-2001 standard for the Verilog Hardware
machines at a higher level of abstraction than is possible
Description Language, IEEE, Pascataway, New Jersey,
with Verilog. These constructs include: 2001.
Enumerated types [2] S. Sutherland, Verilog 2001: A Guide to the new Verilog
A special state data type Standard, Kluwer Academic Publishers, Boston, Massachu-
A transition statement setts, 2001.
A transition operator [3] SystemVerilog 3.0: Accelleras Extensions to Verilog,
Accellera, Napa, California, 2001.
Enumerated types are discussed in section 8 of this paper.
The specific features and syntax for the special state data [4] SUPERLOG Extended Synthesizable Subset Language
type and transitions were not finalized at the time this Definition, Draft 3, May 29, 2001, 1998-2001 Co-Design
paper was prepared for publication. Automation Inc.

30. Assertions 35. About the author

The committee defining the SystemVerilog standard is Mr. Stuart Sutherland is a member of the Accellera HDL+
currently evaluating a proposal to add assertions to the technical subcommittee that is defining SystemVerilog,
proposed SystemVerilog standard. This effort is well and is the technical editor of the SystemVerilog Reference
underway, but the specific features and syntax were not Manual. He is also a member of the IEEE 1364 Verilog
finalized at the time this paper was prepared for Standards Group, where he serves as chair of the PLI task
publication. force. Mr. Sutherland is an independent Verilog consultant,
and specializes in providing comprehensive expert training
on the Verilog HDL and PLI. Mr. Sutherland can be
31. Current status of SystemVerilog
reached by e-mail at [email protected].
The standardization of the first generation of Updated copies of this paper and presentation slides are
SystemVerilog is nearly complete, and is expected to be available at www.sutherland-hdl.com.
ratified by the Accellera board in July, 2002. Once