March 11 - 12, 2002

Verilog: The Next Generation

Accelleras SystemVerilog Standard

by
Stuart Sutherland
Verilog HDL and PLI Expert
Sutherland HDL, Inc.
Sutherland
Training engineers H D
to be HDL wizards L

1
 March 11 - 12, 2002

Sutherland
Overview HD
L

! Define what is SystemVerilog

! Justify the need for SystemVerilog

! A whirlwind tour of the major features

in SystemVerilog

! The status of the SystemVerilog

standard

Stuart Sutherland, Sutherland HDL, Inc. 2

 March 11 - 12, 2002

Sutherland
What is SystemVerilog HD
L

! SystemVerilog is a proposed set of extensions of the IEEE

1364 Verilog-2001 standard
! Adds C language constructs to Verilog
! Adds assertions to Verilog
! Adds interfaces to Verilog
! Gives Verilog a new level of modeling abstraction
! Gives Verilog a new level of design verification
! Will ship in June 2002

Stuart Sutherland, Sutherland HDL, Inc. 3

 March 11 - 12, 2002

Sutherland
Why Enhance Verilog? HD
L

! Hardware size and complexity is increasing

! Engineers must design more gates than ever before

! Larger designs require working at a more abstract level

! Larger designs require new verification techniques

! Hardware is still built with silicon

! Proven engineering methods are still used

! Verilog works, and works well

! Tools such as simulation, synthesis, timing analysis work well
! The right solution is to extend what works

Stuart Sutherland, Sutherland HDL, Inc. 4

 March 11 - 12, 2002

Sutherland
SystemVerilog is an Evolution HD
L

! SystemVerilog evolves Verilog, rather than replacing it

! Gives engineers the best of Verilog and C

typedef
typedef struct
struct {string
{string s;
s; int
int left}
left} node;
node;

C int
int visited
visited == 0;
0; //global
//global data
data
C language
language abstractions
abstractions
Structures
Structures function
function int
int treeFind(string
treeFind(string str,
str, parent);
parent);
Globals
Globals if
if (parent
(parent ==
== null)
null)
++
++ operator
operator return
return null;
null;
Enumerated
Enumerated types
types visited++;
visited++;
...
...
endfunction
endfunction
state
state {S0,
{S0, S1,
S1, S2}
S2} cstate;
cstate; //enumeration
//enumeration types
types
Standard
Standard Verilog
Verilog HDL
HDL always
always @(posedge
@(posedge clk)
clk)
Familiar
Familiar to
to H/W
H/W engineers
engineers begin
begin
Concurrency
Concurrency case
case (cstate)
(cstate)
Proven
Proven to
to work
work ...
...
end
end
Stuart Sutherland, Sutherland HDL, Inc. 5
 March 11 - 12, 2002

Sutherland
Who is Accellera? HD
L

! Accellera is an HDL/HVL standards organization

! Formed by the merger of OVI and VI in 1999

! Made up of volunteers from:

! EDA companies
! Hardware design companies
! Consultants
! Promotes the use and evolution of Verilog and VHDL
! Several subcommittees explore solutions to current and
future needs in hardware design
! The Accellera HDL+ committee is exploring the future needs for
the Verilog language
! SystemVerilog is a result of that exploration
Stuart Sutherland, Sutherland HDL, Inc. 6
 Why is Accellera Specifying March 11 - 12, 2002

Sutherland
Changes to an IEEE Standard? HD
L

! The IEEE 1364 standards group is the official governing body

of the Verilog language
! Defined the 1364-1995 Verilog-1995 standard

! Defined the 1364-2001 Verilog-2001 standard

! Our design needs are changing much faster than the IEEE
can react
! It took the IEEE 4 years to define and ratify Verilog-2001

! Slower than molasses flowing uphill in the winter

! Accellera can react much faster than the IEEE
! A de facto standard can be created in months instead of years
! Accellera expects the IEEE to adopt the enhancements in
SystemVerilog as part of the next IEEE Verilog standard
Stuart Sutherland, Sutherland HDL, Inc. 7
 March 11 - 12, 2002

Sutherland
SystemVerilogs Roots HD
L

! Most enhancements in SystemVerilog are from two sources:

! A subset of the SUPERLOG language

! Co-design Automation donated the synthesizable portion of its

SUPERLOG language to Accellera
! The Accellera HDL+ committee modified the subset to be an
extension to Verilog-2001
! A superset of the OVL assertions library
! Verplex and other companies donated assertions libraries to
Accellera
! The Accellera Assertions committee is defining assertions syntax
and semantics for both Verilog and VHDL
! The Accellera HDL+ committee is adding the Verilog assertions

extensions to SystemVerilog
Stuart Sutherland, Sutherland HDL, Inc. 8
 A Mile High View of March 11 - 12, 2002

Sutherland
SystemVerilog HD
L
SystemVerilog
int enum break continue
User Defined Ports Block Labeling
State Machines shortint typedef return goto
Dynamic Processes
Interfaces Assertions longint struct union ++ -- += -= *=
Packed Arrays 2/4 State Variables shortreal casting /= >>= <<=
Structures
Unions
Timeunits C double const
&= |= ^= %=
unique/priority fork/case/if char void
globals

ANSI C style ports standard file I/O (* attributes *) multi dimensional arrays

Verilog 2001
generate $value$plusargs configurations signed unsigned
localparam `ifndef `elsif `line memory part selects automatic

Verilog 1995
const func @* variable part select ** (power operator)

modules $finish $fopen $fclose initial wire reg begin end +=*/
parameters $display $write disable integer real while %
function/tasks $monitor events time for forever >> <<
always @ `define `ifdef `else wait # @ packed arrays if else
assign `include `timescale fork/join 2D memory repeat

Stuart Sutherland, Sutherland HDL, Inc. 9

 March 11 - 12, 2002

Sutherland
Interfaces HD
L

! Verilog-1995/2001 connects models using module ports

! Requires detailed knowledge of

connections to create module

! Difficult to change connections

if design changes
! Port declarations must be

duplicated in many modules

! SystemVerilog adds interfaces
! Connections between models are

bundled together
! Connection definitions are

independent form all modules

Stuart Sutherland, Sutherland HDL, Inc. 10
 March 11 - 12, 2002

Sutherland
Interface Example HD
L

! An interface is defined separately from any module

! New keywords: interface, endinterface

interface
interface chip_bus;
chip_bus; //
// Define
Define the
the interface
interface
wire
wire read_request,
read_request, read_grant;
read_grant;
wire
wire [7:0]
[7:0] address,
address, data;
data;
endinterface:
endinterface: chip_bus
chip_bus

module
module top;
top;
reg
reg clk
clk == 0;
0;
chip_bus
chip_bus a;a; //instantiate
//instantiate the
the interface
interface

RAM
RAM mem(a,
mem(a, clk);
clk); //connect
//connect interface
interface to
to module
module instance
instance
CPU
CPU cpu(a,
cpu(a, clk);
clk); //connect
//connect interface
interface to
to module
module instance
instance
endmodule
endmodule

module
module RAM(chip_bus
RAM(chip_bus io,
io, input
input clk);
clk);
//io.read_request
//io.read_request references
references aa signal
signal in
in the
the interface
interface
endmodule
endmodule
Stuart Sutherland, Sutherland HDL, Inc. 11
 March 11 - 12, 2002

Sutherland
Interfaces Can Contain Logic HD
L

! SystemVerilog interfaces are more than just a bundle of

wires
! Interfaces can contain declarations

! Variables, parameters and other data that is shared by all users of

an interface can be declared in one location
! Interfaces can contain tasks and functions
! Operations shared by all connections to the interface can be coded
in one place
! Interfaces can contain procedures
! Protocol checking and other verification can be built into
the interface
Attend
Attend the
the tutorial
tutorial this
this afternoon
afternoon for
for an
an in-depth
in-depth
look
look at
at SystemVerilog
SystemVerilog interfaces!
interfaces!
Stuart Sutherland, Sutherland HDL, Inc. 12
 Global Declarations March 11 - 12, 2002

Sutherland
and Global Statements HD
L

! Verilog-1995/2001:
! Does not have a true global name space

! Only module names and primitive names are global

! Cannot declare common variables, functions or blocks
! Verilog-1995/2001 allows multiple top-levels of hierarchy
! SystemVerilog adds a global space
! A $root space is the implied top-level of the hierarchy

! Any declaration not in a module or interface is in $root

! Variables, functions, tasks,

! All modules can reference objects declared in the global
$root space

Stuart Sutherland, Sutherland HDL, Inc. 13

 Global Declaration and March 11 - 12, 2002

Sutherland
Functionality Example HD
L

! Declarations and statements outside of any module or

interface are in the global $root space
reg
reg error
error _flag;
_flag; //global
//global variable
variable

function
function compare
compare (...);
(...); //global
//global function
function global
global declarations
declarations
and
and statements
statements
always
always @(error_flag)
@(error_flag) //global
//global statement
statement
...
...
module
module chip1
chip1 (...);
(...);
FSM
FSM u2
u2 (...);
(...);
always
always @(data)
@(data)
error_flag
error_flag == compare(data,
compare(data, expected);
expected);
endmodule
endmodule
module
module FSM
FSM (...);
(...);
...
...
always
always @(state)
@(state)
error_flag
error_flag == compare(state,
compare(state, expected);
expected);
endmodule
endmodule
Stuart Sutherland, Sutherland HDL, Inc. 14
 March 11 - 12, 2002

Sutherland
Time Unit and Precision HD
L

! In Verilog-1995/2001, time units are a module property

! Declared with the `timescale compiler directive

forever
forever #5
#5 clock
clock == ~clock;
~clock; 55 what?
what?

! SystemVerilog adds:
! Time units can be specified as part of the time value

forever
forever #5ns
#5ns clock
clock == ~clock;
~clock;

! Module time units and precision can be specified with

keywords module
module my_chip
my_chip ();
();
timeunits
timeunits 1ns;
1ns;
timeprecision
timeprecision 10ps;
10ps;

Stuart Sutherland, Sutherland HDL, Inc. 15

 March 11 - 12, 2002

Sutherland
Abstract Data Type HD
L

! Verilog-1995/2001 has hardware-centric net and reg types

! Intended to represent real connections in a chip or system

! 4-state logic, strength levels, wired logic resolution

! Costly to simulation performance; Most hardware is 2-state

! Models real hardware, but costly to simulation performance
! SystemVerilog adds
! Abstract data types

! 2-state types: int, shortint, longint, char, byte, bit

! 4-state type: logic
! Special types: void, shortreal
! Allows modeling at a C-language level of abstraction
! Efficient data types for simulation performance
Stuart Sutherland, Sutherland HDL, Inc. 16
 March 11 - 12, 2002

Sutherland
The 2-state bit Data Type HD
L

! Verilog-1995/2001 uses 4-state logic

! Costly to simulation performance

! Most hardware is 2-state logic

! Some simulators fake 2-state with compilers

! Not portable to other tools (not a standard)

! Can have side affects if part of the design (or verification)

needs 3-state or 4-state

! The SystemVerilog 2-state bit type

! Allows mixing 2-state and 4-state in the same design

! Will work the same on all SystemVerilog simulators

Stuart Sutherland, Sutherland HDL, Inc. 17

 March 11 - 12, 2002

Sutherland
The 4-state logic data type HD
L

! One of the biggest headaches with Verilog-1995/2001 is

determining when to use reg and when to use wire
! Context dependent

! As model changes, the data type required can change

! SystemVerilogs 4-state logic type:

! Can be used in place of a reg

! Can be used in place of a wire, but limited to 1 driver

! Allows evolving a design from algorithmic to behavioral to RTL to

gate without changing data types
! 1-driver limit allows more efficient simulation performance

Stuart Sutherland, Sutherland HDL, Inc. 18

 March 11 - 12, 2002

Sutherland
Signed and Unsigned Modifiers HD
L

! Verilog-1995 had one signed type

! The integer type is a 32-bit signed variable

! Verilog-2001 adds signed nets and regs

! Any vector size can be explicitly declared as signed

reg
reg signed
signed [63:0]
[63:0] data_bus;
data_bus;

! The integer type is still a signed 32-bit variable

! SystemVerilog adds new signed types
! The int, shortint, longint, byte and char are signed

! SystemVerilog adds unsigned declarations

! Any signed type can be explicitly declared as unsigned

byte
byte unsigned
unsigned ubyte;
ubyte;
Stuart Sutherland, Sutherland HDL, Inc. 19
 March 11 - 12, 2002

Sutherland
User-defined Types HD
L

! Verilog-1995/2001 does not have user-defined data types

! SystemVerilog adds user-defined types

! Uses the typedef keyword, as in C

typedef
typedef unsigned
unsigned int
int uint;
uint;
uint
uint a,
a, b;
b; //two
//two unsigned
unsigned integers
integers

! User-defined types can be referenced before being defined

! Requires an empty typedef declaration, as in C
typedef
typedef int48;
int48; //full
//full typedef
typedef definition
definition is
is elsewhere
elsewhere
int48
int48 c;
c;

Stuart Sutherland, Sutherland HDL, Inc. 20

 March 11 - 12, 2002

Sutherland
Enumerated Types HD
L

! Verilog-1995/2001 does not have enumerated types

! All signals must be declared

! All signals must be given a value to be useful

! SystemVerilog adds enumerated types, using enum, as in C

enum
enum {red,green,blue}
{red,green,blue} RGB;
RGB;

! The value of the first enumerated type can be specified

! Subsequent types are incremented from the initial value
! The vector size of the type is the size of the initial value
! The default initial value is an integer of 0
enum
enum {WAIT=2b01,
{WAIT=2b01, LOAD,
LOAD, READY}
READY} states;
states;
! Enumerated types can be given a name, as in C
typedef
typedef enum
enum {FALSE=1b0,
{FALSE=1b0, TRUE}
TRUE} boolean;
boolean;
boolean
boolean ready;
ready; //signal
//signal ready
ready can
can be
be FALSE
FALSE or
or TRUE
TRUE
Stuart Sutherland, Sutherland HDL, Inc. 21
 March 11 - 12, 2002

Sutherland
Structures and Unions HD
L

! Verilog-1995/2001 does not have structures or unions

! SystemVerilog adds structures and unions

! Uses a similar syntax as C

! Can be given a name, using typedef

! Can be assigned a value as a whole

struct
struct {{ typedef
typedef struct
struct {{
reg
reg [15:0]
[15:0] opcode;
opcode; bit
bit [7:0]
[7:0] opcode;
opcode;
reg
reg [23:0]
[23:0] addr;
addr; bit
bit [23:0]
[23:0] addr;
addr;
}} IR;
IR; }} instruction;
instruction; //named
//named structure
structure type
type

union
union {{ instruction
instruction IR;
IR; //allocate
//allocate aa structure
structure
int
int i;
i;
shortreal
shortreal f;
f; IR
IR == {5,
{5, 200};
200}; //fill
//fill the
the structure
structure
}} N;
N;

Stuart Sutherland, Sutherland HDL, Inc. 22

 March 11 - 12, 2002

Sutherland
Module Port Connections HD
L

! Verilog-1995/2001 restricts the data types that can be

connected to module ports
! Only net types on the receiving side

! Nets, regs or integers on the driving side

! SystemVerilog removes all restrictions on port connections

! Any data type on either side of the port

! Real numbers (floating point) can pass

through ports
! Arrays can be passed through ports

! Structures can be passed through ports

Stuart Sutherland, Sutherland HDL, Inc. 23

 March 11 - 12, 2002

Sutherland
Redefinable Data Types HD
L

! Verilog-1995/2001 allows parameterized vector declarations

module
module register
register #(parameter
#(parameter size
size == 16)
16)
(output
(output reg
reg [size-1:0]
[size-1:0] q,
q,
input
input wire
wire [size-1:0]
[size-1:0] d,
d,
input
input wire
wire clock,
clock, reset);
reset);

! SystemVerilog allows data types to be parameterized

! Data types to be changed using parameter definition

module
module foo
foo #(parameter
#(parameter type
type VAR_TYPE
VAR_TYPE == shortint;)
shortint;)
(input
(input logic
logic [7:0]
[7:0] i,
i, output
output logic
logic [7:0]
[7:0] o);
o);
VAR_TYPE
VAR_TYPE jj == 0;
0; /*
/* jj is
is of
of type
type shortint
shortint unless
unless redefined
redefined */
*/
...
...
endmodule
endmodule
module
module bar;
bar;
logic
logic [3:0]
[3:0] i,o;
i,o;
foo
foo #(.VAR_TYPE(int))
#(.VAR_TYPE(int)) u1
u1 (i,
(i, o);
o); //redefines
//redefines VAR_TYPE
VAR_TYPE to
to an
an int
int
endmodule
endmodule
Stuart Sutherland, Sutherland HDL, Inc. 24
 March 11 - 12, 2002

Sutherland
Assigning Literal Values HD
L

! Verilog-1995/2001
! Cannot fill all bits with 1 without specifying a vector size

! Strings are stored differently than in C

! Cannot assign to multiple array addresses in one

statement
! SystemVerilog enhances assignments of a literal value
! All bits of a vector can be filled with a literal 1-bit value

! `0, `1, `z, `x fill all bits with 0, 1, z or x, respectively

data_bus
data_bus == `1;
`1; //set
//set all
all bits
bits of
of data_bus
data_bus to
to 11

! A string assigned to an array of char types will fill like C

! All or slices of arrays can be assigned values
Stuart Sutherland, Sutherland HDL, Inc. 25
 March 11 - 12, 2002

Sutherland
Type Casting HD
L

! Verilog-1995/2001 does not allow a value to be cast from

one data type to another
! SystemVerilog adds three casting operations
! <type>(<value>) cast a value to any data type,

including user-defined types

int(2.0
int(2.0 ** 3.0)
3.0) //cast
//cast operation
operation result
result to
to int
int

! <size>(<value>) cast a value to any vector size

17(n
17(n -- 2)
2) //cast
//cast operation
operation result
result to
to 17
17 bits
bits wide
wide

! <sign>(<value>) cast a value to signed or unsigned

signed(y)
signed(y) //cast
//cast value
value to
to aa signed
signed value
value

Stuart Sutherland, Sutherland HDL, Inc. 26

 March 11 - 12, 2002

Sutherland
New Operators HD
L

! Verilog-1995/2001 does not have increment and decrement

operators
for
for (i
(i == 0;
0; ii <=
<= 255;
255; ii == ii ++ 1)
1)
...
...

! SystemVerilog adds:
! ++ and -- increment and decrement operators

! +=, -=, *=, /=, %=, &=, ^=, |=, <<=, >>=, <<<=, >>>=

assignment operators
for
for (i
(i == 0;
0; ii <=
<= 255;
255; i++)
i++)
...
...

Stuart Sutherland, Sutherland HDL, Inc. 27

 March 11 - 12, 2002

Sutherland
Unique and Priority Decisions HD
L

! Verilog-1995/2001 defines that ifelseif decisions and

case statements execute with priority encoding
! In simulation, only the first matching branch is executed

! Synthesis will infer parallel execution based on context

! Can override the inference with pragmas such as parallel_case

! Parallel evaluation after synthesis often causes a mismatch in
pre-synthesis and post-synthesis simulation results
! SystemVerilog adds unique and priority keywords:
! Priority-encoded or parallel evaluation to be explicitly

defined for both simulation and synthesis

! Software tools can warn if case or ifelse decisions do

not match the behavior specified

Stuart Sutherland, Sutherland HDL, Inc. 28
 March 11 - 12, 2002

Sutherland
Bottom Testing Loops HD
L

! Verilog-1995/2001 has for, repeat and while loops

! Each loop tests its control value at the beginning of each

pass through the loop

! Can require additional code outside the loop to execute statements
once if the test value is false at the first pass of the loop

! SystemVerilog adds a dowhile loop

! The control is tested at the end of each pass of the loop

! Prevents having to write redundant code outside of the loop

do
do
begin
begin
...
... //several
//several lines
lines of
of code
code
end
end
while
while (count
(count <=
<= max_limit)
max_limit)

Stuart Sutherland, Sutherland HDL, Inc. 29

 March 11 - 12, 2002

Sutherland
Jump Statements HD
L

! Verilog-1995/2001 has the odd-ball disable statement

! Causes a named group of statement to jump to the end of

the group
! Can be used as a form of the C break and continue

statements
! Can be used to exit a task or function prematurely

! SystemVerilog adds the C language jump statements:

! break works like the C break

! continue works like the C continue

! return(<value>) return from a non-void function

! return return from a task or void function

Stuart Sutherland, Sutherland HDL, Inc. 30

 Block Names and Statement March 11 - 12, 2002

Sutherland
Labels HD
L

! Verilog-1995/2001 allows a statement group to have a name

! Identifies all statements within the block

! Creates a new level of model hierarchy

begin:
begin: block1
block1 ...
... end
end

! SystemVerilog adds:
! A name can be specified after the end keyword

! Documents which statement group is being ended

begin:
begin: block2
block2 ...
... end:
end: block2
block2
! Specific statements can be given a label
! Identifies a single statement
! Does not create a new level of hierarchy
shifter:
shifter: for
for (i=15;
(i=15; i>0;
i>0; i--)
i--)
Stuart Sutherland, Sutherland HDL, Inc. 31
 March 11 - 12, 2002

Sutherland
Qualified Sensitivity Lists HD
L

! Verilog-1995/2001 uses sensitivity lists to control when

statements in a procedure are evaluated
! Statements within the procedure must be evaluated every

time the sensitivity list triggers, even if no logic changes

always
always @(data
@(data or
or enable)
enable)
if
if (enable
(enable ==
== 1)
1) out
out <=
<= enable;
enable;

! SystemVerilog adds an iff qualifier to sensitivity lists

! Statements within the procedure are only executed if the

sensitivity list triggers and the qualifier is true

! Can improve simulation efficiency

always
always @(data
@(data or
or enable
enable iff
iff enable
enable ==
== 1)
1)
out
out <=
<= enable;
enable;

Stuart Sutherland, Sutherland HDL, Inc. 32

 March 11 - 12, 2002

Sutherland
Expressions in Sensitivity Lists HD
L

! Verilog-1995/2001 does not define when a sensitivity list

should trigger when there is an expression in the list
! Trigger whenever an operand changes?

! Only trigger when the result changes?

always
always @(
@( (a
(a ** b)
b) )) ...
...

always
always @(
@( memory[address]
memory[address] )) ...
...

! SystemVerilog adds a changed keyword

! Only trigger if the result of the expression changes

always
always @(changed
@(changed (a
(a ** b)
b) )) ...
...

always
always @(changed
@(changed memory[address]
memory[address] )) ...
...

Stuart Sutherland, Sutherland HDL, Inc. 33

 March 11 - 12, 2002

Sutherland
Specialized Procedural Blocks HD
L

! Verilog-1995/2001 infers combinational, sequential and

latched logic from an always block based on context
! The designer cannot specify the intended behavior

! Different products may infer different behavior

! SystemVerilog adds three new procedures:

always_comb always_ff always_latch
! Specifies the intended behavior of the procedure
! Tools can issue warnings if the inferred behavior is
different than the intended behavior

Stuart Sutherland, Sutherland HDL, Inc. 34

 March 11 - 12, 2002

Sutherland
Dynamic Processes HD
L

! Verilog-1995/2001 only supports static statement groups

! All statements in the flow must have executed before

reaching the end or join

fork
fork Both
Both tasks
tasks run
run in
in parallel
parallel
send_packet_task(1,255,0);
send_packet_task(1,255,0);
send_packet_task(7,128,5);
send_packet_task(7,128,5);
join
join Wont
Wont join
join until
until both
both tasks
tasks finish
finish

! SystemVerilog adds dynamic process statements

! Each statement is a separate thread

! Statements do not need to complete before the end or join

is reached
begin
begin Both
Both tasks
tasks run
run in
in parallel
parallel
process
process send_packet_task(1,255,0);
send_packet_task(1,255,0);
process
process send_packet_task(7,128,5);
send_packet_task(7,128,5); Will
Will end
end without
without waiting
waiting
end
end for
for tasks
tasks to
to finish
finish
Stuart Sutherland, Sutherland HDL, Inc. 35
 Static and Automatic March 11 - 12, 2002

Sutherland
Task/Function Enhancements HD
L

! Verilog-1995 only supports static tasks and functions

! All local storage is shared by all calls

! Re-entrant tasks and recursive functions do not work

! Verilog-2001 adds automatic tasks and functions

! All local storage is stacked

! Supports re-entrant tasks and recursive functions

! SystemVerilog adds:
! Static storage in an automatic task or function

! Automatic storage in a static task or function

! Uses static and automatic declarations, as in C

Stuart Sutherland, Sutherland HDL, Inc. 36

 Multiple Statements March 11 - 12, 2002

Sutherland
in Tasks and Functions HD
L

! Verilog-1995/2001 only allows a single statement or a single

statement group within a task or function
! Groups are formed with beginend or forkjoin

! SystemVerilog allows any number of statements within a task

or function
! beginend or forkjoin no longer required

! Ungrouped statements execute in sequence, as if enclosed

in a beginend block

Stuart Sutherland, Sutherland HDL, Inc. 37

 Continuous Assignment March 11 - 12, 2002

Sutherland
Enhancements HD
L

! Verilog-1995/2001 only allows net data types to be used on

the left-hand side of continuous assignments statements

! SystemVerilog allows most data types to be used

! Variable types can only be driven by a single continuous

assignments
! The reg variable type cannot be used

Stuart Sutherland, Sutherland HDL, Inc. 38

 March 11 - 12, 2002

Sutherland
State Machine Modeling HD
L

! Verilog-1995/2001 does not have any special constructs to

model state machines
! State machines are inferred from the RTL coding style

! SystemVerilog adds special constructs for modeling state

machines at a more abstract level
! Special state variable type

! Enumerated types

! Special transition statement and transition operator

! Defines changes from one state to another

! Eliminates need for intermediate next_state variables

Stuart Sutherland, Sutherland HDL, Inc. 39

 March 11 - 12, 2002

Sutherland
Assertions HD
L

! Verilog-1995/2001 does not provide an assertion construct

! Model checking must be done by hard-coded logic

! Assertion libraries, such as the OVL library, add assertion checks in

the form of module instances
! Some tools add assertion checks using the Verilog PLI

! SystemVerilog adds assertion syntax and semantics

! Assertion information is built into the language

! No special modules or PLI calls are needed

Stuart Sutherland, Sutherland HDL, Inc. 40

 March 11 - 12, 2002

Sutherland
Status of SystemVerilog HD
L

! SystemVerilog will ship in June 2002

! The Accellera HDL+ committee has completed 90+% of the

SystemVerilog Language Reference Manual

! Still pending (as of March 2002):

! Fine tune new state machine modeling constructs

! Fine time assertions specifications

! Discuss deprecating certain Verilog constructs

(e.g. defparam)
! Review for accuracy

Stuart Sutherland, Sutherland HDL, Inc. 41

 March 11 - 12, 2002

Sutherland
Plans for SystemVerilog HD
L

! June 2002 The first release of the SystemVerilog standard

! Co-design already supports SystemVerilog for simulation

! Get-2-Chip already supports much of SystemVerilog for

synthesis
! Accellera will turn over SystemVerilog to the IEEE 1364
Verilog standards group
! Accellera hopes the IEEE will use SystemVerilog as a basis

for the next version of the Verilog

! Accellera will continue to review design and verification

needs, and define new versions of SystemVerilog as required.

Stuart Sutherland, Sutherland HDL, Inc. 42

 March 11 - 12, 2002

Sutherland
Conclusion HD
L

! SystemVerilog adds a large number of major enhancements

to the Verilog-2001 standard

! Accelleras HDL+ technical committee is developing the

standard
! No red tape, as in the IEEE

! A working standard can be done in less than 1 year

instead of 4 or 5 years

! SystemVerilog should become the next generation of the

IEEE 1364 Verilog standard

Stuart Sutherland, Sutherland HDL, Inc. 43

 March 11 - 12, 2002

Sutherland
HD
L

Any Questions?

A
A copy
copy of
of this
this presentation
presentation will
will be
be available
available at
at
www.sutherland-hdl.com
www.sutherland-hdl.com

Stuart Sutherland, Sutherland HDL, Inc. 44