Encoders/Decoders
Overview
Design Procedure
Code Converters
Binary Decoders
Expansion
Circuit implementation
Binary Encoders
Priority Encoders
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Combinational Circuit Design
Design of a combinational circuit is the
development of a circuit from a description
of its function.
Starts with a problem specification and
produces a logic diagram or set of boolean
equations that represent the circuit.
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Design Procedure
1. Determine the required number of inputs and
outputs and assign variables to them.
2. Derive the truth table that defines the required
relationship between inputs and outputs.
3. Obtain and simplify the Boolean function (K-
maps, algebraic manipulation, CAD tools, ).
Consider any design constraints (area, delay,
power, available libraries, etc).
4. Draw the logic diagram.
5. Verify the correctness of the design.
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Design Example
Design a combinational circuit with 4
inputs that generates a 1 when the # of 1s
equals the # of 0s. Use only 2-input NOR
gates
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More Examples - Code
Converters
Code Converters transform/convert
information from one code to another:
BCD-to-Excess-3 Code Converter
Useful in some cases for digital arithmetic
BCD-to-Seven-Segment Converter
Used to display numeric info on 7 segment
displays
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BCD-to-Excess-3 Code
Converter
Design a circuit that converts a binary-coded-
decimal (BCD) codeword to its corresponding
excess-3 codeword.
Excess-3 code: Given a decimal digit n, its
corresponding excess-3 codeword (n+3)2
Example:
n=5 n+3=8 1000excess-3
n=0 n+3=3 0011excess-3
We need 4 input variables (A,B,C,D) and 4
output functions W(A,B,C,D), X(A,B,C,D),
Y(A,B,C,D), and Z(A,B,C,D).
Chapter 3-ii: Combinational 7
Logic Design (3.4 - 3.6)
BCD-to-Excess-3 Converter
(cont.)
The truth table relating the input and output variables is shown below.
Note that the outputs for inputs 1010 through 1111 are don't cares (not
shown here).
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Maps for BCD-to-Excess-3 Code Converter
The K-
K-maps for are constructed using the don't care terms
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Logic Design (3.4 - 3.6)
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BCD-to-Excess-3 Converter
(cont.)
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Logic Design (3.4 - 3.6)
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Another Code Converter Example:
BCD-to-Seven-Segment Converter
Seven-segment display:
7 LEDs (light emitting diodes), each one
controlled by an input a
1 means on, 0 means off
f b
Display digit 3? g
Set a, b, c, d, g to 1
Set e, f to 0 e c
d
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BCD-to-Seven-Segment
Converter
Input is a 4-bit BCD code 4 inputs (w, x,
y, z).
Output is a 7-bit code (a,b,c,d,e,f,g) that
allows for the decimal equivalent to be
displayed. a
Example: f g b
Input: 0000BCD
Output: 1111110 e c
(a=b=c=d=e=f=1, g=0)
d
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BCD-to-Seven-Segment (cont.)
Truth Table
Digit wxyz abcdefg Digit wxyz abcdefg
0 0000 1111110 8 1000 1111111
1 0001 0110000 9 1001 111X011
2 0010 1101101 1010 XXXXXXX
3 0011 1111001 1011 XXXXXXX
4 0100 0110011 1100 XXXXXXX
5 0101 1011011 1101 XXXXXXX
6 0110 X011111 1110 XXXXXXX
7 0111 11100X0 1111 XXXXXXX
??
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Decoders
A combinational circuit that converts
binary information from n coded inputs to a
maximum 2n decoded outputs
n-to- 2n decoder
n-to-m decoder, m 2n
Examples: BCD-to-7-segment decoder,
where n=4 and m=7
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Decoders (cont.)
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2-to-4 Decoder
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2-to-4 Active Low Decoder
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3-to-8 Decoder
address
data
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3-to-8 Decoder (cont.)
Three inputs, A0, A1, A2, are decoded into eight
outputs, D0 through D7
Each output Di represents one of the minterms
of the 3 input variables.
Di = 1 when the binary number A2A1A0 = i
Shorthand: Di = mi
The output variables are mutually exclusive;
exactly one output has the value 1 at any time,
and the other seven are 0.
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Implementing Boolean functions
using decoders
Any combinational circuit can be constructed using
decoders and OR gates! Why?
Here is an example:
Implement a full adder circuit with a decoder and
two OR gates.
Recall full adder equations, and let X, Y, and Z be
the inputs:
S(X,Y,Z) = X+Y+Z = m(1,2,4,7)
C (X,Y,Z) = m(3, 5, 6, 7).
Since there are 3 inputs and a total of 8 minterms,
we need a 3-to-8 decoder.
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Logic Design (3.4 - 3.6)
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Implementing a Binary Adder
Using a Decoder
S(X,Y,Z) = m(1,2,4,7)
C(X,Y,Z) = m(3,5,6,7)
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Decoder Expansions
Larger decoders can be constructed using
a number of smaller ones.
-> HIERARCHICAL design!
Example:
A 6-to-64 decoder can be designed using
four 4-to-16 and one 2-to-4 decoders.
How? (Hint: Use the 2-to-4 decoder to
generate the enable signals to the four 4-
to-16 decoders).
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3-to-8 decoder using two 2-to-4
decoders
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Logic Design (3.4 - 3.6)
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4-input tree decoder
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Encoders
An encoder is a digital circuit that performs
the inverse operation of a decoder. An
encoder has 2n input lines and n output
lines.
The output lines generate the binary
equivalent of the input line whose value is
1.
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Logic Design (3.4 - 3.6)
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Encoders (cont.)
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Logic Design (3.4 - 3.6)
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Encoder Example
Example: 8-to-3 binary encoder (octal-to-binary)
A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7
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Encoder Example (cont.)
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Simple Encoder Design Issues
There are two ambiguities associated with the
design of a simple encoder:
1. Only one input can be active at any given time. If
two inputs are active simultaneously, the output
produces an undefined combination (for example, if
D3 and D6 are 1 simultaneously, the output of the
encoder will be 111.
2. An output with all 0's can be generated when all the
inputs are 0's,or when D0 is equal to 1.
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Priority Encoders
Solves the ambiguities mentioned above.
Multiple asserted inputs are allowed; one
has priority over all others.
Separate indication of no asserted inputs.
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Logic Design (3.4 - 3.6)
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Example: 4
4--to
to--2 Priority Encoder
Truth Table
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Logic Design (3.4 - 3.6)
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4-to-2 Priority Encoder (cont.)
The operation of the priority encoder is
such that:
If two or more inputs are equal to 1 at the
same time, the input in the highest-
numbered position will take precedence.
A valid output indicator, designated by
V, is set to 1 only when one or more inputs
are equal to 1. V = D3 + D2 + D1 + D0 by
inspection.
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Example: 4-
4-to
to-
-2 Priority Encoder
K-Maps
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Logic Design (3.4 - 3.6)
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Example: 4
4--to
to--2 Priority Encoder
Logic Diagram
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Logic Design (3.4 - 3.6)
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8-to-3 Priority Encoder
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A Matrix of switches = Keypad
C0 C1 C2 C3
1 2 3 F R0
4 5 6 E R1
7 8 9 D R2
0 A B C R3
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Logic Design (3.4 - 3.6)
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Keypad Decoder IC - Encoder
COL.
4-bit
4-bit
Binary
1 2 3 F
(encoded)
4 5 6 E ROW
4-bit
7 8 9 D
0 A B C
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Logic Design (3.4 - 3.6)
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Priority Interrupt
Encoder Schematic
Interrupting Interrupt Microprocessor
Devices Encoder
Device A
Device B Req(1:0)
Device C
Device D
IntRq
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Logic Design (3.4 - 3.6)
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Priority Encoding -
Interrupt Requests
Interrupting Device
A B C D Req (1:0) IntRq
0 0 0 0 00 0
0 0 0 1 00 1
0 0 1 0 01 1
0 0 1 1 01 1
0 1 0 0 10 1
Exercise: Complete this table?
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Logic Design (3.4 - 3.6)
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