ECE 111-Digital

Systems Lab

Introduction to VHDL

Stelios Neophytou
 VHDL

VHDL is a hardware description language used to
specify logic designs.

Sponsored (early 80s) by IEEE and US DoD.

Features:

Hierarchical designs

Interface and behavior specified precisely (and
separately)

Algorithmic or hardware-oriented behavior specifications

Concurrency, timing, clocking can be modeled;
design can be simulated accurately.

12-Apr-10 Introduction to VHDL 2

 VHDL Model Components

A complete VHDL component
description requires a VHDL entity and
a VHDL architecture:

The entity defines a components interface
(name, inputs, outputs).

The architecture defines a components
function.

Several alternative architectures may

be developed for use with the same
entity.
12-Apr-10 Introduction to VHDL 3
 Simple example: Entity
entity My_Component is -- My_Component: name of item
port (X,Y: in BIT; -- interface specification
Z: out BIT);
end My_Component;

port statement
defines inputs
and outputs X
My_Component Z
Comments Y
VHDL keywords
Identifiers
Port Mode
Data Type

12-Apr-10 Introduction to VHDL 4

 Simple example: Architecture
entity My_Component is -- My_Component: name of item
Port (X,Y: in BIT; -- interface specification
Z: out BIT);
end My_Component;

Architecture My_Component_Arch of My_Component is

begin
Z <= 1 when X=1 and Y=0 else 0;
end My_Component_Arch;

Comments
VHDL keywords
Corresponding
Identifiers Z = XY
entity
Port Mode
Data Type
12-Apr-10 Introduction to VHDL 5
 VHDL Language elements

Comments: start with --, go to end of line

Keywords (reserved words): entity, port, is, in,
out, end, architecture, begin, end, when, else, etc.

Identifiers (user-defined variables)

12-Apr-10 Introduction to VHDL 6

 Identifiers

May contain A-Z, a-z, 0-9, _

Must start with letter

May not end with _

May not include two consecutive _

VHDL is case insensitive

Sel, sel and SEL refer to same object

12-Apr-10 Introduction to VHDL 7

 Identifier Examples

A2G

valid

8bit_counter

invalid -- starts with number

_NewValue

invalid -- starts with _

first#

invalid -- illegal character

12-Apr-10 Introduction to VHDL 8

 VHDL Data Objects

Constant

Variable

Signal

File*

* Not supported by synthesis tools

12-Apr-10 Introduction to VHDL 9
 Characters and Strings

Characters

A, 0, 1, $, x, *

Strings

string of characters

00101101

0X110ZZ1

Bit Strings

B011111010110

O3726

X7D6

12-Apr-10 Introduction to VHDL 10

 VHDL Data Types

Scalar

Integer

Enumerated

Real (floating point)*

Composite

Array

Record

Access (pointers)*

* Not supported by synthesis tools

12-Apr-10 Introduction to VHDL 11
 Scalar Data Types

Integer:

Minimum range for any implementation as defined by
standard: - 2,147,483,647 to 2,147,483,647

Example: assignments to a variable of type integer :

ARCHITECTURE
ARCHITECTURE test_int
test_int OF
OF test
test IS
IS
BEGIN
BEGIN
PROCESS
PROCESS (X)
(X)
VARIABLE
VARIABLE a:a: INTEGER;
INTEGER;
BEGIN
BEGIN
aa :=
:= 1;
1; --
-- OK
OK
aa :=
:= -1;
-1; --
-- OK
OK
aa :=
:= 1.0;
1.0; --
-- illegal
illegal
END
END PROCESS;
PROCESS;
END
END test_int;
test_int;

12-Apr-10 Introduction to VHDL 12

 Scalar Data Type (cont.)

Integer (cont.):

We can also define range of integers.

Examples:
type CountValue is range 0 to 15;
type Twenties is range 20 to 29;
type Thirties is range 39 downto 30;

12-Apr-10 Introduction to VHDL 13

 Scalar Data Types (cont.)

Enumerated:

Userspecifies list of possible values

Example declaration and usage of enumerated data type :

TYPE
TYPE binary
binary ISIS (( ON,
ON, OFF
OFF );
);
...
... some
some statements
statements ......
ARCHITECTURE
ARCHITECTURE test_enum
test_enum OF OF test
test IS
IS
BEGIN
BEGIN
PROCESS
PROCESS (X)
(X)
VARIABLE
VARIABLE a:a: binary;
binary;
BEGIN
BEGIN
aa :=
:= ON;
ON; ---- OK
OK
...
... more
more statements
statements ... ...
aa :=
:= OFF;
OFF; ---- OK
OK
...
... more
more statements
statements ... ...
END
END PROCESS;
PROCESS;
END
END test_enum;
test_enum;
12-Apr-10 Introduction to VHDL 14
 Booleans
type boolean is (false, true);
variable A,B,C: boolean;
C := not A
C := A and B
C := A or B VHDL Object
C := A nand B
C := A nor B
C := A xor B Assignment operator
C := A xnor B for variables

12-Apr-10 Introduction to VHDL 15

 Bits

type bit is (0, 1);

signal x,y,z: bit;
x <= 0;
y <= 1;
VHDL Object
z <= x and y;
Assignment operator
for signals

12-Apr-10 Introduction to VHDL 16

 Standard Logic
type std_logic is ( U, -- Uninitialized
X -- Forcing unknown
0 -- Forcing zero
1 ); -- Forcing one

std_logic is part of the ieee package

Packages: precompiled VHDL code stored in a
directory referred to as library
library
library IEEE;
IEEE;
use Must be included in your
useIEEE.std_logic_1164.all;
IEEE.std_logic_1164.all;
source code before declaring
std_logic data types
12-Apr-10 Introduction to VHDL 17
 Composite Data Types

Array:

Used to group elements of the same type into a single VHDL
object

Range may be unconstrained in declaration

Range would then be constrained when array is used

Example declaration for one-dimensional array (vector) :

TYPE
TYPE data_bus
data_bus IS
IS ARRAY(0
ARRAY(0 TO
TO 31)
31) OF
OF BIT;
BIT;

0 ... element indices... 31

0 ...array values... 1

VARIABLE
VARIABLE XX :: data_bus;
data_bus;
VARIABLE
VARIABLE YY :: BIT;
BIT;

YY :=
:= X(12);
X(12); --
-- YY gets
gets value
value of
of element
element at
at index
index 12
12
12-Apr-10 Introduction to VHDL 18
 VHDL Architecture Structure
architecture name_arch of name is
Signal assignments
begin
Concurrent statements Processes contain sequential
statements, but execute
Process 1 concurrently within the
architecture body
Concurrent statements

Process 2

Concurrent statements
end name_arch;
12-Apr-10 Introduction to VHDL 19
 VHDL Process
P1: process (<sensitivity list>)
<variable declarations>
begin
<sequential statements>
end process P1;
Within a process:
Variables are assigned using :=
Optional process label and are updated immediately.
Signals are assigned using <=
and are updated at the end of
the process.

12-Apr-10 Introduction to VHDL 20

Signals Vs Variables in a Process
Let A, B, and C be integer data types with
A=1, B=5, and C=10.
A, B, C: signals A, B, C: variables
begin process begin process

B <= A; B := A;
C <= B; C := B;

end process; end process;
B = 1 and C = 5 B = 1 and C = 1
( uses original value ( uses new value
B (=5) when of B (=1) when
computing C ) computing C )

12-Apr-10
12-Apr-10 Introduction to VHDL 21
 If-Then-Else statement
[ if_label:]
if boolean_expression then
{ sequential_statement; }
{ elsif boolean_expression then
{ sequential_statement; } }
[ else
{ sequential_statement; } ]
end if [ if_label ];

Notation:
[ ] -- optional
{ } -- repeatable

12-Apr-10
12-Apr-10 Introduction to VHDL 22
 CASE statement

[ case_label:]
case expression is
{ when choices =>
{ sequential statement; }
}
end case [case_label];

12-Apr-10
12-Apr-10 Introduction to VHDL 23
 2-to-4 decoder in VHDL:
Gate-level diagram

12-Apr-10 Introduction to VHDL 24

 2-to-4 decoder in VHDL: Interface
-- 2-to-4 Line Decoder: Structural VHDL Description
-- (See Figure 3-13 for logic diagram)
Import library
library ieee, primitives;
functions

use ieee.std_logic_1164.all, primitives.all;

entity decoder_2_to_4 is Inputs & outputs

port(E_n, A0, A1: in std_logic;
D0_n, D1_n, D2_n, D3_n: out std_logic);

end decoder_2_to_4;

12-Apr-10 Introduction to VHDL 25

 2-to-4 decoder in VHDL:
Structural Architecture
architecture structural_1 of decoder_2_to_4 is
component NOT1
port(in1: in std_logic;
out1: out std_logic); Declare
end component; available
component NAND3 components
port(in1, in2, in3: in std_logic;
out1: out std_logic);
end component;

12-Apr-10 Introduction to VHDL 26

 2-to-4 decoder in VHDL:
Structural Architecture (cont.)
signal E, A0_n, A1_n: std_logic; Local signals
begin
g0: NOT1 port map (in1 => A0, out1 => A0_n);
g1: NOT1 port map (in1 => A1, out1 => A1_n);
g2: NOT1 port map (in1 => E_n, out1 => E);
g2: NAND3 port map (in1 => A0_n, in2 => A1_n,
in3 => E, out1 => D0);
g3: NAND3 port map (in1 => A0, in2 => A1_n,
in3 => E, out1 => D1);
g4: NAND3 port map (in1 => A0_n, in2 => A1,
in3 => E, out1 => D2);
g5: NAND3 port map (in1 => A0, in2 => A1,
in3 => E, out1 => D3);
end structural_1;

12-Apr-10 Introduction to VHDL 27

 Another example:
An 4-line 4 x 1 multiplexer

Sel y
a(3:0) 00 a
8-line
b(3 :0) 01 b
4x1 y(3 :0)
c(3 :0) MUX 10 c
d(3 :0) 11 d

sel(1:0)

12-Apr-10 Introduction to VHDL 30

 An 4-line 4 x 1 multiplexer:
Entity Declaration
library IEEE;
use IEEE.std_logic_1164.all;

entity mux4g is
port (
a: in STD_LOGIC_VECTOR (3 downto 0);
b: in STD_LOGIC_VECTOR (3 downto 0);
c: in STD_LOGIC_VECTOR (3 downto 0);
d: in STD_LOGIC_VECTOR (3 downto 0);
sel: in STD_LOGIC_VECTOR (1 downto 0);
y: out STD_LOGIC_VECTOR (3 downto 0)
);
end mux4g;

12-Apr-10 Introduction to VHDL 31

 An 4-line 4 x 1 multiplexer:
Dataflow architecture declaration
using a CASE statement
architecture mux4g_arch of mux4g is
begin
process (sel, a, b, c, d) Sel y
begin
00 a
case sel is
when "00" => y <= a; 01 b
when "01" => y <= b; 10 c
when "10" => y <= c; 11 d
when others => y <= d;
end case;
end process;
end mux4g_arch; Must include ALL posibilities
in case statement

12-Apr-10 Introduction to VHDL 32

 4-bit adder:
Entity declaration

-- 4-bit Adder: Behavioral Description

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity adder_4_b is
port(B, A : in std_logic_vector(3 downto 0);
C0 : in std_logic;
S : out std_logic_vector(3 downto 0);
C4: out std_logic);
end adder_4_b;

12-Apr-10 Introduction to VHDL 40

 4-bit adder:
Behavioral Arch. Specification
architecture behavioral of adder_4_b is

signal sum : std_logic_vector(4 downto 0);

begin
sum <= ('0' & A) + ('0' & B) + ("0000" & C0);
C4 <= sum(4);
S <= sum(3 downto 0);
end behavioral;

0A3A2A1A0 0B3B2B1B0 0000C0

12-Apr-10 Introduction to VHDL 41
 Structural: 4-bit adder
library ieee;
use ieee.std_logic_1164.all;

entity adder4 is - - s = x+y

port (Cin: in std_logic;
x3,x2,x1,x0: in std_logic;
y3,y2,y1,y0: in std_logic;
s3,s2,s1,s0: out std_logic;
Cout: out std_logic );
end adder4;

12-Apr-10 Introduction to VHDL 45

 Structural: 4-bit adder (cont.)
architecture structural of adder4 is
signal c1,c2,c3: std_logic;
component fulladd
port (Cin,x,y: in std_logic;
Same order as
s,Cout: out std_logic); declaration
end component;

begin
stage0: fulladd port map (Cin,x0,y0,s0,c1);
stage1: fulladd port map (c1,x1,y1,s1,c2);
Custom order
stage2: fulladd port map (c2,x2,y2,s2,c3);
stage3: fulladd port map (Cin=>c3,Cout=cout,x=>x3,y=>y3,s=>s3);
end structural;

12-Apr-10 Introduction to VHDL 46

 Decoder
library ieee;
use ieee.std_logic_1164.all;

entity dec2to4 is
port (w: in std_logic_vector(1 downto 0);
e: in std_logic;
y: out std_logic_vector(0 to 3));
end dec2to4;

12-Apr-10 Introduction to VHDL 48

 Decoder (cont.)
architecture behavioral of dec2to4 is
signal ew: std_logic_vector(2 downto 0);
begin
ew <= e & w; -- concatenation!
with ew select
y <= 1000 when 100,
0100 when 101,
0010 when 110,
0001 when 111,
0000 when others;
end behavioral;

12-Apr-10 Introduction to VHDL 49

 Remember the
Structural Architecture ?
architecture structural_1 of decoder_2_to_4 is
component NOT1
port(in1: in std_logic;
out1: out std_logic); Declare
end component; available
component NAND3 components
port(in1, in2, in3: in std_logic;
out1: out std_logic);
end component;

12-Apr-10 Introduction to VHDL 50

 Remember the
Structural Architecture ?
signal E, A0_n, A1_n: std_logic; Local signals
begin
g0: NOT1 port map (in1 => A0, out1 => A0_n);
g1: NOT1 port map (in1 => A1, out1 => A1_n);
g2: NOT1 port map (in1 => E_n, out1 => E);
g2: NAND3 port map (in1 => A0_n, in2 => A1_n,
in3 => E, out1 => D0);
g3: NAND3 port map (in1 => A0, in2 => A1_n,
in3 => E, out1 => D1);
g4: NAND3 port map (in1 => A0_n, in2 => A1,
in3 => E, out1 => D2);
g5: NAND3 port map (in1 => A0, in2 => A1,
in3 => E, out1 => D3);
end structural_1;

12-Apr-10 Introduction to VHDL 51