Section 3.

Exception Processing Outline

Basic Exception Concepts
Nested Vector Interrupt Controller
Registers and Vector table
NVIC and Its Functions Example module
Timer Module

1 2

Basic Concepts of Interrupt Processing Necessary Procedure of an Interrupt Process

A variety of unexpected events in a computer system Interrupt requester CPU

I/O events, error conditions, network events etc Recognition of an interrupt request:
These events are handled by interrupt processing Interrupt requester makes an interrupt request
Speed disparity of various devices in a computer CPU recognizes the interrupt request
Allow multiple and parallel processing of tasks Prioritization: Determining whether granting the request or not
An analogous example: A reading process Requester provides its priority
Phone rings-- Recognition of an event CPU compares it with the priority of its current process
Answer the phone or not? Priority Context saving to be able to come back after interrupt
Book mark the page store context Program counter marks where interrupt happened
Answer the phone handler Status register and possible other necessary context information
Continue the reading process after phone conversation done

3 4

NVIC (Nested Vector Interrupt Controller) SoC interconnect diagram

Low latency Interrupt
Any module capable of generating an interrupt will depend
12 cycles to PUSH on ISR entry
on NVIC operation
12 cycles to POP on ISR exit
NMI can be generated from:
Up to 120 interrupt sources
Includes 16 ARM core specific exceptions
External pin (must configure the MUX)
The remaining are modules specific CoreSight Embedded Trace Buffer (ETB)
Arm supports 0-255 priority levels, K-70 support 16
priority levels, all fully programmable (0 highest)
Reset, NMI and Hard Fault have predefined priority
Change Interrupt Priority dynamically
Relocable vector table

5 6
 Exceptions and Interrupts NVIC

7 8

Wake-up Sources Sequence of register setups

The steps for enabling an interrupt on NVIC:
1. Enable the peripheral to be used
2. Set the proper bit on the NVICSERx to enable the interrupt on
the NVIC
3. Clear any pending interrupt by writing to the NVICCPRx to
avoid any spurious interrupt
4. Configure the interrupt priority by writing to the NVICIPxx
5. Write the ISR
6. Enable global interrupts

9 10

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31 0

ACTIVE bits

Chapter 3 Chip Configuration

Example Registers: NVIC_ISER0-7 Example Registers

9:;<( !=>,%-12,;/',:44/3&?(&'4
Interrupts
Module
ARM Cortex-M4

1/'4 @:?( A*&.'/7&

PPB Nested Vectored
Module
core

Interrupt Controller
OFPH-Q *(!'&M '54#00:;4$8742<#$GB813H
(NVIC) -$R$254#00:;4$5E4$8742<#
Module

Interrupt Priority Registers

P$R$254#00:;4$8742<#=

Figure 3-2. NVIC configuration

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The NVIC_IPR0-NVIC_IPR59
!"#"5 registers
Table 3-2. Reference links to related
%&'())*+',6)/7)/'8,2(3/4'()4
informationprovide an 8-bit

Bits Name priority field for each interrupt and each register holds four
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Related module Reference
#87"$0#1234#0$"EB63$GE:0$;02E024@$G2#B63=$!"#3#$0#1234#03$80#$A@4#.877#332AB#=$>##$4"#$0#1234#0$
Full description Nested Vectored http://www.arm.com
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priority fields. These registers are byte-accessible.
Interrupt Controller

[31:0] SETENA
3"E95H (NVIC)
System memory 31
map 24 23 16 15 System memory map
8 7 0

Function Clocking
IPR59

Power management
PRI_239 PRI_238 PRI_237 Clock distribution
PRI_236

Power management
...

...

Interrupt set-enable bits. Private Peripheral Bus

(PPB)
IPRn
ARM Cortex-M4 core

PRI_4n+3 PRI_4n+2 PRI_4n+1

ARM Cortex-M4 core

PRI_4n

Write: 0 = no effect
...

...

1 = enable interrupt. 3.2.2.1 IPR0Interrupt

PRI_3
priority levels
PRI_2 PRI_1 PRI_0

This device supports 16 priority levels for interrupts. Therefore, in the NVIC each source
9:;<( !=B,%62,;/',:44/3&?(&'4
Read: 0 = interrupt disabled in the
1/'4,
K70
IPR supports
@:?(
16 priority
registers contains 4 bits. levels
A*&.'/7&
for interrupts.
For example, Therefore,
IPR0 is shown below: in the NVIC each
source in the IPR registers contains 4 bits. For example, IPR0 is shown below:
1 = interrupt enabled. OFPHDCQ$

ODFHPTQ$
31
I02E024@N$A@4#$EGG3#4$F$
30 29 28 27 26
I02E024@N$A@4#$EGG3#4$D
25
M87"$2?;B#?#54842E5.6#G25#6$;02E024@$G2#B6$785$"EB6$8$;02E024@$<8B:#N$-.DJJ=$!"#$
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
BE9#0$4"#$<8B:#N$4"#$10#84#0$4"#$;02E024@$EG$4"#$7E00#3;E56251$254#00:;4=$,#1234#0$
;02E024@$<8B:#$G2#B63$80#$#21"4$A243$926#N$856$5E5.2?;B#?#54#6$BE9.E06#0$A243$0#86$83$
5 4 3 2 1 0

R 0 0 0 0 0
S#0E$856$215E0#$9024#3= 0 0 0 0 0 0 0 0 0 0 0
OPJHLQ$ IRQ3
I02E024@N$A@4#$EGG3#4$P IRQ2 IRQ1 IRQ0
W
O/H-Q$ I02E024@N$A@4#$EGG3#4$-

>##$!""#$$%&'()*#(+,-)#./01(234+(-#'%$)#-$(5$%&'(+0646$E5$;81# C.C$GE0$?E0#$25GE0?842E5$
8AE:4$4"#$877#33$4E$4"#$254#00:;4$;02E024@$8008@N$9"27"$;0E<26#3$4"#$3EG4980#$<2#9$EG$4"#$254#00:;4$
11 12
3.2.2.2 ;02E0242#3=
Non-maskable interrupt
The non-maskable interrupt request to the NVIC is controlled by the external NMI signal.
!"#$%&'$())*! !"-2#,3.$*4 5676*89(:*800*#,3.$1*#%1%#;%<: +,-
'%./.0.( The pin the NMI signal is multiplexed
=">'!">?,<%>$,/0 on, must be configured for the NMI function to
generate the non-maskable interrupt request.

3.2.2.3 Interrupt channel assignments

The interrupt source assignments are defined in the following table.

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Freescale Semiconductor, Inc. Preliminary 85
 Core modules

Vector number the value stored on the stack when an interrupt is serviced.
IRQ number non-core interrupt source count, which is the vector number minus
16.
The IRQ number is used within ARM's NVIC documentation.

Picking up a IPR Address Vector

Table 3-4. Interrupt vector assignments
IRQ1 NVIC
non-IPR
NVIC
IPR
Source module Source description

register register

Find the IPR number and byte offset for interrupt m as number number
2 3

follows:
ARM Core System Handler Vectors
0x0000_0000 0 ARM core Initial Stack Pointer
0x0000_0004 1 ARM core Initial Program Counter

the corresponding IPR number, n is given by n = m 0x0000_0008 2 ARM core Non-maskable Interrupt (NMI)
0x0000_000C 3 ARM core Hard Fault

DIV 4 0x0000_0010 4 ARM core MemManage Fault

0x0000_0014 5 ARM core Bus Fault

the byte offset of the required Priority field in this 0x0000_0018

0x0000_001C
6
7






ARM core

Usage Fault

register is m MOD 4, where: 0x0000_0020

0x0000_0024
8
9

byte offset 0 refers to register bits[7:0] 0x0000_0028 10

0x0000_002C 11 ARM core Supervisor call (SVCall)
byte offset 1 refers to register bits[15:8] 0x0000_0030 12 ARM core Debug Monitor

byte offset 2 refers to register bits[23:16] 0x0000_0034 13

0x0000_0038 14 ARM core Pendable request for system service
byte offset 3 refers to register bits[31:24]. (PendableSrvReq)
0x0000_003C 15 ARM core System tick timer (SysTick)
Non-Core Vectors
0x0000_0040 16 0 0 0 DMA DMA channel 0, 16 transfer complete
0x0000_0044 17 1 0 0 DMA DMA channel 1, 17 transfer complete
0x0000_0048 18 2 0 0 DMA DMA channel 2, 18 transfer complete
13 Chapter 3 Chip Configuration 14
0x0000_004C 19 3 0 0 DMA DMA channel 3, 19 transfer complete
Table 3-4. Interrupt vector assignments (continued) 0x0000_0050 20 4 0 1 DMA DMA channel 4, 20 transfer complete
Address Vector IRQ1 NVIC NVIC Source module Source description 0x0000_0054 21 5 0 1 DMA DMA channel 5, 21 transfer complete
non-IPR IPR
register register 0x0000_0058 22 6 0 1 DMA DMA channel 6, 22 transfer complete
number number 0x0000_005C 23 7 0 1 DMA DMA channel 7, 23 transfer complete
2 3
0x0000_0060 24 8 0 2 DMA DMA channel 8, 24 transfer complete
0x0000_0134 77 61 1 15 CMP2
Table continues on the next page...
0x0000_0138 78 62 1 15 FTM0 Single interrupt vector for all sources
0x0000_013C 79 63 1 15 FTM1 Single interrupt vector for all sources
K70 Sub-Family Reference Manual, Rev. 2, Dec 2011
0x0000_0140 80 64 2 16 FTM2 Single interrupt vector for all sources
86 Preliminary Freescale Semiconductor, Inc.
0x0000_0144 81 65 2 16 CMT
0x0000_0148 82 66 2 16 RTC Alarm interrupt
0x0000_014C 83 67 2 16 RTC Seconds interrupt
0x0000_0150 84 68 2 17 PIT Channel 0
0x0000_0154 85 69 2 17 PIT Channel 1
0x0000_0158 86 70 2 17 PIT Channel 2
0x0000_015C
0x0000_0160
0x0000_0164
87
88
89
71
72
73
2
2
2
17
18
18
PIT
PDB
USB OTG
Channel 3


Sample code Explained
0x0000_0168 90 74 2 18 USB Charger

0x0000_016C 91 75 2 18
Detect
Ethernet MAC IEEE 1588 Timer Interrupt
Set up the LPT interrupt:
0x0000_0170 92 76 2 19 Ethernet MAC Transmit interrupt Locate the interrupt vector that you want on the Vector Table list
0x0000_0174 93 77 2 19 Ethernet MAC Receive interrupt
from the Kinetis device used
0x0000_0178 94 78 2 19 Ethernet MAC Error and miscellaneous interrupt
0x0000_017C 95 79 2 19
0x0000_0180 96 80 2 20 SDHC
0x0000_0184 97 81 2 20 DAC0
0x0000_0188 98 82 2 20 DAC1
0x0000_018C 99 83 2 20 TSI Single interrupt vector for all sources
0x0000_0190 100 84 2 21 MCG
0x0000_0194 101 85 2 21 Low Power Timer
0x0000_0198 102 86 2 21
Find the NVIC Interrupt Set Enable Register (NVICISERx) for your vector:
0x0000_019C 103 87 2 21 Port control Pin detect (Port A) NVICISER2 for the LPT
module
0x0000_01A0 104 88 2 22 Port control Pin detect (Port B) Then take the modulo value of your IRQ number by 32 to calculate which bit
module
to set in the NVICISER2 register
0x0000_01A4 105 89 2 22 Port control Pin detect (Port C)
module 85%32 = 21
Table continues on the next page...
NVICISER2 |=(1<<21); //Enable LPT interrupts

K70 Sub-Family Reference Manual, Rev. 2, Dec 2011

Freescale Semiconductor, Inc. Preliminary 89
15 16

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Sample code Explained cont. NVIC Prog Hints

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Clear any pending interrupts

# $%& from
' (((    the
 )NVICICPRx
   *   + void __disable_irq(void) // Disable Interrupts
Use the same !
modulo
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7< 3  :*7:!>:
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7< 2'
result for knowing which bit to set
   + , &  - +
&-
void __enable_irq(void) // Enable Interrupts !"#$% &'(()*+,-,)./0123405).46)78-*)140264$
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  interrupts on
- +
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, &   .
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Set the interrupt priority writing to the NVICIPx
void NVIC_SetPriorityGrouping(uint32_t priority_grouping) .+'#'*+#/0&(0&'F#;0(3/&";
X is the IRQ number &  !   
  1 

Just the 4 most2 significant bits are used ++*   *# .
 :*73 :*7:*;:
7<' void NVIC_EnableIRQ(IRQn_t IRQn) G"$5:+#!>?"
NVICIP85 = 0x30; //Set Priority
 :*7 3 to the LPT module
 0  :*7:>):
7< 3 ++ #
 :*7:!>:
7< 3 ++   void NVIC_DisableIRQ(IRQn_t IRQn) H&2$5:+#!>?"
Write your ISR  :*7:*;:
7< 2'++ .
3 uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn) >+'30"#'03+#I!>?A8345+0J#&6#!>?"#&2#/+"%&";
Void lptmr_isr()
{ LPT0_CSR|=LPT_CSR_TCF_MASK; //Clear

4   +      !  LPT +
 Compare flag
%&  void NVIC_SetPendingIRQ (IRQn_t IRQn) .+'#!>?"#/+"%&";
 :*7   :*7:!>:
7<' ++>    
LPTMR0_CSR = ( LPTMR_CSR_TEN_MASK | //enable timer void NVIC_ClearPendingIRQ (IRQn_t IRQn) ,:+$0#!>?"#/+"%&";#2'$'32
LPTMR_CSR_TIE_MASK | //enable interrupt
uint32_t NVIC_GetActive (IRQn_t IRQn) >+'30"#'*+#!>?#"345+0#(6#'*+#$7'&1+#&"'+003/'
LPTMR_CSR_TCF_MASK );//clear flag
void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority) .+'#/0&(0&'F#6(0#!>?"
}
uint32_t NVIC_GetPriority (IRQn_t IRQn) >+$%#/0&(0&'F#(6#!>?"

void NVIC_SystemReset (void) >+2+'#'*+#2F2'+4

17 ++
 
 .
 - - #     18
 :*7:>):
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 :*7:*;:
7<9%' ++
 =
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 - - #    
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