Lecture 2: Computer Technology & Abstractions

Last Time
Course Overview & Organization
Introduction to Computer Architecture

Today
Computer Elements
Transistors, wires, memory
Exciting times in the computer industry
Homework 1 due February 2
Books available at UT CO-OP Monday or Tuesday

CS352 Spring 2010 Lecture 2 1

Review: Dont forget the simple view

All a computer does is

Store and move data
Communicate with the external world
Do these two things conditionally
According to a recipe specified by a programmer

Its complex because

We want it to be fast
We want it to be reliable and secure
We want it to be simple to use
It must obey the laws of physics

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 What Happens in the Fab?

silicon ingots

blank wafers

CS352 Spring 2010 Lecture 2 3

What Comes out of the Fab?

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 Computer Elements

Transistors (computing)
How can they be connected to do something useful?
How do we evaluate how fast a logic block is?

Wires (transporting)
What and where are they?
How can they be modeled?

Memories (storing)
SRAM vs. DRAM

CS352 Spring 2010 Lecture 2 5

The Mighty Transistor!

D S

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 Transistor As a Switch

Ideal Voltage G
Controlled G
Switch
D S D S
Three
terminals
Gate
Drain VG = 0
Source

VG = 2.5

CS352 Spring 2010 Lecture 2 7

Abstractions in Logic Design

In physical world
Voltages, Currents
Electron flow
voltage
Vdd
In logical world -
abstraction Vhi
1

V < Vlo 0 = FALSE ???

V > Vhi 1 = TRUE Vlo
In between - forbidden 0
0

Simplify design
problem

CS352 Spring 2010 Lecture 2 8

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 Composition of Transistors

Logic Gates
Inverters, And, Or, arbitrary

inverter NAND NOR

Buffers (drive large capacitances, long wires, etc.)

Memory elements
Latches, registers, SRAM, DRAM

CS352 Spring 2010 Lecture 2 9

Basic Components: CMOS Inverter

Vdd
Symbol Logic
Circuit
Input Output PMOS
In Out 0 1 In Out
1 0
NMOS

Inverter Operation
Vout
Vdd Vdd
Vdd Vdd

Charge Open
Out

Open
Discharge
Vdd Vin
Slide courtesy of D. Patterson
CS352 Spring 2010 Lecture 2 10

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 The Ugly Truth

Transistors are not ideal switches!

Gate Capacitance (Cg)
Source-to-Drain resistance (R)
Drain capacitance
Issues
Delay - takes time to turn transistors on and off
Power/Energy
Noise (from transistors, power rails)

But - we can change transistor size

Increase Cg, but decrease R

CS352 Spring 2010 Lecture 2 11

Ideal (CS) versus Reality (EE)

When input 0 -> 1, output 1 -> 0 but NOT instantly

Output goes 1 -> 0: output voltage goes from Vdd (2.5v) to 0v
When input 1 -> 0, output 0 -> 1 but NOT instantly
Output goes 0 -> 1: output voltage goes from 0v to Vdd (2.5v)
Voltage does not like to change instantaneously

Voltage
1 => Vdd Vout

In Out
Vin

0 => GND
Time
Slide courtesy of D. Patterson
CS352 Spring 2010 Lecture 2 12

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 Calculating Delays Through Circuits

Vin V1 V2 Vdd Vdd

Vin V1 V2
G1 G2
C1
V3

Vdd

Sum delays along serial paths G3

V3
Delay (Vin -> V2) ! = Delay (Vin -> V3)
Delay (Vin -> V2) = Delay (Vin -> V1) + Delay (V1 -> V2)
Delay (Vin -> V3) = Delay (Vin -> V1) + Delay (V1 -> V3)
Critical Path = The longest among the N parallel paths
C1 = Wire C + Cin of Gate 2 + Cin of Gate 3
Slide courtesy of D. Patterson
CS352 Spring 2010 Lecture 2 13

Tricks to Reduce Cycle Time

Reduce the number of gate levels A

A B
B
C C
D
D

Pay attention to loading

One gate driving many gates is a bad idea

Avoid using a small gate to drive a long wire

INV4x
Use multiple stages to drive large load

Clarge

INV4x
Slide courtesy of D. Patterson
CS352 Spring 2010 Lecture 2 14

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 Clocking and Storage Elements

Typical Clock
1Hz = 1 cycle per second period
(cycle time)

CLK CLK
Transparent Latch Q
D Q

D Q

CLK=0, Q=oldQ
CLK=1, Q=D

IN D Q D Q OUT
Edge Triggered
Flip-Flop CLK CLK CLK

CS352 Spring 2010 Lecture 2 15

Clocking Methodology

Clk

. . . .
. . Combinational Logic . .
. . . .

All storage elements are clocked by the same clock edge

The combination logic blocks:
Inputs are updated at each clock tick
All outputs MUST be stable before the next clock tick

CS352 Spring 2010 Lecture 2 16

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 Critical Path & Cycle Time

Clk

. . . .
. . . .
. . . .

Critical path: the slowest path between any two storage devices
Cycle time is a function of the critical path
must be greater than:
Clock-to-Q + Longest Path through the Combination Logic + Setup

Slide courtesy of D. Patterson

CS352 Spring 2010 Lecture 2 17

Wires

Limiting Factor
Density
Speed
Power

3 models for wires (model to use depends on

switching frequency)
Short

Lossless

Lossy

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 Wire Density

Communication constraints
Must be able to move bits to/from storage
and computation elements
Example: 9 ported register SRAM file

32x64
9 ported
Register File ?

CS352 Spring 2010 Lecture 2 19

Chip Level

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 Board Level

Core 2 Duo Motherboard

CS352 Spring 2010 Lecture 2 21

Rack Level

DOE ASCI White

MIT J-Machine
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 Memory

Moves information in time (wires move it in space)

Provides state
Requires energy to change state
Feedback circuit - SRAM
Capacitors DRAM
Magnetic media - disk

Required for memories

Storage medium
4Gb DRAM Die
Write mechanism
Read mechanism

CS352 Spring 2010 Lecture 2 23

Summary

Logic Transistors + Wires + Storage = Computer!

Transistors
Composable switches
Electrical considerations
Delay from parasitic capacitors and resistors
Power (P = CV2f)
Wires
Becoming more important from delay and BW perspective
Memories
Density, Access time, Persistence, BW

CS352 Spring 2010 Lecture 2 24

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 Technology Constraints through ~2004

Yearly improvement
Semiconductor technology
60% more devices per chip 1989
(doubles every 18 months)
15% faster devices 1992
(doubles every 5 years)
Magnetic Disks
60% increase in density 1995
3% DRAM speed
Circuit boards
5% increase in wire density 1998
Wire speed
increases slowly & reached its
limit
2004
Cables
no change 100x more devices since 1989
8x faster devices
CS352 Spring 2010 Lecture 2 25

Changing Technology Changes Architecture

Changes Software

1970s 1990s
semiconductor memory lots of transistors
very expensive complex control to exploit
microcoded control instruction-level
complex instruction sets parallelism
(good code density) move to multicore
Fortran Java/C#
software portability 2000s
1980s even more transistors
single-chip CPUs, on-chip slow wires
RAM feasible Power
simple, hard-wired control JavaScript, Ruby, Python
simple instruction sets ???
small on-chip caches
C/C++
CS352 Spring 2010 Lecture 2 26

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 Performance Trends

CS352 Spring 2010 Lecture 2 27

Software & Hardware: The Virtuous Cycle?

Faster Single
Processor
Frequency Scaling Larger, More
Capable Software
Managed Languages

?
More Cores Scalable Software
Scalable Apps +
Multi/Many Core
Scalable Runtime

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 Next Time

Evaluation of Computer Systems

Performance
Amdahls Law, CPI
Power
Benchmarks

Reading assignment
P&H Chapter 1.4, 1.7-9

CS352 Spring 2010 Lecture 2 29

Basic Technology: CMOS

CMOS: Complementary Metal Oxide Semiconductor

NMOS (N-Type Metal Oxide Semiconductor) transistors Vdd = (2.5V)
PMOS (P-Type Metal Oxide Semiconductor) transistors
NMOS Transistor
Apply a HIGH (Vdd) to its gate GND = 0v
turns the transistor into a conductor
Apply a LOW (GND) to its gate
shuts off the conduction path
Vdd = (2.5V)
PMOS Transistor
Apply a HIGH (Vdd) to its gate
shuts off the conduction path GND = 0v
Apply a LOW (GND) to its gate
turns the transistor into a conductor

Slide courtesy of D. Patterson

CS352 Spring 2010 Lecture 2 30

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 Basic Components: CMOS Logic Gates

NAND Gate NOR Gate

A B Out A B Out
A Out 0 0 1 A Out 0 0 1
B 0 1 1 0 1 0
1 0 1 B 1 0 0
1 1 0 1 1 0
Vdd Vdd
A

Out
B
B
Out

Slide courtesy of D. Patterson

CS352 Spring 2010 Lecture 2 31

Series Connection
Vin V1 Vout Vdd Vdd

G1 G2 Vin V1 Vout
G1 G2
Voltage C1 Cout
Vdd
Vin V1 Vout

Vdd/2
d1 d2

GND
Time
Total Propagation Delay = Sum of individual delays = d1 + d2
Capacitance C1 has two components:
Capacitance of the wire connecting the two gates
Input capacitance of the second inverter
Slide courtesy of D. Patterson
CS352 Spring 2010 Lecture 2 32

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