VALLIAMMAI ENGINEERING COLLEGE

SRM Nagar, Kattankulathur 603 203

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING

QUESTION BANK

II SEMESTER M.E COMMUNICATION SYSTEMS

VL7013 VLSI FOR WIRELESS COMMUNICAITON

Regulation 2013

Academic Year 2016 17

Prepared by

Mr.S.MARIRAJAN, Assistant Professor/ECE

 VALLIAMMAI ENGINEERING COLLEGE
SRM Nagar, Kattankulathur 603 203.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

QUESTION BANK
SUBJECT : VL7013 VLSI FOR WIRELESS COMMUNICATION
SEM / YEAR: II / I

UNIT I COMPONENTS AND DEVICES

Integrated inductors, resistors, MOSFET and BJT AMPLIFIER DESIGN: Low Noise Amplifier Design - Wideband LNA
- Design Narrowband LNA - Impedance Matching - Automatic Gain Control Amplifiers Power Amplifiers.
PART A

BT
Q.No Questions Competence
Level

1. Summarize the fabrication steps for integrated inductors. BTL 2 Understanding

2. Predict the common methods for fabricating integrated resistors. BTL 2 Understanding

3. Select the Objectives of Matching networks. BTL 1 Remembering

4. Estimate the transducer power gain GT. BTL 2 Understanding

5. Recall the specifications of LNA for DECT. BTL 1 Remembering

6. Inspect the issues which should be consider while designing wideband BTL 4 Analyzing
amplifier.
7. Differentiate BJT and CMOS. BTL 2 Understanding

8. Show the features of CMOS inter connecting reverse scaling. BTL 1 Remembering

9. Examine noise figure. BTL 4 Analyzing

10. Summarize the basic elements in CMOS technology. BTL 5 Evaluating

11. Analyze the transistor layout. BTL 4 Analyzing

12. Write the importance of high gate resistance. BTL 1 Remembering

13. Compare resistor and inductor layout. BTL 1 Remembering

14. Identify the matching issues in CMOS circuit. BTL 3 Applying

15. Demonstrate the CMOS circuit technology. BTL 3 Applying

16. Elaborate on Q-factor. BTL 6 Creating

17. Determine the importance of automatic gain control amplifier. BTL 5 Evaluating

18. Illustrate amplifier and power amplifier. BTL 3 Applying

19. List the various applications of LNA circuit. BTL 1 Remembering

20. Discuss the reverse isolation. BTL 6 Creating

PART B

1. Describe the following methods used in integrated resistors. BTL 1 Remembering

(a) Diffused (2)
(b) Epitaxial (4)
(c) Pinched (4)
(d) Thin film techniques (3)
2. Demonstrate the various steps involved in Integrated Inductors BTL 2 Understanding
manufacturing. (13)
3. Develop the points to explain about the matching networks. (13) BTL 3 Applying

4. (a) Compare Narrowband and Wideband LNA. (6) BTL 2 Understanding

(b) Summarize the general philosophy of generalized LNA topology with
relevant diagrams. (7)
5. Illustrate the Wideband LNA design by BTL 2 Understanding
(a) DC bias. (3)
(b) Gain and frequency response. (5)
(c) Noise figure. (5)
6. Show how would you match the Imaginary & real part in Narrowband LNA BTL 1 Remembering
impedance matching. (13)
7. Explain the following in Narrowband LNA impedance matching. BTL 4 Analyzing
(a) Interpretation of power matching. (6)
(b) Similarity between Q & n. (7)
8. Write in detail the expressions of noise figure for Narrowband LNA Core BTL 1 Remembering
amplifier. (13)
9. Discuss the following BTL 6 Creating
(a) Trade-off between Noise figure and power. (7)
(b) Noise contribution from other sources. (6)
10. Determine the following BTL 5 Evaluating
(a) Gain of Narrowband LNA Core amplifier. (4)
(b) General considerations for power amplifiers and sketch the general
power amplifier model. (5)
(c) Breakdown phenomenon for MOS & Bipolar devices. (4)
11. Analyze the operation of BTL 4 Analyzing
(a) Class A power amplifier. (7)
(b) Class B power amplifier. (6)
12. Solve the expression of power dissipation for Narrowband LNA core BTL 3 Applying
amplifier. (13)
 13. Examine about BTL 4 Analyzing
(a) Class D power amplifier. (5)
(b) Class E power amplifier. (5)
(c) Inverse Class F power amplifier. (3)
14. Sketch the diagram for the following and give a brief note on BTL 1 Remembering
(a) Class C power amplifier. (7)
(b) Class AB power amplifier. (6)
PART C

1. Examine the layout for BTL 5 Evaluating

(a) Resistor. (3)
(b) Capacitor. (3)
(c) Inductor. (4)
(d) Transformer. (5)
2. Design a CB amplifier for a voltage gain of 10 and an input impedance of BTL 6 Creating
50 ohm. Assume Is =5*10^-19A, Va=,=100,and Vcc=2. (15)

3. Estimate the CS stage for a voltage gain of 5,an input impedance of BTL 5 Evaluating
50Kohm,and a power budget of 5Mw.Assume
uNCox=100uA/v^2,Vth=0.5v,lemada=0,and V DD=1.8v.Also assume a
voltage drop of 400mV across Rs. (15)

4. Formulate in detail about the impedance matching with illustrations. (15) BTL 6 Creating

UNIT II MIXERS

Balancing Mixer - Qualitative Description of the Gilbert Mixer - Conversion Gain Distortion - Low Frequency
Case: Analysis of Gilbert Mixer Distortion - High-Frequency Case Noise - A Complete Active Mixer.
Switching Mixer - Distortion in Unbalanced Switching Mixer - Conversion Gain in Unbalanced Switching Mixer
- Noise in Unbalanced Switching Mixer - A Practical Unbalanced Switching Mixer. Sampling Mixer - Conversion
Gain in Single Ended Sampling Mixer - Distortion in Single Ended Sampling Mixer - Intrinsic Noise in Single
Ended Sampling Mixer - Extrinsic Noise in Single Ended Sampling Mixer.
 PART A

BT
Q.No Questions Competence
Level

1. Survey the mixer modeled as variable gain amplifier. BTL 4 Analyzing

2. Define unbalanced mixer. BTL 1 Remembering

3. What is quad mixer? BTL 1 Remembering

4. Why double balanced mixer is commonly used? Justify. BTL 1 Remembering

5. List the two levels of subscript and superscript distinctions. BTL 1 Remembering

6. Estimate the conversion gain. BTL 5 Evaluating

7. Show the distortion in Gilbert mixer. BTL 1 Remembering

8. Explain about NLTI. BTL 2 Understanding

9. Conclude the properties of Bilinear system. BTL 5 Evaluating

10. Develop the circuit representation1 of an NLTI system. BTL 6 Creating

11. Examine G1 from the first order term id. BTL 4 Analyzing

12. Identify the noise in mixers. BTL 3 Applying

13. Experiment the mixer topology. BTL 3 Applying

14. Tell about mixer linearization. BTL 1 Remembering

15. Outline the block diagram of an unbalanced mixer for noise calculation. BTL 2 Understanding

16. Choose the two scenarios which is used in analysis of noise in unbalanced BTL 3 Applying
mixer.
17. Compare linearity and nonlinearity. BTL 2 Understanding

18. Distinguish between low frequency and high frequency mixers. BTL 4 Analyzing

19. Relate intrinsic noise and extrinsic noise in mixers. BTL 2 Understanding

20. Compile the assumptions which will consider during intermodulation BTL 6 Creating
distortion switching mixer?
PART B

1. Define the following BTL 1 Remembering

(a) Mixer (2)
(b) Unbalanced mixer (4)
(c) Single balanced mixer (4)
(d) Double balanced mixer (3)
2. Explain the qualitative description of the Gilbert mixer. (13) BTL 2 Understanding
3. Point out the detailed analysis of Gilbert mixer for the following BTL 4 Analyzing
(a) Distortion. (4)
(b) Low frequency case. (9)
4. Illustrate the Gilbert Mixer distortion in high frequency case. (13) BTL 2 Understanding

5. Describe the following factors of Noise in balanced mixer BTL 1 Remembering

(a) Vlo not switching case. (3)

(b) Vlo switching case. (10)

6. Develop the theory of linear periodic LPTV system. (13) BTL 3 Applying

7. Calculate the noise in unbalanced mixer in the scenario of V lo not switching BTL 3 Applying
case and Vlo switching case and calculate the following.
(a) Sn2 (2)
(b) HLTI (5)
(c) NF (6)
8. Conclude a detailed note on special Vlo switching case mixers. (13) BTL 5 Evaluating

9. Write the following factors of switching mixer. BTL 1 Remembering

(a) Unbalanced switched mixer. (5)
(b) Single and double balanced switching mixer. (8)
10. Inspect the non idealities of switching mixers and their impact. (13) BTL 4 Analyzing

11. (a) List the assumptions made on model for distortion in unbalanced
switching mixer. (4)
(b) Show the distortion in unbalanced switching mixer in the condition BTL 1 Remembering
of low frequency case. (9)
12. Measure the conversion gain in unbalanced switching mixer with diagrams. BTL 6 Creating
(13)

13. Derive the Intrinsic noise in single ended sampling mixer. (13) BTL 4 Analyzing

14. Compare Sample & hold circuit and Sampling mixer with necessary BTL 2 Understanding
diagrams. (13)
PART C

1. Estimate the equivalent input-referred voltage and current noise sources at BTL 6 Creating
the input with feedback Vi 2 * Ii 2 in terms of the equivalent input referred
voltage and current noise sources without feedback V i Ii. (15)
2. Compare the different LNA architectures according to their gain, NF and BTL 5 Evaluating
matching performances. (15)

3. With the help of Gilbert / Quad mixer assume that M-M6 all have a W/L of BTL 6 Creating
50m/0.6m and make Vgs1 Vt = 0.387V, assuming that k = 7.5uA/V 2.
Then k=6250uA/V2 and gm1=k(VGS-Vt) = 2.4m-1. Design for a
conversion gain of 10dB. Assume that a Gilbert mixer operates under the
following conditions. VGS1 Vt = 0.387 V Arf = Ainterference = 0.316 V or 0dB.
Assume that the LO is not switching. Find the mixers distortion behavior
HD3, IM3 and IIP3.The mixer is assigned as IIP3 of -10dBm. Design this
mixer with some safety margin. Consider the specification arbitrarily. (15)
 4. Evaluate Gc.IM3 and NF of both a 100MHZ IF single-ended sampling mixer BTL 5 Evaluating
and a 1.9GHz RF single-ended sampling mixer in a DECT application for the
following architecture shown in figure. (15)

UNIT III FREQUENCY SYNTHESIZERS

Phase Locked Loops - Voltage Controlled Oscillators - Phase Detector Analog Phase Detectors- Digital Phase
Detectors - Frequency Dividers - LC Oscillators- Ring Oscillators - Phase Noise- A Complete Synthesizer Design
Example (DECT Application).
PART A

BT
Q.No Questions Competence
Level

1. Draw the block diagram of a PLL. BTL 1 Remembering

2. Mention the purpose of phase detector. BTL 2 Understanding

3. List the types of phase detector. BTL 1 Remembering

4. Outline the state diagram of phase frequency detector. BTL 2 Understanding

5. Show the types of VCO. BTL 1 Remembering

6. Analyze the use of LC Tank circuit. BTL 4 Analyzing

7. What is the difference between PLL and VCO? BTL 1 Remembering

8. Define PLL based frequency synthesizer. BTL 1 Remembering

9. Differentiate Colpitts and Hartley oscillator. BTL 4 Analyzing

10. Explain the ring oscillator. BTL 4 Analyzing

11. Tell the use of frequency divider. BTL 5 Evaluating

12. Evaluate the phase noise. BTL 5 Evaluating

13. Analyze the loop filter. BTL 3 Applying

14. What is Figure of Merit.? BTL 1 Remembering

15. Elaborate the applications of digital phase detector. BTL 6 Creating

16. Develop the structure for multi feedback ring oscillator. BTL 6 Creating

17. Predict the role of analog phase detector circuit. BTL 2 Understanding

18. Construct the LC oscillator model. BTL 3 Applying

19. Report the participation of frequency divider in frequency synthesizer BTL 2 Understanding
circuit.
20. Select the applications of DECT. BTL 3 Applying

PART B

1. (a) Write the design and function of phase locked loop with example. BTL 1 Remembering
(10)

(b) Recall the short notes on loop filter. (3)

2. (a) Explain the condition for an oscillator. (4) BTL 2 Understanding

(b) Describe the voltage control oscillator and improved voltage stability
circuit with example. (9)

3. (a) Examine the digital phase detector circuit with example. BTL 1 Remembering
(9)
(b) Tell about the charge pump. (4)

4. (a) Summarize the design procedure of LC oscillator with example. BTL 2 Understanding
(10)
(b) Outline on Tuning Kvco. (3)
5. (a) Conclude the design model of PLL circuit with example. (6) BTL 5 Evaluating

(b) Mark the layout design of PLL. (7)

6. How the ring oscillator operates and explain it with an example circuit. (13) BTL 1 Remembering

7. (a) Construct the frequency divider circuit with examples. (7) BTL 3 Applying
(b) Identify the features of digital equalizers. (6)

8. Demonstrate the digital phase detector circuit with example. (13) BTL 3 Applying

9. Analyze the operation of analog phase detector circuit. (13) BTL 4 Analyzing

10. Create a complete design of synthesizer with DECT application. (13) BTL 6 Creating

11. Inspect the following BTL 4 Analyzing

(a) Overview of PLL. (4)
(b) Draw the architecture of PLL. (3)
(c) Current starved voltage controller oscillator. (6)
 12. (a) List the features of LC oscillator. (6) BTL 1 Remembering
(b) Sketch the implementation of Phase detector using D-Flip flop. (7)
13. Point out the detailed considerations of phase noise. (13) BTL 4 Analyzing

14. Illustrate the procedure of Ring oscillator with example. (13) BTL 2 Understanding

PART C

1. (a) Design the phase detector based on D-FF. (7) BTL 6 Creating
(b) Plot the waveforms at the internal nodes of this phase detector. (8)
2. Determine the following DECT applications. BTL 5 Evaluating
(a) Cordless PBXs (8)
(b) Interworking of cordless equipment with the ISDN. (7)
3. Construct the architecture of DECT with relevant diagrams. (15) BTL 6 Creating

4. (a) Design the adaptive channel estimation. (7) BTL 5 Evaluating

(b) Determine the detection of probabilistic symbol detection with relevant

diagrams. (8)

UNIT IV SUB SYSTEMS

Data converters in communications, adaptive Filters, equalizers and transceivers
PART A

Q.No Questions BT Level Competence

1. List out the features of Ideal Data Converter. BTL 1 Remembering

2. Differentiate Static Performance and Dynamic Performance. BTL 2 Understanding

3. Describe Channel Capacity and Error Probability. BTL 1 Remembering

4. Analyze the frequency Domain Measurement parameters. BTL 4 Analyzing

5. Define Multi-Carrier Systems. BTL 1 Remembering

6. Report about Channel Equalization. BTL 2 Understanding

7. Discuss about Optimum ADCs. BTL 5 Evaluating

8. Explain LMS algorithm. BTL 4 Analyzing

9. Identify the Stability of LMS. BTL 1 Remembering

10. Summarize the applications of adaptive filters. BTL 2 Understanding

11. Discriminate the Selection of Adaptive Parameters. BTL 5 Evaluating

12. Draw the structure of adaptive filter. BTL 3 Applying

13. Tabulate the key features of equalizer. BTL 1 Remembering

14. Examine the Ideal case of adaptive filter. BTL 3 Applying

15. Predict the need of Mixer circuit. BTL 3 Applying

16. Show the importance of LMS Equation. BTL 2 Understanding

17. Compose the limitations of Adaptive filters. BTL 6 Creating

18. State the function of an Adaptive Filter. BTL 1 Remembering

19. Generalize the concept of Inverse Modeling. BTL 6 Creating

20. Compare DAC for Baseband and DAC for Passband. BTL 4 Analyzing

PART B

1. (a) Discuss the DAC data converter. (3) BTL 5 Evaluating

(b) Estimate the design of Current-Steering DAC Topologies.
(10)
2. (a) State sampling theorem. (3) BTL 1 Remembering
(b) Identify the Non-Ideal Effects of Oversampled Sigma-Delta
Converters. (10)
3. Describe the Oversampled Sigma-Delta Converters for High Signal BTL 1 Remembering
Bandwidths.

4. (a) Develop the concept of Time-Interleaved ADCs passive BTL 3 Applying

element. (7)
(b) Sketch the layout for Time-Interleaved ADCs. (6)
5. (a) Demonstrate the Least-Mean-Square algorithm in adaptive BTL 2 Understanding
filter. (9)
(b) Report the advantage and disadvantage of Least-Mean-
Square algorithm. (4)
6. (a) Explain the Pipelined Converter in data convertor BTL 2 Understanding
communication. (8)
(b) Extend the merits and demerits Pipelined Converter in data
convertor communication. (5)
7. (a) Justify the need of an Adaptive Filter. (8) BTL 3 Applying
(b) Select the points to explain the Limitations of SI MDACs. (5)

8. (a) Write the implementation of LMS algorithm using VHDL. BTL 1 Remembering
(10)
(b) Draw the RTL schematic for LMS algorithm. (3)
 9. Inspect the general form of Adaptive FIR Algorithms. (13) BTL 4 Analyzing

10. (a) Predict the requirements for Minimum Data Converter. BTL 6 Creating
(10)
(b) Discuss the performance Limitations of Minimum Data
Converter. (3)
11. Analyze the various applications of adaptive filter in detail. (13) BTL 4 Analyzing

12. (a) Summarize the problem in Adaptive filtering. (7) BTL 2 Understanding
(b) Outline the diagram and explain the filter structures. (6)
13. Examine the following BTL 4 Analyzing

(a) Inter Symbol Interference (6)

(b) Equalization (7)
14. List the various types of ADC data converters. (13) BTL 1 Remembering

PART C
1. BTL 5 Evaluating

2. Analyze the function of front-end of a transceiver sequence by smart BTL 6 Creating

antennas. (15)
3. (a) Analyze the design issues in wireless transceiver system. (7) BTL 5 Evaluating
(b) Discuss the same on FPGA implementation. (8)
4. Analyze the high speed data converters in wireless communication BTL 6 Creating
with appropriate diagrams. (15)

UNIT V IMPLEMENTATIONS
VLSI architecture for Multitier Wireless System - Hardware Design Issues for a Next generation CDMA System
PART A

Q.No Questions BT Level Competence

1. Define channel capacity drive. BTL 1 Remembering

2. Explain Spectral Reuse in CDMA. BTL 2 Understanding

3. List out the objectives of Hardware Software Co-design in multi- BTL 1 Remembering
tier system.
4. Construct the turbo decoding architecture. BTL 3 Applying

5. Demonstrate Configurable Processors. BTL 2 Understanding

6. What is Multitier Network Interface Card? BTL 1 Remembering

7. Describe the Multiuser Channel Capacity. BTL 1 Remembering

8. Summarize the methods to Improve channel Capacity in CDMA. BTL 2 Understanding

9. Conclude the cascaded systems for noise figure computation. BTL 5 Evaluating
10. Explain multitier network interface card. BTL 5 Evaluating

11. Illustrate the Enhance robustness and capacity via cognitive relays. BTL 3 Applying

12. Build the architecture of Reconfigurable Baseband modulator for BTL 3 Applying
software defined radio.
13. Examine the operation of Virtual Antennas. BTL 1 Remembering

14. Inspect the rapid prototyping. BTL 4 Analyzing

15. List out the Network Capacity Results. BTL 4 Analyzing

16. Tell about Underlay Systems. BTL 1 Remembering

17. Analyze the design issues of Communication Architecture. BTL 4 Analyzing

18. Compose the Benefits of Relaying in Cellular Systems. BTL 6 Creating

19. Elaborate the Key Time Scales for System Design. BTL 6 Creating

20. Estimate the Power Efficiency of multi-tier wireless system. BTL 2 Understanding

PART B
1. Evaluate Random Access and Scheduling in CDMA technique. BTL 5 Evaluating
(13)
2. (a) Define the performance issue of CDMA technique. (4) BTL 1 Remembering
(b) Describe the Multiuser Channel Capacity in CDMA
technique. (9)

3. (a) Examine the Relaying in Cellular Systems. (8) BTL 1 Remembering

(b) Write short on merits and demerits of Relaying in
Cellular Systems. (5)
4. How the Home/Desk Area WLAN operates? Explain it in detail. BTL 1 Remembering
(13)

5. (a) Illustrate the Adaptive Resource Allocation for Wireless BTL 2 Understanding
Ad-Hoc Networks. (10)
(b) Summarize the merits and demerits of Adaptive
Resource Allocation. (3)

6. (a) Discuss MIMO Techniques in Cellular system. (8) BTL 6 Creating

(b) Choose the application of MIMO Techniques in Cellular
system. Give reasons.(5)
7. (a) Analyze Routing Techniques of VLSI architecture system. (8) BTL 4 Analyzing
(b) Inspect the SOC level router for VLSI architecture system. (5)
8. (a) Construct the Reconfigurable Multitier Network Interface Card BTL 3 Applying
(mNIC) for Service Continuity. (7)
(b) Develop the point to explain Implementation Challenges for a
Multitier Network Interface Card (mNIC). (6)
9. (a) Discuss about the Cellular Radio Network. (6) BTL 2 Understanding
(b) Outline the Structure of the mobile phone cellular network. (7)
10. (a) Examine about Green Cellular Networks. (10) BTL 3 Applying
(b) Select the point to explain the performance issue of Green Cellular
Networks. (3)
11 Examine the Physical Modelling for Wireless Channels. (13) BTL 4 Analyzing

12 Show the performance of Point to Point Communication. (13) BTL 1 Remembering

13 Demonstrate the following in detail BTL 2 Understanding

(a) Cellular Systems (3)
(b) Multiple Access (5)
(c) Interference Management (5)
14 Discover the capacity of wireless channels. (13) BTL 4 Analyzing

PART C

1. Design a Home/Desk Area WLAN using VLSI Architectures for BTL 6 Creating
Multitier Wireless Systems. (15)
2. (a) Judge the following statement: CDMA is not suitable for 4G BTL 5 Evaluating
system. Justify with relevant diagrams. (7)
(b) Explain the CDMA-Based 2G and 3G Systems with real time
applications and draw the necessary diagrams. (8)
3 Elaborate the BTL 6 Creating
(a) Multiuser Capacity for wireless systems with neat diagrams. (8)
(b) Opportunistic Communication. (7)
4 Conclude the following with diagrams BTL 5 Evaluating
(a) Spatial multiplexing. (8)
(b) Multiplexing architectures MIMO system. (7)