Proceedings of the 2009 IEEE International Conference on Mechatronics.

MaJaga, Spain, April 2009.

Left to Right Serial Multiplier for Large Numbers on

FPGA

H.Bessalah, K.Messaoudi, M.lssad & N.Anane M.Anane

System Architecture & multimedia National informatics institute
CDTA INI
PB 17, Baba Hassen Algiers, Algeria. Algiers, Algeria.
[email protected], [email protected] [email protected]

Abstract- A new high precIsIon serial multiplier with Most several works [3, 4, 5, 6], who clearly reveal the adaptation of
Significant Digit First (MSDF) is presented. This one uses a the on-line arithmetic for this kind of calculation. Since, in the
Borrow-Save (BS) adder to perform the reduction of large length online arithmetic, the operands, as well as the results, flow
partials products required by the multiplication of large serially through the computation in a digit by digit manner
numbers. The results are converted from BS form to the 2's
starting from the most significant digit (MSDF). The
complement representation by the on-the-fly conversion which let
the conversion of the digit result as soon as it is obtained. It is advantages of online arithmetic have been to permit the
shown that the comparison between the residual and these computation of all operations with MSDF mode which reduce
constants (-3/2, -112, 112 and 3/2) needed in the radix-2 on line the interconnection bandwidth between modules and allow
multiplication, present problem in high precision computation. parallelism between several operations. Moreover, to
However, in the proposed method the operands are introduced manipulate large numbers in parallel way presents always a
digit by digit with MSDF mode and results are obtained in the hardware problem, because parallelism requires large
same manner with fixed time delay independently of the operand processing circuits that must comprise several inputs-outputs
size. So, this approach is advantageously used for the long pins according to the size of the operands, what increases
multiplication computation. This method has been tested by the
execution of a program developed with Maple 9.5 for several test
circuitry complexity.
vectors. The results of the implementation of this multiplier for
several operands sizes (128,256, 512, and 1024) on Virtex-I1 Among these works, A.Guyot, Y.Herreros and I-M.Muller
FPGA Circuit confirm that the multiplication is performed in presented in [4] the implementation on VLSI of an online
constant time. Multiplier IDivider for large numbers. Subsequently, Y.Hornik
sustained in the same context in order to implement several
Keywords-component: Multiplication, On-line arithmetic, High online operators for high precision [5]. The drawback ofthese
precision, Architecture, VHDL, FPGA, Virtex-II. operators is that their architectures are proportional to the
operand size, which generates a very important hardware. We
I. INTRODUCTION can also cite the work of M.D.Ercegovac and A.F Tencas in
[6], where they elaborate divider architecture in long precision
In the last two decades the focus of digital design has been while using the online mode for high radix.
primarily on computation performances, however the
precision remained almost unchanged and limited to simple However, the use of the binary on-line arithmetic in high
and double precision of IEEE-754 standard [1]. In addition, precision, presents generally a problem in the selection of the
several scientific and technical computations are numerically result digit. Since, the generation of this digit is done after the
intensive and require arithmetic operators with very high comparison between the residual noted by H[j], which is
precision. A good example of this kind of operation is founded represented in redundant notation, and constants represented
in cryptography [2], where with the constant growth of the in 2's complement. This comparison is possible only after the
data communications; the security becomes more and more an conversion of the total residual to 2's complement. This
important characteristic. Encryption/Decryption data need requires the use of carry propagate adder depending on the
arithmetic operators with very high precision about 200 to operands size. Consequently the delay of generation of the
2000 bits. Several fields can also be cited such as the digit result will be proportional to the time of this adder.
electronic signatures, the medical imagery, the generation of Several works detailed in [7, 8, 9, 10] present solutions based
random numbers, the reduction of fraction in infmite precision on the overlapping of the selection intervals, thus the
and other more critical applications such as the nuclear operation of comparison is carried out only on a fixed part of
simulators of stations and the military batteries of air defense. the residual. This part is deduced after the estimation of the
Therefore, the calculation in high precision was the object of residual to a value which contains only its significant digits.

978-1-4244-4195-2/09/$25.00 (c) 2009 IEEE

While this solution has a correct theoretical base, but it This allows the computation of a sum in a constant time
complicates the representation of the new constants using logical gates equalize with limited inputs numbers. In
corresponding to the new intervals. This increases the such systems, the numbers are represented in radix ~ with
complexity in the hardware implementation of the online digits which does not only belong to the set {O, 1, ... , ~-1}, but
operators. As solution, we present in this paper, a new method to the set {-a, ... , -1, 0, 1, ... , a}. It is easier to see that
to compute a long precision multiplication of 2's complement 2a + 1 ;::: ~ (i.e. if there are at least ~ digits) then all the numbers
numbers. The proposed method is based on the generation of are represented in these systems. The parallel algorithm of
partials products and their reductions with the MSDF mode, addition proposed by Avizienis gives a correct result when
using the Borrow-Save addition approach [11]. The result digit a < ~ and 2a-l ;::: ~ (which requires that ~ ;::: 3).
is converted to 2's complement by the On-the-fly conversion.
This conversion algorithm manipulates the numbers in serial C. Borrow-Save System
MSDF mode, thus the conversion of the result can begin as The latter algorithm presented by Avizienis is suitable for
soon as the ftrst redundant digit result is present. The calculation in radix equal or higher than 3. When, the numbers
architecture of our multiplier is implemented on XC2V2000-6 are represented in radix 2 (i.e. a = 1), digits belonging to {- 1,
FPGA circuit for different size of operands (from 128 bits to 0, I} are used. This system is called Borrow-save system. In
1024 bits). this case, the condition 2a + 1 ;::: ~ is satisfted, except the
The main contributions of our work are as follows: we condition 2a ;::: ~ + 1 which is not. The algorithm of addition
expose the online multiplication problem in high precision and proposed by Avizienis does not work in such a representation
we prove that the truncation of the residual might gives error system. Altematively, there are several algorithms of addition
result. We also propose a new multiplication method in high without carry propagate which work in Borrow-Save system.
precision which provides in constant time independent of More details about this system were presented in [15, 16]. The
operands size. We ftnally achieve the simulation and the digit c is represented by two bits c+ and co, such as c is equal to
implementation of this multiplier for several operand sizes. c+ - CO. In this system of representation, the addition operation
The rest of this paper is organized as follows: The next section is carried out in a constant time independent of the operand
presents the background on the use of on-line arithmetic in size.
high precision. Section III illustrates the proposed method, its
architecture and how we solve the problem of online D. The On-line Multiplication Description
multiplication. Section IV, presents the implementation results Algorithms for on-line multiplication and division are
of our architecture on FPGA circuits of Virtex-II. We fmish given in [17, 18,4, 19]. The on-line multiplication presented
with a conclusion in [20, 21,22] by M.Ercegovac proceeds as follows: suppose
that the radix is equal to 2, with the Dp= {-I, 0, I} set of
II. BACKGROUND
symmetrical redundant numbers. Such as p is the Redundancy
A. On-line Definition factor. So, p is equal to aJ (~ - 1) = 1 and satisfted the
condition 2p+ 1 > 2. Suppose else those operands X, Y,
Online arithmetic has been shown to be very useful for
Z=Xxy, are purely fractional numbers which are represented
many signals processing such as DCT, FFT, CORDIC, matrix-
based operations and high precision computation [12, 13]. in the following way:
Since, the on-line mode gives more advantages than the
conventional serial mode last signiftcant digit ftrst - we will X [j] =Lji~l Xj X 2-i = X [j-l] + Xj x Tj (1)
refer to this direction as LSDF mode-. As we said bellow, this Y [j] =~i~l Yj x Ti = Y [j-I] + Yj x Tj (2)
arithmetic allows computing of usual operations in the same
way. This is not the case for the division and the calculation of Z[j] = Z [j-l] + Zj x Tj (3)
the maxima for two numbers in the LSDF mode. In addition,
with the online, operators can have small sizes with less Xj, Yj and Zj E {-I, 0, I}
number of input/output than their equivalents in parallels. On-
line system are characterized by their delay 0, (i.e. such that p The fundamental proposal of this method is summarized to
digits of the result are deduced from p+o digits of the input establish a recurrence relation between X [j] xY [j] and Z [j],
values), and their period 't (i.e. the time needed in order to where at each iteration; we can obtain a digit Zj as a result.
compute a new digit). The M.Ercegovac's idea consists of the deftnition of partial
To compute all the operations (addition, multiplication, residual P[j] such as: P[j] = X [j]xY [j] - Z[j] by checking the
division, square root, sinus, logarithm and exponent ... ), with following equation:
the MSDF mode, became possible in online arithmetic by the IX [j] xY [j] - Z[j] I < Tj-l
use of redundant systems of number representation.
Which is the nearest rounding approach.
B. Redundant Systems of Numbers Representation P [j+l] =2- 3X [j+l] x Y [j+l] -Z [j+l] (4)
In 1961, Avisenis presented in [14] the redundant P [j+ 1] = [(X [j] + Xj+3+lTj-I-3) x (Y [j] + Yj+3+12-j-I-3 )]
representation of numbers where each digit has a sign. - (Z [j]+ zj+1Tj-l)
P [j+1] = P[j] + 2+ 1-3 (X [j+I] X yj+3+1 + Y [j] x Xj+3+I) (5)

The value T3 of the equation 4, characterize the on-line

multiplication delay which is equal to 3. The partial residual
P[j] contains terms with Tj which is translated in material by j
right shift register. In order to simplify this expression, another
residual R[j] is defined equal to 2jx P[j). So, the expression 5
became:
R [j+ 1] =2- 3 R[j] + (X [j+ 1] X Yj+3+1 +Y [j] x Xj+3+1) 2-3-1_ Zj+1
R [j+ 1] = H[j+ 1] - Zj+l
Such as
H [j+l] = T 3R[j] + (X [j+I] X Yj+3+1 + Y [j] x Xj+3+I) T 3-1
H [j+ 1] = 2 x H[j] - 2 x Zj_I+ L[j+ 1] Figure 1. On-line multiplier Architecture
H[j]: is the total residual at the jth iteration and
The multiplier architecture presented on figure 1 recommends
L [j+I] = X [j+I] X Yj+3+l + Y [j] X Xj+3+l the use of a carry propagate adder CLA for the conversion of
The j+3 first digits of the operands X and Y allow the H[j] to 2's complement. The CLA adder is comparatively slow
calculation of the j first digits of the result Z, with absolute and occupies a significant area in hardware implementation
error of 112 ulp (unit in last place) which is equivalent to Tj-I. for the reason that this adder depends of the operand's size.
Then The selection circuit is merely a table that takes in account
only the tree first significant bits of H [j], (hI, ho, h_ l ) to
I P[j] I ~ Tj-I => IR[j] I:s 1- 112 /2 => I H[j] - Zj I:s 1- 112/2 generate the bit result Zj. It is clear that this selection cannot
take place until all the bits of H [j] are obtained, i.e. after carry
propagation on the whole length H [j] which presents a
(6) drawback in this method for computing in long precision. A
question arises, can we avoid the addition for all the bits of
From the expression 6, we are able to determine the selection H[j] and do it just for the three or four significant digits of
function F (H[jD which permits to know the result value Zj via H[j]? The answer is that these bits don't give all the
the value of the total residual H[j]. This selection function is information concerning the exact value ofH [j] and an error is
defined such follows: introduced. This one can be equal to the last bit value from

{o
which the H [j] has been truncated. This error on H[j], can
-1 if-3/2 ~ HG) < -112 easily in some cases select a false digit result.
Zj = if -112 ~ HG) < 112 (7) So, the long precision computation requires a new online
multiplication where the results digits are generated without the
1 if 112 ~ HG) < 3/2 comparison stage and the carry propagation problem doesn't
occur.
E. On-line Multiplier architecture
III. THE PROPOSED METHOD
The multiplier architecture corresponding to the algorithm
quoted in the latter section is represented on figure 1. This one The multiplication method that we develop in this section is
is composed of: a serial method in MSDF mode. The result is obtained in the
same manner in constant time independently of the operand's
size. The method's principal is based on the classic
Two digit by vector multipliers: used for the multiplication which is done in three steps: the generation of
calculation of partials products X[j]xYj+3 and the partial products, the reduction of the partial products and
Y [j-I] x Xj+3' the final addition. Our approach has the same principle, except
that it runs these three steps in serial with significant digit first.
Tree reduction using CSA adder (carry save adder) for In the proposed method, operands are represented in 2' s
the reduction to two terms in CS notation of the follow complement and introduced bit by bit with most significant bit
expression : first.
H[j] = 2 x (H[j-I] - Zj)+ (X [j] x Yj+3+ Y [j-I] x Xj+3) In order to illustrate the process of this method, we present
an example on the figure 2 which shows the multiplication
Conversion block in order to convert the total residual
calculation of two operands: X and Y which are presented with
from the redundant representation to 2's complement 4 bits as follow:
using a CLA adder.
X=O, XIX2X3}4, Y=O, YIY2Y3Y4 ,such as X and Y < 1
Block used for the calculation of the selection function
S (H[jD. We have to start the process with the initialization step,
which consist in the addition of the four most significant bits
(two bits from each operand). This step may be done in parallel representation. The first block calculates the two partials
or serial, and it presented the method's delay where the fIrst products XjxY [i-I] and YixX[j]. As the bits Xj and Yi are equal
result digit cannot be obtained until the end of this step. During to 0 or 1, the multiplication by these bits is easy to do by a
the fIrst step, the fIrst digit WI is obtained, and the X3 and Y3 group of AND gates. This last has the same size as the
inputs bits are introduced and their corresponding partial operand. Since, each iteration; a new bit is added to the
products are added to the residual R [1]. Then, the second digit operands Y [i-I] and X [j], until obtained completely the
result W2 is obtained which is equal to the most signifIcant digit operands X and Y.
of the partial residual W [2]. In the same manner, all the digits The reduction block, reduces three numbers, twice of them
results are computed, until the appearance of the two last bits are represented in 2's complement and the third one is
of the X and Y operands. The fmal residual W [3], is taken as a represented in the Borrow Save system (B.S). As shown in the
fInal part of the multiplication's result. It is important to note section II.B, with BS representation, number is equal to the
that all the result digits are represented in the redundant form, addition of a positive number and a negative number. The
thus converting them to 2's complement is required. By using schematic block is illustrated on the fIgure 4. This latter,
the on the fly conversion [23] the results digits are converted as contained two stages. The fIrst one is constituted by a carry
soon as they are obtained. save adder (CSA). The second one is constituted by PPM
adders. We noted that this reduction is done in constant time
X3 independently of the operand size used.
Y3 At the iteration G) we obtained result digit Wj, which is
I X1Y1 I Y1 X 2 I Initialisation represented in a BS system. To obtain the result digit in the 2's
I Y 2X 1 I Y2 X 2 I complement representation, two solutions are proposed. The
fIrst one suggests waiting until the reception of all the result
I W1 I W2 I W3 I W4 IW[1] digits then doing the subtraction. This solution, a large delay is
I I I added to the execution time. Since, the final addition requires
R [111 W 2
, W3 W4
X3 *( Y 1 Y2) ,stage1 carry propagation depending on the operands size. The second
solution, is the use of the on the fly conversion [23], which
I Y3*(X1 X2X3) I consists in the conversion of the result as soon as they are
I W2 I W3 I W4 I W5 I W6 IW[2] obtained. This architecture is illustrated in figureS.
I I I stage2
R[2]1 W3 W4 I W5 W6

I x/( Y1Y2Y3) I
I y4 *{ x 1 X 2 x 3 x 4) I
I I I I I I
I+
W[3]1 W3 W4 W5 W6 W7 W 8
~ + + ..... +
I Zl I Z 21 Z3 I Z 4 1 Z5 Z6 I Z7 I ZB I

Figure 2. Execution of the method for n = 4

A. The mathematic formalism of the method

According to the steps of the method defIned above, we
notice that the calculation of Z = XxV comports at each step j,
the computation of the sum noted by W[j] which is equal to
the accumulation of the total residual R[j] with the partials Figure 3. The multiplier Architecture.
products generated at this step. The recurrence equation which
describes this formalism is:

W[O] =0
{ W [1] = X [2] xY [2] (8)
W [j] = 2 x R[j] + T2(Yj x X[j] + Xj x Y[i-I])
o s1-1) riO)s~(O) rin-1) s+(n-1)

With R[j] = W[j] - Wj; and Wj is the most signifIcant digit of

W[i]. Figure 4. The reduction block.
B. Multiplier Architecture
The architecture developed for the proposed method is
composed by tree blocks as illustrated on the fIgure 3. One
block is used for the generation of the partials products,
another to their reduction, and the last to the conversion from
the redundant representation to the 2's complement
 The root of this routing complexity is the insufficient
resources of FPGA and the use of large registers in the on -the
-fly architecture. For example, if we choose the size 256 bits,
the multiplier implementation can't be in the same line of
FPGA. This latter has a limited number of flip-flops which
are disposed like matrix [25]. For the XC2V200-6 circuit the
number of CLBs is 2688 implemented like matrix 56x48. Or
the implementation of the multiplier for 256 bits, we need 512
Flips-Flops for each register. This is larger than the number of
Flips-Flops disposed in the same line which is equal, in this
case, to 440. We have to use others Flips-Flops, so it increases
the routing delay.

V. CONCLUSION
Figure 5. The on the fly conversion architecture. In this paper, we illustrated the on-line multiplication
problem which is located in the selection of the result bit.
Moreover, we demonstrated that this selection probably
IV. IMPLEMENTATION RESULTS can't be done without carry propagate adder. Then, a new
The multiplier architecture presented in this paper multiplication method is presented. This new approach is
was designed using the Xilinx environment used for the multiplication of no redundant numbers. For
Foundation series 7.li. For the description of all the each step, the proposed method consists first, on the
blocks, we employ a VHDL language description. generation of the partials products which are computed after
We have to implement our method for several the reception of the step's inputs. Secondly, the reduction of
operands size, so we describe architecture in generic these partials products is completed using constant time
mode using the parameter n, which characterize the adder. So, the digits results are generated in constant time.
bits number of operands size. To test our method in We conclude that our computation method is suitable for
high precision and study its implementation in the multiplication in high precision. The implementation of
FPGA, we implement four architectures for 128, 256, our multiplier architecture show that for the operands size
512, and 1024 bits. These architectures are simulated more than the number of flips-flops available in the same
with Modelsim PE 6.0. In order to validate the line of the circuit chosen, the on-the -fly conversion (used
simulation result we use the formal tools Maple9.5 for the conversion of the result from the BS form to 2's
[24]. To implement the multiplier architecture we complement) augment the routing delay so the execution
choose one of FPGA circuit: XC2V2000-6(Virtex2 time is delayed. Consequently, the main problem of this
of Xilinx devices). The Table I and Table II, show method is the routing complexity which enlarges the route
the iteration delay and the occupied area for several delay.
operands 128,256,512, and 1024.
These results confirm that the left to right
multiplication is done at constant time. REFERENCES

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