Department of Electrical and Computer Engineering

Delta-Sigma Analog-to-Digital
Converters
From System Architecture to Transistor-level
Design

Vishal Saxena, Boise State University

([email protected])

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -1-

 Delta-Sigma Analog-to-Digital
Converters
Session II Continuous-Time ADCs

Vishal Saxena, Boise State University

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -2-

 Agenda
Fundamentals of continuous-time (CT) ADCs
impulse invariance and CT loop-filter mapping
Inherent anti-alias filtering in CT ADCs
feedback vs. feedforward architectures.
CT ADC non-idealities:
Quantizer Excess loop-delay (ELD)
Clock jitter sensitivity
RC time-constant variation
CT- Design techniques:
NRZ, RZ and switched-capacitor DACs
Active-RC and gm-C implementations
ELD compensation techniques

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -3-

 Continuous-Time Modulators

u(t) Continuous-time fs
yc(t) y[n] v[n]
Loop-Filter
vc(t)
L(s)

DAC

The loop-filter (L(s)) is implemented using continuous-time

circuitry
The modulator is still a discrete-time system
How to design the hybrid continuous- and discrete-time
loop?

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -4-

 Feedback DAC

[n] p(t)

0 n DAC 0 Ts t 0 Ts t 0 Ts t
NRZ DAC RZ DAC SCR DAC

The input to the DAC is a digital code with time-period Ts

The DAC output is an analog waveform
The response of the DAC to the DT impulse, [n], is called
the pulse-shape p(t)
Several choices for p(t)
Return to zero (RZ)
Non-Return to zero (NRZ)
Switched capacitor Resistor (SCR), etc.

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -5-

 Loop Modeling

In general loop-filter is a 2-input, 1-output LTI system

L0(s) is the loop-filter seen by the input signal
L1(s)=L(s), is the loop-filter seen by the feedback signal
The DT loop-response around the ADC-DAC block should
be preserved in the CT loop

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -6-

 Loop Modeling

Set input u(t)=0

Replace ADC-DAC with the linear additive quantization
noise model
Model DAC as a filter with impulse response p(t)
IEEE MWSCAS Aug 5, 2012 Vishal Saxena -7-
 Loop Modeling

Break the loop after the sampler

Apply a DT impulse
The sampled output is lc [n] p(t ) l (t ) |nT
s

The output sequence (lc[n]), should be identical to the DT

loop-filter response l[n] L( z )
IEEE MWSCAS Aug 5, 2012 Vishal Saxena -8-
 Synthesis of CT Loop-Filter

Map the sampled CT loop-response to its DT equivalent

Called Impulse Invariant Transformation (IIT)
lc [n] p(t ) l (t ) |nTs l[n]

NTF(z) is preserved in the DT-to-CT if the transformation is

correctly performed

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -9-

 First-order Example NRZ DAC

Without loss of generality, let fs=1 Hz, Ts=1 s

Sampled loop-response lc[n]={0,1,1,1,1,.}
Identical to the DT loop-response
z 1
L( z )
1 z 1
1
NTF ( z ) 1 z 1
1 L( z )
IEEE MWSCAS Aug 5, 2012 Vishal Saxena -10-
 First-order Example RZ DAC

With RZ DAC, scaling by a factor of k1=2 is need to restore

the loop-response
Can have any number of CT responses to result in the
same DT loop-response
The procedure can be conceptually applied to any other DAC pulse
shape
IEEE MWSCAS Aug 5, 2012 Vishal Saxena -11-
 Second-order Example

NTF ( z ) 1 z
2
1

1 1 z 1 z 1
L( z ) 1 1

1
NTF ( z ) 1 z 1
2
1 z 1 z 1
2

l[n] = {0,1,1,} + {0,1,2,3,} = {0,2,3,4,5}

The loop-response is implemented using a cascade of two
CT integrators
Need to find suitable loop-filter coefficients k1 and k2 using IIT

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -12-

 Second-order Example

l[n] = {0,2,3,4,5}
lc[n] = k1{0,1,1,1,} + k2 {0,1.5, 2.5, 3.5,}
Solving for lc[n]= l[n]: k1=1.5 and k2=1

For NRZ DAC, CT loop-filter, L s 1.5 1

2
s s
Show that for RZ DAC, k1=2.5 and k2=2
IEEE MWSCAS Aug 5, 2012 Vishal Saxena -13-
 Impulse-Invariant Transformation

Impulse-invariant transformation maps DT modulator to CT

l[n] p(t ) l (t ) |t nT
s

Z {L z } L {P( s) L( s)}|t nT
1 1
s

These relations have been derived for standard z-domain

poles
Uses generic rectangular DAC pulse defined by (, ), 0< 1
Tables available for z-domain to s-domain pole equivalence and
vice versa [Cherry]
A DT pole a z=zk transforms to a CT pole at sk=ln(zk) with the same
multiplicity (l)

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -14-

 z-Domain to s-Domain Loop Filter Poles

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -15-

 s-Domain to z-Domain Loop Filter Poles

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -16-

 IIT Example: 2nd-order NTF, RZ DAC
Expand L(z) as pole-form partial fractions

2
1
NTF ( z ) 1 z
2 1
L( z )
z 1 z 12

From the equivalence tables p(t ) , 0,0.5

1 1 1 2

IIT

z 1 s sk s
2
1
1
2


s 1 (2 1.5s)

IIT


z 1
2
s2 s2
Combining the terms, we get
2 2 1.5s 2 2.5s
L( s ) 2

s s s2

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -17-

 Continuous-Time Summary
A DT loop can be emulated using a CT loop-filter
The DT-to-CT transformation depends on the DAC pulse
shape
The transformation can be performed using analytical as
well as numerical methods
This technique can be extended to higher-order NTFs
From the desired NTF(z), find L(z)
Convert L(z) into L(s) using the DAC pulse shape
Schreier Toolbox function realizeNTF_ct can be used for
rectangular DAC pulses
Implement L(s) using a suitable loop-filter topology
A CT modulator has significant advantages over its DT
implementation. stay tuned

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -18-

 Loop-Filter Architectures

Cascade of Integrators with Feedforward Summation (CIFF)

Cascade of Integrators with Distributed Feedback (CIFB)

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -19-

 Resonators for Complex NTF Zeros

j
Complex NTF(z) zeroes, zk e transform into conjugate
loop-filter poles at sk zk j
Here, 123

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -20-

 CIFF Loop-Filter

Integrator unity-gain frequencies 1> 2 > 3

First integrator is the fastest while the last is slowest
Since the first integrator needs to be fastest for noise and
linearity considerations, results in lower power loop-filter
IEEE MWSCAS Aug 5, 2012 Vishal Saxena -21-
 CIFB Loop-Filter

Integrator unity-gain frequencies 1< 2 < 3

First integrator is the slowest while the last is fastest
Not power efficient compared to CIFF

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -22-

 Loop-Filter Time-Scaling

Changing the sampling rate for the normalized design from

1Hz to fs
DAC pulse-shape stretches by Ts
loop-filter scales as
1 f 1
s
s s sTs

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -23-

 Implicit Anti-Aliasing in CT Modulators

Recall that the loop-filter may appear different to the input

signal u(t), and the feedback signal, vc(t).

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -24-

 Implicit Anti-Aliasing in CT Modulators

Re-arrange the blocks

Recall that L1(s)=-L(s) due to the negative feedback inversion

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -25-

 Implicit Anti-Aliasing in CT Modulators

Move the sampler outside the loop

Apply impulse-invariant transformation on the feedback
path Z1{L z } L1{P(s) L(s)}|
t nTs

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -26-

 Implicit Anti-Aliasing in CT Modulators

Transfer function from r to v is given by

1
NTF ( z )
1 L( z )

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -27-

 Implicit Anti-Aliasing in CT Modulators

The input signal is pre-filtered by a CT LPF, L0(s), before

sampling
For an input tone at frequency fin in the signal band
Pre-filtered output before sampling is given by L0(fin)
Due to sampling, a tone at fs+fin can alias at fin
i.e. the first alias-band [fs-fB, fs+fB]
In CT , the alias tone is filtered by L0(fs+fin)

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -28-

 Implicit Anti-Aliasing in CT Modulators

L0 fin
Alias rejection is given by
L0 f s fin

Implicit anti-aliasing due to pre-filtering by L0

Explicit AAF can be eliminated!
Important distinguishing feature of CT
IEEE MWSCAS Aug 5, 2012 Vishal Saxena -29-
 Implicit Anti-Aliasing in CT Modulators

Overall signal transfer function (STF) is given by

STF j L0 ( j ) NTF e j
Signal Transfer Function
100
NTF
L0
50 STF

0
10*log|.|

-50

-100

-150
0 0.5 1 1.5
/

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -30-

 Implicit AAF FF vs FB Loop-Filter
Signal Transfer Function Signal Transfer Function

NTF NTF
40
FF L0
40
FB L0
STF STF
20 20

0 0
10*log|.|

10*log|.|
-20 -20

-40 -40

-60 -60

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1
/ /

Feedforward loop-filter exhibits STF peaking

STF peaking due to zeroes in L0(s)
Zeros at higher frequency flatten | L0(j)| response
For FB, L0(s) has all-pole form
Best STF performance (blocker rejection)
IEEE MWSCAS Aug 5, 2012 Vishal Saxena -31-
 Excess Loop-Delay in CT

Real circuits blocks introduce excess-loop delays (ELD)

Quantizer requires finite regeneration time
ELD due to finite gain-bandwidth of opamps in the loop-filter
DEM/DWA logic in multi-bit adds finite delay
Finite DAC rise/fall time (relatively small)
Important concern in high-sampling rate converters
What effect does ELD have on the loop-response?

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -32-

 ELD First-order Example

fs=1 Hz, ELD due to quantizer delay: 0<Td<1

First sample after unit delay is affected (1-Td)
Resulting DT equivalent loop-response L( z ) z 1 1
T z
1 z 1
d

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -33-

 ELD First-order Example

fs=1 Hz
Sampled loop-response is delayed due to the finite gain-
bandwidth of the opamp
First sample after unit delay is affected (1-Td)

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -34-

 Excess Loop-Delay in CT
NTF with ELD NTF ( z )
1 z
1

1 Td z 1 Td z 2
Order of the loop is increased due to the extra delay
Loop gets unstable at Td=1
NTF peaking as Td increases, leading to modulator becoming more
sensitive and prone to instability

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -35-

 ELD Compensation Basic Idea

Add a direct path (k0) around the quantizer to provide the

first sample l[1]
Here, k0=Td restores L(z)
modulator NTF(z) is restored!
Several other solutions are possible to restore L(z)
IEEE MWSCAS Aug 5, 2012 Vishal Saxena -36-
 ELD Compensation

Normalized ELD due to quantizer delay = Td/Ts=

A direct path around the quantizer (k0) is used to restore
the DT loop-response L(z)
Approach valid for higher-order modulators
For order>1, L(s) is also modified (requires coefficient tuning)
Schreiers Toolbox function realizeNTF_ct
can synthesize CT loop-filters with ELD<1 and rectangular DAC
pulse response.

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -37-

 ELD Compensation

For nth order modulator, the loop-filter coefficients also

need to be tuned. For NRZ DAC: k k k k k n
'
0 1
1
2!
2 n
n!
n
i!
i 1
i i

kn n 1 n ki
k k1 k2
'
i
n 1! i 1 i 1 !
1

kn' kn

Coefficient tuning is better done numerically.

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -38-

 ELD Comp. using DT Differentiator

Proportional path = CT integrator + DT differentiator

Avoids the extra summer at the expense of a register
Scaling factor k k0
a 3

Other variations include k0

ka
Using a (1-z-0.5)differentiator, 23
Can tap first integrator output and perform CT differentiation

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -39-

 ELD Comp. using a PI-Element

Combine the two inner loops into a single PI-element

Note that kb affects other inner loops too
Other coefficients need to be tuned accordingly
Can aggravate STF peaking due to additional zero

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -40-

 Effect of RC Variation
CT- loop-filter coefficients ki are implemented as 1/RC
(or gm/C )
The RC time-constants can vary with process and
temperature by
1% on a single die
20% with from die-to-die
DT- employs implements ki using ratio of capacitors
Much tightly controlled on-chip and hence accurate
What is the impact of RC time-constant variation on CT-
modulator performance?

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -41-

 RC Time-Constant Variation
With an increase in RC time-constant
Coefficients ki decrease ()
Loop-filter Magnitude Response
120
Nominal
Loop-filter bandwidth 100
Smaller RC
Larger RC

In-band loop-gain
NTF OBG 80

In-band quantization noise 60

Magnitude (dB)
Maximum stable amplitude (MSA) 40
More stable but degraded NTF
performance 20

Slower design 0

-20

-40 -2 -1 0 1 2
10 10 10 10 10
Frequency (rad/sec)

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -42-

 RC Time-Constant Variation
With a decrease in RC time-constant
Coefficients ki increase () 120
Loop-filter Magnitude Response

Nominal
Loop-filter bandwidth 100
Smaller RC
Larger RC
In-band loop-gain
NTF OBG 80

In-band quantization noise 60

Magnitude (dB)
Maximum stable amplitude (MSA)
Less stable but more aggressive
40

NTF performance 20

Faster design 0

-20

-40 -2 -1 0 1 2
10 10 10 10 10
Frequency (rad/sec)

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -43-

 RC Time-Constant Variation
Maximally flat 3rd-order NTF with nominal OBG=3
Modulators with 30% RC variation
NTFs
20

-20
dBFS

-40

-60

-80 Nominal Loop

Fast Loop
Slow Loop
-100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
/

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -44-

 RC Time-Constant Variation
Maximally flat 3rd-order NTF with nominal OBG=3, nLev=23
Modulators with 30% RC variation

1 1

0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0 0

-0.2
-0.2

-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
0 50 100 150 200 250 300 350 -1
0 50 100 150 200 250 300 350

Nominal Loop Fast Loop

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -45-

 Clock Jitter in DT-

DT- the input is sampled before the modulator loop

Assume white clock jitter with RMS value j
RMS jitter noise in the signal band: j Ain
OSR 2
Clock jitter limited SNR:

SNR j 20 log10 2 fin j OSR

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -46-

 Clock Jitter in CT

The input signal is sampled inside the modulator loop

Clock jitter affects both ADC decisions as well as the DAC
output

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -47-

 Real Quantizer with Jittery Clock

ADC samples and quantizes CT input yc digital output v[n]

ADC regeneration time - Td
DAC reconstructs samples of v[n] into CT output vc
DAC is clocked with a delay to capture the ADC output
Both ADC and DAC clocks have jitter

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -48-

 ADC Sampling Jitter

ADC sampling jitter is modeled as AWGN

Noise due to sampling jitter is shaped by the loop (NTF)

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -49-

 DAC Reconstruction Jitter

DAC reconstruction error (ej2) follows the DAC

Directly adds to the input
Major contributor of jitter induced noise

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -50-

 DAC Output Waveforms

v[n] n

vc(t)
v[n] DAC vc(t) NRZ DAC t

CLK

vc(t)
RZ DAC
t

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -51-

 Jitter Induced DAC Error- NRZ
v[n]
Ideal
Jittery NRZ DAC v[n-1]
v[n+1] NRZ DAC
Output
Output
t
v[n]
v[n-1]
v[n+1]
(v[n]-v[n-1])tn
t

t DAC Error

(v[n+1]-v[n])tn+1

Error depends on the transition height v[n]-v[n-1]

Granularity of LSB size
Multi-bit NRZ DACs have lower jitter induced error

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -52-

 Jitter Induced DAC Error- RZ
v[n]
Jittery RZ DAC
Output v[n-1] Ideal
v[n] v[n+1] RZ DAC
Output
v[n-1] t

v[n+1]

2v[n]tn 2v[n]tn+1/2
t

DAC Error
t

Error depends on twice the pulse height 2v[n]

Two transitions per time period
RZ DACs are much more sensitive to clock jitter

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -53-

 Jitter Noise with NRZ DAC
tn t
Error due to jitter e j [n] v[n] v[n 1] v[n] n
T T
2t

2
ej
2
v
Ts2
Modulator output variance (neglecting slowly varying input)

2
LSB
2
2v 1 e
j
NTF (e j ) d
0

In-band jitter noise

2T 2
LSB
2
J
T 2
s

OSR 1 e NTF (e )
j j
d
s 0

depends upon the area of differentiated NTF response

NTF behavior at higher frequencies determines most of J
T
To reduce J: OBG, VLSB , , OSR s

Ts

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -54-

 SCR DAC for Lower Jitter Noise
v[n]
Jittery SCR DAC
Output
v[n-1] Ideal
v[n]
v[n+1] Output

v[n-1]
v[n+1]

DAC Error

Use sloping DACs to reduce the error due to jitter

Switched-cap resistor DAC (SCR), cosine-shape, etc.
More stringent requirements on the opamp performance
Possible linearity and AAF degradation

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -55-

 CT Implementation
1 Active-RC Gm1
Gm-RC
sR1C1
R1 C1 sC1
vom vom
vip vim
Gm1 C1
vim
vop vip vop

I1
I1
sC1

IDAC
IDAC

sC1
I1 I1

vvp vvm vvp vvm

CT Integrators used as the loop-filter stages

Active-RC, Gm-C, Active Gm-C, Active-MOS-C, Current-mode
integrators, log-domain integrators
Active-passive Hybrid stages can alternate
IEEE MWSCAS Aug 5, 2012 Vishal Saxena -56-
 CT Implementation
Active-RC Gm-C
Linearity p r
Power consumption r p
Frequency range r p
Tunability r p
Dynamic Range p r
Voltage headroom p r
Parasitic Sensitivity p r
Realization of FF Summation r p

Overall Active-RC preferred for superior dynamic range in CT

designs
Active-RC with two- or higher stage opamp for better linearity

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -57-

 Loop-filter Coefficient Tuning
Sampled integrator and loop-filter outputs
20
l0
u=0
L0 Discrete Time
l1
l[n]
Loop Filter
(n) v L(Z)
l2
15
L1
l3
n
yc

10
L0
Continuous Time lc(t) l[n]
Loop Filter
(n) L(s)
L1
1+ 5
p(t-)
DAC pulse shape Direct path
k0
0

k0 0 1 2 3 4 5 6 7 8
l0(t)

fs
(n) l1(t) l2(t) l3(t) lc(t) l[n]
1+
I1(s) I2(s) I3(s) k3
p(t-)

k2

k1

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -58-

 Loop-filter Coefficient Tuning
Loop-filter coefficients are typically determined using the Schreier's
Toolbox
using impulse-invariance transformation tables is unwieldy for higher-
order modulators and with ELD

Solved using LMS data fitting for N samples (pseudo-inverse)

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -59-

 Problems with Coefficient Tuning
Practical integrators are implemented using opamps
finite opamp gain (AOL) and unity-gain bandwidth (fun), and with extra
poles and zeros.
The excess loop-delay due to finite fun causes significant amount of
gain peaking in the resulting NTF.
Coefficient tuning yields different results depending on the number of
samples used for LMS fitting.
tuning is numerically unstable 2.5
NTFs

higher OBG leads to instability in the modulator

2

1.5

dBFS
1

Ideal
0.5 Real Integrator
N=5
N=20
N=50
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
/

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -60-

 Systematic Design Centering
Instead of fitting the open-loop response, fit NTF(z)(1+L(z)) to 1
h[n] h[n] l[n] [n] h[n] Z 1 ( NTF ( z ))

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -61-

 Systematic Design Centering
The loop-filter coefficients are
tuned to compensate for the
excess loop delay due to the op- NTFs
1.6
amps and the quantizer delay
1.4

NTF response with non-ideal 1.2

integrators is close to the ideal 1

NTF

dBFS
0.8

0.6

The NTFs are indistinguishable for 0.4

Ideal
any value of N=5,20,50 0.2
N=5
N=20
N=50

Coefficient tuning is numerically

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
/
stable

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -62-

 Feedback DAC Architecture

Loop-Filter

u
v
DACim DACip

Thermometer coded v

b0ILSB b1ILSB bN-1ILSB

Array of unit-weighted current steering DACs to pull and

push current from the opamp current summing node
Use high crossover pre-drivers to reduce DAC glitching
noise

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -63-

 Feedback DAC Nonlinearity

In a multibit DAC, element mismatch leads to non-

linearity
v is related to the input (u) by inverse non-linearity of the DAC
A single-bit DAC is always linear

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -64-

 Feedback DAC Nonlinearity

Leads to distortion
intermodulation of quantization noise into the signal
band

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -65-

 Dynamic Element Matching (DEM)

u(t) fs
v[n]
vc(t) L(s)

DAC Scrambler

PN Sequence

Randomize the DAC elements

Distortion components
converted to noise
Increased noise floor

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -66-

 Data Weighted Averaging (DWA)
Cycle through all the current elements Thermometer-Coding

as fast as possible 15

Accumulate the input code and move the10

pointer
First-order mismatch noise shaping 5

0
0 10 20

First-Order Shaping
15

10

0
0 10 20

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -67-

 Data Weighted Averaging (DWA)

N=2B

u(t) fs
v N Thermometer
vc(t) L(s) to Binary

B
Accumulator

Barrel N
DAC Shifter

Barrel shifter delay in the signal path increases loop delay

Not viable at higher sampling rates (>400 MHz)

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -68-

 DAC Calibration

Digital calibration estimate element error and subtract from the

output
Increased Decimation filter complexity
Analog calibration calibrate the elements with respect to a master
Need to calibrate at every cycle

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -69-

 CT Advantages Summary

Lower-power implementation
Relaxed bandwidth requirements for the integrators
Inherent Anti-aliasing filtering (AAF)
Eliminates/relaxes input filtering
Fixed resistive input impedance
Higher sampling-rates extending to GHz-range
Suitable for RF integration
Reduces supply and ground noise impact
Less complicated clocking (compared to DT)

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -70-

 CT Challenges Summary
Complicated design due to hybrid CT-DT modeling
Design doesnt scale with clock frequency
Loop-filter coefficient tuning for clock frequency migration
High sensitivity to clock jitter (DAC reconstruction error)
Excess loop-delay sensitivity
Tuning required for RC time-constant variation
Sensitive to DAC pulse shape, rise/fall time at high-speeds
Comparator metastability at high speeds
Higher-level simulation is challenging compared to DT
Cascaded (MASH) designs are difficult due design
complexity and mismatch in analog and digital transfer
functions
Background calibration techniques

IEEE MWSCAS Aug 5, 2012 Vishal Saxena -71-

 Design Tools
MATLAB and Simulink
Dr. Richard Schreiers Toolbox
SIMSIDES Toolbox from Dr. Jose de la Rosa at University of Seville,
Spain (Available under NDA)
Verilog-A/AMS behavioral modeling in Cadence/Spectre
Config view in Virtuoso comes in handy for simulations
Spectre Simulink Co-simulation Toolkit
Berkeley Design Automation FastSpice for full-chip sims
Synopsis tools for digital logic simulation and synthesis
Mentor Graphics Calibre for DRC/LVS/Extraction

Use top-down design methodology with carefully thought mixed

block-level simulations

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 References
Data Conversion Fundamentals
A.1 M. Gustavsson, J. Wikner, N. Tan, CMOS Data Converters for
Communications, Kluwer Academic Publishers, 2000.
A.2 B. Razavi, Principles of Data Conversion System Design, Wiley-IEEE Press, 1994.
A.3 ADC and DAC Glossary by Maxim.
A.4 B. Murmann, "ADC Performance Survey 1997-2009," [Online].
A.5 S. Pavan, N. Krishnapura, EE658: Data Conversion Circuits Course at
IIT Madras [Online].
A.6 The Fundamentals of FFT-Based Signal Analysis and Measurement, T.I. App Note here.

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 References
Delta-Sigma Data Converters
B.1 R. Schreier, G. C. Temes, Understanding Delta-Sigma Data Converters,
Wiley-IEEE Press, 2005 (the Green Bible of Delta-Sigma Converters).
B.2 S. R. Norsworthy, R. Schreier, G. C. Temes, Delta-Sigma Data Converters:
Theory, Design, and Simulation, Wiley-IEEE Press, 1996 (the Yellow Bible of
Delta-Sigma Converters).
B.3 S. Pavan, N. Krishnapura, Oversampling Analog to Digital Converters
Tutorial, 21st International Conference on VLSI Design, Hyderabad, Jan,
2008.
B.4 S. H. Ardalan, J. J. Paulos, An Analysis of Nonlinear behavior in Delta-Sigma
Modulators, IEEE TCAS, vol. 34, no. 6, June 1987.
B.5 R. Schreier, An Empirical Study of Higher-Order Single-Bit Delta-Sigma
Modulators, IEEE TCAS-II, vol. 40, no. 8, pp. 461-466, Aug. 1993.
B.6 J. G. Kenney and L. R. Carley, Design of multibit noise-shaping data
converters, Analog Integrated Circuits Signal Processing Journal, vol. 3, pp.
259-272, 1993.
B.7 L. Risbo, Delta-Sigma Modulators: Stability Analysis and Optimization,
Doctoral Dissertation, Technical University of Denmark, 1994 [Online].
B.8 R. Schreier, J. Silva, J. Steensgaard, G. C. Temes,Design-Oriented Estimation
of Thermal Noise in Switched-Capacitor Circuits, IEEE TCAS-I, vol. 52, no.
11, pp. 2358-2368, Nov. 2005.

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 References
Continuous-Time Delta-Sigma Converters
C.1 M. Ortmanns, F. Gerfers, Continuous-Time Sigma-Delta A/D Conversion:
Fundamentals, Performance Limits and Robust Implementations, Springer, 2006.
C.2 J.A. Cherry, Theory, Practice, and Fundamental Performance Limits of High-Speed
Data Conversion Using Continuous-Time Delta-Sigma Modulators, PhD
Thesis, Carleton University, 1998 [Online].
C.3 K. Reddy, S. Pavan, Fundamental Limitations of Continuous-time Delta-Sigma
Modulators due to Clock Jitter, IEEE TCAS-I, vol. 54, no. 10, pp. 2185-2194, Oct.
2007.
C.4 S. Pavan, N. Krishnapura, R. Pandarinathan and P. Sankar, A Power Optimized
Continuous-time Delta-Sigma Modulator for Audio Applications, IEEE JSSC, vol. 43,
no. 2, pp. 351-360, Feb. 2008.
C.5 S. Pavan, Excess Loop Delay Compensation in Continuous-time Delta-Sigma
Modulators, IEEE TCAS-II: Express Briefs, vol. 55, no. 11, pp. 1119-1123 , Nov.
2008.
C.6 Z. Li, T. S. Fiez, A 14-bit Continuous-Time Delta-Sigma A/D Modulator with 2.5 MHz
Signal Bandwidth, IEEE JSSC, vol. 42, no. 9, pp. 1873-1883, Sept. 2007.
C.7 S. Pavan and N. Krishnapura, Automatic Tuning of Time-Constants in Continuous-
Time Delta-Sigma Modulators, IEEE TCAS-II: Express Briefs, vol. 54, no. 4, pp. 308-
312, Apr. 2007.

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 References
Continuous-Time Delta-Sigma Converters
C.8 Krishnapura, N. Singh, V. and S. Pavan, "Compensating for Quantizer Delay in Excess
of One Clock Cycle in Continuous-time Delta-Sigma Modulators," in Circuits and
Systems II: Express Briefs, IEEE Transactions on, vol. 57, no. 9, 2010, pp. 676-680.
C.9 M. Ortmanns, F. Gerfers, and Y. Manoli, "Compensation of Finite Gain-Bandwidth
Induced Errors in Continuous-time Sigma-Delta Modulators," IEEE Transactions on
Circuits and Systems I: Regular Papers, vol. 51, no. 6, pp. 1088-1099, 2004.
C.10 S. Pavan, "Systematic Design Centering of Continuous-time Oversampling
Converters," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no.
3, pp. 158-162, 2010.
C.11 S. Pavan and N. Krishnapura, "Automatic Tuning of Time Constants in Continuous-
time Delta-Sigma Modulators," IEEE Transactions on Circuits and Systems II: Express
Briefs, vol. 54, no. 4, pp. 308-312, 2007.
C.12 G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, "A 20-
mW 640-MHz CMOS Continuous-Time SigmaDelta ADC With 20-MHz Signal
Bandwidth, 80-dB Dynamic Range and 12-bit ENOB," IEEE Journal of Solid-State
Circuits, vol. 41, no. 12, pp. 2641-2649, 2006.
C.13 Y. Ke, J. Craninkx, and G. Gielen, "Multi-standard Continuous-time Sigma-Delta
Converters for 4G Radios," Circuits and Systems for Future Generations of Wireless
Communications, pp. 203-221, 2009.

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 References
CAD for Mixed-Signal Design
D.1 K. Kundert, Principles of Top-Down Mixed-Signal Design, Designers Guide
Community [Online].
D.2 R. Schreier, Matlab Delta-Sigma Toolbox, 2009 [Online], [Manual], [One page
summary].
D.3 Jose de la Rosa, SIMSIDES Toolbox: An Interactive Tool for the Behavioral
Simulation of Discrete-and Continuous-time SD Modulators in the MATLAB,
University of Sevilla, Spain, [Contact the authors for the software].
D.4 P. Malcovati, Simulink Delta-Sigma Toolbox 2, 2009. Available [Online].
Example Datasheets
E.1 A 16-bit, 2.5MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time
Sigma-Delta ADC AD9262, Analog Devices, 2008.
E.2 A 24-bit, 192 kHz Multi-bit Audio ADC CS5340, Cirrus Logic, 2008.

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