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| : 2017 MADE EASY Analog Electronics + Digital I Workbook Electronics + Microprocessors (Z Onlenics Digital Electronics. Section-B Unit Number Systems and Binary Codes... Boolean Algebra, Logic Gates and K-Maps Combinational Logic Circuits. Sequential Circuits. Semiconductor Memories am a wD Integrated-Circuit Logic Families 7. ADCand DAC Section-C: Microprocessors. 0000 | © Copii Subject mater to MADE EASY Publications, New Dei. No partcfhis book may be reproduced o utlsedin any form whut the writen permission. Chapter-1 : Introduction © Boolean Algebra: * Boolean basic operators = Basic logic gates * Boolean algebra * Sum of product and Product of sum from Truth table Minterms and Maxterms Literal and variables Derived operators Simplification of boolean functions and ‘equations using properties Universal logic gate * Simplification and equality properties on EX-OR and EX-NOR * Radix based number systems - Standard number systems "Conversion decimal number to any radix number, any radix number to decimal nufnber + (1 1)'s and r's complements - their requirements * Signed binary number representation sign magnitude, signed 1's and signal 2's complement range of number in various representation problems. © K-Map: * Definition of irredundant and minimal expression = Necessity of kmap kemap on 2, 3 and 4 variables * Definition of implicant, prime implicant and essential prime implicant + Finding prime implicant and essential prime implicant * Finding minimal expressions using k-map SOP and POS = Don't care combinations definition and problems. ‘© Copyright “MADE EASY Digital Electronics Description Sheet = Five variable k-map * Objective type question * Conventional questions Chapter-2 : I Circuits ‘© Combination Circuits: = BCD codes: Weighted and non-weighted codes, self complementary codes, reflective codes * Code conversion: => BCD to Excess-3 => Excess-3 to BCD = Binary to gray = Gray to binary =: Any weighted BCD to natural BCD codes © Arithmetic Circuits: + Half-adder, Full-adder, Half subtractor, Full subtractor = Binary adder = Serial adder = Ripple carry adder = Carry look ahead adder = Binary subtractor: Problems with 1's and 2's complement, advantage of 2's complement + 4bit binary adder and binary subtractor circuit "BCD to Excess-3 and Excess-3 to BCD circuit "BCD adder and subtractor circuit design + Binary comparator circuit * Multiplexer: * MUXcircuit with logic gates - Active low and Active high enable "Different applications of MUX’s "Realizing functions using MUX * Analysis of MUX problems * Decoder/DE-MUX circuits and their applications * Encoder and priority endoders wwwmadeeasypublications.org 52 Chapter-3 : Sequential Circuits (wwwmadeeasypublications.org Electrical Engineering © Digital Electronics Flip-Flops: Binary latch and S-R and J-K flip-fiop circuits with NAND gates : Truth table, characteristic table, excitation table, affect of clear and preset input HI Race around condition and its solution Master slave J-K flip-flop DandT flip-flop State diagram of flip-flop General procedure for converting one flip- flop to another flip-flop Analysis of fiip-“lop circuits for finding truth table, characteristic equation, excited table Registers: SISO, SIPO, PISO and PIPO operations and timing diagrams Universal shift registers Application of shift registers Asynchronous counter: Difference between asynchronous and ripple’ counter Mbit ripple up/down counter with timing diagram MOD-N counter: Ripple counter design using clear and preset terminals ‘Synchronous counter: Design procedure for simple sequence and fegular sequence Analysis of synchronous counter state diagram Finite state machine: Moore and Mealey machines ‘Sequence detector problems Chapter-5 : Logic Fami MADE EASY MADE ERSY Chapter-4 : Semiconductor Memories * ROM, SRAMand DRAM circuits and differences = PLD, PLA, PAL = Combinational circuit design using PLOs = Combinational circuit design using ROM, PLAand PAL S * DTL, TTL, NMOS and PMOS, CMOS Logic families © Characteristic of logic IC's © Comparison between logic families + Numerical problems Chapter-6 : Converters * DtoA converter: * Weighted registers * R.2Rand inverse R-2R * AtoD converter * Comparator type * Successive approximation type * Counter type "Dual slope © Numerical problems © Copyright Number Systems and Binary Codes ¢ Q.7 Which of the following represents 'E3,_'? 1CE) 5+ (A2), Multiple Choice Questions | {3} “CD :+ 426 EZ] ©) (BC) .-(Ehe & (0) (2BC),5~(1DE) sg Q.1. What are the values respectively, of A, and A, | ©) (200};5-(11D),g. [ESE-2002] inthe expression (235)m, = (565);9= (1065)2? | | @.8 Which of the following subtraction operations @) 8,16 (b) 16,8+ g resultin Fig? ©) 6.16 () 12.8 § 1. (BA)sg- (AB) ig TESE-2004(EE)] | @ 2 (BC)i5~(CB)ig 2 me & 3. (CB),_-(BC), Q.2 )(2)5 + (3), = (7) & he Ne ae eo (My on g Select the correct answer using the code given a below: (c) None of these + (d) Not possible g (@) Onlytand2 (b) Only 1and3 Q.3° Convert the octal number 127543 into the | (©) Only2and3 (d) 1,2and3 hexadecimal form z [ESE-2006] (a) AFeS. (b) AF53 e Q.9 The binary equivalent of hexadecimal number (©) AFD3, (@) BCDS Z Fan. g (a) 0101 11110010 1100 Q4 If (11x1y)y = (12C9),5 then the values x and y | 5 (b) 0100 1111 0010 1100 are F (c) 0100 11100010 1101 a (@) 3and1. (0) Sand7 a (d) 0100 1111 0010 1101 [ESE-2002] Oven eins sane : Q.10 (FE35),XOR(CB15),, is equal to g (@) (3320),¢ (0) (FF35),5 QS I(23)o50 4+ (1-2)oase 4 = Woase si What is the | £ (©) (FF50)j5 (A) (3520),5 value of y? & [ESE-2000) (@) 104 - (b) 10.01 3 (© 102 (a) 1.02 3] 0.11 F's complement of (2BFD) yo, (8 [ESE-2005] | § (@) £304 (b) D403 g (©) D402 (@) C403 [ESE-2001] Q.6 How many 1’s are present in the binary |F representation of ‘ ‘The 2's complement representation of -17 is (4 x 4096) + (9 x 256) + (7 x 16) +5? 3 (@) 101110 oy al (@ 8 () 9 3 (c) 111110 (@) 110001 © 10 (@) 11 [ese-2004) | 8 [GATE-2001] © Copyright MADE EASH www madeeasypublications.org 54 | Electrical Engineering Q.13 The 2's complement representation (-539),, in hexadecimal is (a) ABE (b) DBC (©) DES (@ 9E7 — [@ATE-2001] Q.14 In signed magnitude representation, the binary equivalent of 22.5625 is (the bit before comma represents the sign) (@) 0, 10110.1011 (©) 1,10101.1001 (b) 0,10110.1001 ~ (d) 1, 10110,1001 [ESE-2002] CR 11001, 1001 and 111001 correspond to the 2s ‘complement representation of which one of the following sets of number? (@) 25, 9and 57 respectively (0), -6, -~6 and -6 respectively ~ 40) -7,-7 and-7 respectively (0) -25,-9 and -57 respectively [GATE-2004] range of signed decimal numbers that can be represented by 6-bit 1's complement number's @ -31t0+31. (b) -63to + 63 (©) -64t0+63 (0) -32to +31 IGATE-2004] Q.17 Which of the following statement is Incorrect for the range of nits binary numbers (@) Range of unsigned numbers is 0 to (2"— 1) (©) Range of signed magnitude number is = (92"-1— 1) to (271-1) Je} Range of signed 1's compliment numbers. is (-2"-" + 1) to (27-1) (@) Range of signed 2's compliment numbers is (-2°-1) to (2"-1-1) Q.18 Anumberin 4-bit2s complement representation is X,XpX, Xp. This number when stored using &-bits will be (@) 0000 X,X,X,Xq (©) 1111.X5X5X;j Xp RPK Xa Xa Ma Xo Xo Xs Xo © Digital Electronics ° 3 z SON jo poanpaidei aq few 4000 5) MADE ERSY (@) 0001 - (©) 0010 (© 1101 (d) cannot be expressed in 4-bit 2's complement [GATE-IN:2003] Q.20 Which of the following is an invalid state in 8-4-2-1 Binary Coded Decimal counter (@ 1000 () 1001 (90011 () 4,100 [GATE-2014] Q.21 The BCD code for a decimal number (874) 9 is 2) (100001110100) (©) (010001111000) 5 (©) (100001000111) se (6) (011110000100) ge [ESE-2012] Q.22 Adecimal number 6 is written in excess-3 code as @ o110 (©) 1101 (b) 0011 (@) 1001 « Q.23 Which of the following weighted code will give 9's complement by changing (complementing) each individual bit? (@) Excess-3 (o) 5421 (©) 2aety = (@) Both (a)and(c) Q.24 Whatis the Gray code word for the binary binary 1010117 (a) 101011 (©) 110101 (©) o1nttt (@) 111110 [ESE-2006] Numerical Data Type Questions eS) The minimum decimal equivalent of the number 11C.0is__. (B) 1X5 X3X3X5XXj Xp [GATE-1999] (ESE 2000} Q:19 Two 4-bit 2s complement numbers 1011 and | # / @.26 The decimal equivalent of hexadecimal number 0110 are added. The result expressed in 4-bit | 3 of 2AOF is 2's complement notation is [ESE-2002(EE)] ‘(wwew.madeeasypublications.org MADE EASY ©Copyright MADE EASY Q.27 The decimal equivalent of binary number 10110.11 is Q.28 Ina particular number system having base B. (Vata = Q.29 (-64),. + (80),g= (20 10» The value of *B" is [ESE-2007] 2.80 Given (135)oasox + (144)oae0x= (B2easex The value of base x is [ESE-2005) 33) 2's complement representation of a 16-bit number (one sign bit and 15 magnitude bits) is. FFFF. Its magnitude in decimal representation [GATE-1993] Q.32 A number is expressed in binary two's complement as 10011. Its decimal equivalent value is . [ESE-2002] Q.33 (X), s expressed in gray code as (11110),. The value of X is, os Q.34 Consider a system which has two eight bit inputs D, = 01010101, D, = 00000000, the system produces eight bit output that is bitwise XOR of the inputs. The eight bit output of the system is input to the Gray Code Converter, the decimal equivalent of the output from Gray Code Converter is___ rhs Q.35 The 16-bit 2's complement representation of an integer is 1111 1111 1111 0101; its decimal representation is__. \\ [GATE-2016] £ Try Yourself T1. Find the value of x. (135), + (144), = (214), ev Ans: x = 7] T2, Consider the addition of numbers with different bases ©Copyright ° 8 3 2 5 g (00 men $00 “hae uy postin 70 paanpordes eq Kew you sin 118d ON ‘Uojsejaed vanum exp OLA Ua 3. 14. 15. 6. MADE EASS Workbook | 55 ,+ (p+ (Myo + (Zs = (Ky 1fX=36, Y= 67, W=98 and K= 241 then find the value of Z. [Ans: 34] For radix r, decimal value of (110), is 4rthen ris, and decimal value of (010), is _ lf (10), x (10), = (100),; (100), x (100), = (10000), then x can take value: 2 (©) 10 (b) 5 () Allof these Consider the equation (123), = (x8), with and 88 unknown. The number of possible solutions is [GATE-2014, Ans: (3)] IF73, (in base-x number system) is equal to 54, (in base-y number system), the possible values ofxandy are (@) 8,16 (&) 10,12 (c) 9, 13 (d) 8,11 IGATE-2004, Ans: (d)] Consider the following multiplication (1012), x (15);9 = (¥0101 1001), Which one of the following gives appropriate values of w, yand z? [ESE-2004(EE)] Identify the correct statement with respect to following circuit? Numbers are represented in signed magnitude format. % % % % ‘Abit parallel Aidor } z(sbitabp) 56 19. T10. @ T13. Electrical Engineering © Digital Electronics (@) Itoutputs x + y (b) It outputs y—x (©) Itoutputs x + 1 (d) It outpus y +1 ‘An equivalent 2's complement representation of the 2's complement number 1101 is (@) 110100 (©) 001101 (© 110111 (d) 141101 [GATE-1998, Ans: (d)] ‘Twos complement format of + 127 is (@) o1tttt41 (’) 10000000 (©) 01101101 (a) 10010010 [Ans: (a)] ‘The number of 1's in 8-bits representation of ~127 in 2's complement form is m and that in 1's complement form is n. What is the value of m/n? [ESE-2005] The range of integers that can be represented by an n-bit 2's complement number system is (@) -2"to (2-*- 1) (b) ~(2”-*— 1) to (2"-*- 1) (©) 42m" +1) 10.2%" (0) 42"-" + 1) to (2-1-4) [ISRO-2009, Ans: (a)] MADE EASY system H dy “H % 4} 8ystem|~| system} —jsystem! —O ue nos s Hs bo 4 os lithe applied input (Z, J, 1, J5)is 1010, then what is the output (Q, 0,0, Op) [Ans: 1101] 14. The circuit shown in the figure converts INPUTS use. outputs. (@) BCD tobinary code (b) Binary to excess - 3 code (c) Excess - 3 to Gray code (6) Gray to Binary code . j0 Wed ON “Wleq MON “SUONBOIIana ASV SOWA 01 JoHeus Taalang AuBuAdoD © 115. Thecircuitshown below converts. (here ® is XOR) 79 peonpoido1 eq few Wood S) Js dy 4 ty Consider a System S as shown in the figure . below: | ——=— bila I ts a % t compiment |_| corpinent % | 4 % % 9, % ‘System Sperforms 1's compliment of the input and then 2's compliment to produce output. ‘Anew System His designed in which 3 System Sare cascaded. Ze) Binary to gray (b) Binary to Excess 3 (©) Excess 30 gray (@) Gray to binary 116. Write gray code for binary numbers from 0000 tot ‘o|ss|uied Uarium ou) OUIM wo) ABR ui E Ensy Publication Boolean Algebra, Logic Gates and K-Maps [¥42{¥ (2+ x1) {8 + 2004 YY} = tthen ‘The Boolean expression ABCD + ABCD + ABCD + ABCD is equivalent to @A (bo) AC (© ABC 1 [ESE-2008] If xand y are Boolean variables, which one of the following is the equivalent of x ® y@ xy? (@ x+y () 0 ) x+y @1 [ESE-2004(EE)] The Boolean expression YZ+XY+XZ is logically equivalent to @) yz+X (0) X¥Z+XVZ+XVZ4XVZ (©) XYZ+XVZ () XV4 YZ+ XZ The total number of Boolean functions that can be constructed for n Boolean variables is fan (b) 2" (©) yr (a) 2" [DRDO-2009] With 4 Boolean variables, how many Boolean expressions can be formed? * @ 16 (b) 256 (©) 1024(1k) —(d) 64K (64x 1024) [ESE-2002] Q.10 Consider the statement below: eee qe 2/5 Multiple Choice Questions | | = g Q.1 The precedence order while solving Boolean |= expression is z (@) ()NOT> AND > OR : (&) ()NOT>OR 8 Q.2 What logic gate is represented by the circuit | ‘shown below? zlaz g z 4 Bub z A @ (a) AND (>) NAND. g (©) NOR (@) EQUIVALENCE Her Q3 The expression A+ AB is represented by | a @/@® fol) ft glas © @ 5 @]°[(@] Q.4 IfX=1 inthe logic equation i 2 £ i 3 é 8 ©Copyright 1. If the output waveform from an OR gate is @ ¥=Z (oe) Y=Z the same as the waveform at one of its (c) Z=0 (d) Z=1 inputs, the other Input is being held [GATE-2009] permanently LOW. MADE ERSY www.madeeasypublications.org | Electrical Engineering 58 2. Ifthe output waveform from an OR gate is always HIGH, one of its input is being held permanently HIGH. ‘The statement, which is always true, is (@) Both and2 (b) Only 1 (©) Only2 (2) None of these Q.11 If the output of a logic gate is ‘1’ when all its inputs are at logic ‘0’, the gate is either (a) ANAND or ANOR (b) ANAND or an EX-NOR (c) AnOR oranNAND (@) ANEX-ORoranEX-NOR — [ESE-2014] Q.12 Which one of the following statements is correct? For a 4-input NOR gate, when only two inputs are to be used, the best option for the unused | inputs is to (@) connect them to the ground (©) connect them to Vag (c) keep them open (d) connect them to the used inputs [ESE-2004(EE)] Q.13 How is inversion achieved using EX-OR gate? (@) Giving input signal to the two input ines of the gate tied together. (b) Giving input to one input ine and logic zero to the other line. (©) Giving input to one input line and logic one to the other line. (d) Inversion cannot be achieved using EX-OR gate. [ESE-2002] Q.14 Consider: Y =A@A@A®BADAGAGAGABAIHEY is equivalent to: (@) 10RE (b) AEXORO (©) 1NORB (d) AANDA Q.15 The function f=(ABC + ABC + ABC +ABC)@ A can be written as: (a) B@C (b) A@BOA OA (@) None of these ‘www.madeeasypublications.org Hs © Digital Electronics e 3 TON Wi 29 peanpardel eq Kew 3008 5 jad uorium eu anouiim wi0y Aue wpe MADE EASY MADE EASY Q.16 [(A+ AB\(A + AB)]+[(CD + CD) +(C @ D) @) B (b) A (0 (1 Q.17 Statement (|): XOR gate is not a universal gate. Statement (II): It is not possible to realize any Boolean function using XOR gates only. (@) Both Statement (I) and Statement (II) are individually true and Statement (Il) is the correct explanation of Statement (I). (©) Both Statement (I) and Statement (Il) are individually true but Statement (II)is not the correct explanation of Statement (I) (©) Statement (|) is true but Statement (II) is false. (d) Statement (|) is false but Statement (II) is true. [ESE-2012] Q.18 All the logic gates in the circuit shown below have finite propagation delay. The circuit can be used as a clock generator, if >be ey x! (@) X=0 (b) x: (©) X=0ort @) X= [GATE-IN:2006] Q.19 The logic circuit of figure is a A in y @ Haltadder () XOR (c) Equality detector (d) NAND [GATE-2003] Q.20 If avariable is having Ex-OR operation itself 'n’ number of times, then the result is (2) Complement of variable if ‘n’ is even. (0) Uncomplement of variable if ‘nis even. (c) Complement of the variable ifn’ is odd. (@) Uncomplement of the variable if ‘nis odd, © Copyright su /An odd function involving three Boolean variables is @ £(1,3,5,7) (©) 2(1,2,4,7) (b) £(0,2, 4,6) () £(0,3,5,6) [DRDO-2009] Q.22 Black box inverts the phase of input V when control'A’ is 1 and lets it pass through uninverted, when control ‘A’ is 0 then circuit is | \" ay aca (a) XNORgate — (b) XOR gate (c) NANDgate — (d) NORgate Q.23 For the logic circuit shown in figure below, the output 'Y’ is equal to D> L_¢p-—! (@) AB+BC+5+C (6) AB+BC (©) A+B+E (d) Allof these Q.24 What's the boolean expression for the output f of the combinational logic circuit of NOR gates given below? P @ @ : De Pp R @ R (@) GR (&) P+Q () P+R @) P+O4R [GATE-2010] Q.25 In the circuit shown in the figure, if C=O, the expression for Yis © Copyright. jang Asva aavi o) anew Toolans wWBUAdOD @ Te peonpoide: oq Kew yoog aiui Jo 8d ON TuleG MON “SU MADE EASY Workbook 59 co A a y ast a (@) Y=AB+AB (b) Y=A+B () Y=A+B (d) Y=AB IGATE-2014] Q.26 Identify the logic function performed by the circuit shown re oo) A yo (@) Exclusive OR (b) Exclusive NOR (©) NAND (@) NOR [GATE-1993] Q.27 Consider thefollowing circuitcomposed of XOR gates and non-inverting butters. A 8 ADP B=2ne > Be dns ‘The non-inverting buffers have delays d, = 2ns and d, = 4.nsas shownin the figure. Both XOR gates and all wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0 at time 0. If the following waveform is applied at input 4, how many transition(s) (change of logic levels) occur(s) at Bduring the interval from 0 to 10 ns rt a Timea 1.23 4 5 6 7 8 8 10 tins (a1 (bo) 2 © 3 @) 4 [GATE-2003] 2s) 1 gates G, and'G, in the figure have Propagation delays of 10nsec and 20 nsec respectively. If the input V, makes an abrupt wwwimadeeasypublications.org Electrical Engineering @ 60 change from logic Oto 1 at time t = fy, then the output waveform V, is e (t= § + 101s, t= t+ 20ns, t= fy +30ns) |2 g 1 & © 4 3 bo hob & 3 1 g (o) 0 6 4 & 4 3 ‘ z @ 0 2 & ho& g [GATE-2002] | = Q.29 The switching expression corresponding to AA, B, C, D) = E(1, 4.5, 9, 11, 12) is (@) BCD + ACD +ABD (0) ABC’ + ACD + BCD (©) ACD’ + ABC’ + AC’ (@) NBD + ACD + BCD’ {ISRO-2009} Q.30 The Boolean expression AC + BC is equivalent to @) AC+BC+AC (b) BC+AC+BC+ACB ©) AC+BC+BC+ABC (¢) ABC+ABC + ABC+ ABC [GATE-EC:2004] Q.31 What is the minimized logic expression corresponding to the given Karnaugh Map? we ooo it 00 1] ofafs[a " 1[a [4 10 1 10 wojeeed Digital Electronics (wwwmadeeasypublications org MADE EASY MADE ERSY (@ x2 (0) x7 + myz+wy2+ way (©) Wxy+ yz + wy Z+wsy (@) xz+ yz 4 0x+ way +wyz [ESE-2005] Q.32 The function (A, B,C, D) = 2(5, 7,9, 11, 13, 15) is independent of variabie(s) f@ 6 (o) C (© Aandc () 0 [DRDO-2009] Q.33 Consider the following boolean function of four, variables fw, x, ¥, 2) =2(1, 3, 4, 6, 9,11, 12, 14), The function is (@) independent of one variable (b) independent of two variables (©) independent of three var abies (@) dependent on all the variables [iSRO-2009] Q.34 The min termof (P,Q, R) = PQ + QR’ + PR’ is, (@) my + my +m +m, (b) my +m, + my + ms (©) my+m,+ m+ m, (2) my + m+ m,+ ms IGATE-2010] Q.35 The Boolean functions can be expressed in canonical SOP (sum of products) and POS (product of sums) form. For the functions, Y =A+BC, which are such two forms (@) Y=(1,2,6,7) and Y= (0, 2, 4) (©) Y=(1,4,5.6, 7) and Y=11 (0, 2,3) (©) Y=2(1,2,5,6, 7)and Y=1 (0, 1,3) @ Y==(1,2,4,5,6,7)and Y=11 (0,23, 4) [GATE-2008] Q.36 The SOP (sum of products) form of a Boolean function is £(0, 1, 3, 7, 11), where inputs are A, B,C, D(Ais MSB, and Dis LSB), The equivalent minimized expression of the function is (@) (B+C)(A+C)(A+B) (C+D) © Copyright MADE EASY (b) (B+C)(A+C)(A+C)(C+D) (©) B+O)(A+0)(A+T)C+D) () (B+C)(A+B) (A+B) (C+D) [GATE-2014] Q.37 What is the minimum number of NAND gates required to implement A +AB+BC(4+C)? (a) 0 (o) 2 4 (6 IGATE-2004] Linked Answer Questions (38 and 39): The following Karnaugh mep represents a function F. Foo ot 11 10 + T 0] 4[ +] *]o s[ofolafo Q.38 A minimized form of the function F (@) F=XY+YZ_ (b) F=X-Y+YZ (©) F=X¥+¥Z (d) F=XV+¥Z [GATE-2010) Q.39 Which of the following circuits is a realization of the above function F? ) x DP ) - @ ADD 7D BD [GATE-2010] Q.40 The minterms for AB + ACDare (a) ABCD+ ABCD + ABCD +ABCD+ ABCD Tolssjued voyizm oui noun wi0) Aue Uy pasyian 20 paonpoda aq Kew 00g Sul Jo UE ON WieG MON “SuONeS}aRd ASV SAWN O1 8Heu ToATaNS WWONAGOD @ Workbook | 61 he minimized function f obtained from the ‘K-map given below is ack oe (@) CE’ + ABCE + BCDE (b) BCE + ABCE + ABCDE + BCE (0) CE + ABCD + BCDE (@) BCE + NBCE + ABCDE + BCE [DRDO-208] Q.42 Which are the essential prime implicants of the following Boolean function? a,b, )= do+ ac’ + Be: (@) @candac’ (b) #candbc (©) 4 only (d) @ and be’ [GATE-2004] Q.43 Consider the Boolean function, Fw, x.¥.2) wy tay +ixyz+ Way +32 +E 2. Which one of the following Is the complete set of essential prime implicants? (a) Wy.xz,F2 (db) my.az (oe) yxyz (d) y.x2,¥Z Q.44 The output of the combinational circuit given belowis A Lp) ate LD (@) A+B+E — (b) AB+C) () B(C+A) — (d) QA+B) [GATE-2016] Q.45 The minimum number of 2-Input NAND gates, (b) ABCB+ ABCD + ABCD + ABCD + ABCD required to implement a 2-input XOR gate is (c) ABcD+ ABCD +ABCD+ ABCD + ABCD @4 (bo) 5 (@) asCD+ABcD+ABCO + ABCD +ABCD o6 7 [ESE-2013] IGATE-2016] ‘©Copyright MADE EASY ‘wor madeeasypublcations org ar 62 Electrical Engineering © Digital Electronics MADE EASY .46 Followingis the K-map of a Boolean function of (@ xv+vZ () xv+¥z five variables P, Q, R, S and X. The minimum ° oye > ° (©) X¥+¥Z @) xZ+7 suratpredit(SOP) expressiontorthefuncton | 8 [GATE-2016] ps Of 1 10 pe? 00 or 0 |p Numerical Data Type 0 0 0 0 0 oo 0 4 lg Questions 2 Q.51 Consider the logical functions given below. 1(A. B, C) = 212, 3, 4) £(A, B, C) = n(0, 1, 3,6, 7) f f If Fis logic zero, then maximum number of Possible minterms in function f, are ° of oof o1 0 0 0 0 woo 10 0 0 oO 100 0 00 woe ye? x=0 a (@) POSR+POSR+QASX+ORSX © asrsosx O— (0) OSx+Q5R = (@) Os+0s z [GATE-2016] | 2 | @-52 For the ring oscillator shown in the figure, the z propagation delay of each inverter is 100 pico Q.47 The chairman requested the aggrieved 8 sec. Whatis the fundamental frequency (in GHz) shareholders to_ him. 2 of the oscillator output? (a) bare with (©) bore with z , (©) bearwith —(@) bare 3 ‘ IGATE-2016] |= .48;he Boolean expression (a +5 +03) +(b+2) |8| @.55 The average propagation delay of each NOR simplifies is gate shown below is 10 ns. The frequency of @1 () 25 the output signal V, is Miz © ab @o PDD DADAD > — ve [GATE-2016] Q.49 Consider the Boolean operator # with the following properties: x#O=x,x#1=%,x#x=0 and x#¥ Then x# yis equivalent to Q.54 The minimum number of NAND gates required toimplement a 2-input EXCLUSIVE-OR function without using any other logic gate is___. IGATE-2004] (@) x+y (bo) 37 +37 Q.55 Minimum number of 2 input NAND gates (© y+ () ay457 required to implement the logic function [GATE-2016] FoA+B+C+Dare___. Q.50 In the digital circuit given below, Fis: Q.56 The minimum number of 2 input NAND gates ‘Uojesjuied Ganium eu owiim wioj Kaw uj pesiin 1o peonpoldal aa Kew yooa 8 ——4 required to realize the Boolean function ¥ » D= 4A, B,C) = ABC D .57 Consider the function: ~L f= ABC + BCD) + BD(A +C) + ABC d= AB(CD + ED) + ACD “uww madeeasypublications org MADE EASY ‘©Copyright MADE EASY Where ‘f' represents Boolean function and ‘d" represents don't care condition Then simplified Boolean expression 'f is reduced to literals, Q.58 The number of prime-implicants for the given function (A, B, C) = Xm (0, 2, 5, 6, 7) is ___ .59 Thenumber of essential prime-implicants inthe given function f(w, x, y, 2) = Zm(0, 2,6, 7, 8,9, 13, 15) is_. ® i Try Yourself If f(y, 2)=Em(0, 1,3, 5), f(x, y, 2) = Em (4, 5) and fx, y, 2) = Lm (1, 4, 5) then fy (x, ¥. 2) is (@) Xm(1, 4,5) (b) TIM(1, 4.5) (©) Um(1, 4,5) + d(2, 6,7) (© TIM(1, 4,5)-a12,6,7) [Ans: (c)] 72. Determine the function fif SwEztyZ+xZ and the overall transmission function of the given logic circuit is to be ((w, x, y, 2) = Zm(1, 3,5, 6, 9, 12, 13) f & Fwnxy2) 4—bo—_ (@) f= Em(0, 2,4, 7,8, 10, 11, 14, 15) (©) £=Zm (6,9, 12) (©) &=EM0.2.4,7,8,10,11,14,15) +46, 9,12) (0) f= Em E,9, 12) + AO, 2,4, 7, 8, 10, 11, 14, 15) [Ans: (c)] © Copyright maADE su yaalang WwOUKdO @ i> pasnpoides 0q Kew yoo sh 0 Ved ON TIE MON ‘SUONBO||GNa ASVA BV OD 13. 14, 15. Workbook | 63 |. Ininput to digital circuit consisting of a cascade of 20 EXOR gates is ‘X" then output 'Y” is: (ao xX (o) 1 (@) x [Ans: (b)] Define the connective «for the Boolean variables X and Y as X+Y =XY +X’! Let Z=X#¥. Consider the following expressions P, Q and R. P:X=Y*Z Q:Y=X#Z RiX#Y*Z= Which of the following is TRUE? 8) Only P and Q are valid (©) Only Q and R are valid (©) Only P and R are valid (@) AIP, Q, Rare valid, [GATE-2007, Ans: (d)] Which one of the following figures represents the coincidence logic? A @? 7 ¥ F A HH (0) f A 8 @ 3 F [ESE-2000] 7 _ z www madeeasypublications org } nena su) 64 | Electrical Engineering © Di T6. Ifthe waveforms A, B, Cshown in figure below are applied to the Ex-NOR gates. Find the frequency of output. ae i i i i 6 Td pitt ddd Litt ctiis + Li oT 18 [Ans: 125 kHz] | 7. Minimized expression for Yis 8 A | y»et F ‘a A B y (2) A+B+C — () A¥BC (©) A+BC (©) A+B+é 18. A switching circuit is given below. Based on this circuit find the Boolean expression for the bulb. —2 E oa, / a LL. \ eo a Input \ A Bubb ° T9. A Boolean function f of two variables x and yis defined as follows: AO, 0) = KO, 1) = K1, 1) = 1; 1,0) =0 www.madeeasypublications.org eatang 1461Kd09 © (aha ASva 3A sd ON 7m Bua INOWIT WO} AUB U| PABIINN 10 POSHPO: ‘wolseuuned I Electronics T10. T12. 13. MADE EASY — Publications ‘Assuming complements of x and y are not available, a minimum cost solution for realizing fusing only 2-input NOR gates and 2-input OR gates (each having unit cost) would have a total cost of (@) tunit (©) Sunt (b) 4 unit (@) 2unit [GATE-2004] AT gate is having the output 7[A, 8) = AB. Which of the following is/are have about Tgate. (@) {This functionally complete (©) {7. 1)is functionally complete (©) {7,0} is functionally complete (d) both a and b [Ans: (b)] . The simplification of Boolean expressions, a+ab+3bc-.... is (@) a+b4+T+.. (©) a+b+e+... (&) a+b+o+ @) a+b+c+.. fans: (d)] ‘The following labelled 1, 2, 3 and 4 in the network shown in the figure is redundant [ESE-1999] For the box shown the output D is true if and only if a majority of the inputs are true. a—| Input B—+} 1p ouput co The Boolean function for the outputis (@) D= ABC + ABC + ABC (b) D= ABC + ABC + ABC+ ABC (©) D=ABC+AB+AC+BC (d) D= ABC + ABC + ABC + ABC [ESE-2013] © Copyright 114. T15. T16. ©Copyright E EAS! Whats the Boolean expression for the truth table shown below? AJO[O]O[O]+[ 1] 1]1 Blolol4|tfolfol1|1 Clofijol1[o|1folt ffofofo{1fojo|1o (@ B(A+C)(A+C) (&) BA+C)(A+C) (0) BA+C)(A+C) (@) BiA+C)(A+C) [GATE-2006] A bark has 3 locks with 1 key for each lock, Each ley s owned by a different person. In order to open the vault atleast two people must insert their keys into the assigned locks. All the keys arend inserted at the same time. ifthe system is to be designed with only two input NAND gates, then find the number of NAND gates required, [Ans: 6] Alogi circuit implements the following Boolean function: F(A,B,C,D) = AC+ACD it is found that m the circuit the input combination A= C can never occur. Find a simpbr expression for F. [ESE-2014] a aalang wWOUACOD @ “oyesiuiied Usjlam ai9 oul Unio) uw uj Pasisin 70 peonpordel oq Ket y00d SA jO Wed ON THIeG NEN "SUONIEONGAG ASV SOV Ol 718. T19, 117. Workbook 65 ‘The standard sum of products of the function f= A+ B’Cis expressed as: (a) Em(1, 4,5, 6,7) + a2, 3) () Em(1, 4, 5, 6, 7) (©) Zm(0, 2,3) + d(1, 4, 5, 6,7) (a) Tim(1, 4, 5,6, 7) [DRDO-2008] The black box in the above figure consists of a minimum complexity circuit that uses only AND, OR and NOT gates. The function f(x, y, z) = 1 whenever x, yare different and 0 otherwise. In addition the 3 inputs x, y, Z are never all the same value. Which one of the following equations leads to the correct design for the minimum complexity circuit? y BLACK BOX F692) @ xy+x7 (b) x +z (© ¥¥z+x7z @aytyztz [GATE-2007} A logic circuit has 3 inputs A, 8, C and one output ¥. The output is logic 1 when majority number of inputs are at logic 1. Find minimized ‘expression for output ¥. ‘www madeeasypublications.org, Combinational Logic Circuits 8 | 2.3. Ithalf adders and iull adders are implemented Multiple Choice Questions | 3 using gates, then for the addition of two 17 bit ¢ numbers (using minimum gates) the number of ge half adders and full adders required will be Q.1) The circuit shown below does not represent | @ 0,17 (b) 16,4 4 t (©) 1,167 (@) 8,8 o |" 5 - ~ BP & Consider the function F(a, b,c)=b G+ bo+ab. by MUX es 3 if you implement F by means of 4-to-1 fe 14 2 multiplexer then what will be the values of p, q, ss |' f 1, 8, in the following figure. ld i >t 5 a—, @ S(A,B)=2(1,2) ? aay (b) EXOR gate with A and B as inputs z cas © S(A, 8) =11(0,3) e ie (a) Equality function $ SS Q.2 /The circuit below represents function |% rT X(A,B,C, g = ¢ Das fe @ Fa1¢c 1 : ie : () C.. C0 | o , : est , C ig MUX 2 ©) 10,66, aecae| ——* g 661.6 ms £]@.5_ xand yaretwo n-bitnumbers. These numbers IS 5: Sa : are added by a n-bit carry-lookahed adder, o TTI 3 which uses k logic-levels. If the average gate ABC z delay of carry-lookahead adder Is d then what ) £(3, 8,9, 10) a will be the maximum delay of carry-lookahead (b) 2(3, 8, 10, 14) iS adder circuit? WZ {c) (0, 1, 2, 4,5, 6,7, 11, 12, 13, 15) i (a) nr? (b) kd | (d) 100, 1, 2,4, 5,6, 7, 10, 12, 13, 15) 8 (©) nkd () ng | ( wrmmadeeasypublications org MADE EASY Sconight MADE EASY = ay Consider the following circuit z—a 2 1 1 Lena) dy S& T | py Itt (x, y.2)is 2(0, 3, 5, 7) then what will be the value of at J, and J, (respectively)? @ Zz &) 2.2 © 2z @) 22 &r\ne Boolean expression for the output fof the multiplexer shown below is. R R ' R R Pa (@) PeQeR = b) PEQOR () P+O+R () P+Q+R [GATE-2010] Qs) In a look-ahead carry generator, the carry generate function G, and the carry propagate function P, for inputs, A, and 8, are given by The expressions for the sum bit S, and carry bit C,,, Ofthe look-ahead carry adder are given by S,= P,® C,and C,, , = G,+ PiC, where Cy is the input carry. Consider a two-level logic implementation of the look-ahead carry generator. Assume that all P, and G,are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates Workbook | 67 @) 6,3 — © 64 ‘Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed? (@) 2% line to 1 line (©) 223 line to 1 Kine LAF 2" 1 Hine to 1 line (@) 2-2 line to 1 line (b) 10,4! (d) 10.5 [GATE-2007] Q.10 Consider two 4-bit numers A= A, A, A, Ayand B=B,B,B,B, and the expression x =AB +A B, for i=0, 1, 2, 3. The expression ‘Ag Ba + 33 AgBp + 3 22A,Bi + 23221 AB evaluates to 1 if (a) A=8 . (b) A#B A>B () A" 3 a a 7 a op 5. Dy= 1 when A, =0, A, = 0 g D,=1 when Ay=1,A,=0 3 Dy = t when A =0, A, = 1 g Dy = 1 when Ay= 1, A, = 1 The value of fix, y, 2) is (@) 0 () z @z wrt imum number of NOR gates required to implement Sum in half-adder circuits: (@) 2 (b) 3 ©4 ors Q.16 In the circuit shown, Wand Y are MSBs of the control inputs. The output is given by Q415 ‘oan inoqiim wi0} Aue UI pest Mux Q)-* F 5 MADE EASY Pubitations (@) F=WX+Wx+¥Z (0) F=W+Wx+72 SOF = WY XP @) FaW@+XY¥Z Q.17 The logic circuit realized by the circuit shown in the given figure will be c re fi) a tox FE io c. lb Sy} I] (@) BoC (b) Fe B@C () AoC = far F=A@C [ESE-1999] Q.18 Consider the multiplexer based logic circuit shown in the figure. Which one of the following Boolean functions is realized by the circuit? ©) F=W+S,+S, OE wes,es, [GATE-2014] Q.19 The minimum number of 2 x 1 multiplexers required to implement a half adder circuit are [when only basic inputs are available, compliments are not available]. @4 (b) 2 r3 @5 Q.20 The Boolean function ‘f’ implemented as shown in the figure using two input multiplexers is MADE EASY Workbook 69 Publications c—fo 2x1 MUX ey ia aecn net () ABC+ABC (c) ABC+ABC (d) ABC+ABC Q.21 An 8-to-1 multiplexer is used to implement a logical function Y as shown in the figure. The output o—fic on on, ol, ol, = ok ue in ot ss 8 TTT ABC (@ Y=ABC+ACD (b) Y= ABC+ ABD =ABC+ACD (d) Y= ABD+ ABC IGATE-2014] wt Q.22 The funationality implemented by the circuit below is Pp th teats bur (@) 240-1 multiplexer (b) 4-to-1 multiplexer = (©) 740-1 multiplexer (0) 6-0-1 multiplexer IGATE-2016] ( ©Copyright rang AGva 3GWW 61 JoneuToeTaNg AVOUACOD @ oa man “Su0T To poonpoide: 04 Kou yoo smi j0 ed ON Tojssjuned veniam eq inownyn we) AUR U MADE EASY Q.23 A 4:1 multiplexer is to be used for generating the output carry ofa full adder. Aand Bare the bits to be added while C,, is the input carry and C,u.is the output carry. A and Bare to be used as the select bits with A being the more significant select bit. Which one of the following statements correctly describes the choice of signals to be connected tothe inputs Ip, J,, J, and J, 80 that the output is, Con? (@) 1y=0,1,= Cy J, =C, and I= 1> (0) Jy = 1,1, = yy Ly = Gy and I, = 1 (©) p= Gy l,=0,L,=1andh=C, @) h=0,1,= Cy b= 1and l= Cy, IGATE-2016] Q.24 Consider the following circuitwhich uses a 2-0-1 multiplexer as shown in the figure below. The Boolean expression for output F in terms of Aand Bis? (a) AeB (©) A+B () Jo Q.25 Consider the two cascaded 2-t0-1 multiplexers as shown in the figure. > @ a [GATE-2016] www.madeeasypublications.org | 70 Electrical Engineering @ Digital Electronics MADE EASY Publications Q.29 The number of 2-to-4-line decodes with enable R input are needed to construct a 4-to-16-line ojo Fe ° ws pox decoder are (as: g [DRDO-2009] t t Pp @ erson wants to design a 4 x 1 multiplexer ‘The minimal sum of products form of the output. using only NAND gates. If NAND gates with any Xis number ofinputsare avaiable, hentoial numba, (@ PO+PQR () FaxaR OfNAND gates required are_. 4% () PO+POR Ro+PaR Q.31 A one bit full adder takes 75 nsec to produce ‘sum and 50 nsec to produce carry. A4bit parallel ‘adder is designed using this type of full adder. ‘The maximum rate of additions per second can be provided by 4 bit parallel adder is A x 19°. additions/sec. The value of A is [GATE-2016] Q.26 A 4to 1 multiplexer to realize a Boolean function F(X, ¥, Z) is shown in the figure below. The inputs Yand Zare connected to the selectors of the MUX (Ys more significant). The canonical sum-of-product expression for F(X, Y, Z)is (aha ASV 3aWW 01 ONRU oelang WOUKCOD @ Q.32 A 1 bitfull adder takes 20 ns to generate carry- out bit and 40 ns for the sum bit. What is the maximum rate of addition per second, when four _ MON "80 xh 1 bit full address are cascade? oN ot [ESE-2005] xt, Mux [—F%Y.2) — Try Yourself | rd T1. Design a logic circuit for detecting equality of (2) Em(2,3,4,7) — (b) Em(1,3,5,7) 2-bit binary numbers ©) Em(0,2,4,6 — (d) Em(2,3,5,6) in 0 pesnpaidei oq Kew yooa sia jo wed ON 7 [GATE-2016] |$ | T2. Design a combination circuit that accepts a 2 bit number as input and generate binary Data Type number equal to square of the input number. Questions 3. Forthe circuit shown in the following figure, Jy — J, are inputs to the 4 : 1 multiplexer. R (MSB) and Q.27 Minimum number of NAND gates required to Sare control bits. implement Sum in half-adder circuit is_¢y .28 Minimum number of 2x 1 multiplexers srequied to realize the following function is. MABC)=ABC+ABC 0 ee (Assume that inputs are available only in true form and Boolean constants 1 and 0 are available.) J0d wliym oui MoU WE) AUB UPR (‘emadeessypubcationsog MADE Ensy ° Copyright) MADE EASY The output Zcan be represented by @ PQ+PGS+OR5 * (&) PO+PQR+POS (©) POR+PQR+PQRS+ORS (d) PQR+PQRS+PORS +ORS [GATE-2008] Statement for Linked Answer Question (4 and ‘Two products are sold from a vending machine, which has two push buttons P, and P,. When a button is pressed, the price of the corresponding produc displayed in a 7-segment display. If no buttons are pressed is displayed, signifying ‘Rs. 0° Itonly P, is pressed, 2's displayed, signifying ‘Rs.2! Ifonly Ps pressed, ‘S's displayed, signifying ‘Rs. If both P, and P, are pressed, ‘E' is displayed, signifying ‘Error’ ‘The names of the segments in the 7-segment display, and the glow of the display for ‘0’, '2', ‘8’ and’ are shown below. € 2 o 2 5 Fl a a Consider: () push button pressedinot pressed in equivalent to logic 1/0 respectivey, (i) asegment glowinginot glowing in the display is equivalent to logic 1/0 respectively jeu oofang wwBuAdoO @ aha ASV SV OF 3 ‘Tolssjured uotizim e1y inowim WO) Ave U| PAS|INA 10 PSaNpOG T6. Workbook 71 (@) SNOT and 40R (b) 2NOT and 4 OR () 1NOTand3OR () 2NOT and 3OR a The number of 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates mond ‘A 2-to-1 digital multiplexer having a switching delay of 1 isis connected as shown inthe figure. The output of the multiplexer is tied to its own select input S. The input which gets selected when $= 0 is tied to 1 and the input that gets selected when $= 1 is tied to 0. The output Vy will be 2to 1 MUX fo (0) 1 (©) Pulse train of frequency 0.5 MHz * (6) Pulse train of frequency 1.0 MHz A4bit carry lookahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the dealy of each gate is1 time unit, what is the overall 4, Itsegments ato g are considered as functions of propagation delay of the adder? Assume that and F,, then which of the folowing is correct? the carry network has been implemented using @ 9-Fth,d=cre two-level AND-OR logic. (0) g=P.+P,d=c+e (@) 4time units (b) 6 times unts -—~_ (©) g=F.+Pre=bec (6) 10times units (d) 12 times units (@) g=Py+ Py e=b+o [GATE-2004] TS. What are the minimum numbers of NOT gates a The logic function (A, B, C, B) implemented by and 2-input OR gates required to design the the circuit shown below is logic of the driver for this 7-segment display? (oCopyright MADE EASY wor madeeasypublications. org) 72 Electrical Engineering © Digital Electronics MADE ERSY @ DiAe@c) (©) DiA@B) () DAoC). (@) D(AoB) T10. Without any additional circuitry, an 8 :1 MUX can be used to obtain (@) some but not all Boolean functions of 3 variables (b) all functions of 3 variables but none of 4 variables () all functions of 3 variables and some but not all of 4 variables (d) all functions of 4 variables [GATE-EC:2003] T11, Two Half Adders are connected in cascade as shown in figure below. The output *S" and "C" are HA, a, z a é (@) S= A@B, C=AB (b) S= A@B,C=0 (©) S=A+B,C=0% [aha ASW JaWW Ol oNRU ToelanS WBUKOD jo peanpexdei oq foul yoo sii Jo ved ON Tle MON "SU Publications. 712. Consider the logic circuit given below cy 1x4 x 0 MUX 0 19D AB The minimized expression for Fis @c (d) Jy oc @ Rr A4 bit binary adder is adding two BCDnumbers and producing the sum output $,$,S,5, along with the carry output C,, Itis required to design a checking circuit such that the checking circuit ‘output must be zero, whenever the binary adder output is invalid BCD, the boolean expression of checking circuit is (@) CoS +Co5,5, © %+ 88+ 8,5; (©) (Cy +)-(Cy+5,+5) @ None of the above 114, For the given multiplexer, Yis equal to ; ty . te mux © 7 = Ig es 7 Tyt @) ACD+ABC+AD * (b) ABC-+ ACD + AD 5 = 3 = (@) S=AB,C=0 zg z (©) ABC + ACD + AD 5 ee eee z (@) ACD +ABD+ AD i (Gaciocteempaherntie MADE EASY Publications >) ° Copyright) Sequential Circuits Multiple Choice Questions Q.1 Identify the type of the flip-flop Ss- x S-R ol fal (@ RStlipslop — (b) JK flip-flop (©) Dilip-op ——(d)FHlip-fo Q.2 The circuit acts as

Q.6 Thecharacteristic equation of the T-FF is given by (@) Q*=T0+QK (b) Q=TQ+TQ (c) Qt=TQ ( Q*=T0 a [©Copyright MADE EASY Publications vworemadeasypublcationsorg 74 Q7 Electrical Engineering © Digital Electronics The circuit realization of the combination logic block shown in figure to obtain the following truth table will be, ALB Onn 0}0/ G, fo[it 4 1{0] Q, 1jij 0 A ‘Combinationa | J Qo 8 ae, apo ing ASW 3QWW O1 HEU Foalans WBUKdoD © joa men av TON Publications @ A (b) B © 7B -(@) AB Q.9 _X-Yflip flop, whose Characteristic Table is given below is to be implement using a J-K flip flop XY | Qnat ofo| 4 ol1| a, 7/o| T/if 0 This can be done by making (@) J=¥.K=x (b) (c) J=Y,K=¥ (qd) Q.10 Match List4 with List-Il and select the correct answer using the codes given below the lists: List-| A. Shiftregister B. Counter C. Decoder List-It z 1. Frequency division g 2. Addressing in memory chips po——L))»—x 8 3. Serial to parallel data conversion (@ ao— i Codes: , > z A BC 3 @ 3 2 1 D— a ) 102 2 Bo- « 5 © 2 1 3 8 Torealize the given uth table fom the cireuit]2] « () 3 1 2 TEC : GATE-2004] ‘Shown in the figure, the input to Jin terms of A g | Q.11 Two D-flip flops, as shown below are to be and Bwould have to be s connected as a synchronous counter that goes 3 through the following Q, Q, sequence eee ieee = 00-401 > 11 10 00. Bo ee 3 The inputs D, and D, respectively should be Clock —! 2 connected as Truth Table a Tm BH OF ATE To, g use Ise pa {ene t 3 cK, cK Bf ofol a, 3 Clock] o}if 4 3 = — Tote z (@ OF anda, ab) Banda, e 7/110 ° © Ga, and@ a (d) Ganda, ~ " [EC : GATE-2006] ‘wwwmadeeasypublications.org MADE EASY ©Copyright) MADE EASY Publications Q.12 The clock frequency applied to the digital circuit shown in figure below is 1 kHz. Ifthe initial state of the output Q of the flip-flop is ‘0’, then the frequency of the output waveform Q in kHz is Dp, Workbook | 75 Q.16 The mod-number of the asynchronous counter shown in figure op Of ANOS (2 (@) 0.25 1 Q.13 Astate diagram of a logic which exhibits a delay S t t t “pur NOK pater HIGH (a) 24" (b) 48 () 25 () 36 [@ATE-2013] | | 2-17 The output of moore sequential machine is @ function of 4) all present states of machine (b) all inputs in the output is shown in the figure, where Xis the do not care condition, and Qs the output (©) all combination of inputs and present state MON SUOTROTIaRG ASVS BGVA 61 onBU ToATaS AWBUAGOD @ representing the site (d) few combination of inputs and present state If Tis set highis circuit given below then Q,,,, is wn @ ©) Jenn fF 770 | pf 7a, The logic gate represented by the state | 5 diagram is 7 CP (a) XOR (b) OR 3 x % (© AND (0) NAND [GATE-2014] |3 @.14 Latches constructed with NOR and NAND |& | k= gates tend to remain in the latched condition | 3 44) complementary (b) Q, due to which configuration feature? e (c) high (a) low 8 timate 8 | @.19 The numberof unused states ina 4-bit Johnson (©) Gate impedance & on is ws (d) Cross coupling [ESE-2013] |& i.) ae 2) 2 / Q.15 Synchronous counters eliminate the delay | 3 [ESE-2003) Prone) eunnert wuntered wah asynchronous | | @.20 A 4 bt ripple counter and a 4 bt synchronous (@) input clock pulses are applied only tothe | counter are made using flip flops having a first and the last stages £ propagation delay of 10 nseach. Ifthe worst case () input clock pulses are applied only to the 7 delay in the ripple counter and the synchronous last stage 3 counter be Rand S respectively, then (©) input clock pulses are not used to activate (@) R=10ns, S=40ns any of the counter stages 0) R= 40ns, S=10 ns (@) input clock pulses are applied (0) R= 10ns, S=30n8 simultaneously (@) R= 30ns, S=10ns [ESE-2013] [GATE-2003] © Copyright MADE EASY wwwmadeeasypublicationsorg ) Electrical Engineering 76 Q.21 In the modulo-6 ripple counter shown in the figure, the output of the 2-input gate is used to clear the J-K flip-flops. The 2-nput gate is (@) aNAND gate Ac) anOR gate (b) aNOR gate (6) an AND gate IGATE-2004] Q.22 The following binary values were applied to the Xand Yinputs of the NAND latch shown in the figure in the sequence indicated below: X=0, Y=1;X=0, ¥=0;X=1, Y=1. The corresponding stable P,Q outputs will be x P [GATE-2007] Q.23 For the circuit shown, the counter state (Q,Q,) follows the sequence © Digital Electronics Wed ON 118g MON “SUONEOT|ANd ASV SOYA 0} 18HBU YoBTaNg WOLKE @ jo poonpoidei @@ feu wood si ‘o|ssiued uetipm ui noyi|m WHO} ADE Uy pe MADE ERSY ) 00, 01, 10, 11, 00 (0) 00, 01, 10, 00, 01 ... (©) 00, 01, 11, 00, 01 (A) 00, 10, 11, 00, 10... [GATE-2007] 24 The figure below shows a 3-bit ripple counter, with Q, as the MSB. The flip-flop are rising-edge triggered. The counting direction is a of fr oe Croce cur ux de dt He of Hk 4d) always down (©) always up (©) upor down depending on the initial state of Qgonly (@) up or down depending on the initial states. of Q,, Q, and Q, [GATE-IN:2009] Q.25 The input A and clock applied to the Dfip-flop are shown in figure below. The output Qis, Crock |_| Input A oa Kp ou I @) x) © @ Q.26 The output Q, of aK tlip-flop is zero. itchanges to 1 when aclock pulse is applied. The input v,, a K, are respectively (Xrepresents don't care condition): \Uay7 and x (b) Oand x (c) Xando (d) Xand1 [ESE-2013] Q.27 The Q-output of J-K flip-flop is ‘1’. The output does not change when a clock-pulse is applied, The input J and K will be respectively (x-don't care state) ae (a) Oandx (b) Oand1 (c) tando er xand 0 (wwwmadeeasypublications org MADE EASY Ocopynght) (wo : Scopyiat) MADE EASY ‘Common Data for Questions (28 and 29): ‘Acounteris shown below: 1% ——% —a au hye hd ox fd] ic ky fet cur [our Q.28 The counter shown is, (@) Mod-12.-~ (©) Mod-14 far far (b) Mod-9 (d) None of these Q.29 Frequency of output Qp for 1 MHz clock is. (a) 63.3kHz 06) 83.3KHZ a (©) 73.3kHz (d) None of these Q.30 What are the counting states (Q,, Q,) for the counter shown in the figure below? a a | aa! JIKFlip-h (b) 11, 10,00, 11, 10... (A) 01, 10,00, 01, 10... [EC GATE-2009] (@) 01, 10, 11, 00, 01 (©) 00, 14, 01, 10, 00. Q.31 Following state diagram shows clocked sequential circuit: How many minimum number of states the sequential circuithas? ‘© Copyright (ang ASV BaVW OL neu IDAIGNS TUOUAGOD @ iro poonpoider 6a Kew 7009 Sih FO ‘an inowpm wi0) Aue UI pes MADE EASY Workbook 77 @é (o) 7 5s 4 Q.32 The state transition diagram for a finite state machine with states A, 8 and C, and binary inputs X, Yand Z, is shown in the figure. Which one of the following statements is correct? oe et (@) Transitions from State A are anvaeay defined. (b) Transitions from State B are ambiguously fined. ‘Transitions from State C are ambiguously defined. (d) All of the state transitions are defined unambiguously. [GATE-2016] Q.33 For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero. , (Ls8) 3- bit a ‘Syndhronous: ‘Counter cK— (SB) Roast Ifthe clock (Cik) frequency is 1 GHz, then the counter behaves asa (@) mod-Scounter {b). mod-6 counter (©) mod-7 counter (d) mod-8 countere<~ 2 IGATE-2016] . vwewwsmadeeasypublications 019 ) ? 78 | Electrical Engineering © Digital Electronics MADE EASY Q.34 Asynchronous counter using two J- K flip flops that goes through the sequence of states: Q,Q, =00-> 10-4 01-4 11+ 00... is required, ‘To achieve this, the inputs to the flip flops are: i al fs ab jaha ASV SGVW O} neu yoelang WuBEAAED @ i IGATE-2016] Numerical Data Type Questions Q.35 The minimum number of flip-flops required by a Module-8 counter i 34 Reus 004 511 701180 ON Q.36 Five JK flip-slops are cascaded to form the circuit shown in Figure. Clock pulses ata frequency of 4 MHzare eppliedas shown. The frequency (in kHz) of the waveform at Q,is_ 16 oe SM an Beonpar cox LLIN [GATE-2014] Q.37 A digital circuit is designed with three Dip flops and an Ex-OR gate as shown in below figure. Ifthe intial value of Q, Q, Qc was 110 then the minimum number of clock pulses required to get Q, Q,Q,as O11 is. jwied uetiom ou InoWim v0) Rue ui pa Publications oa —! Q.38 Three 4 bit shift registers are connected in ‘cascade as shown in figure below. Each register is applied with a common clock pulse. input] S180 ‘SiPO PISO Shit ‘Shit shit cock ” Regsier 1] [ [Register 2| [“|Registr| A 4 bit data 1011 is applied to the shift register 1.The minimum number of clockpulses required to get same input data at output with same clock are. t-output ‘Common Data for Questions (39 and 40}: ‘A Mealy system produces a 1 output f the input has been 0 for at least two consecutive clocks followed immediately by two or more consecutive 1's. Q.39 The minimum number of states for this system is Q.40 The flip-lops required o implement this system are Try Yourself T1. Reduce the following state diagram and also write the reduced state table. | wwnnmadeeasypublications.org MADE EASY MADE ERSY Workbook 79 Publications 2. Consider the circuit given below: moo 10 [| 4 Ripple [4 A, Down [| ‘Counter . o Ha |MSB La> MOD 10 Ao Ripple Up ‘Clock- Counter | 4SB cy }aA 10301511 mie. ane Sendo ce enh nenbit cin 1B. Consider a mod-1000 ripple up counter The uy using S-R flip-flop: cycle for its MSB is __%. T16. Consider the flip-flop circuit diagram shown Sequence] Required State below. Draw output waveform for the circuit. No. Sequence g ojo oo g 1+ f 1 0 a 2 jo 4 1 g 3 1 1 0 a fo 3 i slo 0 1 -+Repeatfromooo | Show the state table indicating the present state, | £ the next state for each present state along with | 3 the input requirements of each of the S and R | 5 inputs. Show clearly the minimization of logic |2 requirements using K-maps. Write the logical | $ expressions for each excitation input ofall the | = flip-flops. Draw the logic diagram of the counter | 3 designed by you. 3 = [ESE-2009] || T17. Refer to the NAND and NOR latches shown in T11. Using Tlip-flop and logic gates, design a L-M |8 the figure. The inputs (P,, P,) for both the latches edge triggered flip-flop having a truth table as are frst mace (0, 1) and then after a few second, given below: g made (1, 1). The corresponding stable outputs (Q,, Q,) are wwwmadeeasypublications org MADE EASY ©Copyright) MADE ERSY a Q, P, % p, o (2) NAND: first(0, 1) then (0, 1) NOR: first (1, 0) then (0, 0) (b) NAND: first (1,0) then (1, 0) NOR: then (0,0) (©) NAND: first (1, 0) then (1, 1) NOR: first(0, 1) then (0, 1) (6) NAND: first (1, 0) then (1, 0) NOR: frst (0, 1) then (0, 0) rst (1,0) [EC : GATE-2009, Ans: (b)] The shift register shown in the given figure is initially loaded with the bit pattern 1010. Subsequently the shift register is clocked, and with each clock pulse the pattern gets shifted by one bit position to the right. With each shift, the bit at the serial input is pushed to the left most position (msb). After how many clock pulses will the content of the shift register become 1010 again? T18. rock Serial Tole Input n J * [Ans: (7)] 19, The given figure shows a ripple counter using positive edge triggered flip-flops. If the present state of the counter is Q, Q, Q, = 041, then its next state (Q, Q, Qe) will be__[o? 4 We ay Le ay | Touse|ured denim ou oun wid) Aue U1 pesiITN Je paanpolde: 6q feu yoo si] VEG ON TWI6G MON ‘suORBOHIGNd ASVI TGV 8 eHEW YoeIaNS AUBLACOD @ Workbook 81 720. Consider the circuit in the diagram. The @ operator represents Ex-OR. The Dflip-flops are initialized to zeroes (cleared). D a %| 2 q| | % ee ox | Lox ok i t [Cock The following data : 100110000 is supplied to the “data” terminal in nine clock cycles. After that the values of q, 4; q are (@) 000 (b) 001 (©) 010 () 101 [GATE-2006, Ans: (c)] 721, Forthe initial state of 000, the function performed by the arrangement of the J-K flipflops in the figure (a) Shift Register (©) Mod-6counter (d) Mod-2counter [EC : GATE-1993] (b) Mod-3 counter 722. A 4 bit right shift, shift register is shitting the data to the right for every clock pulse The serial input D is derived by using Ex-OR gates as shown in the figure. After three clock pulses the content in the shift register is to be 1010 at Q,Q,Q,Q,, what will be the initial content of the register. ae a a % a bitshin register aK al a a, cone T (@ 1100 b) 1010 up are-200, ‘Ans: (100)] (©) cot o10t ~ MADE EASY WaWansdbessypublicationsom) © Copyright S 82 | Electrical Engineering © Digital Electronics MADE EASY 23. Consider the following state transition table with two state variables A and B and the input variable x and the output variable y Present State | Input | Next Stato | Output Atel: [aval y o | o [o folfeo 0 o fo [1 fols 0 o | 1 fo fol? 4 o f+ [+ti[+fol o + |0 [o [ofo 1 a fo [a tata ° a 4 111 [1Tofo 4 Ifthe initial state is A = O and B = 0, what is the minimum length of an input string which will take the macine to the state A= 1 and B = 1 with output y= 1? (3 (bo) 4 @s @6 [DRDO-2009} ng aWBukdOD © in 70 poanpordes eq ABW yoo Si To ed ON WI8 MON 'SUO) ‘Wojss|uned wenium ui inouHIM lO) ALB Ue Publications 24. Ifacounter having 10 FF's is initially at 0, what count wil it hold after 2060 pulses? (@) 0000001100 (b) 000001 1100 () 0000011000 (d) 0000001110 25. The frequency of the clock signal applied to the rising edge triggered D-flip flop shown in the following figure is 10 kHz. What is the output frequency at the flip flop output Q? (in kHz) Dp af cK —p a How many pulses are needed to change the contents of a 8-bit up-counter from 10101100 to 00100111 (right most bit is the LSB)? [IT GATE-2005] Gaza MADE ERSY Publications © Copyright Semiconductor Memories ©|Q.4 How may address inputs, data outputs are Multiple Choice Questions g required for a 16k x 12 memory 2 @) 12,12 (b) 16,12 Q.1. Which one of the following statements is | & (©) 14.12 (@) 16.16 correct? 2 Q.5 Consider the following statements for a DRAM: (@) PROM contains programmable’AND' array | § 1. Bitis stored as a charge. and a fixed OR’ array 5 2. Itis made of MOS transistors. {b) PLA contains a fixed ‘AND' array and a 1 3. Speed of DRAM is faster than processors, programmable ‘OR' array g 4. Each memory cell requires six transistors. (©) PROM contains a fixed ‘AND’ array and a | & Which of these statements are correct? Programmable ‘OF arrey i (@) 1and2only —(b) Zand only (d) PLA contains a programmable ‘AND’ array | 2 (©) 3and4only (4) 1,2,Sand4 and a programmable ‘NOR’ array : TESE-2004) |= Numerical Data Type Q.2 AROMisto be used to implementa “squarer’, |Z Questions which outputs the square of a 4-bit number. What | 2 must be the size of the ROM? {| 28 A semiconductor RAM has a 12 bit adcrss (a) 16address lines and 16 data lines 3 register and an 8 bit data register. The total (b) 4 address lines and 8 data lines. Ss number of bits in the memory is KO) ES Selcteee Wee cee cam nee, H$ | @.7 tis desired to have 64 x 8 memory and if only (0) 4 address lines and 16 data lines i 16 x 4 size chips are available then number of (ESE-2004] € chips required are Q.3._AsingleROMis used to design a combinational |£)q.g The minimum number of MOS transistors circuit described by a truth table, What isthe |g requiredtomake.a dynamic RAMCel ero number of address lines in the ROM? 3 (@) Number ofinput variables in the truth table |? |@.9 The minimum number of MOS transistors (0) Numberof output variables inthe truth table | required to make a static RAM cell are, (©) Number of input plus output variables inthe | 3 truth table i (6) Number of lines in the truth table e [ESE-2006] i (copyrignt MADE EASY vwnmmadeeasypublcationsorg 84 z Try Yourself 1. Electrical Engineering © Digital Electronics Consider the ROM shown below. (se) % % XX % Peppy BCD t© Deaimal decoder By Dy Dy Dy Dy Dy Dy Dy Dy Dy ¥, (MsB) Ifthe coding scheme for X, X, X; X9is BCD then find coding scheme for ¥ YY; Yo impliment the following logical expression using ROM circuit. ¥, (A, B, C) = Em(1, 2, 4,7) ¥, (A, B, ©) = Ent, 3, 5, 6) ¥, (A, B, ©) = E40, 2, 3, 4, 7) ¥ (A, B, C) = Zm43, 5, 6, 7) Implement BCD to excess - 3 convertor. ‘Gojseiur0d Uoriiw ew inowaym wio} Aue U| peslIan 70 Paonpoldel oq few yoo si) jo Ved ON Ted MAN UOHUDT|anG AVS SVN A JeNeW yoolang AYOUKGOD @ MADE EASY © Copyright| Integrated-Circuit Logic Families Multiple Choice Questions on Q2 Consider the following statements describing the property of a complementary MOS (CMOS) inverter: 1. Itis a combination of an n-channel FET and ap-channel FET. 2, There is power dissipation when the input carries the logical 1 signal 3. Thereisno power dissipation when the input carries the logical 1 signal. 4. There is power dissipation during transition, from 0 to 1 or from 1 10 0. Which of the statements given above are correct? (@) 1,2and3 (pb) 2,3and4 (©) 1,3and4 — (d) 1,2and4 [ESE-2006] ‘The NMOS circuit shown below is a gate of the type | ao (@) NAND © (b) NOR () AND (¢) EXCLUSIVE -OR [ESE-2003(EE)] ‘oyssnuiod ulm a yg ay Ale posi 79 paorpexda/ oq feu yBoe SO ed ON "NEG MEN VOHBO|ANG ASVS SAMI SHE BAIANS IHOGOO @ Qs Q4 Qs Qé Ainverter gate has guaranteed output levels logic't' = 3.8 and logic ‘0'= 0.7 V. The maximum, low level input voltage at which the output remains high = 2V. The minimum high-level input voltage atwhich the output remains low = 3.1 V, What are the noise margins of this gate? (a) NM, =2.4V, NM, =1.8V (0) NM, = 1.8 V, NM, = 1.3V (0) NM, =0.7 V, NM, =1.8V (8) NM, =0.7 V,NM, = 1.3V [ESE-2004(EE)] For a logic family Voy.is the minimum output high level voltage Vo, is the maximum output low level voltage Vis the minimum acceptable input high level voltage Vj, is the maximum acceptable input low level voltage ‘The correct relationship among these is: (©) Yan> Vou? Ya > You (©) Vou Yin Vin > You (©) Yn> You? Vou> Vir (A) Vou> Vin> You? Vir [ESE-1999] The open collector output of two 2-input NAND gates are connected to a common pull-up resistor. If the inputs of the gates are A, Band C, Drespectiyely, the output is equal to (@) ABCD (v) AB+CD (c) AB+CD (d) ABxCD {ESE-2002] The figure shows the internal schematic of a TTL ‘AND-OR-Invert (AO!) gate. For the inputs shown in the figure, the output Y is www.madeeasypublications.org 36 | Electrical Engineering * Digital Electronies 1D A 8 Naina { @o (©) AB () 1 © 7B [GATE-2004] Q.7 The logical expression for the output 'Y of the diode circuit below is ° 3 e z Veo®5V 5ka Ace 3 ace: —0y 3 o—$—o| : tha z am 2 (a) (A+B)C (ot) A¥B+C (©) (A¥B)C (¢) AB+C Q.8 An NMOS circuit is shown in the figure below: = arf 7M |ber Od ‘The logical expression for the output (Y) equals to (a) PQ+A)+ST (b) P(Q+R)-ST 3 (0) P+(QA)(S+T)(d) (P+O)R+5T 3 www.madeeasypublications.org MADE EASY Q.9 Consider a DTL circuit as given below: Ifall the inputs (A, 8, C) are high then, (@) Input diodes D, is ON and D,, is OFF, Q, is in cut-off mode and Y = ABC. (b) Inputdiodes D, and D, is ON, Q, isin active mode and Y = A+B+C. (©) Input diodes D, and D, is ON, Q, is in ‘saturation mode and Y = ABC. (@) Input diodes D, is ON and D, is OFF, Q, is in saturation and Y= ABC, Q.10 Inthe TTL circuitin the figure, S,, S, and S, are select lines and.x, and x, are input lines. S, and xp ate LSBs. The output Y is 1 € 8:1 MUX Ss es, Game ab Y (@) indeterminate ©) AeB () Aes () C(A®B)+C(A@B) [GATE-EC:2001] Q.11 Which of the following is not a type of output configuration in TTL gates? (a) Totem-pole output (b) Open-coliector output (0) Transmission-Gate output (0) Tristate output © Copyright mi EASY Q.12 The DTL, TTL, ECL and CMOS family of digital ICs are compared in the following 4 columns eon © Fanoutis minimum OTL DTL TTL CMOS Powor Consumption ie minimum Propagation day's cys Ec. TTL CMOS ECL DTL ™ TH The correct columnis (a) P (b) @ (AR @s [GATE-EC;:2003] Q.13 Identify the logic gate given in the figure rd (a) NOR (c) AND (b) NAND (d) OR [GATE-IN:2005] Q.14 A CMOS implementation of a logic gate is shown in the following figure: 5Y ‘The boolean logic function realized by the circuitis (@) AND (6) NAND. (c) NOR (@) OR [GATE-IN:2007] ‘©Copyright z & g z Tojssjuied vonjm 4) IROUI/M lnvoy Aue uy paRt|RA 20 poonpoide: eq Kew YON SI Workbook | 37 Q.15 The expression for output "Y" forthe circuit given belowis Moo 4 aff e4 4 : ¥ (a) A-(6+C) (b) A+ BC (©) A+BC (@) A(B+O) Q.16 The switching speed of ECL is very high, because the transistors (@) are switched between cut-off and saturation region (b) are switched between active and saturation region (©) are switched between active and cut-off region (d) may operate in any of the three regions Q.17 The figure of merit of a logic family is given by (a) Gain bandwidth product (©) (Propagation delay time) x (power dissipation) (©) (Fan out) x (Propagation delay time) (d) (Noise-margin) x (Power dissipation) Q.18 Match List-I with List-II and select the correct answer using the code given below the Lists: List-1 List-Il A.HTL 1. Highfan-out B. CMOS 2. Highest speed of operation C. PL 3. High noise immunity DECL 4. Lowestproductof power & delay Codes: AB cD @3 4 1 2 2 4 1 3 @3 1 4 2 @2 143 www.madeeasypublications.org Electrical Engineering 88 Q.19 The inverter 74 AL S01 has the following specifications: DAMA, Toy mae = 8 MA, Jhpymax = 20 UA. Imex = 0-1 MA. ‘The fan out based on the above will be. Numerical Data Type Questions Foumax Q.20 An IC family has an average propagation delay of 10 ns and an average power dissipation of 5 mW. Figure of merit of IC family is__pJ. @ T1. The fan-out of the TTL gate having Joy = — BHA, Iyj= 40 BA, To, : Jy, = -1.6 mAis equal to www.madeeasypublications.org © Digital Electronics a oalang WOUND jang ASWa 3aWW O18) in 10 poonpordoy aq Kew yoo Ba jo wed ON 14laG MON 20D) 3 TRO ojsehur0d ua Publ T2, “MADE EASY e oy The transistors used in a portion of the TTL gate shown in the figure have a B = 100. The base- emitter voltage of is 0.7 V for a transistor n active region and 0.75 V for a transistor in saturation. the sink current J = 1 mA and the output is at logic 0, then the current J, will be equal to mA, BV 1.4 ka Eames) © Copyright) ee) ADC and DAC Multiple Choice Questions a4 Q2 The resolution of a 12 bit Analog to Digital converter in percentis (a) 001220 (b) 0.02441 (c) 0.04882 (¢) 0.09760 [ESE-2002(EE)] Consider a 6-bit D/A converter having full scale output of 3mA and a full-scale error of +0.4% FS. For a binary input sequence of 10111 1, therange of possible outputs willbe (2) (2220 2240) WA (b) (492-512) yA (c) (2226-2250) pA (d)(1295 - 1325) yA Linked Data for Questions (3 and 4): A 3bit weighted resistor D/A converter with MSB resistance R= 10k@ having input bit stream bb, b, = 1 0 1 is shown in figure below: Ra bka Qs a4 © Copyright The total input current ‘7 in the circuit will be (@) 0.125mA —(b) OS mA (©) 0625mA —(d) 1.0 mA ‘Whats the analog output voltage by this DAC? (@ -3.125 volt. —_(b) 0.625 volt (©) -25 volt (@) -8.0 volt —asshunodUotan Boy ty foe paso pacrpaxdar 0 Fu Bee Bo EU ON IBC =A BUDREOIGAG ASV SAVIO BHU DeaNS MABUAGED @ Qs ae az as MADE ERS lea The circuit shown below is a R-2R ladder type DAC with reference voltage +6 V and R,= 9k. and R= Vor Vout Vea = #8 Volt ‘As above figure-2 switches are ON and 1 is OFF, the output voltage will be (@) -675V () 135 (c) -20.25V (d) -40.5V The output voltage of a 5-bit D/A binary ladder that has a digital input of 11010 (Assuming 0 = 0 Vand 1 = +10 V) is (@) 3.4375V () 60V (©) 8.125V (d) 9.6875V [ESE-2001] Which one of the following D/A converters has the resolution of approximately 0.4% of its full scale range? (@) Beit (©), 12-bit (b) 10-bit (d) 16-bit [ESE-2006) An 8 bit successive approximation analog to digital converter has full scale reading of 2.55 V and its conversion time for an analog input of 1 Vis 20s, The conversion time fora 2V input willbe wwwmadeeasypublications.org 90 | Electrical Engineering « 1 Electronics (@) 10ys (b) 20us (©) 40us (6) 50 us [GATE-2000] Q.9_ The minimum number of comparators required to build an 8 bit flash ADC is @s8 (b) (©) 255 (d) 256 [GATE-2002] Q.10 4 bit binary weighted resistor DAC has LSB resistance of 32 kQ. The corresponding MSB resistance is (@) 2ka (b) 4k (0) 8kQ (d) 32kQ ‘Statement for Linked Answer Questions (11 and 12): In the Digital-to-Analog converter circuit shown in the figure below, V, = 10 Vand A= 10k. RoR Ri oR 9 Reus yoo 514119 WEG ON 14/90 NON "SUOTBDIGNA ASV TOWN Ol HEU I9BTaNS TUOUAdOD @ [GATE-EC:2007] Q.11 The currentiis (a) 31.25uA (b) 62.544 (©) 125pA (d) 250A [GATE-£C:2007) Q.12 The voltage Vis (@ -0.781V (b) -1.562V (©) -3.125V (6) -6.250V [GATE-EC:2007] Q.13 A4it successive approximation type ADC has a full scale value of 15 V. The sequence of the states, the SAR will traverse, for the conversion of an input of 8.15 Vis (@) >a ce-ce-E) (0) {9108-SHEB-SOTS OE -OED-GE jad uovium oui noun wo} Aue ul peaian Jo paanpalda) wwwmadeeasypublications.org MADE ERSY ‘ub ©) CBEMSIED-OLT (G) Geri ~SES-RISD-TE-SHIETD ~~) [GATE-IN:2010] Q.14 Which of the following statements is/are correct, about Analog to Digital converters (ADCs). (i) Flash type ADCs are fastest (i) In successive approximation type ADCs conversion time depends on magnitude of analog voltage. (il) Counter type ADCs has fixed conversion time (iv) Dual-siope type ADCs are slowest (@) Allofthese —(b) (ii) and (ii) (© (and(iv) — d) (ionly Q.15 For a 4-bit digital to analog convertor, analog voltage varies from Oto 1.5 volts. The resolution of DACis (a) 10% (b) 6.25 % (©) 6.67% (@ 9.375% Numerical Data Type Questions Q.16 An 8-bit D/A converter has a full scale output voltage of 20 V. The output voltage when the input is 11011011, is V. [ESE-2001] Q.17 Forthe 4 bit DAC shown in the figure, the output voltage Vy is v. 1K 7 [GATE-2000] © Copyright Ee Q.18 A 10-bit DAC provides an analog output which has a maximum value of 10.23 volts. Resolution of the DAC is, mv. [ESE-2012] Q.19 The analog output voltage of a 6 bit DAC with reference voltage as 20 V for the digital input 011101 is Volts. Q.20 AS bit D/A converter has a current output. Ifan output current J,4,= 10 mA is product for a digital inputof 10100, the value of f,, fora digital input of 11101 will be. mA. 1. A 4+bit D/A converter is connected to a free- running 3-bit UP counter, as shown in the following figure. Which of the following waveforms will be observed at V,? s ‘« }—}o, see 0,}=4o, i Mo Sm | EK Clock ae a = cour = DAC In the figure shown above, the ground has been shown by the symbol V. OV ON [GATE-2006] T2. A&-bit AD convertor is used over a span of Zero to 2.56. The binary represen-tation of 1.0V signal is (2) 01100100 (©) 10100101 (b) 01110001 (d) 101.000 10 [ESE-2013] © Copyright fang W6UAdOD © : g g (90 MON "=u ojsejuied UoHlIm uy IROUIH 10) Aue Ul Pasyin 70 peanpardes ea Few yoOg SIN 70 Wed ON 73. 14, Clock Workbook 91 Consider the circuit given below. MsB, MSB yf T | cry | F| vigil to Inputs bis! | Code | {| Analog -—V, 1 |eonverter| |_| Converter ise Ls8 The full scale reading of Digital to Analog converter is 10.5 V. Each bit of Gray code converter output is given to digital to analog converter through an invertor. If input to the circuit is 110011, then corresponding output voltage V, is __ Volts. [Ans: 3.45 V] Consider the system given below: The clock input is connected to the 4 bit ring counter, The output of the ring counter acts as the clock for the other counters. All the counters shown in figure are positive edge triggered. ‘The output ofall counters act as input to. 14 bit DAC with step size (D) equal to 1 mV. If intially all counter are cleared then find the output o° DAC after 20 clock pulses. [Ans: 10.96 V] wwwmadeeasypublications.org | MADE EASY Analog Electronics +Digital workbook Electronics + Microprocessors _ G (EGG Sera CTi Ee Microprocessors SI. Unit | 1. Intel 8085 and intel 8086. 2 Programming of Microprocessors... 3. Memory and I/O Interfacing 0000 ‘cenit Sbjct ater n MADEEASYPblcatos NewDe Nope tisboxkneyberepoaiedcr edn aye hau ne wes comin | 808s 1. Introduction: * Microprocessor definitions © Computer block diagrams * Differences between microprocessor and microcontroller (for interview purpose) © Memory (Memory architecture) differences ‘* Importance of Hexa-Decimal Numbers 2. Systems BUS:- Address, Data and Control © Memory basic 3. Internal Architecture * Register unit: General purpose registers, Special purpose registers © Arithmetical Logical Unit © Timing and Control unit, Signals, ALU, RD, WR, |O/M , HOLD and HLDA © Interrupts Unit: Types, Triggering, Vector address, applications * Serial /O control unit SID and SOD PIN Layout (Optional) 4, Programming Model * Softwares definitions © Programming cycle - Steps in writing 5, Instruction Format: Opcode, Operand © According to length-1 byte, 2 byte, 3 byte © Memory representation of a program 6 Addressing Mode: conventional). [Both for objective and 7. Timing Diagram: Definition: T-state, Machine cycle and instruction cycle, Example for an instruction. Microprocessors Description Sheet & Instruction Set Classification: ® Data transfer/Copy instructions ® Arithmetic and Logical instructions © Branching instructions ‘® Machine control instructions 9. Programs: Objective and Conventional © Simple addresses * Loops and I/O applications 10, Interfacing: * Memories - Basics, Classification Notation of memory, (M x N) © Problems: = Memory mapping * Starting and Ending addresses, = Using decoders © Interfacing IC's: 8251, 8253, 8255, 8257/37, 8279 © Interfaces: "Different buses (for ESE) = SPI, PC, CAN, USA2J © Applications of Microprocessors (for ESE)] * ESE - 8086 - Basics (Outline) 11, Microcontrollers * 8051 (Basics and architecture) © Types of controllers * Applications, 12, Embedded System * Definition * Application MADE EASY Electrical Engineering @ Microprocessors 94 3) Josses01d0121y S808 TSLNI JO eaMDeNYDIy a | 8 sageacenry = mg sapey suas aos save _ no 1aS3u | 7 | wot's °s STv uM gy ino» oS fy t titititt sh tf | (@ una ssappvreea] [(@) une ssaippy foot aE nee eee. ik it onudo pue Suma eae | — [op on a oN) os bt : | | <9 | fon anaes | | heeee ; sty} fo fo s/f) ps ee es (2) 3 (s) @ g uogonuysuy @ 9 |@ @ ZN “Boy dway ‘Boy “dway (g) 2 (Ca (9) ses60u aoa? | | oon [pico on eves | Tonuog wdrusew umadeeasypublications.org (ror LI ate ds wzlow| solou), ube MADE EASY Workbook 95 Publications Address/Siatus ‘Adéross Data bus Aed8s~ Ade ‘AD; ~ ADs Memory address and data bus interfacing intemal data bus ar u 8 1 N ‘niacin bye T uous 6 bytes: E R F A c E u N i i Intemel data bus Decoding Circuit E x| * ax E El ex ul x T| 0x ° N u N i T Register bank Flags (16) Timing and contr ict Clock and control Signals Architecture of INTEL 8086 Microprocessor MADE EASY wwwsmadeeasypublications.org 3) Publications Intel 8085 and Intel 8086 Multiple Choice Questions Q.1__ INTEL 8085is @) 16bitmicroprocessor (b) 32 bit microprocessor (c) 8 bit microprocessor (@) 4bit microprocessor Q.2_ Inan8 bit microcomputer, maximum memory can be connected Is 32 K bytes, the length of stack pointer, program counter and number of data lines are respectively @ 16, 16,8 (0) 15, 16,7 (©) 15, 15,8 (0) 16, 15,8 For the purpose of data processing an efficient assembly language programmer makes use of the general purpose registers rather than memory. The reason is (@) The set of instruction for data processing with memory is limited (b) Data processing becomes easier when register are used (©) More memory related instructions are required in the program for data processing (4) Data processing with registers takes fewer cycles than that with memory Qs [lEs-2011] Consider the following statements in 8085 microprocessor data-bus and address bus are multiplexed in order to 1. Increase the speed of microprocessor 2. Reduce the number of pins 3. Connect more peripheral chips Which of these statements is/are correct ? as ‘wwwmadeeasypublications org ‘ores uation a ynoaim wy Aue Ur paian 0 paonpendar a Keu}eo9 A Ve ON NBO MBN SUORES|aRG ABV OWN GU SHEL IGNS "NBUIGCO @ Qs a7 Qs (@) tonly (© 2and3 (b) 2 only (0) 1,2and3 [IES-2009] The content of the program counter of an 8085 microprocessor is (@) The total number of instructions in the program already executed (b) The total number of times a subroutine is called (©) The memory address of the instruction that is being currently executed (0) The memory address of the instruction that is to be executed next. [lES-2010} In an INTEL 8085A microprocessor, why is READY signal used? (@) To indicate to user that the microprocessor is working and is ready for use (b) To provide proper WAIT states when the microprocessor is communicating with a slow peripheral device (©) Toslow down a fast peripheral device soas to communicate at the microprocessors device (@) None of the above IES 2008] In DMA operation, the processor is interfered more in (@) Cycle stealing technique (b) Burst mode (©) Interleaved DMA (6) None In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively (@ BandF (b) Aand F (© HandF (d) Aandc ©coprio) iw Q.9 After an arithmetic operation, the flag register ‘of a 8085 microprocessor has the following look Dy]. [D6 | | Ps] |, | O +fotx|7]x]o|x]? The arithmetic operation has resulted in (@) Acarry and odd parity number having 1 as the MSB (b) Zero and the auxiliary carry flag being set (©) Anumber with even parity and 1 as the MSB (@) Anumber with odd parity and 0 as the MSB {1ES-2003] Q.10 The number of output pins of a 8085 microprocessor are (@) 40 (b) 27 (©) 21 @) 19 [lES-2002] Q.11 Match List-I(Interrupt) with List-II (Property) and select the correct answer using the code given below the lists: List-I A. RST7.5 B. RST5.5 Cc. INTR D. TRAP Codes : AB @1 (o) 2 1 (2 List-11 Non-maskable Edge sensitive Level sensitive Non-vectored soONe 3 4 4 3 ROBO D 2 1 2 Q.12 INTA is requried only for (@) RST5.5& RST 65 (b) RST75 (c) INTR (@) TRAP Q.13 Output of the assembler in machine codes is referred to as (a) Object program (b) Source program (©) Macro instruction (d) Symbolic addressing [lEs-2003} Q.14 The correct sequence of steps in the instruction cycle of a basic computer is TON WieG MEN “SUOTBDNAAG ASV AGW 01 JONEW JO0IaNS AYBUAGOD @ 2a fou yooa Workbook 97 (@) Fetch, Execute, Decode and Read effective address (b) Read effective address, Decode, Fetch and Execute (©) Fetch, Decode, Read effective address and Execute (0) Fetch, Read effective address, Decode and Execute [IES-2012] Q.15 Which one of the following cycle is required to fetch and execute an instruction in a 8085 microprocessor ? (@) Clockcycle —_(b) Memory cycle (©) Machine cycle (d) Instruction cycle Q.16 With referennce to 8085 microprocessor, which ofthe following statements are correct? 1. INRis 1 byte instruction 2. OUTis 2 byte instru 3. STAis 3 byte instruction (@ 1and2only — (b) 2and3 only (©) 1and3only (6) 1,2and3 Q.17 For INTEL 8085, match List-I(Addressing Mode) with List-II (Instruction) and select the correct answer using the code given below the lists: List-1 List-It A. Implicitaddressing 1. JMP 3FADH B. Register-Indirect 2. MOVA,M C. Immediate 3. LDAOSFCH D. Directaddressing 4. RAL Codes: A Bc D @4 12 3 4 21 3 @3 21 4 @3 12 4 [lEs-2004] Q.18 Which of the following statements is/are correct? In INTEL 8085 the interrupt enable flip-flop can be reset by () Dlinstruction. (ii) System RESET. (ii) Interruptacknowledgment. (W)SIM instruction. (@) (ii), iii) and (iv) (©) (i) and (iv) (©) (@, (é and (ii) (d) All of these © Copyright MADE EASY ree wonwemadeeasypublcationsorg) 98 Electrical Engineering ¢ Microprocessors Q.19 Content of accumulatoris 8€ H, IfSIM instruction is executed, the which of the following statement is true (@) Serial output data is 1 (v) RST6.5, 7.5 are enable (©) RST5.5is enable (d) None of these jou walang wweuAdSO @ Q.20 To have the multiprocessing capabilities of the 8086 microprocessor, the pin connected to the grounds g (@) DEN (b) ALE & (©) INTR (@) MN g Q.21 Effective address is calculated by adding or subtracting displacement value to (@) immediate address (6) relative address 2 (©) absolute address 2 (d) base address g [lES-2001] z Q.22 In 8086, CS : 907 H, IP: OFFF H find effective |= or physical address (a) 9OFFFH (©) FFFOOH (b) 9170FH (d) None Numerical Data Type Questions Q.23 The total number of memory access involved (inclusive of opcode fetch) when an 8085 processor executes the instruction LDA 2016 H is 70 paonpoides 04 feu ¥008 5 Q.24 If the clock frequency of a microprocessor is 5 MHz. Then the time required to execute PUSH B instruction is __ usec. Q.25 Consider the execution of the following instruction by a 8085 microprocessor LXIH, O1FFH ‘SHLD 2050 H ‘After execution the contents of memory locations 2050 H and 2051 H and the registers H and L, H and__H aed vi will be ___H,, H respectively, ‘waww.madeeasypublications.org MADE ERSY Q.26 If the accumulator of the INTEL 8085A microprocessor contians 37 H and the previous operation has set the carry flag, the instruction ACI 56 H will result _ Hex, Q.27 Ifthe content of accumulator after execution of RIMis AGH, then interrupt pending is___and serial data received is & Conventional Questions Q.28 Draw and explain architecture and pin diagram ‘of 8085 microprocessor. Q.29 Draw the timing diagram of OUT 80H instruction If [A] = 50 H and fo, = 5 MHz. Q.30 Explain the sequence of steps involved in CALL and RETURN instruction in 8085. Q.31 Draw and explain architecture of 8086, > Try Yourself Tt. Explain flag register in 8085 with suitable ‘example. T2, Expl in 8085. DMA (Direct memory access) operation T3, The following program starts at locations 0100 H. LXISP, OOFF H LX, 0107 H MVIA, 20H sUBM Find the content of accumulator when the program counter reaches 0109 Hs. [Ans: 00H] © Copyright ) Programming of Microprocessors Q.4 Consider the following 8085 instructions : vw Multiple Choice Questions a4 ‘An 8085 microprocessor executes "STA 1234 H” with starting address location 1FFE H (STA copies the contents of the Accumulator to the 46-bit address location). While the instruction is fetched and executed, the sequence of values written at the address pins Ay, ~ Ag is. (@) 1FH,1FH, 20H, 12H (b) 1F HH, FEH, 17H, FFH, 12H ANA A, ORA A, XRA A, SUB A, CMP A Now consider the following statements 1. Allare arithmetic and logic instructions 2. All cause the accumulator to be cleared irrespective of its original contents 3. Allreset the carry flag 4. Allof them are 1 byte instructions Which of these statements is/are correct ? (@) 1,2,3and4 — (b) Zonly (9) 1,2and4 (4) 1,3and4 [ES-2005] (c) 1FH, 1FH, 12H, 12H Q.5_ Consider the following 8085 microprocessor (d) 1FH, 1FH, 12H, 20H, 12H program [GATE-2014] FFOOH: MVI A, DC H Q.2Thestackpointer of an 8085 micro-processoris sive ABCD H. At the end of execution of the UH, FFO8 H sequence of instructions, what willbe the content SUBM of the stack pointer? OUT A2H PUSH PSW bins a Alter execution of the command HLT, data Sr displayed at output port A2 H is MP FC70H (@) SAH (@) ABCBH (0) ABCAH (b) OC H (©) ABCOH (d) ABCBH (©) A2H [IES-2009] ~Tyssed vean 6 MO ID Fa uy pas 2 paaNpe;de 6g FeYSOR BM 0 EGON "MEG MN =LOREOIERS ASV BEG} OuUBAIANS AEAICO @ (6) Can'tbe determined due to insufficient data @3_ In an 8085 microprocessor, the contents of |# | 2:8 Consider the following program to be executed accumulator, after the following instructions are in INTEL 8085 starts at 3000 H executed will become LXISP, 4000 H XRA A PUSHH MVIB, FOH PUSHD SUBB CALL 3050 H () O1H (b) OFH ie H (©) FOH (@) 10H UT Seat MADE EASY -wwnw.madeeasypublications.org Electrical Engineering ¢ 100 ‘After execution of HLT instruction, the program counter and stack pointer contains respectively (@) 300A H.3FFC H (b) 3009 H,3FFC H (©) 300A H, SFFE H (6) 3009 H, SFFE H Q.7 The content of stack pointer and accumulator after the execution of program are respectively 9000H : LXI SP, FFOOH 9003 H: LX! H, 9009H 9006 H: PCHL 9007 H: MVIB, 66H 9009H: CALL Rt 900C H: JMP QUIT 900F H : XRA A 9010 H: RP QUIT: 9011 H: HLT (a) FFOOH, OOH (©) FEFFH, 90H RI: (b) FEFEH, OCH (d) FEO1H, 66H Q.8 Whichone of the following 8085 microprocessor programs correctly calculates the product of two 8-bit numbers stored in registers B and C? @ MVIA, 00H JNZLOOP cMPC DCRB HUT MVI, A, OOH MPC DCRB Huo MVIA, OOH. ADDC DcRB JNZLOOP HO MVIA, OOH. ADDC JNZLOOP INR B HUT Loop (o) Loop (©) LOOP (d) Loop Q.9 Consider the following assembly language program in INTEL 8085. MADE EASY Microprocessors MADE EASY MVLB, XX H 7 \2:DCRB 9 JNZL2 S HO $ Find 'XX’ if fg, = 8 MHz and total execution 2 time of program is 500 us. : (a) B9H (b) B2H 2 (©) 32H (d) ABH Q.10 Consider the following assembly language If the above program is executed in 8085 then data displayed at PORT 1 and content of flag register is respectively. (a) 00H, 95H (©) C5H,94H (6) C5H, 95H (d) 00H, 44H Q.12 Match List-I (Instruction) with List-IT (Application) and select the correct answer using the code given below : = program in INTEL 8085, 0; given & LXIB, 0004 H g 12: DCXB 8 UNZL2 & HLT z How many times the loop L2 is executed ? z @) Zero (o) 1 z 4 (@) Infinite | Q.11 Consider the assembly language program given z below z () MVIA, 8FH g (2) sul CAH & ® JC DISPLAY 7 @ OUT PORT! z 6) HL 3 (6) DISPLAY XRA A z @ OUT PORT g ® Hu 3 2 List-t Ust-1 A. SIM 1. 16bitaddition B. DAD 2. Initializing the stack pointer 5 C. DAA 3. Serial output data 3 D. SPHL 4, Checking the 3 currentinterrupt & mask setting 7 5, BCD addition Publicaton © Copyright MADE EASY Workbook Publications on | 101 Codes Q.17 Consider the assembly language program given ABC D o below. @5 4214 8 MVIA, 84H OSE ere 3 MVIB, ABH @5 12 4 z 3 45 1 2 aided s MOV D, A 2 HI Numerical Data Type Questions Q.13 LXIH, 9876 H ‘SHLD 5000H MOV A, M STA 4000 H Hu Length of the program is bytes. Q.14 Consider the following assembly language program in INTEL 8085, XRAA LXIB, 000FH DCxB ANI JC HUT While execution of above program the loop will be executed _ times. Loop FFH LOOP Q.16 Consider the following assembly language program in INTEL 8085. MVIC, 00H L3:DCRC JNZL3 HO How many times the instructions DCR C is executed. Q.16 Consider the following assembly language program in INTEL 8085. If 8085 is operating at a frequency of 3 MHz then total time required to execute the above program __ysec. Q.18 Consider the program given below for INTEL 8085 MVIC, OB H <1, 2400 H “LX, 3400H MOV A, M STAXD INRL INRE DCRC NZLOOP HUT The total number of memory accesses required are (ahd ASV BOW OV Loop Q.19 Consider the following 8085 microprocessor assembly language program. LXISP, 0200 H LxIB, 1028 H UXIH, 42FF H PUSHH LXID, 20FE H DADB XCHG DADD HLT ‘After execution of above program content of HL register pair is hex. Serna aena 3 = 2 3 MVIA, 1CH ORA A Conventional Questions U1: RAL JNCLA ; HU Q.20 Write an assembly language program to fou = 2 MHz, then time for which loop executes transfers 5 bytes of data from location 5000 H is, usec. to 9000 H in INTEL 8086. —— —$—_—_~ > © Copyright MADE EASY worwemadeeasypublications org 102 | Electrical Engineering © Microprocessors MADE ERSY Publications Q.21 Write on assembly language program to find | | T2. Consider the following 8085 microprocessor number of even and odd number from bytes | @ program of data . Store the count of even numbers in B | 2 MVIC, FF H and odd numbers in C. S MVIB, FFH Q.22 Write an ALP to find smallest number from | = L1:D6RC 40 bytes of data. E Se z ocRB Q.23 Write an assembly language program to | 3 JNZLA generate a delay of 100 msec in INTEL 8085. HIT 7 How many times DCR C instruction executes? Try Yourself 3 [Ans: 65,279] §| 73. Consider the following instructions executed in T1. Consider the following assembly language | @ 8086 program PUSH AX; AX has 0020H in it XRAA PUSH BX; BX has 1234H in it MVIA, 50H POP AX; MVIB, OF H ADD AX, BX; LOOP DCRA POP. CX JNZLOOP Find the content of CX register after execution. INRB [Ans: 20 H] JCLOOP HLT The program is executed in INTEL 8085, find the number of times INR B executed. [an To peonpoider eq Ke y00a sit JO ed ON TUleG MON "SU0I ‘ojssjuned UaTITI ey) TROY WHO} AUR UI pe Memory and I/O Interfacing Multiple Choice Questions Q.1_ RAMand ROM, both are (@) Sequentially accessed memory (b) Randomly accessed memory (©) Either (a) or (b) (@) RAM: Randomly accessed, sequentially accessed ROM Q.2. Memory chips of four different sizes as below are available 1, 82Kx4 2. 82K x 16 3. BKx8 4, 16K x4 Allthe memory chips as mentioned in the above list are Read/Write memory. What minimal ‘combination of chips alone can map full address space of 8085 microprocessor? (@) 1and2 (0) 1 only (©) 2only (@) 4only (IES-2005) Amemory of 8 KB is designed using 2048 x 8 RAM chips. The number of chips required are (@)4 (0) 6 (8 (@) 16 Ina512 x 4 ROM chip, the number of address lines are (a) 512 (bo) 4 ©9 @ 1 Which of the following components are used in interfacing memory with microprocessor (@) Tristate buffer (b) Encoder (©) Latch (d) Allof the above Qs Q4 Qs © Copyright MADE EASY Q.6 Ending address of an 8 KB ROM is B72E H find starting address (@) D72DH (b) 972FH (0) 6543H (d) None Q.7 Consider'the 3 x 8 decoder given below If this to be used with 8085 to generate read and write control signals then valid outputs are (@) Day Dy, Dz, Dy Dy, Day Dey (©) Dg, Dy, Dp, Dy, Ds Dg (©) Dy, Dy Dy, Dg (€) Dy, Dy, Dy, Dy Q.8 Memory map of given interfacing logic is 6800 H- 6FFFH 7800 H - 7FFFH 7000H -77FFH None fa) (b) © (@) “Tojssjaed ueaiw 6 ROL Glo ua a pesign 20 peanpaide! 69 KA yo09 aa Hed ONC MON SUOTBDIGNA ASV SAVIN BHU OSIaNS BHBUAGOD vwunemadeessypublcations org) Pub 104 Q.9 What memory address range is NOT represented by chip#1 and chip #2 in the figure. A, to Ag in this figure are the address lines and CSmeans Chip select. A 256 bytes Chip #1 cs Db PD cs 256 bytes Chip #2 —_ AowAsh Posts (@) 0100-02FF (bo) 1500-16FF (©) FQ00-FAFF (a) F800-FOFF [GATE-2005] Q.10 Consider the figure given below. so 2ST] tow | i | Micro- CSom | | | jae oS 1 | 1S) | 0S By fewer my ok feo tes cua B= St Port pt — Light 1 3 ta ar ts gue ‘The following instructions are executed, IN 01H XRI C2H RAL OUT 10H ‘www.madeeasypublications.org x = Electrical Engineering © Microprocessors an 70 poonpoidai eq feu yood Sui jo ved ON UIBO MON “SUOTaHIand ASV SVN O1eiTeu BATaNS TUBERGOD @ ‘ojseluned uanipw oui inOUHIM wz0} AUB UI pO " MADE ERSU Pul EASY Publications MADE Which of the following statements is/are true. (i) Airconditioner and coffee pot are ON. (ii) Heater and TV. are ON. (iiiyOnly 2 Lights are ON. (iv) TV. and only Light 4 are ON. (@) (@iand(@) ——(b) (ii) only (©) (ii) and (iv) (6) (ii) and (iv) Q.11 For the 8085 microprocessor, the interfacing circuit to input 8-bit digital data (Di, ~ Diy) from an external device is shown in the figure. The instruction for correct data transfer is woDevce 2%,-01, 00, 00,| bs, os, (@) MVIA,F8H (bd) INFBH (©) OUTFBH (@) LOAF8FBH [2014 : 2 Marks, Set-2] Q.12 The following is not true for RS232 standards (@) Itestablishes the way data is coded (b) It defines signal voltage levels (c) Does not decide data transmission rate (d) Itdefines standard connector configurations Q.13 The interfacing device used to generate accurate time delay in a microcomputer system is (@) INTEL8251 —(b) INTEL 6253 (© INTEL8257 —(@) INTEL 6259 Q.14 What is the maximum memory that can be interfaced with INTEL 80867 (b) 1MB (@) 2MB (@) 64KB (©) 8KB i © Copyright MADE EASY Numerical Data Type Questions Q.15 The internal memory of INTEL 8085 is. byte Q.16 Maximum number of 256 x 4 memory chips that can be interfaced with INTEL 8085 microprocessor are Q.17 A read write memory chip has a capacity of 32 kb. Ifthe memory chip is having equal number address lines and data lines, then minimum number of data lines are Q.18 A memory system of 128 K bytes needs to be designed with RAM chips of 2 K bytes each and a decoder circuitry constructed with 1x 2. decoder chips with “enable” input. The minimum number of decoder chips required in design are Q.19 In INTEL 8085, suppose the peripheral mapped VO has address length of M and memory mapped I/O has address length of N. Then M+N= Conventional Questions Q.20 Describe various interfacing components. Q.21 Design a memory of 8 KB using 2048 x 8 RAM chips such that the memory map is 2000 H to 3FFFH, Q.22 What are the differences between memory mapped lO and I/O mapped 0? Q.23 Write an ALP to access a data byte from port address 60 H and send it to port address 70H wherea display is connected. Draw the required interfacing logic circuit, Q.24 If the output of the NAND gate is connected to ‘memory chip GS line then find the capacity and memory map of the memory chip. © Copyright ‘Tojse1uod Voniam uy yROUIyM 70) AUB Ul PaRTn 70 poanpordas eq ABW YOO 8) MADE EASY Workbook | 105 Try Yourself T1. Ifa page of memory is assumed to be 256 bytes then in how many pages total memory of 8085 can be treated ? [Ans: 256] T2. A 1Kbyte memory module has to be interfaced with an 8-bit microprocessor that has 16 address lines. The address lines A, to A, of the processor are connected to the corresponding address lines of the memory module. The active low chip select CS of the memory module is connected to the y, output of a 3 to 8 decoder with active low outputs. S,, S,, and S, are the input lines to the decoder, with S, as the MSB. The decoder has one active low EN; and one active high EN, enable lines as shown below. The address range(s) that gets mapped onto this memory module is (are) Aa As Aw & Ss & Ay EN2 910 8 decoder AvP EN, Yo Yr Ye Ya Ya Ys Yo Yr es (@) 3000, 10 33FF,, and £000,, to ESF), (b) 1400,t0 17FF, (©) 5300, to 53FF,,and A300, to ASFF,, (d) 5800,,to SBFF,, and D800,, to DBF, tt (Ans: (d)] ww madeeasypubliationsor9 Publications

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