Q.6 Thecharacteristic equation of the T-FF is given by (@) Q*=T0+QK (b) Q=TQ+TQ (c) Qt=TQ ( Q*=T0 a [©Copyright MADE EASY Publications vworemadeasypublcationsorg74 Q7 Electrical Engineering © Digital Electronics The circuit realization of the combination logic block shown in figure to obtain the following truth table will be, ALB Onn 0}0/ G, fo[it 4 1{0] Q, 1jij 0 A ‘Combinationa | J Qo 8 ae, apo ing ASW 3QWW O1 HEU Foalans WBUKdoD © joa men av TON Publications @ A (b) B © 7B -(@) AB Q.9 _X-Yflip flop, whose Characteristic Table is given below is to be implement using a J-K flip flop XY | Qnat ofo| 4 ol1| a, 7/o| T/if 0 This can be done by making (@) J=¥.K=x (b) (c) J=Y,K=¥ (qd) Q.10 Match List4 with List-Il and select the correct answer using the codes given below the lists: List-| A. Shiftregister B. Counter C. Decoder List-It z 1. Frequency division g 2. Addressing in memory chips po——L))»—x 8 3. Serial to parallel data conversion (@ ao— i Codes: , > z A BC 3 @ 3 2 1 D— a ) 102 2 Bo- « 5 © 2 1 3 8 Torealize the given uth table fom the cireuit]2] « () 3 1 2 TEC : GATE-2004] ‘Shown in the figure, the input to Jin terms of A g | Q.11 Two D-flip flops, as shown below are to be and Bwould have to be s connected as a synchronous counter that goes 3 through the following Q, Q, sequence eee ieee = 00-401 > 11 10 00. Bo ee 3 The inputs D, and D, respectively should be Clock —! 2 connected as Truth Table a Tm BH OF ATE To, g use Ise pa {ene t 3 cK, cK Bf ofol a, 3 Clock] o}if 4 3 = — Tote z (@ OF anda, ab) Banda, e 7/110 ° © Ga, and@ a (d) Ganda, ~ " [EC : GATE-2006] ‘wwwmadeeasypublications.org MADE EASY ©Copyright)MADE EASY Publications Q.12 The clock frequency applied to the digital circuit shown in figure below is 1 kHz. Ifthe initial state of the output Q of the flip-flop is ‘0’, then the frequency of the output waveform Q in kHz is Dp, Workbook | 75 Q.16 The mod-number of the asynchronous counter shown in figure op Of ANOS (2 (@) 0.25 1 Q.13 Astate diagram of a logic which exhibits a delay S t t t “pur NOK pater HIGH (a) 24" (b) 48 () 25 () 36 [@ATE-2013] | | 2-17 The output of moore sequential machine is @ function of 4) all present states of machine (b) all inputs in the output is shown in the figure, where Xis the do not care condition, and Qs the output (©) all combination of inputs and present state MON SUOTROTIaRG ASVS BGVA 61 onBU ToATaS AWBUAGOD @ representing the site (d) few combination of inputs and present state If Tis set highis circuit given below then Q,,,, is wn @ ©) Jenn fF 770 | pf 7a, The logic gate represented by the state | 5 diagram is 7 CP (a) XOR (b) OR 3 x % (© AND (0) NAND [GATE-2014] |3 @.14 Latches constructed with NOR and NAND |& | k= gates tend to remain in the latched condition | 3 44) complementary (b) Q, due to which configuration feature? e (c) high (a) low 8 timate 8 | @.19 The numberof unused states ina 4-bit Johnson (©) Gate impedance & on is ws (d) Cross coupling [ESE-2013] |& i.) ae 2) 2 / Q.15 Synchronous counters eliminate the delay | 3 [ESE-2003) Prone) eunnert wuntered wah asynchronous | | @.20 A 4 bt ripple counter and a 4 bt synchronous (@) input clock pulses are applied only tothe | counter are made using flip flops having a first and the last stages £ propagation delay of 10 nseach. Ifthe worst case () input clock pulses are applied only to the 7 delay in the ripple counter and the synchronous last stage 3 counter be Rand S respectively, then (©) input clock pulses are not used to activate (@) R=10ns, S=40ns any of the counter stages 0) R= 40ns, S=10 ns (@) input clock pulses are applied (0) R= 10ns, S=30n8 simultaneously (@) R= 30ns, S=10ns [ESE-2013] [GATE-2003] © Copyright MADE EASY wwwmadeeasypublicationsorg )Electrical Engineering 76 Q.21 In the modulo-6 ripple counter shown in the figure, the output of the 2-input gate is used to clear the J-K flip-flops. The 2-nput gate is (@) aNAND gate Ac) anOR gate (b) aNOR gate (6) an AND gate IGATE-2004] Q.22 The following binary values were applied to the Xand Yinputs of the NAND latch shown in the figure in the sequence indicated below: X=0, Y=1;X=0, ¥=0;X=1, Y=1. The corresponding stable P,Q outputs will be x P [GATE-2007] Q.23 For the circuit shown, the counter state (Q,Q,) follows the sequence © Digital Electronics Wed ON 118g MON “SUONEOT|ANd ASV SOYA 0} 18HBU YoBTaNg WOLKE @ jo poonpoidei @@ feu wood si ‘o|ssiued uetipm ui noyi|m WHO} ADE Uy pe MADE ERSY ) 00, 01, 10, 11, 00 (0) 00, 01, 10, 00, 01 ... (©) 00, 01, 11, 00, 01 (A) 00, 10, 11, 00, 10... [GATE-2007] 24 The figure below shows a 3-bit ripple counter, with Q, as the MSB. The flip-flop are rising-edge triggered. The counting direction is a of fr oe Croce cur ux de dt He of Hk 4d) always down (©) always up (©) upor down depending on the initial state of Qgonly (@) up or down depending on the initial states. of Q,, Q, and Q, [GATE-IN:2009] Q.25 The input A and clock applied to the Dfip-flop are shown in figure below. The output Qis, Crock |_| Input A oa Kp ou I @) x) © @ Q.26 The output Q, of aK tlip-flop is zero. itchanges to 1 when aclock pulse is applied. The input v,, a K, are respectively (Xrepresents don't care condition): \Uay7 and x (b) Oand x (c) Xando (d) Xand1 [ESE-2013] Q.27 The Q-output of J-K flip-flop is ‘1’. The output does not change when a clock-pulse is applied, The input J and K will be respectively (x-don't care state) ae (a) Oandx (b) Oand1 (c) tando er xand 0 (wwwmadeeasypublications org MADE EASY Ocopynght) (wo : Scopyiat)MADE EASY ‘Common Data for Questions (28 and 29): ‘Acounteris shown below: 1% ——% —a au hye hd ox fd] ic ky fet cur [our Q.28 The counter shown is, (@) Mod-12.-~ (©) Mod-14 far far (b) Mod-9 (d) None of these Q.29 Frequency of output Qp for 1 MHz clock is. (a) 63.3kHz 06) 83.3KHZ a (©) 73.3kHz (d) None of these Q.30 What are the counting states (Q,, Q,) for the counter shown in the figure below? a a | aa! JIKFlip-h (b) 11, 10,00, 11, 10... (A) 01, 10,00, 01, 10... [EC GATE-2009] (@) 01, 10, 11, 00, 01 (©) 00, 14, 01, 10, 00. Q.31 Following state diagram shows clocked sequential circuit: How many minimum number of states the sequential circuithas? ‘© Copyright (ang ASV BaVW OL neu IDAIGNS TUOUAGOD @ iro poonpoider 6a Kew 7009 Sih FO ‘an inowpm wi0) Aue UI pes MADE EASY Workbook 77 @é (o) 7 5s 4 Q.32 The state transition diagram for a finite state machine with states A, 8 and C, and binary inputs X, Yand Z, is shown in the figure. Which one of the following statements is correct? oe et (@) Transitions from State A are anvaeay defined. (b) Transitions from State B are ambiguously fined. ‘Transitions from State C are ambiguously defined. (d) All of the state transitions are defined unambiguously. [GATE-2016] Q.33 For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero. , (Ls8) 3- bit a ‘Syndhronous: ‘Counter cK— (SB) Roast Ifthe clock (Cik) frequency is 1 GHz, then the counter behaves asa (@) mod-Scounter {b). mod-6 counter (©) mod-7 counter (d) mod-8 countere<~ 2 IGATE-2016] . vwewwsmadeeasypublications 019 ) ?78 | Electrical Engineering © Digital Electronics MADE EASY Q.34 Asynchronous counter using two J- K flip flops that goes through the sequence of states: Q,Q, =00-> 10-4 01-4 11+ 00... is required, ‘To achieve this, the inputs to the flip flops are: i al fs ab jaha ASV SGVW O} neu yoelang WuBEAAED @ i IGATE-2016] Numerical Data Type Questions Q.35 The minimum number of flip-flops required by a Module-8 counter i 34 Reus 004 511 701180 ON Q.36 Five JK flip-slops are cascaded to form the circuit shown in Figure. Clock pulses ata frequency of 4 MHzare eppliedas shown. The frequency (in kHz) of the waveform at Q,is_ 16 oe SM an Beonpar cox LLIN [GATE-2014] Q.37 A digital circuit is designed with three Dip flops and an Ex-OR gate as shown in below figure. Ifthe intial value of Q, Q, Qc was 110 then the minimum number of clock pulses required to get Q, Q,Q,as O11 is. jwied uetiom ou InoWim v0) Rue ui pa Publications oa —! Q.38 Three 4 bit shift registers are connected in ‘cascade as shown in figure below. Each register is applied with a common clock pulse. input] S180 ‘SiPO PISO Shit ‘Shit shit cock ” Regsier 1] [ [Register 2| [“|Registr| A 4 bit data 1011 is applied to the shift register 1.The minimum number of clockpulses required to get same input data at output with same clock are. t-output ‘Common Data for Questions (39 and 40}: ‘A Mealy system produces a 1 output f the input has been 0 for at least two consecutive clocks followed immediately by two or more consecutive 1's. Q.39 The minimum number of states for this system is Q.40 The flip-lops required o implement this system are Try Yourself T1. Reduce the following state diagram and also write the reduced state table. | wwnnmadeeasypublications.org MADE EASYMADE ERSY Workbook 79 Publications 2. Consider the circuit given below: moo 10 [| 4 Ripple [4 A, Down [| ‘Counter . o Ha |MSB La> MOD 10 Ao Ripple Up ‘Clock- Counter | 4SB cy }aA 10301511 mie. ane Sendo ce enh nenbit cin 1B. Consider a mod-1000 ripple up counter The uy using S-R flip-flop: cycle for its MSB is __%. T16. Consider the flip-flop circuit diagram shown Sequence] Required State below. Draw output waveform for the circuit. No. Sequence g ojo oo g 1+ f 1 0 a 2 jo 4 1 g 3 1 1 0 a fo 3 i slo 0 1 -+Repeatfromooo | Show the state table indicating the present state, | £ the next state for each present state along with | 3 the input requirements of each of the S and R | 5 inputs. Show clearly the minimization of logic |2 requirements using K-maps. Write the logical | $ expressions for each excitation input ofall the | = flip-flops. Draw the logic diagram of the counter | 3 designed by you. 3 = [ESE-2009] || T17. Refer to the NAND and NOR latches shown in T11. Using Tlip-flop and logic gates, design a L-M |8 the figure. The inputs (P,, P,) for both the latches edge triggered flip-flop having a truth table as are frst mace (0, 1) and then after a few second, given below: g made (1, 1). The corresponding stable outputs (Q,, Q,) are wwwmadeeasypublications org MADE EASY ©Copyright)MADE ERSY a Q, P, % p, o (2) NAND: first(0, 1) then (0, 1) NOR: first (1, 0) then (0, 0) (b) NAND: first (1,0) then (1, 0) NOR: then (0,0) (©) NAND: first (1, 0) then (1, 1) NOR: first(0, 1) then (0, 1) (6) NAND: first (1, 0) then (1, 0) NOR: frst (0, 1) then (0, 0) rst (1,0) [EC : GATE-2009, Ans: (b)] The shift register shown in the given figure is initially loaded with the bit pattern 1010. Subsequently the shift register is clocked, and with each clock pulse the pattern gets shifted by one bit position to the right. With each shift, the bit at the serial input is pushed to the left most position (msb). After how many clock pulses will the content of the shift register become 1010 again? T18. rock Serial Tole Input n J * [Ans: (7)] 19, The given figure shows a ripple counter using positive edge triggered flip-flops. If the present state of the counter is Q, Q, Q, = 041, then its next state (Q, Q, Qe) will be__[o? 4 We ay Le ay | Touse|ured denim ou oun wid) Aue U1 pesiITN Je paanpolde: 6q feu yoo si] VEG ON TWI6G MON ‘suORBOHIGNd ASVI TGV 8 eHEW YoeIaNS AUBLACOD @ Workbook 81 720. Consider the circuit in the diagram. The @ operator represents Ex-OR. The Dflip-flops are initialized to zeroes (cleared). D a %| 2 q| | % ee ox | Lox ok i t [Cock The following data : 100110000 is supplied to the “data” terminal in nine clock cycles. After that the values of q, 4; q are (@) 000 (b) 001 (©) 010 () 101 [GATE-2006, Ans: (c)] 721, Forthe initial state of 000, the function performed by the arrangement of the J-K flipflops in the figure (a) Shift Register (©) Mod-6counter (d) Mod-2counter [EC : GATE-1993] (b) Mod-3 counter 722. A 4 bit right shift, shift register is shitting the data to the right for every clock pulse The serial input D is derived by using Ex-OR gates as shown in the figure. After three clock pulses the content in the shift register is to be 1010 at Q,Q,Q,Q,, what will be the initial content of the register. ae a a % a bitshin register aK al a a, cone T (@ 1100 b) 1010 up are-200, ‘Ans: (100)] (©) cot o10t ~ MADE EASY WaWansdbessypublicationsom) © Copyright S82 | Electrical Engineering © Digital Electronics MADE EASY 23. Consider the following state transition table with two state variables A and B and the input variable x and the output variable y Present State | Input | Next Stato | Output Atel: [aval y o | o [o folfeo 0 o fo [1 fols 0 o | 1 fo fol? 4 o f+ [+ti[+fol o + |0 [o [ofo 1 a fo [a tata ° a 4 111 [1Tofo 4 Ifthe initial state is A = O and B = 0, what is the minimum length of an input string which will take the macine to the state A= 1 and B = 1 with output y= 1? (3 (bo) 4 @s @6 [DRDO-2009} ng aWBukdOD © in 70 poanpordes eq ABW yoo Si To ed ON WI8 MON 'SUO) ‘Wojss|uned wenium ui inouHIM lO) ALB Ue Publications 24. Ifacounter having 10 FF's is initially at 0, what count wil it hold after 2060 pulses? (@) 0000001100 (b) 000001 1100 () 0000011000 (d) 0000001110 25. The frequency of the clock signal applied to the rising edge triggered D-flip flop shown in the following figure is 10 kHz. What is the output frequency at the flip flop output Q? (in kHz) Dp af cK —p a How many pulses are needed to change the contents of a 8-bit up-counter from 10101100 to 00100111 (right most bit is the LSB)? [IT GATE-2005] Gaza MADE ERSY Publications © CopyrightSemiconductor Memories ©|Q.4 How may address inputs, data outputs are Multiple Choice Questions g required for a 16k x 12 memory 2 @) 12,12 (b) 16,12 Q.1. Which one of the following statements is | & (©) 14.12 (@) 16.16 correct? 2 Q.5 Consider the following statements for a DRAM: (@) PROM contains programmable’AND' array | § 1. Bitis stored as a charge. and a fixed OR’ array 5 2. Itis made of MOS transistors. {b) PLA contains a fixed ‘AND' array and a 1 3. Speed of DRAM is faster than processors, programmable ‘OR' array g 4. Each memory cell requires six transistors. (©) PROM contains a fixed ‘AND’ array and a | & Which of these statements are correct? Programmable ‘OF arrey i (@) 1and2only —(b) Zand only (d) PLA contains a programmable ‘AND’ array | 2 (©) 3and4only (4) 1,2,Sand4 and a programmable ‘NOR’ array : TESE-2004) |= Numerical Data Type Q.2 AROMisto be used to implementa “squarer’, |Z Questions which outputs the square of a 4-bit number. What | 2 must be the size of the ROM? {| 28 A semiconductor RAM has a 12 bit adcrss (a) 16address lines and 16 data lines 3 register and an 8 bit data register. The total (b) 4 address lines and 8 data lines. Ss number of bits in the memory is KO) ES Selcteee Wee cee cam nee, H$ | @.7 tis desired to have 64 x 8 memory and if only (0) 4 address lines and 16 data lines i 16 x 4 size chips are available then number of (ESE-2004] € chips required are Q.3._AsingleROMis used to design a combinational |£)q.g The minimum number of MOS transistors circuit described by a truth table, What isthe |g requiredtomake.a dynamic RAMCel ero number of address lines in the ROM? 3 (@) Number ofinput variables in the truth table |? |@.9 The minimum number of MOS transistors (0) Numberof output variables inthe truth table | required to make a static RAM cell are, (©) Number of input plus output variables inthe | 3 truth table i (6) Number of lines in the truth table e [ESE-2006] i (copyrignt MADE EASY vwnmmadeeasypublcationsorg84 z Try Yourself 1. Electrical Engineering © Digital Electronics Consider the ROM shown below. (se) % % XX % Peppy BCD t© Deaimal decoder By Dy Dy Dy Dy Dy Dy Dy Dy Dy ¥, (MsB) Ifthe coding scheme for X, X, X; X9is BCD then find coding scheme for ¥ YY; Yo impliment the following logical expression using ROM circuit. ¥, (A, B, C) = Em(1, 2, 4,7) ¥, (A, B, ©) = Ent, 3, 5, 6) ¥, (A, B, ©) = E40, 2, 3, 4, 7) ¥ (A, B, C) = Zm43, 5, 6, 7) Implement BCD to excess - 3 convertor. ‘Gojseiur0d Uoriiw ew inowaym wio} Aue U| peslIan 70 Paonpoldel oq few yoo si) jo Ved ON Ted MAN UOHUDT|anG AVS SVN A JeNeW yoolang AYOUKGOD @ MADE EASY © Copyright|Integrated-Circuit Logic Families Multiple Choice Questions on Q2 Consider the following statements describing the property of a complementary MOS (CMOS) inverter: 1. Itis a combination of an n-channel FET and ap-channel FET. 2, There is power dissipation when the input carries the logical 1 signal 3. Thereisno power dissipation when the input carries the logical 1 signal. 4. There is power dissipation during transition, from 0 to 1 or from 1 10 0. Which of the statements given above are correct? (@) 1,2and3 (pb) 2,3and4 (©) 1,3and4 — (d) 1,2and4 [ESE-2006] ‘The NMOS circuit shown below is a gate of the type | ao (@) NAND © (b) NOR () AND (¢) EXCLUSIVE -OR [ESE-2003(EE)] ‘oyssnuiod ulm a yg ay Ale posi 79 paorpexda/ oq feu yBoe SO ed ON "NEG MEN VOHBO|ANG ASVS SAMI SHE BAIANS IHOGOO @ Qs Q4 Qs Qé Ainverter gate has guaranteed output levels logic't' = 3.8 and logic ‘0'= 0.7 V. The maximum, low level input voltage at which the output remains high = 2V. The minimum high-level input voltage atwhich the output remains low = 3.1 V, What are the noise margins of this gate? (a) NM, =2.4V, NM, =1.8V (0) NM, = 1.8 V, NM, = 1.3V (0) NM, =0.7 V, NM, =1.8V (8) NM, =0.7 V,NM, = 1.3V [ESE-2004(EE)] For a logic family Voy.is the minimum output high level voltage Vo, is the maximum output low level voltage Vis the minimum acceptable input high level voltage Vj, is the maximum acceptable input low level voltage ‘The correct relationship among these is: (©) Yan> Vou? Ya > You (©) Vou Yin Vin > You (©) Yn> You? Vou> Vir (A) Vou> Vin> You? Vir [ESE-1999] The open collector output of two 2-input NAND gates are connected to a common pull-up resistor. If the inputs of the gates are A, Band C, Drespectiyely, the output is equal to (@) ABCD (v) AB+CD (c) AB+CD (d) ABxCD {ESE-2002] The figure shows the internal schematic of a TTL ‘AND-OR-Invert (AO!) gate. For the inputs shown in the figure, the output Y is www.madeeasypublications.org36 | Electrical Engineering * Digital Electronies 1D A 8 Naina { @o (©) AB () 1 © 7B [GATE-2004] Q.7 The logical expression for the output 'Y of the diode circuit below is ° 3 e z Veo®5V 5ka Ace 3 ace: —0y 3 o—$—o| : tha z am 2 (a) (A+B)C (ot) A¥B+C (©) (A¥B)C (¢) AB+C Q.8 An NMOS circuit is shown in the figure below: = arf 7M |ber Od ‘The logical expression for the output (Y) equals to (a) PQ+A)+ST (b) P(Q+R)-ST 3 (0) P+(QA)(S+T)(d) (P+O)R+5T 3 www.madeeasypublications.org MADE EASY Q.9 Consider a DTL circuit as given below: Ifall the inputs (A, 8, C) are high then, (@) Input diodes D, is ON and D,, is OFF, Q, is in cut-off mode and Y = ABC. (b) Inputdiodes D, and D, is ON, Q, isin active mode and Y = A+B+C. (©) Input diodes D, and D, is ON, Q, is in ‘saturation mode and Y = ABC. (@) Input diodes D, is ON and D, is OFF, Q, is in saturation and Y= ABC, Q.10 Inthe TTL circuitin the figure, S,, S, and S, are select lines and.x, and x, are input lines. S, and xp ate LSBs. The output Y is 1 € 8:1 MUX Ss es, Game ab Y (@) indeterminate ©) AeB () Aes () C(A®B)+C(A@B) [GATE-EC:2001] Q.11 Which of the following is not a type of output configuration in TTL gates? (a) Totem-pole output (b) Open-coliector output (0) Transmission-Gate output (0) Tristate output © Copyrightmi EASY Q.12 The DTL, TTL, ECL and CMOS family of digital ICs are compared in the following 4 columns eon © Fanoutis minimum OTL DTL TTL CMOS Powor Consumption ie minimum Propagation day's cys Ec. TTL CMOS ECL DTL ™ TH The correct columnis (a) P (b) @ (AR @s [GATE-EC;:2003] Q.13 Identify the logic gate given in the figure rd (a) NOR (c) AND (b) NAND (d) OR [GATE-IN:2005] Q.14 A CMOS implementation of a logic gate is shown in the following figure: 5Y ‘The boolean logic function realized by the circuitis (@) AND (6) NAND. (c) NOR (@) OR [GATE-IN:2007] ‘©Copyright z & g z Tojssjuied vonjm 4) IROUI/M lnvoy Aue uy paRt|RA 20 poonpoide: eq Kew YON SI Workbook | 37 Q.15 The expression for output "Y" forthe circuit given belowis Moo 4 aff e4 4 : ¥ (a) A-(6+C) (b) A+ BC (©) A+BC (@) A(B+O) Q.16 The switching speed of ECL is very high, because the transistors (@) are switched between cut-off and saturation region (b) are switched between active and saturation region (©) are switched between active and cut-off region (d) may operate in any of the three regions Q.17 The figure of merit of a logic family is given by (a) Gain bandwidth product (©) (Propagation delay time) x (power dissipation) (©) (Fan out) x (Propagation delay time) (d) (Noise-margin) x (Power dissipation) Q.18 Match List-I with List-II and select the correct answer using the code given below the Lists: List-1 List-Il A.HTL 1. Highfan-out B. CMOS 2. Highest speed of operation C. PL 3. High noise immunity DECL 4. Lowestproductof power & delay Codes: AB cD @3 4 1 2 2 4 1 3 @3 1 4 2 @2 143 www.madeeasypublications.orgElectrical Engineering 88 Q.19 The inverter 74 AL S01 has the following specifications: DAMA, Toy mae = 8 MA, Jhpymax = 20 UA. Imex = 0-1 MA. ‘The fan out based on the above will be. Numerical Data Type Questions Foumax Q.20 An IC family has an average propagation delay of 10 ns and an average power dissipation of 5 mW. Figure of merit of IC family is__pJ. @ T1. The fan-out of the TTL gate having Joy = — BHA, Iyj= 40 BA, To, : Jy, = -1.6 mAis equal to www.madeeasypublications.org © Digital Electronics a oalang WOUND jang ASWa 3aWW O18) in 10 poonpordoy aq Kew yoo Ba jo wed ON 14laG MON 20D) 3 TRO ojsehur0d ua Publ T2, “MADE EASY e oy The transistors used in a portion of the TTL gate shown in the figure have a B = 100. The base- emitter voltage of is 0.7 V for a transistor n active region and 0.75 V for a transistor in saturation. the sink current J = 1 mA and the output is at logic 0, then the current J, will be equal to mA, BV 1.4 ka Eames) © Copyright) ee)ADC and DAC Multiple Choice Questions a4 Q2 The resolution of a 12 bit Analog to Digital converter in percentis (a) 001220 (b) 0.02441 (c) 0.04882 (¢) 0.09760 [ESE-2002(EE)] Consider a 6-bit D/A converter having full scale output of 3mA and a full-scale error of +0.4% FS. For a binary input sequence of 10111 1, therange of possible outputs willbe (2) (2220 2240) WA (b) (492-512) yA (c) (2226-2250) pA (d)(1295 - 1325) yA Linked Data for Questions (3 and 4): A 3bit weighted resistor D/A converter with MSB resistance R= 10k@ having input bit stream bb, b, = 1 0 1 is shown in figure below: Ra bka Qs a4 © Copyright The total input current ‘7 in the circuit will be (@) 0.125mA —(b) OS mA (©) 0625mA —(d) 1.0 mA ‘Whats the analog output voltage by this DAC? (@ -3.125 volt. —_(b) 0.625 volt (©) -25 volt (@) -8.0 volt —asshunodUotan Boy ty foe paso pacrpaxdar 0 Fu Bee Bo EU ON IBC =A BUDREOIGAG ASV SAVIO BHU DeaNS MABUAGED @ Qs ae az as MADE ERS lea The circuit shown below is a R-2R ladder type DAC with reference voltage +6 V and R,= 9k. and R= Vor Vout Vea = #8 Volt ‘As above figure-2 switches are ON and 1 is OFF, the output voltage will be (@) -675V () 135 (c) -20.25V (d) -40.5V The output voltage of a 5-bit D/A binary ladder that has a digital input of 11010 (Assuming 0 = 0 Vand 1 = +10 V) is (@) 3.4375V () 60V (©) 8.125V (d) 9.6875V [ESE-2001] Which one of the following D/A converters has the resolution of approximately 0.4% of its full scale range? (@) Beit (©), 12-bit (b) 10-bit (d) 16-bit [ESE-2006) An 8 bit successive approximation analog to digital converter has full scale reading of 2.55 V and its conversion time for an analog input of 1 Vis 20s, The conversion time fora 2V input willbe wwwmadeeasypublications.org90 | Electrical Engineering « 1 Electronics (@) 10ys (b) 20us (©) 40us (6) 50 us [GATE-2000] Q.9_ The minimum number of comparators required to build an 8 bit flash ADC is @s8 (b) (©) 255 (d) 256 [GATE-2002] Q.10 4 bit binary weighted resistor DAC has LSB resistance of 32 kQ. The corresponding MSB resistance is (@) 2ka (b) 4k (0) 8kQ (d) 32kQ ‘Statement for Linked Answer Questions (11 and 12): In the Digital-to-Analog converter circuit shown in the figure below, V, = 10 Vand A= 10k. RoR Ri oR 9 Reus yoo 514119 WEG ON 14/90 NON "SUOTBDIGNA ASV TOWN Ol HEU I9BTaNS TUOUAdOD @ [GATE-EC:2007] Q.11 The currentiis (a) 31.25uA (b) 62.544 (©) 125pA (d) 250A [GATE-£C:2007) Q.12 The voltage Vis (@ -0.781V (b) -1.562V (©) -3.125V (6) -6.250V [GATE-EC:2007] Q.13 A4it successive approximation type ADC has a full scale value of 15 V. The sequence of the states, the SAR will traverse, for the conversion of an input of 8.15 Vis (@) >a ce-ce-E) (0) {9108-SHEB-SOTS OE -OED-GE jad uovium oui noun wo} Aue ul peaian Jo paanpalda) wwwmadeeasypublications.org MADE ERSY ‘ub ©) CBEMSIED-OLT (G) Geri ~SES-RISD-TE-SHIETD ~~) [GATE-IN:2010] Q.14 Which of the following statements is/are correct, about Analog to Digital converters (ADCs). (i) Flash type ADCs are fastest (i) In successive approximation type ADCs conversion time depends on magnitude of analog voltage. (il) Counter type ADCs has fixed conversion time (iv) Dual-siope type ADCs are slowest (@) Allofthese —(b) (ii) and (ii) (© (and(iv) — d) (ionly Q.15 For a 4-bit digital to analog convertor, analog voltage varies from Oto 1.5 volts. The resolution of DACis (a) 10% (b) 6.25 % (©) 6.67% (@ 9.375% Numerical Data Type Questions Q.16 An 8-bit D/A converter has a full scale output voltage of 20 V. The output voltage when the input is 11011011, is V. [ESE-2001] Q.17 Forthe 4 bit DAC shown in the figure, the output voltage Vy is v. 1K 7 [GATE-2000] © CopyrightEe Q.18 A 10-bit DAC provides an analog output which has a maximum value of 10.23 volts. Resolution of the DAC is, mv. [ESE-2012] Q.19 The analog output voltage of a 6 bit DAC with reference voltage as 20 V for the digital input 011101 is Volts. Q.20 AS bit D/A converter has a current output. Ifan output current J,4,= 10 mA is product for a digital inputof 10100, the value of f,, fora digital input of 11101 will be. mA. 1. A 4+bit D/A converter is connected to a free- running 3-bit UP counter, as shown in the following figure. Which of the following waveforms will be observed at V,? s ‘« }—}o, see 0,}=4o, i Mo Sm | EK Clock ae a = cour = DAC In the figure shown above, the ground has been shown by the symbol V. OV ON [GATE-2006] T2. A&-bit AD convertor is used over a span of Zero to 2.56. The binary represen-tation of 1.0V signal is (2) 01100100 (©) 10100101 (b) 01110001 (d) 101.000 10 [ESE-2013] © Copyright fang W6UAdOD © : g g (90 MON "=u ojsejuied UoHlIm uy IROUIH 10) Aue Ul Pasyin 70 peanpardes ea Few yoOg SIN 70 Wed ON 73. 14, Clock Workbook 91 Consider the circuit given below. MsB, MSB yf T | cry | F| vigil to Inputs bis! | Code | {| Analog -—V, 1 |eonverter| |_| Converter ise Ls8 The full scale reading of Digital to Analog converter is 10.5 V. Each bit of Gray code converter output is given to digital to analog converter through an invertor. If input to the circuit is 110011, then corresponding output voltage V, is __ Volts. [Ans: 3.45 V] Consider the system given below: The clock input is connected to the 4 bit ring counter, The output of the ring counter acts as the clock for the other counters. All the counters shown in figure are positive edge triggered. ‘The output ofall counters act as input to. 14 bit DAC with step size (D) equal to 1 mV. If intially all counter are cleared then find the output o° DAC after 20 clock pulses. [Ans: 10.96 V] wwwmadeeasypublications.org| MADE EASY Analog Electronics +Digital workbook Electronics + Microprocessors _ G (EGG Sera CTi Ee Microprocessors SI. Unit | 1. Intel 8085 and intel 8086. 2 Programming of Microprocessors... 3. Memory and I/O Interfacing 0000 ‘cenit Sbjct ater n MADEEASYPblcatos NewDe Nope tisboxkneyberepoaiedcr edn aye hau ne wes comin |808s 1. Introduction: * Microprocessor definitions © Computer block diagrams * Differences between microprocessor and microcontroller (for interview purpose) © Memory (Memory architecture) differences ‘* Importance of Hexa-Decimal Numbers 2. Systems BUS:- Address, Data and Control © Memory basic 3. Internal Architecture * Register unit: General purpose registers, Special purpose registers © Arithmetical Logical Unit © Timing and Control unit, Signals, ALU, RD, WR, |O/M , HOLD and HLDA © Interrupts Unit: Types, Triggering, Vector address, applications * Serial /O control unit SID and SOD PIN Layout (Optional) 4, Programming Model * Softwares definitions © Programming cycle - Steps in writing 5, Instruction Format: Opcode, Operand © According to length-1 byte, 2 byte, 3 byte © Memory representation of a program 6 Addressing Mode: conventional). [Both for objective and 7. Timing Diagram: Definition: T-state, Machine cycle and instruction cycle, Example for an instruction. Microprocessors Description Sheet & Instruction Set Classification: ® Data transfer/Copy instructions ® Arithmetic and Logical instructions © Branching instructions ‘® Machine control instructions 9. Programs: Objective and Conventional © Simple addresses * Loops and I/O applications 10, Interfacing: * Memories - Basics, Classification Notation of memory, (M x N) © Problems: = Memory mapping * Starting and Ending addresses, = Using decoders © Interfacing IC's: 8251, 8253, 8255, 8257/37, 8279 © Interfaces: "Different buses (for ESE) = SPI, PC, CAN, USA2J © Applications of Microprocessors (for ESE)] * ESE - 8086 - Basics (Outline) 11, Microcontrollers * 8051 (Basics and architecture) © Types of controllers * Applications, 12, Embedded System * Definition * ApplicationMADE EASY Electrical Engineering @ Microprocessors 94 3) Josses01d0121y S808 TSLNI JO eaMDeNYDIy a | 8 sageacenry = mg sapey suas aos save _ no 1aS3u | 7 | wot's °s STv uM gy ino» oS fy t titititt sh tf | (@ una ssappvreea] [(@) une ssaippy foot aE nee eee. ik it onudo pue Suma eae | — [op on a oN) os bt : | | <9 | fon anaes | | heeee ; sty} fo fo s/f) ps ee es (2) 3 (s) @ g uogonuysuy @ 9 |@ @ ZN “Boy dway ‘Boy “dway (g) 2 (Ca (9) ses60u aoa? | | oon [pico on eves | Tonuog wdrusew umadeeasypublications.org (ror LI ate ds wzlow| solou), ubeMADE EASY Workbook 95 Publications Address/Siatus ‘Adéross Data bus Aed8s~ Ade ‘AD; ~ ADs Memory address and data bus interfacing intemal data bus ar u 8 1 N ‘niacin bye T uous 6 bytes: E R F A c E u N i i Intemel data bus Decoding Circuit E x| * ax E El ex ul x T| 0x ° N u N i T Register bank Flags (16) Timing and contr ict Clock and control Signals Architecture of INTEL 8086 Microprocessor MADE EASY wwwsmadeeasypublications.org 3) PublicationsIntel 8085 and Intel 8086 Multiple Choice Questions Q.1__ INTEL 8085is @) 16bitmicroprocessor (b) 32 bit microprocessor (c) 8 bit microprocessor (@) 4bit microprocessor Q.2_ Inan8 bit microcomputer, maximum memory can be connected Is 32 K bytes, the length of stack pointer, program counter and number of data lines are respectively @ 16, 16,8 (0) 15, 16,7 (©) 15, 15,8 (0) 16, 15,8 For the purpose of data processing an efficient assembly language programmer makes use of the general purpose registers rather than memory. The reason is (@) The set of instruction for data processing with memory is limited (b) Data processing becomes easier when register are used (©) More memory related instructions are required in the program for data processing (4) Data processing with registers takes fewer cycles than that with memory Qs [lEs-2011] Consider the following statements in 8085 microprocessor data-bus and address bus are multiplexed in order to 1. Increase the speed of microprocessor 2. Reduce the number of pins 3. Connect more peripheral chips Which of these statements is/are correct ? as ‘wwwmadeeasypublications org ‘ores uation a ynoaim wy Aue Ur paian 0 paonpendar a Keu}eo9 A Ve ON NBO MBN SUORES|aRG ABV OWN GU SHEL IGNS "NBUIGCO @ Qs a7 Qs (@) tonly (© 2and3 (b) 2 only (0) 1,2and3 [IES-2009] The content of the program counter of an 8085 microprocessor is (@) The total number of instructions in the program already executed (b) The total number of times a subroutine is called (©) The memory address of the instruction that is being currently executed (0) The memory address of the instruction that is to be executed next. [lES-2010} In an INTEL 8085A microprocessor, why is READY signal used? (@) To indicate to user that the microprocessor is working and is ready for use (b) To provide proper WAIT states when the microprocessor is communicating with a slow peripheral device (©) Toslow down a fast peripheral device soas to communicate at the microprocessors device (@) None of the above IES 2008] In DMA operation, the processor is interfered more in (@) Cycle stealing technique (b) Burst mode (©) Interleaved DMA (6) None In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively (@ BandF (b) Aand F (© HandF (d) Aandc ©coprio)iw Q.9 After an arithmetic operation, the flag register ‘of a 8085 microprocessor has the following look Dy]. [D6 | | Ps] |, | O +fotx|7]x]o|x]? The arithmetic operation has resulted in (@) Acarry and odd parity number having 1 as the MSB (b) Zero and the auxiliary carry flag being set (©) Anumber with even parity and 1 as the MSB (@) Anumber with odd parity and 0 as the MSB {1ES-2003] Q.10 The number of output pins of a 8085 microprocessor are (@) 40 (b) 27 (©) 21 @) 19 [lES-2002] Q.11 Match List-I(Interrupt) with List-II (Property) and select the correct answer using the code given below the lists: List-I A. RST7.5 B. RST5.5 Cc. INTR D. TRAP Codes : AB @1 (o) 2 1 (2 List-11 Non-maskable Edge sensitive Level sensitive Non-vectored soONe 3 4 4 3 ROBO D 2 1 2 Q.12 INTA is requried only for (@) RST5.5& RST 65 (b) RST75 (c) INTR (@) TRAP Q.13 Output of the assembler in machine codes is referred to as (a) Object program (b) Source program (©) Macro instruction (d) Symbolic addressing [lEs-2003} Q.14 The correct sequence of steps in the instruction cycle of a basic computer is TON WieG MEN “SUOTBDNAAG ASV AGW 01 JONEW JO0IaNS AYBUAGOD @ 2a fou yooa Workbook 97 (@) Fetch, Execute, Decode and Read effective address (b) Read effective address, Decode, Fetch and Execute (©) Fetch, Decode, Read effective address and Execute (0) Fetch, Read effective address, Decode and Execute [IES-2012] Q.15 Which one of the following cycle is required to fetch and execute an instruction in a 8085 microprocessor ? (@) Clockcycle —_(b) Memory cycle (©) Machine cycle (d) Instruction cycle Q.16 With referennce to 8085 microprocessor, which ofthe following statements are correct? 1. INRis 1 byte instruction 2. OUTis 2 byte instru 3. STAis 3 byte instruction (@ 1and2only — (b) 2and3 only (©) 1and3only (6) 1,2and3 Q.17 For INTEL 8085, match List-I(Addressing Mode) with List-II (Instruction) and select the correct answer using the code given below the lists: List-1 List-It A. Implicitaddressing 1. JMP 3FADH B. Register-Indirect 2. MOVA,M C. Immediate 3. LDAOSFCH D. Directaddressing 4. RAL Codes: A Bc D @4 12 3 4 21 3 @3 21 4 @3 12 4 [lEs-2004] Q.18 Which of the following statements is/are correct? In INTEL 8085 the interrupt enable flip-flop can be reset by () Dlinstruction. (ii) System RESET. (ii) Interruptacknowledgment. (W)SIM instruction. (@) (ii), iii) and (iv) (©) (i) and (iv) (©) (@, (é and (ii) (d) All of these © Copyright MADE EASY ree wonwemadeeasypublcationsorg)98 Electrical Engineering ¢ Microprocessors Q.19 Content of accumulatoris 8€ H, IfSIM instruction is executed, the which of the following statement is true (@) Serial output data is 1 (v) RST6.5, 7.5 are enable (©) RST5.5is enable (d) None of these jou walang wweuAdSO @ Q.20 To have the multiprocessing capabilities of the 8086 microprocessor, the pin connected to the grounds g (@) DEN (b) ALE & (©) INTR (@) MN g Q.21 Effective address is calculated by adding or subtracting displacement value to (@) immediate address (6) relative address 2 (©) absolute address 2 (d) base address g [lES-2001] z Q.22 In 8086, CS : 907 H, IP: OFFF H find effective |= or physical address (a) 9OFFFH (©) FFFOOH (b) 9170FH (d) None Numerical Data Type Questions Q.23 The total number of memory access involved (inclusive of opcode fetch) when an 8085 processor executes the instruction LDA 2016 H is 70 paonpoides 04 feu ¥008 5 Q.24 If the clock frequency of a microprocessor is 5 MHz. Then the time required to execute PUSH B instruction is __ usec. Q.25 Consider the execution of the following instruction by a 8085 microprocessor LXIH, O1FFH ‘SHLD 2050 H ‘After execution the contents of memory locations 2050 H and 2051 H and the registers H and L, H and__H aed vi will be ___H,, H respectively, ‘waww.madeeasypublications.org MADE ERSY Q.26 If the accumulator of the INTEL 8085A microprocessor contians 37 H and the previous operation has set the carry flag, the instruction ACI 56 H will result _ Hex, Q.27 Ifthe content of accumulator after execution of RIMis AGH, then interrupt pending is___and serial data received is & Conventional Questions Q.28 Draw and explain architecture and pin diagram ‘of 8085 microprocessor. Q.29 Draw the timing diagram of OUT 80H instruction If [A] = 50 H and fo, = 5 MHz. Q.30 Explain the sequence of steps involved in CALL and RETURN instruction in 8085. Q.31 Draw and explain architecture of 8086, > Try Yourself Tt. Explain flag register in 8085 with suitable ‘example. T2, Expl in 8085. DMA (Direct memory access) operation T3, The following program starts at locations 0100 H. LXISP, OOFF H LX, 0107 H MVIA, 20H sUBM Find the content of accumulator when the program counter reaches 0109 Hs. [Ans: 00H] © Copyright )Programming of Microprocessors Q.4 Consider the following 8085 instructions : vw Multiple Choice Questions a4 ‘An 8085 microprocessor executes "STA 1234 H” with starting address location 1FFE H (STA copies the contents of the Accumulator to the 46-bit address location). While the instruction is fetched and executed, the sequence of values written at the address pins Ay, ~ Ag is. (@) 1FH,1FH, 20H, 12H (b) 1F HH, FEH, 17H, FFH, 12H ANA A, ORA A, XRA A, SUB A, CMP A Now consider the following statements 1. Allare arithmetic and logic instructions 2. All cause the accumulator to be cleared irrespective of its original contents 3. Allreset the carry flag 4. Allof them are 1 byte instructions Which of these statements is/are correct ? (@) 1,2,3and4 — (b) Zonly (9) 1,2and4 (4) 1,3and4 [ES-2005] (c) 1FH, 1FH, 12H, 12H Q.5_ Consider the following 8085 microprocessor (d) 1FH, 1FH, 12H, 20H, 12H program [GATE-2014] FFOOH: MVI A, DC H Q.2Thestackpointer of an 8085 micro-processoris sive ABCD H. At the end of execution of the UH, FFO8 H sequence of instructions, what willbe the content SUBM of the stack pointer? OUT A2H PUSH PSW bins a Alter execution of the command HLT, data Sr displayed at output port A2 H is MP FC70H (@) SAH (@) ABCBH (0) ABCAH (b) OC H (©) ABCOH (d) ABCBH (©) A2H [IES-2009] ~Tyssed vean 6 MO ID Fa uy pas 2 paaNpe;de 6g FeYSOR BM 0 EGON "MEG MN =LOREOIERS ASV BEG} OuUBAIANS AEAICO @ (6) Can'tbe determined due to insufficient data @3_ In an 8085 microprocessor, the contents of |# | 2:8 Consider the following program to be executed accumulator, after the following instructions are in INTEL 8085 starts at 3000 H executed will become LXISP, 4000 H XRA A PUSHH MVIB, FOH PUSHD SUBB CALL 3050 H () O1H (b) OFH ie H (©) FOH (@) 10H UT Seat MADE EASY -wwnw.madeeasypublications.orgElectrical Engineering ¢ 100 ‘After execution of HLT instruction, the program counter and stack pointer contains respectively (@) 300A H.3FFC H (b) 3009 H,3FFC H (©) 300A H, SFFE H (6) 3009 H, SFFE H Q.7 The content of stack pointer and accumulator after the execution of program are respectively 9000H : LXI SP, FFOOH 9003 H: LX! H, 9009H 9006 H: PCHL 9007 H: MVIB, 66H 9009H: CALL Rt 900C H: JMP QUIT 900F H : XRA A 9010 H: RP QUIT: 9011 H: HLT (a) FFOOH, OOH (©) FEFFH, 90H RI: (b) FEFEH, OCH (d) FEO1H, 66H Q.8 Whichone of the following 8085 microprocessor programs correctly calculates the product of two 8-bit numbers stored in registers B and C? @ MVIA, 00H JNZLOOP cMPC DCRB HUT MVI, A, OOH MPC DCRB Huo MVIA, OOH. ADDC DcRB JNZLOOP HO MVIA, OOH. ADDC JNZLOOP INR B HUT Loop (o) Loop (©) LOOP (d) Loop Q.9 Consider the following assembly language program in INTEL 8085. MADE EASY Microprocessors MADE EASY MVLB, XX H 7 \2:DCRB 9 JNZL2 S HO $ Find 'XX’ if fg, = 8 MHz and total execution 2 time of program is 500 us. : (a) B9H (b) B2H 2 (©) 32H (d) ABH Q.10 Consider the following assembly language If the above program is executed in 8085 then data displayed at PORT 1 and content of flag register is respectively. (a) 00H, 95H (©) C5H,94H (6) C5H, 95H (d) 00H, 44H Q.12 Match List-I (Instruction) with List-IT (Application) and select the correct answer using the code given below : = program in INTEL 8085, 0; given & LXIB, 0004 H g 12: DCXB 8 UNZL2 & HLT z How many times the loop L2 is executed ? z @) Zero (o) 1 z 4 (@) Infinite | Q.11 Consider the assembly language program given z below z () MVIA, 8FH g (2) sul CAH & ® JC DISPLAY 7 @ OUT PORT! z 6) HL 3 (6) DISPLAY XRA A z @ OUT PORT g ® Hu 3 2 List-t Ust-1 A. SIM 1. 16bitaddition B. DAD 2. Initializing the stack pointer 5 C. DAA 3. Serial output data 3 D. SPHL 4, Checking the 3 currentinterrupt & mask setting 7 5, BCD addition Publicaton © CopyrightMADE EASY Workbook Publications on | 101 Codes Q.17 Consider the assembly language program given ABC D o below. @5 4214 8 MVIA, 84H OSE ere 3 MVIB, ABH @5 12 4 z 3 45 1 2 aided s MOV D, A 2 HI Numerical Data Type Questions Q.13 LXIH, 9876 H ‘SHLD 5000H MOV A, M STA 4000 H Hu Length of the program is bytes. Q.14 Consider the following assembly language program in INTEL 8085, XRAA LXIB, 000FH DCxB ANI JC HUT While execution of above program the loop will be executed _ times. Loop FFH LOOP Q.16 Consider the following assembly language program in INTEL 8085. MVIC, 00H L3:DCRC JNZL3 HO How many times the instructions DCR C is executed. Q.16 Consider the following assembly language program in INTEL 8085. If 8085 is operating at a frequency of 3 MHz then total time required to execute the above program __ysec. Q.18 Consider the program given below for INTEL 8085 MVIC, OB H <1, 2400 H “LX, 3400H MOV A, M STAXD INRL INRE DCRC NZLOOP HUT The total number of memory accesses required are (ahd ASV BOW OV Loop Q.19 Consider the following 8085 microprocessor assembly language program. LXISP, 0200 H LxIB, 1028 H UXIH, 42FF H PUSHH LXID, 20FE H DADB XCHG DADD HLT ‘After execution of above program content of HL register pair is hex. Serna aena 3 = 2 3 MVIA, 1CH ORA A Conventional Questions U1: RAL JNCLA ; HU Q.20 Write an assembly language program to fou = 2 MHz, then time for which loop executes transfers 5 bytes of data from location 5000 H is, usec. to 9000 H in INTEL 8086. —— —$—_—_~ > © Copyright MADE EASY worwemadeeasypublications org102 | Electrical Engineering © Microprocessors MADE ERSY Publications Q.21 Write on assembly language program to find | | T2. Consider the following 8085 microprocessor number of even and odd number from bytes | @ program of data . Store the count of even numbers in B | 2 MVIC, FF H and odd numbers in C. S MVIB, FFH Q.22 Write an ALP to find smallest number from | = L1:D6RC 40 bytes of data. E Se z ocRB Q.23 Write an assembly language program to | 3 JNZLA generate a delay of 100 msec in INTEL 8085. HIT 7 How many times DCR C instruction executes? Try Yourself 3 [Ans: 65,279] §| 73. Consider the following instructions executed in T1. Consider the following assembly language | @ 8086 program PUSH AX; AX has 0020H in it XRAA PUSH BX; BX has 1234H in it MVIA, 50H POP AX; MVIB, OF H ADD AX, BX; LOOP DCRA POP. CX JNZLOOP Find the content of CX register after execution. INRB [Ans: 20 H] JCLOOP HLT The program is executed in INTEL 8085, find the number of times INR B executed. [an To peonpoider eq Ke y00a sit JO ed ON TUleG MON "SU0I ‘ojssjuned UaTITI ey) TROY WHO} AUR UI peMemory and I/O Interfacing Multiple Choice Questions Q.1_ RAMand ROM, both are (@) Sequentially accessed memory (b) Randomly accessed memory (©) Either (a) or (b) (@) RAM: Randomly accessed, sequentially accessed ROM Q.2. Memory chips of four different sizes as below are available 1, 82Kx4 2. 82K x 16 3. BKx8 4, 16K x4 Allthe memory chips as mentioned in the above list are Read/Write memory. What minimal ‘combination of chips alone can map full address space of 8085 microprocessor? (@) 1and2 (0) 1 only (©) 2only (@) 4only (IES-2005) Amemory of 8 KB is designed using 2048 x 8 RAM chips. The number of chips required are (@)4 (0) 6 (8 (@) 16 Ina512 x 4 ROM chip, the number of address lines are (a) 512 (bo) 4 ©9 @ 1 Which of the following components are used in interfacing memory with microprocessor (@) Tristate buffer (b) Encoder (©) Latch (d) Allof the above Qs Q4 Qs © Copyright MADE EASY Q.6 Ending address of an 8 KB ROM is B72E H find starting address (@) D72DH (b) 972FH (0) 6543H (d) None Q.7 Consider'the 3 x 8 decoder given below If this to be used with 8085 to generate read and write control signals then valid outputs are (@) Day Dy, Dz, Dy Dy, Day Dey (©) Dg, Dy, Dp, Dy, Ds Dg (©) Dy, Dy Dy, Dg (€) Dy, Dy, Dy, Dy Q.8 Memory map of given interfacing logic is 6800 H- 6FFFH 7800 H - 7FFFH 7000H -77FFH None fa) (b) © (@) “Tojssjaed ueaiw 6 ROL Glo ua a pesign 20 peanpaide! 69 KA yo09 aa Hed ONC MON SUOTBDIGNA ASV SAVIN BHU OSIaNS BHBUAGOD vwunemadeessypublcations org) Pub104 Q.9 What memory address range is NOT represented by chip#1 and chip #2 in the figure. A, to Ag in this figure are the address lines and CSmeans Chip select. A 256 bytes Chip #1 cs Db PD cs 256 bytes Chip #2 —_ AowAsh Posts (@) 0100-02FF (bo) 1500-16FF (©) FQ00-FAFF (a) F800-FOFF [GATE-2005] Q.10 Consider the figure given below. so 2ST] tow | i | Micro- CSom | | | jae oS 1 | 1S) | 0S By fewer my ok feo tes cua B= St Port pt — Light 1 3 ta ar ts gue ‘The following instructions are executed, IN 01H XRI C2H RAL OUT 10H ‘www.madeeasypublications.org x = Electrical Engineering © Microprocessors an 70 poonpoidai eq feu yood Sui jo ved ON UIBO MON “SUOTaHIand ASV SVN O1eiTeu BATaNS TUBERGOD @ ‘ojseluned uanipw oui inOUHIM wz0} AUB UI pO " MADE ERSU Pul EASY Publications MADE Which of the following statements is/are true. (i) Airconditioner and coffee pot are ON. (ii) Heater and TV. are ON. (iiiyOnly 2 Lights are ON. (iv) TV. and only Light 4 are ON. (@) (@iand(@) ——(b) (ii) only (©) (ii) and (iv) (6) (ii) and (iv) Q.11 For the 8085 microprocessor, the interfacing circuit to input 8-bit digital data (Di, ~ Diy) from an external device is shown in the figure. The instruction for correct data transfer is woDevce 2%,-01, 00, 00,| bs, os, (@) MVIA,F8H (bd) INFBH (©) OUTFBH (@) LOAF8FBH [2014 : 2 Marks, Set-2] Q.12 The following is not true for RS232 standards (@) Itestablishes the way data is coded (b) It defines signal voltage levels (c) Does not decide data transmission rate (d) Itdefines standard connector configurations Q.13 The interfacing device used to generate accurate time delay in a microcomputer system is (@) INTEL8251 —(b) INTEL 6253 (© INTEL8257 —(@) INTEL 6259 Q.14 What is the maximum memory that can be interfaced with INTEL 80867 (b) 1MB (@) 2MB (@) 64KB (©) 8KB i © CopyrightMADE EASY Numerical Data Type Questions Q.15 The internal memory of INTEL 8085 is. byte Q.16 Maximum number of 256 x 4 memory chips that can be interfaced with INTEL 8085 microprocessor are Q.17 A read write memory chip has a capacity of 32 kb. Ifthe memory chip is having equal number address lines and data lines, then minimum number of data lines are Q.18 A memory system of 128 K bytes needs to be designed with RAM chips of 2 K bytes each and a decoder circuitry constructed with 1x 2. decoder chips with “enable” input. The minimum number of decoder chips required in design are Q.19 In INTEL 8085, suppose the peripheral mapped VO has address length of M and memory mapped I/O has address length of N. Then M+N= Conventional Questions Q.20 Describe various interfacing components. Q.21 Design a memory of 8 KB using 2048 x 8 RAM chips such that the memory map is 2000 H to 3FFFH, Q.22 What are the differences between memory mapped lO and I/O mapped 0? Q.23 Write an ALP to access a data byte from port address 60 H and send it to port address 70H wherea display is connected. Draw the required interfacing logic circuit, Q.24 If the output of the NAND gate is connected to ‘memory chip GS line then find the capacity and memory map of the memory chip. © Copyright ‘Tojse1uod Voniam uy yROUIyM 70) AUB Ul PaRTn 70 poanpordas eq ABW YOO 8) MADE EASY Workbook | 105 Try Yourself T1. Ifa page of memory is assumed to be 256 bytes then in how many pages total memory of 8085 can be treated ? [Ans: 256] T2. A 1Kbyte memory module has to be interfaced with an 8-bit microprocessor that has 16 address lines. The address lines A, to A, of the processor are connected to the corresponding address lines of the memory module. The active low chip select CS of the memory module is connected to the y, output of a 3 to 8 decoder with active low outputs. S,, S,, and S, are the input lines to the decoder, with S, as the MSB. The decoder has one active low EN; and one active high EN, enable lines as shown below. The address range(s) that gets mapped onto this memory module is (are) Aa As Aw & Ss & Ay EN2 910 8 decoder AvP EN, Yo Yr Ye Ya Ya Ys Yo Yr es (@) 3000, 10 33FF,, and £000,, to ESF), (b) 1400,t0 17FF, (©) 5300, to 53FF,,and A300, to ASFF,, (d) 5800,,to SBFF,, and D800,, to DBF, tt (Ans: (d)] ww madeeasypubliationsor9 Publications