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Scheduling, Binding and Pipelining

This document discusses scheduling, binding, and pipelining in digital circuit design. It describes basic scheduling techniques that trade off hardware resources and clock cycles. It also discusses pipelining, including how it is used to increase throughput by overlapping operations across multiple clock cycles. Pipelining can be applied to functional units like multipliers to reduce their latency. Behavioral synthesis tools can automatically schedule and pipeline designs to meet timing constraints.

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54 views7 pages

Scheduling, Binding and Pipelining

This document discusses scheduling, binding, and pipelining in digital circuit design. It describes basic scheduling techniques that trade off hardware resources and clock cycles. It also discusses pipelining, including how it is used to increase throughput by overlapping operations across multiple clock cycles. Pipelining can be applied to functional units like multipliers to reduce their latency. Behavioral synthesis tools can automatically schedule and pipeline designs to meet timing constraints.

Uploaded by

litoduter
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Scheduling, Binding and Pipelining

Dr DC Hendry

April 29, 2006

1 Scheduling

Basic Scheduling

1. Given a set of computations (where each computation is for example a


multiplication or addition) there is a choice between less hardware or fewer
clock cycles.
2. Fewer clock cycles means higher performance (and normally implies lower
energy consumption) but at a higher cost in hardware.
3. Less hardware means lower cost due to reduced silicon area, but less per-
formance and normally higher energy consumption.
4. For a given design you must decide which is more important for the par-
ticular marketplace.

a*x[n] + b*x[n-1]

Here is a design using the minimum of clock cycles (basically two multipliers):
Scheduling, Binding and Pipelining

a b

ax
+ y[n]
*
*
bx

x[n] x[n1]

Register Transfer Language

cycle{
ax = a x[n];
bx = b x[n 1];
y ax + bx;
}

1. Note how the designer has had to take account of the delays needed for
correct operation of the algorithm.
2. Registers x[n] and x[n-1] updated every clock cycle.
3. Area for the design is dominated by the area of the multiplier (but how
does the designer know this?).
4. Nevertheless provides a useful solution, one clock per computation.

a*x[n] + b*x[n-1]

and a design using the minimum hardware (a single multiplier):

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Scheduling, Binding and Pipelining

a b

+ y

*
pr

x input
stream

Register Transfer Language

Assume that at the start of the calculation x contains the value of x[n-1].

cycle1 {
y b x[n 1];
x x[n];
cycle2 ;
}
cycle2 {
y y + a x[n];
cycle1 ;
}

Comparison of the two designs:

1. The first design uses two multipliers, so the hardware cost is greater. A
single clock cycle only is needed for each output value.
2. The second design uses a single multiplier, so reducing hardware cost.
Two clock cycles are required however to generate an output value.
3. Both designs require the designer to break down the overall calculation
into clock cycles, and to track the location of required values.
4. The second design, that with a single multiplier, requires additional mul-
tiplexors (not great area cost), that increase power dissipation.

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Scheduling, Binding and Pipelining

Behavioural Synthesis

1. In a behavioural synthesis system the user enters equations that describe


the required behaviour.
2. Commands to the synthesis system then prescribe the number of clock
cycles required, or limits on the area available.
3. The synthesis tool is then responsible for deciding on the number of func-
tional units (multipliers etc.) needed to implement the design.
4. A typical language is System C, although that language has competitors
and may not eventually become a mainstream commercial product.

2 Pipelining

Pipelining

1. The word pipelining is used in two similar meanings.


2. In the context of a processor (such as the Pentium, or the PIC) pipelining
refers to the overlapping execution of instructions.
3. In the context of functional units, this refers to the use of multiple clock
cycles for an individual operation, with registers between stages.
4. Another related technique is the multi-cycle unit.
5. In all cases the intention is to increase clock frequency, and so data
throughput, despite the delays within combinational logic.

Multi-cycle Units

1. A multi-cycle unit is simply one that requires multiple clock cycles to


produce a result.
2. This arises from long combinational logic delays in the unit.
3. Such units, if on the critical path of a design, would reduce data through-
put.
4. If off of the critical path, there is no loss of data throughput.

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Scheduling, Binding and Pipelining

Pipelined Units

1. In a pipelined unit, a long combinational logic delay is split into multiple


clock cycles.
2. Each sub-block of the combinational logic is placed between registers.
3. The effect is that a number of clock cycles are needed to produce the
required output - this is the latency of the pipeline.
4. The intermediate registers however mean that more than one computation
is in progress at a time.
5. Very good for digital signal processing applications.
6. Problem can be the latency when the output of a unit is needed to process
further inputs.

Pipelined Adder

NonPipelined Pipelined

Pipelined Multipliers

1. Multipliers do require considerable time for signals to propagate.


2. Such units are therefore often pipelined, with the number of pipeline stages
being up to at least five.

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Scheduling, Binding and Pipelining

3. Behavioural synthesis systems can choose the required multiplier as nec-


essary.
4. For RTL synthesis the designer needs to choose the required multiplier
typically from a library.
5. Cadences PKS provides such a multiplier for example in the library
AWARITH called AWARITH PIPEMULT.

Synthesising Arbitrary Pipelined Units

1. For a general block of combinational logic the synthesis tool can be used
to pipeline that block.
2. A technique known as register balancing is applied.
3. Consider the following circuit:

5 nS 2 nS 9 nS

Balanced design ...

1. If we move the unit with 2 nS delay to before the center register, then the
clock period is reduced from 11 nS to 9 nS.
2. and the circuit becomes:

5 nS 2 nS 9 nS

3. Such balancing can be done with two, three or more stages in most syn-
thesis tools.

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Scheduling, Binding and Pipelining

Balancing Logic Delays

1. Consider the circuit:

2. Now request the synthesis tool to move the tail registers into the logic
block to balance the logic. This may mean adding additional flip-flops to
the design.

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