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The document discusses the control word register of the 8253 counter/timer chip. It states that the control word register is selected when A1A0=11. The control word register stores the data written to the 8253 to define the counter's operation. The control word register can only be written to and status information must be obtained using the read-back command.

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36 views1 page

Print

The document discusses the control word register of the 8253 counter/timer chip. It states that the control word register is selected when A1A0=11. The control word register stores the data written to the 8253 to define the counter's operation. The control word register can only be written to and status information must be obtained using the read-back command.

Uploaded by

hari
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Control Word Register: It is selected by Read/Write logic when A1A0=11.

If the CPU does a write operation to the 8253, the data is stored in the control word register
and is used to define the operation of the counter. The control word register can only be
written to, status information is available with the Read—Back command.

1) Discuss below mentioned terms with the help of INTEL 8259 diagram. [3M]
1) SP / EN b) IRR c) Interrupt Control Logic d)CAS2-CAS0 [6M]

̅̅̅̅/𝐄𝐍
𝑺𝑷 ̅̅̅̅: Slave Program / Enable Buffer. This is a dual function pin.
It is used as an input to determine whether the 8259A is to a master (/ = 1) or as a slave (/ =
0).
It is also used as an output to disable the data bus transceivers when data are being transferred
from the 8259A to the CPU.
When in buffered mode, it can be used as an output and when not in the buffered mode it is
used as an input.

Interrupt request register (IRR): IRR stores all the interrupt inputs that are requesting
service. Basically, it keeps all the interrupt requests in it in order to serve them one by
one on the priority basis.

Interrupt request register (IRR): IRR stores all the interrupt inputs that are requesting
service. Basically, it keeps all the interrupt requests in it in order to serve them one by one
on the priority basis

CAS0-CAS2: Cascade lines: The CAS lines form a private 8259A bus to control a multiple
8259A structure i.e. to identify a particular slave device. These pins are outputs of a master
8259A and inputs for a slave 8259A.

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