Lesson 4

FPGA I/O

TOPICS
A. Configuring FPGA I/O
B. FPGA I/O Palettes
C. I/O Types
D. Integer Math
E. Converting Binary Representations
F. Fixed-Point Math

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A. Configuring FPGA I/O
Unnecessary if FPGA Project
Wizard used to configure the
LabVIEW Project
• The FPGA Project Wizard
automatically adds all FPGA I/O
channels for you.

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A. Configuring FPGA I/O
If you did not use the FPGA Project Wizard to create your LabVIEW
Project, then you must add all FPGA I/O channels by hand.
If you would like to add the channels on your own, you must right-click
the FPGA target from the Project Explorer and select New»FPGA I/O
to launch the New FPGA I/O dialog box. Select I/O in the left pane of
the New FPGA I/O dialog box and click Add to add the I/O to the
project. You can name your I/O by clicking the default name and
entering a meaningful name for your application.
Some developers find it simpler to only have the project contain the
channels necessary for their application; whereas other develops prefer
to see all available channels at all times. Neither method creates more
efficient code than the other, so using or not using all FPGA I/O
channels is a matter of preference.

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Using FPGA I/O Nodes

Two ways to use FPGA I/O:

Drag and drop from LabVIEW Project
Add empty I/O node to the block diagram and left-click
to select I/O

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After adding the FPGA I/O node to the Project, drag
and drop the node from the Project Explorer to the
block diagram. to add the appropriate FPGA I/O node to
the block diagram.
You can also add an FPGA I/O node from the
Functions palette. To select your I/O, click the I/O
name portion of the FPGA I/O node and select your I/O.
You can also add additional I/O to your Project from the
FPGA I/O node. Click the node as mentioned previously
and select Add New FPGA I/O to launch the New
FPGA I/O dialog box.

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B. FPGA I/O Palettes

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B. FPGA I/O Palettes
The FPGA I/O palette includes the following functions for
configuring the I/O hardware.
• FPGA I/O Node—Reads or writes data from or to the FPGA
I/O.
• FPGA I/O Constant—Specifies an FPGA I/O item on the block
diagram.
• FPGA I/O Method Node—Invokes an I/O method for a specific
channel or C Series module.
• FPGA I/O Property Node—Reads or sets property attributes
of a specific channel or C Series module.

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C. I/O Types

Digital Lines—writes/reads Boolean value

to/from digital line
Digital Ports—writes/reads unsigned
integer value to/from digital port (grouping
of digital lines)
Analog I/O—writes/reads data to/from an
analog channel
• R Series—returns an integer value
• CompactRIO—returns a fixed-point value (can revert to integer)

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C. I/O Types
There are three basic FPGA I/O types in LabVIEW FPGA hardware: digital
lines, digital ports, and analog I/O. Digital lines are basic digital I/O. Digital
lines are bi-directional on all R Series devices and some CompactRIO
modules. Refer to the documentation for your specific device for more
information about digital enable and digital data functionality.
The Digital Port is a group of digital lines. The ports use a data type that is
dependent on the target. Ports for most I/O will be a group of 8 bits, but others
can be 16, or 32 bits. One bit is used for each line. The read and write
functions take data form all lines in a given port.
The analog input node reads data from the specified line. The analog output
node writes data to a given line. The values from the I/O lines are binary
values. The binary value is based on the resolution of the device. The device
resolution is divided into discrete values based on the range of the device. All
I/O values must be converted from a nominal value to a matching binary value
or vice versa to be correctly interpreted by the FPGA device.

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Creating Counters from Digital I/O
Minimum input pulse width detectable depends on loop period

NI Example Finder: Toolkits and Modules»FPGA»Compact RIO/R Series»

FPGA Fundamentals»Counters

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The FPGA devices do not have built-in counter hardware. All counters
must be programmed into the FPGA itself. The count register can be
32, 16, or 8 bits, depending on the type of integer selected for the
counter indicator. The loop period also determines the minimum
detectable pulse width. The example above has the following
specifications:
− About 10 ticks per iteration
− 250 ns to guarantee a high or low read
− 500 ns period = 2 MHz signals.
It can read a signal at a maximum of 2 MHz. It is important to
benchmark your counter before using it in a final application. Refer to
Toolkits and Modules»FPGA»Compact RIO/R Series» FPGA
Fundamentals»Counters in the NI Example Finder for related
examples.

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FPGA Mathematical Limitations

Cannot perform floating-point operations on the FPGA

• Only the host can perform floating-point analysis

All arithmetic on the FPGA Target done with:

• Integer Math
• Fixed-Point Math

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When using an FPGA you cannot use the normal floating-
point numerical data types. Because the FPGA requires
fixed gates to be created for its logical pathways it cannot
handle data with floating mantissa and exponent data. If
you need to perform floating-point analysis it is typically
simplest to offload those calculations to the host for
processing.
However, not all calculations can or should be offloaded to
the host. Therefore if you wish to perform calculations with
the FPGA VI then all of those calculations will have to be
done with Integer Math or Fixed-Point Math.

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D. Integer Math

• Data returned from I/O is

typically in binary
representation
− Typically pass to host for
conversion
• Most basic numeric
functions can be done on
the FPGA target
• No Divide function available
in Integer Math

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D. Integer Math
Data returned from I/O channels is in binary
representation and must be handled with integer math.
As a result, some functions, such as divide, are not
included on the FPGA palette.

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Scaling Data in LabVIEW FPGA

For variable scaling, you can determine and set the scaling factor and
bit shift from the host application

For example: Scaling Factor: 11500

Downshift: –14 bits
Result Multiplication: 11500 / 214 = 0.7019

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There are some ways to manipulate integer math functions
so that you can create ―floating-point‖ operations. The most
common techniques use the Scale By Power of 2 function
which essentially multiplies or divides by any power of 2.
This figure above shows an example of scaling data in
LabVIEW FPGA. We want to be able to scale the data by
.70. To get this scaling very close we multiply the analog
input by a scaling factor of 11500 then divide it by 16384
(use the Scale by the Power of 2 function to the –14th
power).
Additionally, you can divide numbers using the quotient and
remainder function, however, this can use many slices when
implemented.

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E. Converting Binary Representations

FPGA I/O Node:

• returns a binary representation of the
voltage input
• value is signed integer

Convert value to a physical quantity with

engineering units
Conversion occurs in the Host VI because
FPGA does not support floating-point math

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E. Converting Binary Representations
When you configure the FPGA I/O Node to read an
analog input, the FPGA I/O Node initiates a conversion,
waits for the result, and returns the binary, uncalibrated
representation of the voltage as a signed integer. The
equation that converts the binary representation to a
physical quantity depends on the FPGA target and
transducer.

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E. Converting Binary Representations (cont.)

Conversion is hardware dependent

Hardware-specific factors used in conversion
• Voltage Range
• ADC Resolution
• Offset
• CJC Value
• Autozero Value

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Conversion to Binary Representation is hardware
dependent. Each hardware target has its own specific
voltage range, analog to digital converter precision,
offset and autozero values. By looking at the Help
documentation for the device that you are using you can
find these hardware-specific values and use the values
for conversion of the binary data on the host or by using
fixed-point math on the FPGA target.

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 Demonstration

Show how to convert binary values to nominal values both

on the R Series DAQ Devices and for CompactRIO
GOAL

Devices.

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Open Example finder and Search Descriptions for 7831R.
Open the Examples Analog Input – R Series.lvproj and
Analog Output – R Series.lvproj. Point out how the
conversion factors are applied to the binary data on the host
side of the application.
For CompactRIO Targets show how the use of Binary to
Nominal.vi and Nominal to Binary.vi are used to take into
account the module specific properties. Search Keywords
for CompactRIO and open up the Analog Input –
cRIO.lvproj and Analog Output –cRIO.lvproj. Open the
Host VIs and show how the conversion VIs work. Feel free
to open the VIs to show that all the scaling information is in
those VIs and how the VIs ease the conversion process.

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F. Fixed-Point Math

Greatly simplifies arithmetic on the FPGA

• Simplifies computations
• Size and speed advantages of integer math
• Must configure the appropriate range when using fixed-point math
• Some I/O nodes return scaled and calibrated fixed-point values
Caveats
• FIFOs, memory, FPGA Math & Analysis VIs unsupported
• Wiring a fixed-point number to an integer, might lose significant
fractional bits

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F. Fixed-Point Math
The fixed-point data type provides some of the flexibility of
the floating-point data type while maintaining the size and
speed advantages of integer arithmetic. By default, each
operation on the fixed-point data type generates a fixed-
point result that is large enough to hold all possible output
values specified by the input types.
Note FIFOs, memory, FPGA Math & Analysis VIs,
and some functions do not support the fixed-
point data type.
Caution If you wire a fixed-point number to an integer,
you might lose significant fractional bits.

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Setting the Desired Range

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Use the Data Type options on the Properties dialog box to
increase or decrease the resources a function uses. Right-click a
numeric constant, control, indicator, or function that accepts
fixed-point data and select Properties from the shortcut menu to
display the Properties dialog box. When you set the range on
inputs, the FPGA Module propagates the range throughout the
block diagram. The propagation reduces resources when possible.
The FPGA Module does not propagate through subVIs, so
coercion dots appear on the inputs of subVIs if the desired range
is different than the range being propagated.
Note If you set the Desired Range in places other than
the inputs, the VI might require additional
hardware resources.

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Selecting an Overflow and Quantization Mode

• Use same format for all related

functions
• Mixing fixed-point
configuration types can cause
data loss
• Configure math functions to
handle saturation, truncation,
and rounding as needed.

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Functions that support the fixed-point data type include modes to handle the overflow
and quantization. Use the Properties dialog box for the function to select the overflow
and quantization modes. Right-click a function and select Properties from the
shortcut menu to display the Properties dialog box.
The overflow modes affect the logic generated within the FPGA as follows:
Saturate—Requires additional hardware resources to determine if the input value is
within the desired range of the output type. Saturate is the default overflow mode. If
you specify a desired range other than the default minimum and maximum, the
Saturate mode performs a full comparison between the desired range and input value,
which might require additional clock cycles to complete. If you do not specify a
desired range, the Saturate mode checks all bits above the most significant bit of the
output type to ensure the output did not overflow.
Wrap—Does not require additional hardware resources.
Each of the quantization modes affect the logic generated within the FPGA as
follows:
Truncate—Removes fractional bit and therefore does not require any additional
hardware resources. However, this mode produces the largest mean error for most
data streams. This mode is the default for integer operations.
Round-Half-Up (Asymmetric)—Adds the least significant bit and therefore requires
an adder that is the width of the output type.

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Quiz

1. FPGA I/O Nodes only 2. Which of the following

give access to a module’s numeric representations
digital lines: can be used on the
a. True FPGA?
b. False a. Integer
b. Double
c. Fixed-Point
d. Complex Single
e. Unsigned Integer

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Quiz

3. Conversion of binary data 4. Binary values are always

can only be done on the between 0 and 50000.
host. a. True
a. True b. False
b. False

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Quiz

5. Fixed-Point numbers 6. LabVIEW automatically

require representation- knows the expected data
specific functions. range for all fixed-point
a. True values and chooses the
b. False appropriate configuration.
a. True
b. False

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1.False
FPGA I/O Nodes give access to all physical lines on the device.
2.Unsigned Integer, Fixed-Point, and Integer
Double and Complex Single are floating-point representations.
3.False
Although typically easier to convert on the host, you could convert the
binary value to a fixed-point number on the target by using some binary
math ‗tricks‘.
4.False
Binary values are dependent upon the specs for the hardware in use.
5.False
The same polymorphic mathematical functions can be used for all
numeric data types.
6.False
You must configure the appropriate range before using a fixed-point
number.

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