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Mediotek Health Systems PVT Ltd. Chennai

This document is a resume for M.Murali summarizing his professional experience and qualifications. It states that he has 4 years of experience in RTL design, embedded product development, and FPGA/ASIC design using Verilog and various FPGA tools. Some of his projects include designing a 128-bit AES encryption system and developing medical monitoring systems. He has worked as a design engineer and VLSI engineer for various companies. He also has a Bachelor's degree in Electronics and Communication Engineering and has published papers related to FPGA design.

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Murali
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128 views2 pages

Mediotek Health Systems PVT Ltd. Chennai

This document is a resume for M.Murali summarizing his professional experience and qualifications. It states that he has 4 years of experience in RTL design, embedded product development, and FPGA/ASIC design using Verilog and various FPGA tools. Some of his projects include designing a 128-bit AES encryption system and developing medical monitoring systems. He has worked as a design engineer and VLSI engineer for various companies. He also has a Bachelor's degree in Electronics and Communication Engineering and has published papers related to FPGA design.

Uploaded by

Murali
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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M.

MURALI
E-Mail: [email protected] Mobile: +91-9791105891
3/1476, Mettu Street, Athimanjeripet (P.O), Pallipattu (T.K), Thiruvallur (DT), PIN:631202, Tamil Nadu
OBJECTIVE:
Seeking challenging and rewarding power conscious designer in Hardware accelerated RTL Design
for ASIC/FPGA platform
EXPERIENCE SUMMARY:
 4 years of industrial experience which includes RTL(VLSI) Design and Embedded product
development.
 Good working knowledge on Xilinx and Altera FPGA and development tools.
 Experience in RTL design, Integration, Synthesis and Test-Cases development.
 Experience in Embedded product development, includes Embedded firmware implementation,
Validation and hardware bring up.

2016 to till date Design Engineer, MedIoTek Health Systems Pvt Ltd. Chennai
2014 to 2015 VLSI and Embedded Engineer, Polenza Technologies. Chennai
2011 to 2013 Assistant Professor-1, Oxford Engineering College. Trichy
ACADEMICS:
2007 to 2011 Oxford Engineering college. Anna university, Trichy.
Bachelor of Engineering in Electronics and Communication Engineering.
TECHNICAL SKILLS:
Languages : Verilog HDL, C, Embedded C, MATLAB.
FPGA Tools : Quartus II, Xilinx (ISE, Vivado).
FPGA : Altera’s Cyclone II, Cyclone III & Xilinx’s Spartan 2, Spartan 3.
ASIC Tools : Mentor Graphics (HDL designer, Leonardo Spectrum, Modelsim).
Cadence (RTL compiler, NcSim, SOC Encounter).
Embedded IDE : Code Composer Studio, IAR, Keil uVision, Microchip IDE.
Microcontroller : MSP430FR5969, CC2541, CC2650, nRF52832, PIC 16F877A.
Protocols worked : UART, SPI, I2C, ADC.
Company: MedIoTek Health Systems Pvt Ltd 2016 to till date
128-bit Advanced Encryption Standard (AES)
 This project involves design and implementation of Advanced Encryption Standard has been
developed using Rijndael algorithm. As a part of team, RTL development and simulation are
done.
 Language used for RTL and simulation – Verilog.
VinCense Wireless Health Monitoring System (WHMS)
 A wearable to collect four vital parameters (Heart rate, SPO2, Skin temperature and respiration
rate). Contributed in developing algorithms to calculate vital parameters, updating the interrupt
strategies and over all functionality of the embedded firmware. Modified and improved BLE 4.0
stack profiles.
Vin Data Aggregator (VinDA)
 VinDA – Vin Data Aggregator is designed to ease the integration of non-internet enabled device
to the cloud platform. It can collect and upload the data from serial port enabled end device to
cloud platform. VinDA has an onboard GSM/GPRS (Wi-Fi as optional) module for internet
connection.
Company: Polenza Technologies 2014 to 2015
An area efficient multiplexer based CORDIC
 Multiplexer based ASIC implementation of unrolled CORDIC processor designed. The efficacy
of this approach is studied for the implementation on FPGA. The results show great reduction of
area and power.
Institution: Oxford Engineering College 2011 to 2013
Low Power High Speed Wave Pipelining circuits
 Low power multipliers and CORDIC circuits are designed using wave pipelining technique. By
using this technique, I achieved high speed circuits without increase of area in layout.
PUBLICATIONS:
 Published paper on “Comparison on various adders and multipliers in different FPGA’s
architectures and ASIC and their performance study” in International Journal of Applied
Engineering Research, ISSN 0973-4562 Vol. 10 No.20 (2015).
ACHIEVEMENTS:
 First prize for recitation competition from Andhra Samskrithi Manjari, Athimanjeripet.
 Second prize for “Rain water wiper” from Oxford engineering college, Trichy.
PERSONAL INFORMATION:
Date of Birth : 30 - 06 - 1989.
Languages know : English, Telugu, and Tamil.
Passport Number : M0168778
Valid Until : 13th July 2024
Reference : Available on request.
Preferred Location : Anywhere in India, Overseas.

Place:
Date: (MURALI.M)

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