EE421/621 Digital Circuits

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 Lecture #4 Overview

- Boolean Logic and Gate Network

- Optimized Implementation of Logic Function
- Number Representation & Arithmetic

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 SYSTEM

MODULE
+
Boolean Logic
GATE

CIRCUIT
and Gate Network
DEVICE
G
S D
n+ n+

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 Boolean Algebra

Axioms of Boolean Algebra Single-Variable Theorems

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 Boolean Algebra (cont)
Two- and Three- Variable Properties

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 Boolean Algebra (cont)

Proof of DeMorgan’s theorem in 15a

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 Do Boolean Algebra to Learn
Boolean Algebra (cont)
Prove:

16a. LHS= X+XY=X(1+Y)+XY=X+XY+XY=X+ (X+X)Y=X+Y

17a. LHS= XY+YZ+XZ= XY+YZ(X+X)+XZ=…

17b. LHS= (XY+XZ+Y+YZ)(X+Z)=…

17b. RHS= XZ+YX+YZ

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 Do Boolean Algebra to Learn
Boolean Algebra
Prove:

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 Boolean Algebra (cont)

x y x y

(a) Constant 1 (b) Constant 0 (e) x  y (f) x + y

x y
x x x x x y
z

(c) Variable x (d) x (g) x  y (h) x y+z

The Venn diagram representation

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 x y x y

z z

(a) x (d) x  y
Verification of the
distributive property
x y x y x (y + z) = x y + x z

z z

(b) y + z (e) x  z

x y x y

z z

(c) x  ( y + z) (f) x  y + x  z
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 x y x y

z z

x y xy

x y x y

z z

xz xz

x y x y x y

z z z

yz x  y + x z+ y z x y+ x z

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EE421/621
Basic Gates for Boolean Algebra
x1
(a) AND gates x2
x1
x1  x2 x1  x2    xn
x2

xn

(b) OR gates
x1
x2
x1
x1 + x2 x1 + x2 +  + xn
x2

xn

(c) NOT gate

x x

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Basic Gates for Boolean Algebra (cont)
   1 1 0 0
x1 0 0 1 1
A
1 1  0  1 f
0 0 01 B
0  1 0  1
x2
(a) Network that implements f = x1 + x1  x2

x1 1
0
x x f (x , x )
1 2 1 2 A B x2 1
1 0
0
0 0 1
1
0 1 1 1 0 A
0
1 0 0 0 0 1
1 1 1 B
0 1 0
1
(b) Truth table f
0 Time
(c) Timing diagram

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Basic Gates for Boolean Algebra (cont)

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Basic Gates for Boolean Algebra (cont)
Minterm
 For a function of n variables, a product term in which each of the n
variables appears once is called a minterm.
 The variables may appear in a minterm either in uncomplemented or
complemented form.
 For a given row of the truth table, the minterm is formed by including xi if
xi = 1 and by including xi if xi = 0.

SOP (Sum-of-Products)
 A logic expression consisting of product ( AND) terms that are summed
(ORed) is said to be of the sum- of-products ( SOP) form.
 If each product term is a minterm, then the expression is called a canonical
sum- of- products for the function f .

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 16
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Basic Gates for Boolean Algebra (cont)
Maxterm
 For a function of n variables, a sum term in which each of the n variables
appears once is called a maxterm.
 The variables may appear in a maxterm either in uncomplemented or
complemented form.
 For a given row of the truth table, the maxterm is formed by including xi if
xi = 0 and by including xi if xi = 1.

POS (Product-of-Sum)
 A logic expression consisting of sum ( OR) terms that are the factors of a
logical product ( AND) is said to be of the product- of- sums ( POS) form.
 If each sum term is a maxterm, then the expression is called a canonical
product- of- sums for the given function.
 Any function f can be synthesized by finding its canonical product- of-
sums. This involves taking the maxterm for each row in the truth table for
which f = 0 and forming a product of these maxterms.
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Gate implementation of the function

x1
x2
x3
(a) Sum-of-products realization

x3
x2
x1

(b) Product-of-sums realization 18

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Basic Gates for Boolean Algebra (cont)
x1 X1X2
x2

X1X2
f

X1X2
f=X1X2+X1X2+X1X2
(a) Canonical sum-of-products
Minimized

x1
f=X1+X1X2 f
x2

(b) Minimal-cost realization

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Basic Gates for Boolean Algebra (cont)
x1
x2
x1
x1  x2 x1  x2    xn
x2

xn

(a) NAND gates

x1
x2
x1
x1 + x2 x1 + x2 +  + xn
x2

xn

(b) NOR gates

Easiest Implementation in CMOS 20

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Basic Gates for Boolean Algebra (cont)
x x
1 1
x x
2 2

x x
3 3
x x
4 4
x x
5 5

x
x 1 x
1 1
x x x
2 x 2 1
2 x
2

x x = x +x x
3
12 1 2
x
4
x
5

Using NAND gates to implement a sum-of-products. 21

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Basic Gates for Boolean Algebra (cont)
x1 x1
x2 x2

x3 x3
x4 x4
x5 x5

x
x 1 x
1 1
x x x1
2 x 2
2
x2

x +x = x x x3
1 2 1 2
x4
x5

Using NOR gates to implement a product-of sums. 22

EE421/621
Basic Gates for Boolean Algebra (cont)
x2
Example 2.3 in Book
f
x1

x3

(a) SOP implementation

x1

f
x2

x3

(b) NAND implementation

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 SYSTEM

MODULE
+
Optimized
GATE

CIRCUIT
Implementation of
DEVICE
Logic Function
G
S D
n+ n+

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Why to Optimize Implementation of
Logic Function
 Optimization means low cost
 Fewer gates or transistors
 Smaller die area
 Less power consumption
 Lower costs

 Done by CAD (numerous researches on this topic)

 Still important for beginners to learn the concept
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Karnaugh Map -Two Variables
x1 x2 x1
x2
0 0 m0 0 1
0 1 m1 0 m0 m2
1 0 m2
1 m1 m3
1 1 m3

(a) Truth table (b) Karnaugh map

Location of two-variable minterms.

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Karnaugh Map -Two Variables
x1
x2
1

0 1

0 1 0
f = x2 + x1
1 1 1

Example

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Karnaugh Map -Three Variables
x1 x2 x3
x1 x2
0 0 0 m0 x3
00 01 11 10
0 0 1 m1
0 m0 m2 m6 m4
0 1 0 m2
0 1 1 m3 1 m1 m3 m7 m5
1 0 0 m4
1 0 1 m5 (b) Karnaugh map
1 1 0 m6
1 1 1 m7

(a) Truth table

Location of three-variable minterms.

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Karnaugh Map -Three Variables
x1x2
x3
00 01 11 10
0 0 0 1 1
f = x1x3 + x2x3
1 1 0 0 1

(a) The function of Figure 2.18

x x
1 2
x3
00 01 11 10
0 1 1 1 1
f = x3 + x x2
1 0 0 0 1 1

(b) The function of Figure 4.1

Examples of three-variable Karnaugh maps 29
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Karnaugh Map –Four Variables
x1
x1 x2
x3 x4
00 01 11 10

00 m0 m4 m 12 m8

01 m1 m5 m 13 m9
x4
11 m3 m7 m 15 m 11
x3
10 m2 m6 m 14 m 10

x2

A four-variable Karnaugh map

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 x1 x2 x1x2
x3x4 x3 x4
00 01 11 10 00 01 11 10
00 0 0 0 0 00 0 0 0 0

01 0 0 1 1 01 0 0 1 1

11 1 0 0 1 11 1 1 1 1

10 1 0 0 1 10 1 1 1 1

f 1 = x2 x3 + x1 x3 x4 f 2 = x3 + x1x4

x1 x2 x1x2
x3x4 x3 x4
00 01 11 10 00 01 11 10
00 1 0 0 1 00 1 1 1 0

01 0 0 0 0 01 1 1 1 0

11 1 1 1 0 11 0 0 1 1

10 1 1 0 1 10 0 0 1 1

x1x2
f 3 = x2 x4 + x1x3 + x2x3x4 f 4 = x1 x3 + x1x3 + or
x2x3
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 Strategy for Minimization (cont)
Incompletely Specified Functions
x1x2
x3x4
00 01 11 10

00 0 1 d 0
x2x3
01 0 1 d 0

11 0 0 d 0

10 1 1 d 1 x3x4

SOP implementation

Two implementations of the function f ( x1,…, x4) =

 m(2, 4, 5, 6, 10) + D(12, 13, 14, 15).
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 SYSTEM

MODULE
+
Number
GATE

CIRCUIT
Representation &
DEVICE
Arithmetic
G
S D
n+ n+

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Number Representations &
Arithmetic in Digital Systems
Unsigned Integers

radix

Decimal (117)10=1×102+1×101+7×100

Binary (117)10=(1110101)2=1×26+1×25+1×24+0×23+1×22+0×21+1×20

Octal (117)10=(165)8=1×82+6×81+5×80

Hexadecimal (117)10=(75)16=7×161+5×160

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Number Representations &
Arithmetic in Digital Systems
Unsigned Integers
Binary (117)10=(1110101)2=1×26+1×25+1×24+0×23+1×22+0×21+1×20

Octal (117)10=(165)8=1×82+6×81+5×80

Hexadecimal (117)10=(75)16=7×161+5×160

1 1 1 0 1 01

1 1 1 0 101
1 6 5

1 1 1 0 1 01
7 5

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Number Representations &
Arithmetic in Digital Systems

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EE421/621 Numbers in different systems
 Carry Sum
x 0 0 1 1 x y c s

+y +0 +1 +0 +1
Number Representations & c s 0 0 0 1 0 1 1 0
0
0
0
1
0
0
0
1

Arithmetic in Digital Systems Carry Sum

1
1
0
1
0
1
1
0
(a) The four possible cases
Addition of unsigned Integers (b) Truth table
x 0 0 1 1 Carry Sum
x 0 0 1 1
++ yy +0
+0 +1
+ 1 + 0+ 0 + 1 + 1 x y c s

x
cc ss 000 0 0 01 1 0 10 1 1 0 1 0 s
0 0 0 y 0
x
0 1 0 1
Carry
Carry Sum
Sum y
1 0 0 1
c
1 1 1 0
(a) The
(a) The four
fourpossible
possiblecases
cases

Carry Sum
Half-adder
(b) Truth table (c) Circuit (d) G
Carry Sum
x y c s

x y c s

x
0 0 0 0 s
0 0 0 y 0
0 1 0 1 x s
01 1
0 0
0 1
1 HA
y c
11 10 10 0 1 c
1 1 1 0
(b) Truth table (c) Circuit (d) Graphical symbol
(b) Truth table
x 37
EE421/621 s
x y x
Number Representations &
Arithmetic in Digital Systems
Addition of unsigned Integers

X = x4 x3 x2 x1 x0 01111 ( 15 ) 10

+ Y = y4 y3 y2 y1 y0 01010 ( 10 ) 10

1110 Generated carries

S = s4 s3s2 s1s0 11001 ( 25 ) 10

(11001)2=1×24+1×23+0×22+0×21+1×20=(16+8+1)10=(25)10

An example of addition.
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Number Representations &
Arithmetic in Digital Systems
Addition of unsigned Integers x i yi
ci 00 01 11 10
ci x i yi ci + 1 si 0 1 1
0 0 0 0 0 1 1 1
0 0 1 0 1
0 1 0 0 1 si = xi  yi  ci
0 1 1 1 0
1 0 0 0 1 x i yi
1 0 1 1 0 ci
1 1 0 1 0 00 01 11 10
1 1 1 1 1 0 1

(a) Truth table 1 1 1 1

ci + 1 = x i y i + x i c i + y i c i
xi
(b) Karnaugh maps
yi si
ci

Full-adder
ci +1

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(c) Circuit
Number Representations &
Arithmetic in Digital Systems
A decomposed implementation of the full-adder circuit

ci s si
s HA c
xi
HA c ci + 1
yi

(a) Block diagram

ci
si
xi
yi

ci + 1

(b) Detailed diagram

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Number Representations &
Arithmetic in Digital Systems
Addition of unsigned Integers
Ripple-carry adder
xn – 1 yn– 1 x1 y1 x0 y0

c1
cn FA cn ” 1 c2 FA FA c0

sn– 1 s1 s0
MSB position LSB position

x8 x1 x0 y8 y7 y0
c8
s8 s0

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Number Representations &
Arithmetic in Digital Systems
Examples A : a7 a0

P=3A
x7 x0 y7 y0
c7
s7 s0

x8 x7 x0 y8 y7 y0
c8
s8 s0

P = 3 A : P9 P8 P0

(a) Naive approach

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Number Representations &
Arithmetic in Digital Systems
Examples
A : a7 a0

P=3A
0 0

x8 x1 x0 y8 y7 y0
c8
s8 s0

? P=4A P = 3 A : P9 P8 P0

(b) Efficient design

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Number Representations &
Arithmetic in Digital Systems
bn – 1 b1 b0
Signed Integers
sign- and- magnitude

+5 0101
Magnitude

-5 1101 MSB (a) Unsigned number

bn – 1 bn – 2 b1 b0

+5 0101

-5 1101 Magnitude
Sign
0 denotes +
0 0010 1 denotes – MSB

0 0000 (b) Signed number

General Formats for representation of integers 44

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Number Representations &
Arithmetic in Digital Systems
Signed Integers (positive number) 1’s complement =itself
•s i g n - a n d - m a g n i t u d e
•1’s complement
•2’s complement
In the 1’s complement scheme, an negative number, K,
is obtained by subtracting its equivalent positive
number, P, from 2n - 1; that is, K = ( 2n - 1) - P.
(n is the bit number to represent K or P)
n=4 n=8
(– 2) (– 2)

2n-1=15 28-1=255
15-2=13 1101 255-2=253 11111101

Consider it as
unsigned integer 45
EE421/621
Number Representations &
Arithmetic in Digital Systems
Signed Integers
•s i g n - a n d - m a g n i t u d e
•1’s complement
•2’s complement
An efficient way to get 1’s complement of a negative number:
(– 2) (– 2)

2n-1=15 28-1=255
15-2=13 1101 255-2=253 11111101
(2) 0010 (2) 00000010

Complementing 1101 11111101

(1101)1’s complement=1×23+1×22+0×21+1×20=(8+4+1)10=(13)10
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EE421/621 {(24) -1}-(13)10 =15-13=2
Number Representations &
Arithmetic in Digital Systems
Signed Integers
•s i g n - a n d - m a g n i t u d e
•1’s complement
•2’s complement
(+ 5) 0101 (– 5 ) 1010
+ (+ 2) +0010 + (+2) +0010
1’scomplement 1’scomplement
(+ 7) 0111 (- 3 ) 1100
x8 x1 x0 y8 y7 y0
c8
s8 s0

(+ 5) 0101 (–5 ) 1010

+ (– 2) +1101 + (– 2 ) +1101
(+ 3) 10010 (–7 ) 1 0111
x8 x1 x0 y8 y7 y0 1 1
c8
s8 s0 0011 1000

1’scomplement
Examples of 1’s complement addition
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Number Representations &
Arithmetic in Digital Systems
Signed Integers (positive number) 2’s complement =itself
•s i g n - a n d - m a g n i t u d e
•1’s complement
•2’s complement
In the 2’s complement scheme, a negative number, K, is
obtained by subtracting its equivalent positive number, P,
from 2n; namely, K = 2n - P.
n=4 n=8
(– 2) (– 2)

24=16 28=256
16-2=14 1110 256-2=254 11111110

Consider it as
unsigned integer 48
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Number Representations &
Arithmetic in Digital Systems
Signed Integers
•s i g n - a n d - m a g n i t u d e
•1’s complement
•2’s complement
An efficient way to get 2’s complement of a negative number:

(– 2) (– 2)

24=16 28=256
16-2=14 1110 256-2=254 11111110
(2) 0010 (2) 00000010

Complementing 1101 11111101

Adding 1 1 2+1×21+0×20=(8+4+2)10=(14)10
(1110)2’s complement=1×23+1×2 1
111
(24) -(14)10 =16-14=2 0 11111110 49
EE421/621
Number Representations &
Arithmetic in Digital Systems
Signed Integers
•s i g n - a n d - m a g n i t u d e
•1’s complement
•2’s complement
An efficient way to get 2’s complement of a negative number:

(-12) (-12)

24=16 28=256
16-12=4 0100 256-12=244 1 1 1 1 0 1 0 0
(12) 1100 (12) 00001100

Complementing 0011 11110011

Adding 1 1 What’s wrong??
1
0100 11110100 50
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Number Representations &
Arithmetic in Digital Systems
Signed Integers
•s i g n - a n d - m a g n i t u d e In the 2’s complement scheme, a
•1’s complement negative number, K, is obtained by
•2’s complement subtracting its equivalent positive
number, P, from 2n; namely, K = 2n - P.

2n-1-1

(0X…X)2’s complement=0×2n-1+X×2n-2+…+X×21+X×20  (011…1)2’s complement

(1X…X)2’s complement=1×2n-1+X×2n-2+…+X×21+X×20

K=-{2n-{1×2n-1+X×2n-2+…+X×21+X×20 }}=-1×2n-1+X×2n-2+…+X×21+X×20
 -1×2n-1+1×2n-2+…+1×21+1×20
-2n-1 51

EE421/621
Number Representations &
Arithmetic in Digital Systems
Signed Integers
•s i g n - a n d - m a g n i t u d e
•1’s complement
•2’s complement
An efficient way to get 2’s complement of a negative number:

(-12) (-12)
25=32
24=16 10100 28=256
32-12=20
16-12=4 0100 256-12=244 1 1 1 1 0 1 0 0
(12) 0 1 1 0 01 1 0 0 (12) 00001100
10011
Complementing 0011 11110011
Adding 1 1 1
1 0 1 0 00 1 0 0 11110100 52
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Number Representations &
Arithmetic in Digital Systems
Signed Integers
•s i g n - a n d - m a g n i t u d e In the 2’s complement scheme, a
•1’s complement negative number, K, is obtained by
•2’s complement subtracting its equivalent positive
number, P, from 2n; namely, K = 2n - P.
(1X…X)2’s complement=1×2n-1+X×2n-2+…+X×21+X×20

K=-{2n-{1×2n-1+X×2n-2+…+X×21+X×20 }}=-1×2n-1+X×2n-2+…+X×21+X×20

-(0X…X)=-{0×2n-1+X×2n-2+…+X×21+X×20 }
=-1×2n-1 +1×2n-1-{0×2n-1+X×2n-2+…+X×21+X×20 }
=-1×2n-1 + {1×2n-2+…+1×21+1×20 }+1 -{0×2n-1+X×2n-2+
{1×2n-2+…+1×21+1×20 }=2n-1-1
…+X×21+X×20 }
={-1×2n-1+(1-X)×2n-2+…+(1-X)×21+(1-X)×20 }+1
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 Number Representations &
Arithmetic in Digital Systems
Signed Integers
•s i g n - a n d - m a g n i t u d e In the 2’s complement scheme, a
•1’s complement negative number, K, is obtained by
•2’s complement subtracting its equivalent positive
number, P, from 2n; namely, K = 2n - P.
(1X…X)2’s complement=1×2n-1+X×2n-2+…+X×21+X×20

K=-{2n-{1×2n-1+X×2n-2+…+X×21+X×20 }}=-1×2n-1+X×2n-2+…+X×21+X×20

-(1X…X)2’s complement=-{1×2n-1+X×2n-2+…+X×21+X×20 }
-K={2n-{1×2n-1+X×2n-2+…+X×21+X×20 }}=-{-1×2n-1+X×2n-2+…+X×21+X×20 }
=1×2n-1-X×2n-2-…-X×21-X×20 }
= {1×2n-2+…+1×21+1×20 }+1-X×2n-2-…-X×21-X×20 }
{1×2n-2+…+1×21+1×20 }=2n-1-1 = {0×2n-1 + (1-X)×2n-2+…(1-X)×21+(1-X)×20 } }+1

(0X…X)2’s complement={0×2n-1+X×2n-2+…+X×21+X×20 } 54
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Number Representations &
Arithmetic in Digital Systems
Signed Integers
•s i g n - a n d - m a g n i t u d e
•1’s complement
•2’s complement ( + 5) 0101 (–5) 1011
+ ( + 2) + 0010 + ( + 2) + 0010
( + 7) 0111 (–3) 1101
2’scomplement 2’scomplement

x8 x1 x0 y8 y7 y0 ( + 5) 0101 (–5) 1011

c8
s8 s0 + ( –2) + 1110 + (–2) + 1110
( + 3) 10011 (–7) 11 0 0 1
2’scomplement

ignore ignore
Examples of 2’s complement addition
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Number Representations &
Arithmetic in Digital Systems
Signed Integers ( + 21) 010101
+ ( –2) + 1110
•s i g n - a n d - m a g n i t u d e
•1’s complement ( + 19 )
•2’s complement

( + 21) 010101
+ ( –2) + 001110 ?
Sign: Auto extension ( + 19 ) 100011
in addition
( + 21) 010101
(010011)2’s complement= + ( –2) + 111110 ?
0×25+1×24+0×23+0×22+1×21+1×20 ( + 19 ) 1010011
=19
ignore
Examples of 2’s complement addition 56
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Number Representations &
Arithmetic in Digital Systems
Signed Integers ( + 21) 010101
+ ( +2) + 0010
•s i g n - a n d - m a g n i t u d e
•1’s complement ( + 23 )
•2’s complement

( + 21) 010101
+ ( +2) + 000010 ?
Sign: Auto extension ( + 23 ) 010111
in addition
( + 21) 010101
(010111)2’s complement= + ( +2) + 110010 ?
0×25+1×24+0×23+1×22+1×21+1×20 ( + 23 ) 1000111
=23
ignore
Examples of 2’s complement addition 57
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Number Representations &
Arithmetic in Digital Systems
( + 5) 0101 0101
Signed Integers – ( + 2) – 0010 + 1110
•s i g n - a n d - m a g n i t u d e ( + 3) 10011
•1’s complement
•2’s complement
ignore
( –5 ) 1011 1011
– + 2)
( – 0010 + 1110
( –7 ) 11001

ignore
( + 5) 0101 0101
– ( –2) – 1110 + 0010
( + 7) 0111

( –5 ) 1011 1011
– ( –2) – 1110 + 0010
( –3 ) 1101

EE421/621 Examples of 2’s complement subtraction 58

Number Representations &
Arithmetic in Digital Systems
Signed Integers yn– 1 y1 y0
•2’s complement
Add Sub
control

xn– 1 x1 x0

cn n-bit adder c0

sn– 1 s1 s0

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Number Representations &
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Signed Integers
•2’s complement

Overflow
•If n bits are used to represent signed numbers, then the result must be in
the range – 2n- 1 to 2n- 1 - 1.

•If the result does not fit in this range, then we say that arithmetic overflow
has occurred.

•To ensure the correct operation of an arithmetic circuit, it is important to be

able to detect the occurrence of overflow.

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Number Representations &
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Signed Integers In the following additions, which operation is out of range?
•2’s complement (n=4)

(+ 7) 0111 (–7) 1001

+ (+ 2) +0 0 1 0 + (+ 2) +0 0 1 0
(+ 9) 1001 (–5) 1011
c4 = 0 c4 = 0
c3 = 1 c3 = 0

(+ 7) 0111 (–7) 1001

+ (– 2) +1 1 1 0 + (–2) +1 1 1 0
(+ 5) 10 1 0 1 (–9) 10 1 1 1
c4 = 1 c4 = 1
c3 = 1 c3 = 0

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Examples of determination of overflow 61
Number Representations &
Arithmetic in Digital Systems
Signed Integers
•2’s complement

Multiplicand M (+14) 01110

Multiplier Q (+11) x 01011
Partial product 0 0 00 1 1 1 0
+ 00 1 1 1 0
Partial product 1 00 1 0 1 0 1
+ 00 0 0 0 0
Partial product 2 00 0 1 0 1 0
+ 00 1 1 1 0
Partial product 3 00 1 0 0 1 1
+ 00 0 0 0 0
Product P (+154) 0010011010

(a) Positive multiplicand

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Multiplication of signed numbers 62
Number Representations &
Arithmetic in Digital Systems
Signed Integers
•2’s complement
Multiplicand M (– 14) 10010
Multiplier Q (+11) 01011
Partial product 0 1 11 0 0 1 0
+ 11 0 0 1 0
Partial product 1 11 0 1 0 1 1
+ 00 0 0 0 0
Partial product 2 11 1 0 1 0 1
+ 11 0 0 1 0
Partial product 3 11 0 1 1 0 0
+ 00 0 0 0 0
Product P (–154) 1101100110

(b) Negative multiplicand

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Multiplication of signed numbers 63
Number Representations &
Arithmetic in Digital Systems
Fixed-Point Format
 A fixed- point number consists of integer and fraction parts.
 Logic circuits that deal with fixed- point numbers are
essentially the same as those used for integers.

bn – 1 bn – 2 b1 b0 b –1 b–2 b-k+1 b-k

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Number Representations &
Arithmetic in Digital Systems

Conversion of fractions
from decimal to binary

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Number Representations &
Arithmetic in Digital Systems
BCD Code - Addition
X 0111 7
+ Y +0 1 0 1 +5
Z 1100 12
+0 1 1 0
carry 10010

S=2

X 1000 8
+ Y +1 0 0 1 +9
Z 10001 17
+0 1 1 0
Binary-coded decimal digits carry 10111
S=7 67
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Number Representations &
Arithmetic in Digital Systems
X Y
BCD Code - Addition
c in
4-bit adder
carry-out

Detect if
sum 9>

6 0

Block diagram for a

one-digit BCD adder MUX
Adjust

c out 4-bit adder 0

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Number Representations &
Arithmetic in Digital Systems
BCD Code - Subtraction
X 0111 7
- Y -0101 - 5
Z 0010 2

S=2

X 01000 8
- Y + 1 0 1 1 1 - 9
Z 11111 -1

- 00001

Binary-coded decimal digits S = -1

Other approaches??
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Number Representations &
Arithmetic in Digital Systems
ASCII Code

The ASCII code

 ASCII uses only seven bits
 ASCII includes definitions for
128 characters
 ASCII codes represent text in
computers, communications
equipment, and other devices
that work with text.

 The 8th bit is parity, which

ensures the total number in 8bit
data is even or odd
 The parity is used for error-
checking

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 Summary
 Boolean Logic and Gate Network
 Optimized Implementation of Logic Function
 Number Representation & Arithmetic

EE421/621