Scribd
Upload
153 views12 pages

HDL Verilog Programs Vtu 5th Sem

The document contains Verilog code examples for various digital logic circuits including logic gates, decoders, encoders, multiplexers, demultiplexers, and comparators. The code examples demonstrate behavioral, data flow, and gate level modeling in Verilog. Behavioral modeling uses if-else statements or case statements to model the logic functions. Data flow modeling assigns outputs based on inputs. Gate level modeling instantiates basic gates like AND, OR, NOT to model the logic functions.

Uploaded by

Nikhil Kulkarni
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
153 views12 pages

HDL Verilog Programs Vtu 5th Sem

The document contains Verilog code examples for various digital logic circuits including logic gates, decoders, encoders, multiplexers, demultiplexers, and comparators. The code examples demonstrate behavioral, data flow, and gate level modeling in Verilog. Behavioral modeling uses if-else statements or case statements to model the logic functions. Data flow modeling assigns outputs based on inputs. Gate level modeling instantiates basic gates like AND, OR, NOT to model the logic functions.

Uploaded by

Nikhil Kulkarni
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 12

1.

VERILOG CODE FOR ALL LOGIC GATES

BEHAVIORAL MODELING DATA FLOW MODELING GATE LEVEL MODELING

module allgatesverilog(a,b,y); module allgatesverilog(a,b,y); module allgatesverilog(a,b,y);


input a; input a; input a;
input b; input b; input b;
output reg[6:0] y; output [6:0] y; output [6:0] y;
always@(a,b) assign y[0]=~a; not n0(y[0],a);
begin assign y[1]=a&b; and n1(y[1],a,b);
y[0]=~a; assign y[2]=a|b; or n2(y[2],a,b);
y[1]=a&b; assign y[3]=~(a&b); nand n3(y[3],a,b);
y[2]=a|b; assign y[4]=~(a|b); nor n4(y[4],a,b);
y[3]=~(a&b); assign y[5]=a^b; xor n5(y[5],a,b);
y[4]=~(a|b); assign y[6]=~(a^b); xnor n6(y[6],a,b);
y[5]=a^b; endmodule endmodule
y[6]=~(a^b);
end
endmodule

OUTPUT:
2a.VERILOG CODE FOR 2 TO 4 DECODER

BEHAVIORAL MODELING DATA FLOW MODELING GATE LEVEL MODELING

module decoder24(x,y,en); module decoder24(x,y,en); module decoder24(x,y,en);


input en; input en; input en;
input [1:0] x; input [1:0] x;
input [1:0] x;
output [3:0] y; output [3:0] y;
output [3:0] y; assign y[0]=~x[1]&~x[0]&en; wire x1b,x0b;
reg[3:0]y; assign y[1]=~x[1]&x[0]&en; not n1(x1b,x[1]);
always@(x,en) assign y[2]=x[1]&~x[0]&en; not n2(x0b,x[0]);
begin assign y[3]=x[1]&x[0]&en; and a1(y[0],x1b,x0b,en);
if(en==1) endmodule and a2(y[1],x1b,x[0],en);
and a3(y[2],x[1],x0b,en);
case(x)
and a4(y[3],x[1],x[0],en)
2'b00:y=4'b0001; endmodule
2'b01:y=4'b0010;
2'b10:y=4'b0100;
2'b11:y=4'b1000;
endcase
else
y=4'b0000;
end
endmodule

OUTPUT
2b.VERILOG CODE FOR8 TO 3 ENCODER WITH PRIORITY

BEHAVIORAL MODELING USING BEHAVIORAL MODELING USING case


nested if-else statement
module encoder83wp(din,dout,en); module encoder83wp(en,din,dout);
input en; input en;
input [7:0] din; input [7:0] din;
output [2:0] dout; output [2:0] dout;
reg[2:0]dout; reg [2:0] dout;
always @(din,en) always @(en,din)
begin begin
if(en==1) if(en==1)
begin casex(din)
if(din[7]==1) 8’b1xxxxxxx:dout=3’b111;
dout=3'b111; 8’b01xxxxxx:dout=3’b110;
else if(din[6]==1) 8’b001xxxxx:dout=3’b101;
dout=3'b110; 8’b0001xxxx:dout=3’b100;
else if(din[5]==1) 8’b00001xxx:dout=3’b011;
dout=3'b101; 8’b000001xx:dout=3’b010;
else if(din[4]==1) 8’b0000001x:dout=3’b001;
dout=3'b100; 8’b00000001:dout=3’b000;
else if(din[3]==1) default:dout=3’bxxx;
dout=3'b011; endcase
else if(din[2]==1) else
dout=3'b010; dout=3’bzzz;
else if(din[1]==1) end
dout=3'b001; endmodule
else if(din[0]==1)
dout=3’b000;
else
dout=3’bxxx;
end
else
dout=3'bzzz;
end
endmodule

OUTPUT
2b.VERILOG CODE FOR8 TO 3 ENCODER WITHOUT PRIORITY
BEHAVIORAL MODELING

module encoder83withoutp(en,din,dout);
input en;
input [7:0] din;
output [2:0] dout;
reg [2:0] dout;
always @(en,din)
begin
if(en==1)
case(din)
8’b10000000:dout=3’b111;
8’b01000000:dout=3’b110;
8’b00100000:dout=3’b101;
8’b00010000:dout=3’b100;
8’b00001000:dout=3’b011;
8’b00000100:dout=3’b010;
8’b00000010:dout=3’b001;
8’b00000001:dout=3’b000;
default:dout=3’bxxx;
endcase
else
dout=3’bzzz;
end
endmodule

OUTPUT
2c.VERILOG CODE FOR8 TO 1 MULTIPLEXER
BEHAVIORAL MODELING using nested BEHAVIORAL MODELING using case
if-else statement
module mux8_1(a,sel,en,y); module mux8_1(en,a,sel,y);
input en; input en;
input[7:0]a; input[7:0]a;
input[2:0]sel; output reg y;
output reg y; input[2:0]sel;
always@(a,sel,en) always@(a,sel,en)
begin begin
if(en==1) if(en==1)
begin case(sel)
if(sel==0) 3'd0:y=a[0];
y=a[0]; 3'd1:y=a[1];
else if(sel==1) y=a[1]; 3'd2:y=a[2];
else if(sel==2) y=a[2]; 3'd3:y=a[3];
else if(sel==3) y=a[3]; 3'd4:y=a[4];
else if(sel==4) y=a[4]; 3'd5:y=a[5];
else if(sel==5) y=a[5]; 3'd6:y=a[6];
else if(sel==6) y=a[6]; 3'd7:y=a[7];
else if(sel==7) y=a[7]; default:y=1’bx;
else y=1’bx; endcase
end else y=1'bz;
else end
y=1'bz; endmodule
end
endmodule

OUTPUT
2d.VERILOG CODE FOR4-BIT BINARY TO GRAY CONVERTER

BEHAVIORAL MODELING DATA FLOW MODELING GATE LEVEL MODELING

module b_g(b,g); module b_g(b,g); module b_g(b,g);


input[3:0]b; input[3:0]b; input[3:0]b;
output reg[3:0]g; output[3:0]g; output[3:0]g;
always@(b,g) assign g[3]=b[3]; assign g[3]=b[3];
begin assign g[2]=b[3]^b[2]; xor(g[2],b[2],b[3]);
g[3]=b[3]; assign g[1]=b[2]^b[1]; xor(g[1],b[1],b[2]);
g[2]=b[3]^b[2]; assign g[0]=b[1]^b[0]; xor(g[0],b[0],b[1]);
g[1]=b[2]^b[1]; endmodule endmodule
g[0]=b[1]^b[0];
end
endmodule

OUTPUT
2e.VERILOG CODE FOR4 TO 1 MULTIPLEXER

BEHAVIORAL MODELING DATA FLOW MODELING GATE LEVEL MODELING

module mux4_1(d,s,out); module mux4_1(d,s,out); module mux4_1(d,s,out);


input[3:0]d; input[3:0]d; input[3:0]d;
input[1:0]s; input[1:0]s; input[1:0]s;
output reg out; output out; output out;
always@(d,s) assign out=(~s[1] & ~s[0] & wire s1n,s0n;
begin d[0])|(~s[1] & s[0] & wire [3:0]y;
case(s) d[1])|(s[1] & ~s[0] &
2'b00:out=d[0]; d[2])|(s[1] & s[0] & d[3]); not(s1n,s[1]);
2'b01:out=d[1]; endmodule not(s0n,s[0]);
2'b10:out=d[2]; and(y[0],d[0],s1n,s0n);
default:out=d[3]; and(y[1],d[1],s1n,s[0]);
endcase and(y[2],d[2],s[1],s0n);
end and(y[3],d[3],s[1],s[0]);
endmodule or(out,y[0],y[1],y[2],y[3]);
endmodule
OUTPUT

2e.VERILOG CODE FOR1 TO 4 DEMULTIPLEXER

BEHAVIORAL MODELING DATA FLOW MODELING GATE LEVEL


MODELING

module demux1_4(d,s,out); module demux1_4(d,s,out); module demux1_4(d,s,out);


input d; input d; input d;
input[1:0]s; input[1:0]s; input[1:0]s;
output reg [3:0] out; output [3:0]out; output [3:0]out;
always@(d,s) assign out[0]=(~s[1] & ~s[0] & d); wire s1n,s0n;
begin assign out[1]=(~s[1] & s[0] & d); not(s1n,s[1]);
case(s) assign out[2]=(s[1] & ~s[0] & d); not(s0n,s[0]);
2'b00:begin assign out[3]=(s[1] & s[0] & d); and(out[0],d,s1n,s0n);
out[0]=d;out[1]=0;out[2]=0;out[3]=0;end endmodule and(out[1],d,s1n,s[0]);
2'b01:begin and(out[2],d,s[1],s0n);
out[0]=0;out[1]=d;out[2]=0;out[3]=0;end and(out[3],d,s[1],s[0]);
2'b10:begin endmodule
out[0]=0;out[1]=0;out[2]=d;out[3]=0;end
2'b11:begin
out[0]=0;out[1]=0;out[2]=0;out[3]=d;end
endcase
end
endmodule
OUTPUT

2e.VERILOG CODE FOR2-BIT COMPARATOR

BEHAVIORAL MODELING BEHAVIORAL MODELING GATE LEVEL MODELING


Using if-else using nested if-else
module comp(x,y,xlty,xgty,xeqy); module comp(x,y,xlty,xgty,xeqy ); module comp(x,y,xlty,xgty,xeqy );
input [1:0] x; input[1:0]x,y; input[1:0]x,y;
input [1:0] y; output regxlty,xgty,xeqy; output xlty,xgty,xeqy;
output xlty; always@(x,y) wire
output xgty; begin c1,c2,c3,c4,c5,c6,x1b,x0b,y1b,y0b;
output xeqy; xlty=1'b0; not n1(x1b,x[1]);
regxlty,xgty,xeqy; xgty=1'b0; not n2(x0b,x[0]);
always @(x,y) xeqy=1'b0; not n3(y1b,y[1]);
begin if(x==y) not n4(y0b,y[0]);
if(x==y) xeqy=1;
xeqy=1; and a1(c1,y1b,x[1]);
else if(x>y)
else and a2(c2,y1b,y0b,x[0]);
xgty=1;
xeqy=0; else xlty=1; and a3(c3,y0b,x[1],x[0]);
if(x>y) end or r1(xgty,c1,c2,c3);
xgty=1; endmodule and a4(c4,x1b,y[1]);
else and a5(c5,x0b,x1b,y[0]);
xgty=0;
and a6(c6,x0b,y[0],y[1]);
if(x<y)
xlty=1; or r2(xlty,c4,c5,c6);
else nor n5(xeqy,xgty,xlty);
xlty=0; endmodule
end
endmodule

DATA FLOW MODELING


module comparator(x,y,xlty,xgty,xeqy );
input[1:0]x,y;
output xlty,xgty,xeqy;
assign xgty=(x[1]&~y[1])|(x[0]&~y[1]&~y[0])|(x[0]&x[1]&~y[0]);
assign xlty=(y[1]&~x[1])|(~x[0]&y[0]&y[1])|(~x[0]&~x[1]&y[0]);
assign xeqy=~(xgty|xlty);
endmodule
OUTPUT

3.VERILOG CODE FOR FULL ADDER

BEHAVIORAL MODELING BEHAVIORAL MODELING GATE LEVEL MODELING


USING case statement

module fadd(sum,cout,a,b,cin); module fadd(sum,cout,a,b,cin); module fadd( sum,cout,a,b,cin);


input a,b,cin; input a,b,cin; input a,b,cin;
output regsum,cout; output regsum,cout; output sum,cout;
always@(a,b,cin) always@(a,b,cin) wire c1,c2,s1;
begin begin half_adder h1(s1,c1,a,b);
case({a,b,cin}) sum=a^b^cin; half_adder h2(sum,c2,s1,cin);
3'b000:begin sum=1'b0;cout=1'b0;end cout=(a&b)|(b&cin)|(cin&a); or o1(cout,c1,c2);
3'b001:begin sum=1'b1;cout=1'b0;end end endmodule
3'b010:begin sum=1'b1;cout=1'b0;end endmodule
3'b011:begin sum=1'b0;cout=1'b1;end //HA PROGRAM
3'b100:begin sum=1'b1;cout=1'b0;end module half_adder(s,c,x,y);
3'b101:begin sum=1'b0;cout=1'b1;end input x,y;
3'b110:begin sum=1'b0;cout=1'b1;end output s,c;
3'b111:begin sum=1'b1;cout=1'b1;end assign s=x^y;
endcase assign c=x&y;
end endmodule
endmodule

DATAFLOW MODELING
module fadd( sum,cout,a,b,cin);
input a,b,cin;
output sum,cout;
assign sum=a^b^cin;
assign cout=(a&b)|(b&cin)|(cin&a);
endmodule

OUTPUT

4.VERILOG CODE FOR 32-BIT ALU

module alu_32(a,b,en,cin,opcode,out);
input en,cin;
input [31:0]a,b;
input [3:0]opcode;
output reg [31:0]out;
always@(a,b,en,opcode)
begin
if(en==1)
case(opcode)
4'b0000:out=a;
4'b0001:out=a+1;
4'b0010:out=b;
4'b0011:out=a+b;
4'b0100:out=b+1;
4'b0101:out=a*b;
4'b0110:out=a-b;
4'b0111:out=~b;
4'b1000:out=a+b+cin;
4'b1001:out=~(a&b);
4'b1010:out=~(a|b);
4'b1011:out=a^b;
4'b1100:out=~(a^b);
4'b1101:out=~a;
4'b1110:out= a&b;
4'b1111:out= a|b;
endcase
else out=32'bxxx;
end
endmodule

OUTPUT

You might also like