ECE 2300

Digital Logic & Computer Organization

Spring 2018

Memories

Lecture 14: 1
 Announcements
• HW6 will be posted tonight

• Lab 4b next week: Debug your design before the

in-lab exercise

Lecture 14: 2
Review: ALU Operation Encodings
NAME OP BSEL CI LOP SOP OSEL Operation
ADD 000 00 0 - - 00 Y = A + B + CI
SUB 001 01 1 - - 00 Y = A + B’ + 1
AND 011 00 - 0 - 01 Y = A AND B
OR 100 00 - 1 - 01 Y = A OR B
SHL 101 - - - 0 10 Y = A[6..0],SI
SHR 110 - - - 1 10 Y = SI,A[7..1]
PASS A 111 10 0 - - 00 Y = A
Adder
8 8 A 8
A Y
8 B CO CO
B 8 8 00 CI CI O O
8 8 01
8
Logical 00
0 10 8
A
8 Y 8 01 8 Y
B
LOP 10 8
Control Logic Shifter
2 8 NOR Z
BSEL A 8
3 Y
OP OP LOP SI SI
SO SO
SOP SOP
OSEL 2
Lecture 14: 3
 Comparison Operations (Byproduct of SUB)
• To compare A and B, perform A − B
– If the result is 0, then A = B
– Z flag set to 1 whenever ALU result is 0
– Can check for A ≥ B and A < B by observing the MSB
of the result of A − B

Adder
8 8 A 8
A Y
8 B CO CO
B 8 8 00 CI CI O O
8 8 01
8
Logical 00
0 10 8
A
8 Y 8 01 8 Y
B
LOP 10 8
Control Logic Shifter
2 8 NOR Z
BSEL A 8
3 Y
OP OP LOP SI SI
SO SO
SOP SOP
OSEL 2
Lecture 14: 4
 Our Microprocessor Needs Memory
MUX
0
+2 Adder 1
sext({OFF,0})
MP
Fm … F0
DR RF DataA
Inst. RAM

SA M_address
Decoder

SB RW
DataB ALU Data
PC

MB SA 0 Data_in RAM 0
FS SB 1
1
MD DR
RW D_in VCZN
SE
MW MB MW MD
IMM

Lecture 14: 5
 General Memory Organization
General Memory Organization
• Two dimensional array of bit cells
• Two dimensional
– Each array
bit cell stores 1 bit of bit cells
• Each bit cell stores 1 bit
• •Address
Addressselects
selects aa word
row of data
with (multiple
multiple bit cells)
bit cells
A 3-bit word
Address Data
11 0 1 0
2
Address Array 10 1 0 0
depth
01 1 1 0
3 00 0 1 1
Data width
Lecture 14: 6
 General Memory Organization
• More detail
General Memory Structure
2:4
2:4
Decoder
decoder bitline2 bitline1 bitline0
wordline3
11
2 stored stored stored
Address bit = 0 bit = 1 bit = 0
wordline2
10
stored stored stored
wordline1 bit = 1 bit = 0 bit = 0
01
stored stored stored
bit = 1 bit = 1 bit = 0
wordline0
00
stored stored stored
bit = 0 bit = 1 bit = 1

Data2 Data1 Data0

Lecture 14: !14

Lecture 14: 7
 Types of Memories
• Read-Only Memory (ROM)
– Truly read-only
• Written in the factory, and never written after installation
– Mostly read and rarely written
• Much faster to read than write
– Non-volatile, e.g., flash memory

• Random Access Memory (RAM)

– Read and write any location at similar speeds
– Volatile: loses contents when powered off
– SRAM, DRAM

Lecture 14: 8
 Read-Only Memory (ROM) Structure
fixed at factory
or rarely written

n address memory
lines • decoder 2n word array
• (2n × m)
• lines

• • •
m bit lines

Lecture 14: 9
Example ROM Implementation

resistors

word line

data
output
bit line

Lecture 14: 10
 Applications of ROM
• Program storage
– e.g., Boot code for personal computers, Complete
application storage for embedded systems

• Data storage
– e.g., Configuration information, music players, SSDs

• Combinational logic functions

– Lookup table
• Address inputs = function inputs
• Data outputs = function outputs

Lecture 14: 11
Using ROMs for Combinational Logic

A B C F0 F1 F2 F3
F0 = A' B' C + A B' C' + A B' C 0 0 0 0 0 1 0
0 0 1 1 1 1 0
F1 = A' B' C + A' B C' + ABC 0 1 0 0 1 0 0
0 1 1 0 0 0 1
F2 = A' B' C' + A' B' C + A B' C' 1 0 0 1 0 1 1
1 0 1 1 0 0 0
F3 = A' B C + A B' C' + A B C' 1 1 0 0 0 0 1
1 1 1 0 1 0 0

A memory
B decoder 8 word array
C lines (8 words
by 4 bits)

F0 F1 F2 F3
Lecture 14: 12
What Function does this ROM Implement?
Y1, Y0, X1, X0 Z3, Z2, Z1, Z0
(address) (output)
0000 0000
0001 0000
16 x 4 ROM 0010 0000
Y1 A3 D3 Z3 0011 0000
0100 0000
Y0 A2 D2 Z2
0101 0001
X1 A1 D1 Z1
0110 0010
X0 A0 D0 Z0
0111 0011
1000 0000
1001 0010
1010 0100
1011 0110
1100 0000
1101 0011
1110 0110
1111 1001

Lecture 14: 13
 ROM As a “Random-Logic” Circuit
• ROM advantages
– Design time is short
– Can implement any function of n inputs

• ROM problems
– Size doubles for each additional input
– Cannot exploit logic minimization (e.g., don't cares)

Lecture 14: 14
 Types of Memories
• Read-Only Memory (ROM)
– Truly read-only
• Written in the factory, and never written after installation
– Mostly read and rarely written
• Much faster to read than write
– Non-volatile, e.g., flash memory

• Random Access Memory (RAM)

– Read and write any location at similar speeds
– Volatile: loses contents when powered off
– SRAM, DRAM

Lecture 14: 15
Dynamic RAM (DRAM)

Lecture 14: 16
 DRAM Bit Cell
• Capacitor accessed
through a transistor
Bit line
(BL)
Word line
• Capacitor is charged or (WL)

discharged to produce 1-Bit

DRAM Cell
a 1 or a 0

• DRAM cells loses their

state overtime and must
be refreshed
periodically, hence the
name dynamic

Lecture 14: 17
 DRAM Write
• Word line is asserted
Bit line
• Bit line is driven with the Word line
(BL)
(WL)
desired value
– Capacitor is charged by the bit 1-Bit
DRAM Cell
line to store a 1
– Or discharged by the bit line to
store a 0

Lecture 14: 18
 DRAM Read
• Word line is asserted
Bit line
(BL)
• Bit line precharged halfway Word line
(WL)
between 0 and 1
– Capacitor voltage pulls the bit 1-Bit
DRAM Cell
line slightly higher or lower
– Sense amplifier detects this
small change (1 or 0)

• Read destroys the stored

value
– Need to rewrite the value
afterwards

Lecture 14: 19
 Common DRAM Structure (1)
• Multiplexed address inputs
– Row and column address

Row Addr Latch

& Row Decoder
share same pins
• Row address bits arrive first;
Memory

…
followed by column address bits
Array
– Row-address strobe (RAS)
• Selects a row
– Column-address strobe (CAS)
• Selects a column
RAS Sense Amps
– Row and column address bits
combined form the complete
…
ADDR
address Colum Addr Latch,
CAS Column Mux & Demux

Data In/Out
WE
Buffer

Lecture 14: 20
Example: Read Access to 1Mx1 DRAM Chip
1Mb DRAM array = 1024 rows x 1024 columns

Row Addr Latch

& Row Decoder
Memory

…
Array
10 row address bits
arrive first

RAS asserted …
1024 bits are
read out
10 column address bits
Colum Addr Latch 1 bit returned
arrive later
Column Mux & Demux
CAS asserted

Lecture 14: 21
 Common DRAM Structure (2)
• Bi-directional data
input/output (to save pins)
Row Addr Latch
& Row Decoder

– Write enable strobe (WE)

Memory
…

• WE = 1 : Write mode
Array • WE = 0 : Read mode

RAS Sense Amps

WE
…
ADDR
Colum Addr Latch,
CAS Column Mux & Demux
Dinout

Data In/Out
WE Bit line
Buffer

Lecture 14: 22
 Tri-State Drivers
• Along with 0 and 1, there is a third Hi-Z output
– Output “floats” - no connection to supply or ground

EN A OUT
0 0 Hi-Z
0 1 Hi-Z
1 0 0
1 1 1
• Allows bidirectional data bus
• Allows multiple circuits drive the same line (e.g., wire,
bus)
– Only one node drives the line; others in Hi-Z state

Lecture 14: 23
 Tri-State Drivers

EN C Q2

OUT

D
Q1
A

EN A C D Q1 Q2 OUT

L L H L off off Hi-Z

L H H L off off Hi-Z
H L H H on off L
H H L L off on H

Lecture 14: 24
 Bidirectional Input/Output
via Tri-State Drivers
Write Enable
(WE)

Dinout

Bit line

• WE = 0 (read mode): Dinout is used as output and driven by Bit line

• WE = 1 (write mode): Dinout is used as input and driving Bit line

Lecture 14: 25
 DRAM Refresh
• Capacitors discharge over time
• Refresh cycles recharge each memory bit
– Refresh an entire row at a time
• Each row periodically accessed using RAS, which restores
the charge

0 written 1 written refresh refresh refresh

Vcap
VDD

HIGH

LOW

0V
time

Lecture 14: 26
 Static RAM (SRAM) Bit Cell
• One cell requires six transistors
– The core is two cross-coupled inverters
• Maintaining the state of the cell requires a
constant power
– The cell is stable; no refresh cycles needed
WL

Vdd
6-Transistor SRAM Cell

BL = bit line
WL = word line BL BL

Lecture 14: 27
 SRAM Write
• Drive one bit line high, the
other low (depending on the WL
desired value)

• Then turn on word line

• Bit lines over power cell

BL BL
with new value

Lecture 14: 28
 SRAM Read
• Precharge both bit lines high
WL
• Then turn on word line

• One of the two bit lines will be

pulled down by the cell
– Change detected by sensor
BL BL
amplifier

Lecture 14: 29
 Write Enable SRAM Architecture
Dinn-1 … Dinn-2 Din1 Din0

Column Driver Column Driver Column Driver Column Driver

WL

...
WL

A0…An-1
Address
...
Decoder

...
...

...
…

WL

…
BL BL BL BL BL BL BL BL

Sense Amp Sense Amp Sense Amp Sense Amp

Doutn-1 Doutn-2 … Dout1 Dout0

Lecture 14: 30
 Before Next Class
• H&H 7.3.2-7.3.4

Next Time

Single Cycle Microprocessor

Lecture 14: 31