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Analisis Rangkaian Sekuensial: Moch - Rif'an, ST.,MT

The document discusses sequential circuit analysis using state diagrams and tables. It provides examples of Mealy and Moore state diagrams and their corresponding state tables. It also shows an example timing diagram. The steps of sequential circuit analysis are described as creating equations, K-maps, state tables, and completing the timing diagram.

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Galih Yuga
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53 views16 pages

Analisis Rangkaian Sekuensial: Moch - Rif'an, ST.,MT

The document discusses sequential circuit analysis using state diagrams and tables. It provides examples of Mealy and Moore state diagrams and their corresponding state tables. It also shows an example timing diagram. The steps of sequential circuit analysis are described as creating equations, K-maps, state tables, and completing the timing diagram.

Uploaded by

Galih Yuga
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPS, PDF, TXT or read online on Scribd
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Analisis Rangkaian

Sekuensial

Moch.Rif'an,ST.,MT
State Diagram
(Model Mealy)

A
1/1
1/0
0/0 0/1 0/0 1/0

B C

X/Z

Moch.Rif'an,ST.,MT
State Table
A
Present Input 1/1
1/0
State 0 1 0/0 0/1 0/0 1/0
A B/1 C/0 B C

B B/0 A/1

C A/0 C/0

Moch.Rif'an,ST.,MT
Contoh:
• Time: 0 1 2 3 4 5 6
• Present State: A B A C A C A
• Input: 0 1 1 0 1 0
• Output: 1 1 0 0 0 0
• Next State: B A C A C A

Moch.Rif'an,ST.,MT
State Diagram
(Model Moore)
1

W/0 X/1
1 1
0/0 0
0
0
Y/0

Moch.Rif'an,ST.,MT
State Table
1
Present Input X Output
W/0 X/1
State 0 1 1 1
0/0 0
0
W Y X 0 0
Y/0

X X Y 1

Y X W 0

Moch.Rif'an,ST.,MT
Contoh:
• Time: 0 1 2 3 4 5 6
• Present State: W Y W X X Y X
• Input: 0 1 1 0 1 0
• Output: 0 0 0 1 1 0
• Next State: Y W X X Y X

Moch.Rif'an,ST.,MT
Analisa State Diagram Rangkaian
Sekuensial
0/0 1/0 1/1
1/0 0/0

00 01 11

0/0

Clock
x 0 0 1 1 1 0 1 1 0 0
y1 0 0 0 0 0 0 1 1 1 0
y2 0 0 0 1 1 1 1 1 1 0
z 0 0 0
Moch.Rif'an,ST.,MT 0 0 0 1 1 0 0
Analisa Diagram Logika Rangkaian
Sekuensial
z
x

y SET Y
Q D

Clock
Q CLR

Moch.Rif'an,ST.,MT
Analisa Diagram Logika Rangkaian
Sekuensial
Langkah-langkah:
Buat persamaan
Buat K-map
Buat state table
Lengkapi Timing diagram

Moch.Rif'an,ST.,MT
Buat Persamaan
z z  xy
x
D  x y  xy
y
Q
SET
D
Y D x y
Clock
Q CLR

Moch.Rif'an,ST.,MT
Buat K-map
z  xy
x
Y  x y  xy y 0 1
Y  x y 0 0 0
1 0 1
x z

y 0 1
0 0 1
1 1 0
D
Moch.Rif'an,ST.,MT
Buat State Table
x
y 0 1 x
y 0 1
0 0 1
0 0 1
1 1 0
1 1 0
D
Y
D(t) C Q(t) Input
Q+ = Q( t+ )
0 ↑ 0 0
Present
0 ↑ 1 00 1
1State↑ 0 1
1 ↑ 1 1
x 0 0 Q(t) 0/0= Q(1/0
Q+ t+ )

1 1/0 0/1
Moch.Rif'an,ST.,MT
Y/z
Lengkapi Timing Diagram
Input
Present 0 1
State
0 0/0 1/0
1 1/0 0/1
Y/z
Clock
x
y
z

Moch.Rif'an,ST.,MT
Latihan:
• Buatlah State diagram untuk rangkaian berikut.
z

y SET Y
Q J

Clock
Q CLR K
Moch.Rif'an,ST.,MT
Moch.Rif'an,ST.,MT

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