The Error Correcting Codes (ECC) Page

Welcome!

This page contains several computer programs, written in C/C++ language (and some Matlab
scripts), that implement encoding and decoding routines of popular error correcting codes (ECC),
such as Reed-Solomon codes, BCH codes, the binary Golay code, a binary Goppa code, a Viterbi
decoder and more. Note that no effort has been made to `optimize' most of the algorithms used
in the programs below. The algorithms work well, but by no means should be used as a basis for
an implementation. All these programs are free to use for academic and personal purposes only.
Use them at your own discretion. Enjoy!

If you have an interest in digital communication or storage system design and implementation
that involves (and believe me, it will!) error control coding, drop me a line, I will be happy to
learn more about novel applications of ECC and also to offer my advice.

I still recommend the following best textbooks to learn more about the fascinating topic of error
correcting codes:

1. S. Lin and D. J. Costello, Jr., Error Control Coding: Fundamentals and Applications,
second edition, Prentice Hall: Englewood Cliffs, NJ, 2004.
2. W.W. Peterson and E.J. Weldon, Jr., Error-Correcting Codes, 2nd edition, MIT Press:
Cambridge, Mass., 1972.
3. F.J. MacWilliams and N.J.A. Sloane, The Theory of Error-Correcting Codes, North-
Holland: New York, NY, 1977.

My textbook, now in its second edition, offers a gentle and hands-on (with a companion website
containing more C and Matlab programs) introduction to the basic principles and applications of
error correcting codes:
Copyright (c) 1996-2008. Robert Morelos-Zaragoza. All rights reserved.

1. The Ubiquitous Reed-Solomon Codes

by Barry A. Cipra, Reprinted from SIAM News, Volume 26-1, January 1993

2. Reed-Solomon (RS) codes

Decoding the Berlekamp-Masssey (BM) algorithm, with error evaluation as explained in

Lin and Costello's book.
(Simon Rockliff, 1989)

3. Reed-Solomon errors-and-erasures decoder

Based on the above program to handle errors and erasures, plus other features. Note: The
program does not work with shortened codes and codes over GF(2^m), m<8 ... it gives
good ideas though.
(Thirumoorthy, 1995)

4. Another Reed-Solomon errors-and-erasures decoder

 Nicely written, greatly improved version of the program above. It now lets the user create
multiple encoders at run time with specified parameters You can get the latest package
here. Check also Phil's home page.
(Phil Karn, 2006).

5. BCH codes

Enter only the length and error correcting capability. The program computes the
generator polynomial of any binary BCH code, plus encoding and decoding using the BM
algorithm.
(Morelos-Zaragoza, 1994).

6. Binary (48,36,5) BCH code.

This BCH code is used in control channels for cellular TDMA in the U.S. Since this code
has only two-error correcting capability, fast decoding is done by pre-solving a system of
two equations (the syndromes) in two unknowns (the error positions), see MacWilliams
and Slone's book, chapter 3. NOTE: There was a "bug" in this program, fixed on 8/27/97.

(Morelos-Zaragoza, 1994).

7. Binary (31,21,5) BCH code.

This BCH code is used in the POCSAG protocol specification for pagers. The program is
identical to the one above, except for the parameters. NOTE: There was a "bug" in this
program. It was fixed 8/27/97.
(Morelos-Zaragoza, 1997).

8. Golay (23,12,7) code

Fast encoding and decoding by software with look-up tables. The program uses a 16K-
by-16 bit encoding table and an 8K-by-32 bit decoding table.
(Morelos-Zaragoza, 1994).

9. A Goppa code

Encoding/Decoding of a (1024,654,75) Goppa code (originally written with a public key

cryptographic scheme in mind). This program is a compact implementation of Goppa
codes with parameters m=10, t=37 for 32-bit machines. Decoding method due to N.
Patterson, ``Algebraic Decoding of Goppa Codes,'' IEEE Trans. Info.Theory, 21 (1975),
203-207.
(Anonymous, as far as I know)

10. CRC-32
 Computes the CRC value of a file, as used in ZMODEM or PKZIP.
(Craig Bruce, 1994)

11. ecc-1.2.1.tar (106496 bytes)

Routines to encode and decode a file using a (255,249,7) RS code.

(Paul Flaherty, 1993)

12. Turbo-codes home page at JPL

13. TURBO decoder archive: BCJR_turbo.tar

An implementation of the BCJR algorithm, based on the pseudocode in W.E.Ryan's

tutorial paper (PS file).
(Mathys Walma, 1998)

14. Viterbi decoding

Package viterbi-3.0.1.tar contains programs to implement Viterbi decoding of (de-facto

standard) rate-1/2 and rate-1/3 m=7 convolutional codes. Package simd-viterbi-2.0.1.tar
contains programs to implement Viterbi decoders for r=1/2 k=7 and k=9 codes that use
the Intel/AMD SIMD instruction sets (MMX/SSE/SSE2). Check also Phil's home page.
(Phil Karn, 2006)

15. galois.tar

Encoding/decoding for BCH/RS codes.

(Bart De Canne, 1994)

16. A block coded QPSK modulation for unequal error protection (UEP)

This program was used to simulate the performance of a coding scheme proposed in my
Ph.D. thesis for UEP over an AWGN channel. For more details, see R.H. Morelos-
Zaragoza and S. Lin, ``QPSK Block Modulation Codes for Unequal Error Protection,''
IEEE Transactions on Information Theory, Vol. 41, No. 2, pp. 576-581, March 1995.
(Morelos-Zaragoza, 1993)

17. Linear code bound

How good is a code? What are the lower and upper bounds on the minimum distance of a
linear block code given its length and dimension? The answer to this question may be
found on-line! ([email protected], 1995). Also try: http://www.codetables.de/
maintained by Markus Grassl (Thanks to Axel Kohnert for the pointer).

18. Erasure-correcting codes

 An implementation of a block code for erasure correction in network communication
protocols. The encoder/decoder runs quite fast (up to several MB/s on a Pentium).
(Luigi Rizzo, 1996)

19. Finite Field Calculator and Reed-Solomon Simulator

Java applet of GF calculator and an RS encoder/decoder

(Emina Soljanin, 1997)

20. A Windows 95/NT program to do Galois Field math

(Andrew Lin, 1997)

21. Properties of binary linear codes

This is a C++ program (compiled for Sparcs) that computes properties of binary codes,
from more basic items such as minimum distance and dimension to more complicated
properties such as trellis decoding complexity and whether the Tanner graph of the code
is cycle-free.
(Ari Trachtenberg, 1998)

22. Maximal LFSR program

A program to find primitive polynomials of maximum cycle length

(Steve Ungstad, 1999)

23. A Tutorial on Convolutional Coding with Viterbi Decoding

The purpose of this tutorial is to introduce the reader to a forward error correction
technique known as convolutional coding with Viterbi decoding. More particularly, this
tutorial will focus primarily on the Viterbi decoding algorithm itself. The intended
audience is anyone interested in designing or understanding wireless digital
communications systems.
(Chip Fleming, 1999)

24. David MacKay's Gallager low density parity-check (LDPC) code resources.

An excellent reference for iterative decoding. Papers on Gallager codes. Matrices for
codes. Source code for decoding.
(David MacKay, 1997)

25. MATLAB routines for LDPC codes over GF(q), q=2^m.

A few MATLAB routines for encoding/decoding low density parity check codes.
(Igor Kozintsev, 1999)
 26. Perl script for a type-C2 algebraic interleaver.

Generates a sequence of distinct numbers such that the length of the sequence can be any
power of 2. A particular characteristic of the generated sequence is that it is symmetric in
the sense that an entry j in row i implies that the entry in row j is i. (Interleaver and
deinterleaver are identical!)
(Oscar Takeshita, 1997)

27. Forward Error Correction (FEC) Page

This site contains some examples of Forward Error Correction (FEC) software and
hardware. You will find software and hardware examples for free download, which are
available as 'C' source code, VHDL source code or as 'VHDL' code generators for
SUN/Solaris.
(Christian Schuler, 1998. Updated 2001)

28. A fast and accurate degree distribution optimizer for ldpc code ensembles

The tool ldpcopt was developed in Switzerland, to search for optimized LDPC degree
distributions for various channels.
(Abdelaziz AMRAOUI, 2001.)

29. Tc_Ds_Analysis.exe 

Windows program to compute the distance spectrum of a turbo code and the union bound
on the BER. See the read_me file
(Seokhyun Yoon, 2002.)

This page was last updated on August 6, 2008. Robert Morelos-Zaragoza

--====================================================================--
-- Design units : RS232_Receive(RTL) (Entity and architecture)
--
-- File name : rs232_receive.vhd
--
-- Purpose : The module receives a serial RS-232 bit stream. The
-- bit stream should contain 1 start bit (’0’), 8 data
-- bits and finally 2 stop bits (’1’). The baud rate
-- is selectable to 1200, 2400, 4800 or 9600. The last
-- received data is output in 8-bit parallel format.
--
-- Note : This model can be synthesized by Synopsys VHDL
-- Compiler and Mentor AutoLogic VHDL.
--
-- Limitations : The baud rates have been approximated in order to
-- allow a simpler implementation. A Clk frequency of
-- 10 MHz is assumed.
--
-- Errors: : None known
--
-- Library : XYZ_Lib
--
-- Dependencies : None
--
-- Author : Peter Sinander
-- ESTEC Onboard Data Division (WD)
-- P.O. Box 299
-- 2200 AG Noordwijk
-- The Netherlands
--
-- Simulator : Synopsys v. 3.0c, on Sun Sparcstation 10, SunOS 4.1.3
------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 1.0 PSI 4 Mar 94 New version
-- 2.0 PSI 10 May 94 Baudrate index changed to descending;
-- Constants introduced for baud count;
-- Header and comments modified.
------------------------------------------------------------------------
-- Naming convention: Active low signals are indicated by "_N",
-- synchronized signals are indicated by "Sync".
entity RS232_Receive is
port(
Clk: in Bit; -- Clock, nominally 10 MHz
Reset_N: in Bit; -- Asynchronous Reset
RxIn: in Bit; -- Serial data in
BaudRate: in Bit_Vector(1 downto 0); -- Bit rate selection
RxOut: out Bit_Vector(7 downto 0)); -- Last received data,
end RS232_Receive; -- Bit 0 is LSB
european space agency 31 ASIC/001 Issue 1
--=========================== ARCHITECTURE ===========================--
architecture RTL of RS232_Receive is
-- These constant would normally be placed in a package defining all
-- constants and subprograms used by the design, but in this
-- example they have been placed here.
constant Baud1200: Bit_Vector := "00"; -- Baud selections
constant Baud2400: Bit_Vector := "01";
constant Baud4800: Bit_Vector := "10";
constant Baud9600: Bit_Vector := "11";
constant Count1200: Integer := 4096; -- End count values
constant Count2400: Integer := 2048;
constant Count4800: Integer := 1024;
constant Count9600: Integer := 512;
constant InitRxReg: Bit_Vector := "1111111110"; -- Init. pattern
signal RxInSync: Bit; -- Synchronised Rx
begin -- Architecture RTL of RS232_Receive
---------------------------------------------------------------------
-- Input serial data is synchronized with Clk to protect against
-- meta-stability. This process could be merged with the Rs232
-- process in order to increase the simulation performance (it was
-- written separately here for the cause of clarity).
---------------------------------------------------------------------
SyncRxIn: process (Clk, Reset_N)
begin
if Reset_N = ’0’ then -- Asynchron. reset
RxInSync <= ’1’;
elsif Clk’Event and Clk = ’1’ then -- Rising Clk edge
RxInSync <= RxIn;
end if;
end process SyncRxIn;
---------------------------------------------------------------------
-- The Rs232 process contains a counter which toggles the Sample
-- signal two times per bit period. The rising edge of Sample (which
-- occurs in the middle of the input bit) is synchronously detected
-- by comparing it to DelaySample (the Sample signal delayed one Clk
-- cycle); at this time the data bit is clocked into the shift
-- register.
--
-- The State machine controlling the shift register has been merged
-- with the shift register itself. When the last bit - RxReg(0) - is
-- 0 the retrieval cycle has completed and the process is waiting
-- for the next start bit. When a start bit is detected, the counter
-- starts incrementing, at each sample time shifting in one data bit
-- (a start bit shorter than a half bit period will have no impact).
-- When the start bit, which is ’0’, reaches RxReg(0) the data is
-- copied to the output, and the process will wait for the next start
-- bit.
---------------------------------------------------------------------
Rs232: process (Clk, Reset_N)
variable BaudCount: Integer range 0 to 8191; -- 13 bit counter
variable Sample: Bit; -- For bit sample
variable DelaySample: Bit; -- To detect edge
variable RxReg: Bit_Vector(9 downto 0); -- 10 bit shift
-- register
ASIC/001 Issue 1 32 european space agency
begin
if Reset_N = ’0’ then -- Asynchron. reset,
BaudCount := 0; -- initialize all
Sample := ’0’; -- values
DelaySample := ’0’;
RxReg := InitRxReg;
RxOut <= X"00";
elsif Clk’Event and Clk = ’1’ then -- Rising Clk edge
-- Wait for RxInSync to be 0, i.e. the start bit in the serial
-- input stream.
if RxInSync = ’1’ and RxReg(0) = ’0’ then
-- Waiting for the start bit; initialise values
BaudCount := 0;
Sample := ’0’;
RxReg := InitRxReg;
elsif (BaudRate = Baud1200 and BaudCount >= Count1200) or
(BaudRate = Baud2400 and BaudCount >= Count2400) or
(BaudRate = Baud4800 and BaudCount >= Count4800) or
(BaudRate = Baud9600 and BaudCount >= Count9600) then
-- The counter has reached half a bit period (assuming that
-- Clk runs at 10 MHz); reset counter and toggle the Sample
-- signal (the exact bit rates are 1220, 2441, 4882 & 9765)
BaudCount := 0;
Sample := not Sample;
else -- RxInSync = ’0’ or RxReg(0) = ’1’
BaudCount := BaudCount + 1;
end if;
if Sample = ’1’ and DelaySample = ’0’ then
-- Rising Sample edge; shift in one data bit
RxReg := RxInSync & RxReg(9 downto 1);
if RxReg(0) = ’0’ and RxReg(8) = ’1’ and RxReg(9) = ’1’ then
-- Last bit acquired, copy data to output if stop
-- bits are both ’1’
RxOut <= RxReg(8 downto 1);
end if;
end if;
-- Sample delayed one Clk
DelaySample := Sample;
end if;
end process Rs232;
end RTL; --=========== End of RS232_Receive(RTL) =====================--