PLC Command Index

[Introduction Page] [Programming References]

Register
Basic Compare Data Math
Timer / / Program
Instructio Comman Comman Comman
Counter Sequence Control
ns ds ds ds
r

EQU MOV SCI IIM

CTD
OSR GEQ MVM SCP IOM
CTU BSL
OTE GRT NEG SIN JMP
HSC BSR
OTL LEQ NOT SQR JSR
RES SQC
OTU LES OR SUB LBL
RTO SQL
XIC LIM RAD SWP MCR
TOF SQO
XIO MEQ TOD TAN REF
TON
NEQ XOR XPY RET

A.B. MicroLogix and SLC Family

Basic Input/Output Instructions
[Introduction Page] [Command Index] [Programming References]

This page contains basic input and output instructions and their use in PLC logic
programs. These instructions are used to perform basic tasks such as bit control: ON or
OFF.

Location of Commands in the Software

 Command Table
Command Name Description
Examine If
XIC Examines a bit for an ON condition
Closed
Examine If
XIO Examines a bit for an OFF condition
Open
Output
OTE Turns a bit ON or OFF
Energize
OTL turns a bit on when the rung is executed, and this bit retains its
OTL Output Latch
state when the rung is not executed or a power cycle occurs.
Output
OTU OTU turns off the bit and retains it.
Unlatch
One-Shot
OSR Triggers a one time event
Rising

Timer/Counter Instructions
[Introduction Page] [Command Index] [Programming References]

This page contains timer and counter instructions and their use in PLC logic programs.
These instructions are used for timing a process or counting the number of times a process
occurs.

Location of Commands in the Software

 Command Table

Command Name Description

Timer On-
TON Counts timebase intervals when the instruction is true
Delay

Timer Off-
TOF Counts timebase intervals when the instruction is false
Delay

Counts timebase intervals when the instruction is true and retains the
Retentive
RTO accumulated value when the instruction goes false or when power cycle
Timer
occurs

Increments the accumulated value at each false-to-true transition and

CTU Count Up retains the accumulated value when the instruction goes false or when
power cycle occurs

Decrements the accumulated value at each false-to-true transition and

CTD Count Down retains the accumulated value when the instruction goes false or when
power cycle occurs

High-Speed
HSC Counts high-speed pulses from a fixed controller high-speed input
Counter

Resets the accumulated value and status bits of a timer or counter. Do not
RES Reset
use with TOF timers
 Comparison Instructions
[Introduction Page] [Command Index] [Programming References]

Comparison instructions are used to test pairs of values using one of the eight following
logical operators to determine if a rung is true.

Location of Commands in the Software

Command Table
Command Name Purpose
Test whether one value is within the limit range of two other
LIM Limit Test
values.
Masked Test portions of two values to see whether they are equal.
MEQ Comparison for Compares 16 bit data of a source address to 16 bit data at a
Equal reference address through a mask.
EQU Equal Test whether two values are equal.
NEQ Not Equal Test whether one value is not equal to a second value.
LES Less Than Test whether one value is less than a second value.
Less Than or
LEQ Test whether one value is less than or equal to a second value.
Equal
GRT Greater Than Test whether one value is greater than another is.
Greater Than or
GEQ Test whether one value is greater or equal to a second value.
Equal
 Data Handling Instructions
[Introduction Page] [Command Index] [Programming References]

These instructions are used to convert information, manipulate data in the controller, and
perform logic operations.

Location of Conversion Commands in the

Software

Command Table
Command Name Purpose
Converts the integer source value to BCD format and stores it in
TOD Convert to BCD
the designation.
Convert from Converts the BCD source value to an integer and store it in the
FRD
BCD destination.
NEG Negate Changes the sign of the source and stores it in the destination.

Command Table
Command Name Purpose
Convert from Radians Converts radians (source) to degrees and stores the result
DEG
to Degrees in the destination.
RAD Convert from Degrees Converts degrees (source) to radians and stores the result
 to Radians in the destination.
Decode 4 to 1 Decodes a 4-bit value (0 to 15), turning on the
DCD
of 16 corresponding bit in the 16-bit destination.

Location of Copy Commands in the Software

Command Table
Command Name Purpose
COP Copy File Copies data from the source file to the destination file.
FLL Fill File Loads a source value into each position in the destination file.

Location of Move and Logic Commands in the

Software

Command Table
Command Name Purpose
MOV Move Moves the source value to the destination.
Masked Moves data from a source location to a selected portion of the
MVM
Move destination.
AND And Performs a bitwise AND operation.
OR Or Performs a bitwise inclusive OR operation.
XOR Exclusive Or Performs a bitwise exclusive OR operation.
 NOT Not Performs a NOT operation.

Command Table
Command Name Purpose
The FIFO instructions load words into a file and unload them in
FFL and FIFO Load and
the same order as they were loaded. The first word in is the first
FFU FIFO Unload
word out.
The LIFO instructions load words into a file and unload them in
LFL and LIFO Load and
the opposite order as they were loaded. The last word in is the
LFU LIFO Unload
first word out.

Math Instructions
[Introduction Page] [Command Index] [Programming References]

This page contains math instructions and their use in PLC logic programs. Use this page to
create programs that perform mathematical functions such as addition, subtraction, and
trigonometric forms. Most instructions take two input values and perform the function that
is assigned to an output location.

Location of Commands in the Software

 Command Table
Command Name Purpose
ADD Add Adds source A to source B and stores the result in the destination.
Subtracts source B from source A and stores the result in the
SUB Subtract
destination.
MUL Multiply Multiplies source A by source B and stores the result in the destination.
Divides source A by source B and stores the result in the destination
DIV Divide
and the math register.
Square Calculates the square root of the source and places the integer result in
SQR
Root the destination.
CPT Compute Evaluates an expression and stores the result in the destination.

Location of Commands in the Software

Command Table
Command Name Purpose
CLR Clear Sets all bits of a word to zero.
 Location of Commands in the Software

Command Table
Command Name Purpose
Double Divides the contents of the math register by the source and stores the
DDV
Divide result in the destination and the math register.
Multiplies the source by a specigfied rate, adds to an offset value, and
SCL Scale Data
stores the result in the destination.

Location of Commands in the Software

Command Table
Command Name Purpose
COS Cosine Takes the cosine of a number and stores the result in the destination.
SIN Sine Takes the sine of a number and stores the result in the destination.
TAN Tangent Takes the tangent of a number and stores the result in the destination.
Takes the arc sine of a number and and stores the result in (in radians)
ASN Arc Sine
in the destination.
Takes the arc cosine of a number and and stores the result (in radians)
ACS Arc Cosine
in the destination.
Arc Takes the arc tangent of a numberand stores the result (in radians) in
ATN
Tangent the destination.

Location of Commands in the Software

Command Table
Command Name Purpose
Takes the natural log of the value in the source and stores it in
LN Natural Log
the destination.
Log to the Base Takes the log base 10 of the value in the source and stores the
LOG
10 result in the destination.
X to the Power of Raise the value to a power and stores the result in the
XPY
Y destination.
Swaps the low and high bytes of a specified number of words in
SWP Swap
a bit, integer, ASCII, or string file.
Calculates the absolute value of the source and places the result
ABS Absolute
in the destination.
Scale with Produces a scaled output value that has a linear relationship
SCP
Parameters between the input and scaled values.
 Shift Register and Sequencer
[Introduction Page] [Command Index] [Programming References]

Shift Register and Sequencer instructions simplify your ladder program by allowing you to
use a single instruction or pair of instructions to perform common complex operations.

Location of Commands in the Software

Command Table
Command Name Purpose
Loads a bit of data array, shifts the pattern of data through the array
Bit Shift Left
BSL to the left and unloads the last bit of data in the array.
Loads a bit of data array, shifts the pattern of data through the array
BSR Bit Shift Right
to the right and unloads the last bit of data in the array.
Sequencer Controls sequential machine operation by transfering 16-bit through
SQO
Output a mask to image addresses for controlling outputs.
Sequencer Controls sequential machine operation by transfering 16-bit through
SQC
Compare a mask to image addresses to reference data for monitoring inputs.
Sequencer Capture reference conditions by manually stepping the machine
SQL
Load through its operating sequences.

Program Control Instructions

[Introduction Page] [Command Index] [ Programming References]

Use these instructions to control the sequence in which your program is executed. Control
instructions allow you to change the order in which the processor scans a ladder program.
 Typically, these instructions are used to minimize scan time, create a more efficient
program, and to troubleshoot a ladder program.

Location of Commands in the Program Control

Section

Command Table
Command Name Purpose
JMP Jump to Label Jump forward to the specified label instruction.
LBL Label Specifies label location.
JSR Jump to Subroutine Jump to a designated subroutine instruction.
Return from
RET Exists current subroutine and returns to previous condition.
Subroutine
SBR Subroutine Identifies the subroutine program.
TND Temporary End Mark a temporary end that halts program execution.
Master Control
MCR Clears all set outputs between the paired MCR instructions.
Reset
Identifies specific conditions for program debugging and
SUS Suspend
system troubleshooting.
 Location of Commands in the Input/Output
Section

Command Table
Immediate Input with
Program and immediate input with Mask.
IIM Mask
Immediate Output with
IOM Program an immediate Output with Mask.
Mask
Interrupt the program scan to execute the I/O scan and service
REF Refresh
communications.

Communications Instructions
[Introduction Page] [Command Index] [Programming References]

Command Name Purpose

This instruction transfers data from one Node to another on the
Message Read / communication network. When the instruction is enabled,
MSG
Write message transfer is pending. Actual data transfer takes place at
the scan. (Used with DH+)
When conditions preceding the SVC instruction in the rung are
Service
SVC true, the SVC instruction interrupts the program scan to execute
Communications
the service communication portion of the operating cycle.
 Programming References
[Introduction Page] [Command Index]

This page contains a list of SLC processor Status Files, recommends corrective action for
Faults, Guide to Wiring and other information.

Status File Overview

The status file lets you monitor how your operating system works and lets you direct how
you want it to work. This is done by using the status file to set up interrupts, load memory
module programs, and monitor both hardware and software faults.

Note:Do not write to status file data unless the word or bit is listed as dynamic/static
configuration in the descriptions that follow. If you intend writing to status file data, it is
imperative that you first understand the function fully.
The status file S: contains the following words:

Word Function applies to all processors

S:0 Arithmetic Flags

S:1 Processor Mode Status/Control

S:2 STI Bits / DH485 Comms.

S:3L Current/Last Scan Time

S:3H Watchdog Scan Time

 S:4 Free Running Clock

S:5 Minor Error Bits

S:6 Major Error Code

S:7,S:8 Suspend Code/Suspend File

S:9,S:10 Active Nodes (DH-485)

S:11,S:12 I/O Slot Enables

S:13,S:14 Math Register

S:15L Node Address

S:15H Baud Rate

Word Function applies to SLC 5/02, SLC 5/03,SLC 5/04 processors

S:16,S:17 Test Single Step - Start Step On - Rung/File

S:18,S:19 Test Single Step - Breakpoint - Rung/File

S:20,S:21 Test - Fault/Power down - Rung/File

S:22 Maximum Observed Scan Time

S:23 Average Scan Time

S:24 Index Register

S:25,S:26 I/O Interrupt Pending

S:27,S:28 I/O Interrupt Enabled

S:29 User Fault Routine File Number

S:30 Selectable Timed Interrupt Set point

S:31 Selectable Timed Interrupt File Number

S:32 I/O Interrupt Executing

Word Function applies to SLC 5/03, and SLC 5/04 processors

S:33 Extended Processor Status and Control Word

S:34 Pass thru Disabled (SLC 5/04 only)

S:35 Last 1 ms Scan Time

S:36 Extended Minor Error Bits

S:37 Clock/Calendar Year

S:38 Clock/Calendar Month

S:39 Clock/Calendar Day

S:40 Clock/Calendar Hours

S:41 Clock/Calendar Minutes

S:42 Clock/Calendar Seconds

S:43 STI Interrupt Time (SLC 5/03 and SLC 5/04)

S:44 I/O Event Interrupt Time (SLC 5/03 and SLC 5/04)

S:46 Discrete Input Interrupt - FIle Number

S:47 Discrete Input Interrupt - Slot Number

S:50 Discrete Input Interrupt - Preset

S:51 Discrete Input Interrupt - Return Mask

S:52 Discrete Input Interrupt - Accumulator

S:55 Last DII Scan Time

S:56 Maximum Observed DII Scan Time

S:57 Operating System Catalog Number

S:61 Processor Series

S:62 Processor Revision

 S:63 User Program Type

S:65 User RAM Size

S:66 Flash EEPROM Size

S:67,S:68 Channel 0 Active Nodes

Word Function applies to SLC 5/04 processors

S:69 to S:82 Reserved

S:83 to S:86 DH+ Active Nodes (Channel 1 SLC 5/04 only)

S:87 to S:98 Reserved

S:99 Global Status Word

S:100 to S:163 Global Status File

The Following Table Describes Some Status Files Functions

Address Bit Classification Description

This bit is set by the controller when the result of a

mathematical operation does not fit in its
S:0/1 Overflow Status destination. Whenever this bit is set, the overflow
trap bit S:5/0 is also set except for the ENC bit.
Refer to S:5/0.

When set, this bit causes the controller to at Power

up Configuration the Major Error Halted bit S:1/13
Fault and Minor error bits S:5/0 to S:5/7 on power up if
Static
S:1/8 Override at the processor had previously been in the REM run
Configuration
Powerup mode and had faulted. The controller then attempts
to enter the REM Run mode. Set this bit using the
Data Monitor function offline only.

S:1/9 Startup Static When this bit is set and power is cycled while the
 Protection Configuration controller is in the REM Run mode, the controller
Fault executes the user-fault routine prior to the execution
of the first scan of your program. You have the
option of clearing the Major Error Halted bit S:1/13
to resume operation in the REM Run mode. If user-
fault routine does not reset bit S:1/13, the fault
mode results. Program the user-fault routine logic
accordingly. When executing the startup protection
fault routine, S:6 (major error fault code) will
contain the value 001 6H.

This bit is set by the controller any time a major

error is encountered. The controller enters a fault
condition. Word S:6, the Fault Code will contain a
code that can be used to diagnose the fault
condition. Any time bit S:1/13 is set, the controller:

 either places all outputs in a safe state

(outputs are off) and energizes the fault
LED,
 or enters the user-fault routine with outputs
Major active (if in REM Run mode), allowing the
Dynamic
S:1/13 Error fault routine ladder logic to attempt recovery
Configuration
Halted from the fault condition. If the user-fault
routine determines that recovery is required,
clear S:1/13 using ladder logic prior to
exiting the fault routine. If the fault routine
ladder logic does not understand the fault
code, or if the routine determines that it is
not desirable to continue operation, the
controller exits the fault routine with bit
S:1113 set. The outputs are placed in a safe
state and the FAULT LED is energized.

Using this bit you can control access to a controller

file. To program this feature, select Future Access
Disallow when saving your program. When this bit
Static
S:1/14 OEM Lock is set, only an programming device with an
Configuration
matching copy of the processor file in its memory
can monitor the ladder program, others are denied
access.

Math Dynamic Set this bit when you intend to use 32-bit addition
S:2/14
Overflow Configuration and subtraction. When 5.2/14 is set, and the result
 Selection of an ADD, SUB, MUL, or DIV instruction cannot
be represented in the destination address (underflow
or overflow),

 the overflow bit S:0/l is set,

 the overflow trap bit S:5/Ois set,
 and the destination address contains the
unsigned truncated least significant 16 bits
of the result.

Use this bit to initialize your program as the

application requires. Indicates the first scan of the
S:1/15 First Pass Status
user program. Makes rung true only for the first
scan after entering the run mode.

You can use any individual bit of this word in your

user program as a 50% duty cycle clock bit. (S:4/0
S:4/7 Timebase Status
to S:4/15 are 20, 40, 80, 160, 320, 640, 1280, 2560,
5120, 10240, 20480, 40960, 81920....)

When this bit is set by the controller, it indicates

Overflow Dynamic
S:5/0 that a mathematical overflow has occurred in the
Trap Configuration
ladder program

A hexadecimal code is entered in this word by the

controller when a major error is declared. Refer to
S:1/13. The code defines the type of fault, as
indicated on the following pages. This word is not
cleared by the controller. Error codes are presented,
Major stored, and displayed in a hexadecimal format. If
S:6 Status
Error Code you enter a fault code as a parameter in an
instruction in your ladder program, you must
convert the code to decimal. Application note: You
can declare your own application specific major
fault by writing a unique value to S:6 and then
setting bit S:1/13.

File Organization

Program Files
 Program files contain controller information, the main ladder program, interrupt
subroutines, and any subroutine programs. These files are:

 System Program (file 0) - This file contains various system related information and
user-programmed information such as processor type, I/O configuration, processor file
name, and password.

 Reserved (file 1) - This file is reserved.

 Main Ladder Program (file 2) - This file contains user-programmed instructions

defining how the controller is to operate.

 Subroutine Ladder Program (file 3-255) - These files are user-created and accessed
according to subroutine instructions residing in the main ladder program file.

Data Files

Data files contain the status information associated with external I/O and all other
instructions you use in your main and subroutine ladder program files. In addition, these
files store information concerning processor operation. You can also use the files to store
"recipes" and look-up tables if needed. These files are organized by the type of data they
contain. The data file types are:

 Output (file 0) - This file stores

Size in
the state of the output terminals Address Range File
Elements
for the controller.

 Input (file 1) - This file stores O:000 - O:037 Output Image File 32
the status of the input terminals
I:000 - I:037 Input Image File 32
for the controller.

 Status (file 2) - This file stores S:000 - S:031 Processor Status 32

controller operation information,
This file is useful for B3:000 - B3:999 Bit File 1 - 1000
troubleshooting controller and
program operation. T4:000 - T4:999 Timer File 1 - 1000

C5:000 - C5:999 Counter File 1 - 1000

Instruction Set Reference R6:000 - R6:999 Control File 1 - 1000

N7:000 - N7:999 Integer File 1 - 1000

 F8:000 - F8:999 Floating Point File 1 - 1000
 Bit (file 3) - This file is used for
internal relay logic storage.
1 - 1000
B3:1/0 or B3/16 9 - 999 Files to be assigned
per file
 Timer (file 4) - This file stores
the timer accumulator and preset
values and status bits. T4:0.PRE,
T4:0.ACC, T4:0/DN, T4:0/TT,
T4:0/EN

 Counter (file 5) - This file stores

the counter accumulator and
preset values and the status bits.
C5:0.PRE, C5:0.ACC,
C5:0/DN, C5:0/CU, C5:0/CD,
C5:0/OV, C5:0/UN

 Control (file 6) This file stores

the length, pointer position, and
statu bits for specific instructions
such as shift registers and
sequencers. R6:0, R6:0.Len
(Length), R6:0.Pos (Position)

 Integer (file 7) - This file is used

to store numeric values or bit
information. N7:1/3

 Floating Point (file 8) - This file

stores single precision non-
extended 32-bit numbers. Applies
to SLC 5/03 and SLC 5/04
processors.F8:000 to F8:9999

Valid Addressing Modes and File Types

Addressing Modes File Types

 Addressing Mode Example O Output
Direct N7:O I Input
Indexed Direct #N7:O S Status
Indexed N7:[N10:3] B Binary
Indexed Indirect #N7:[N1O:3] T Timer
C Counter
R Control
N Integer
F Float
A ASCII
ST String
M M0/M1

Direct Addressing

 The data stored in the specified address is used in the instruction. For example:
 N7:0, T4:8.ACC, T4:8.PRE, ST20:5

Indexed Addressing

 You may specify an address as being indexed by placing the "#" character in front of the
address. When an address of this form is encountered in the program, the processor takes
the element number of the address and adds to it the value contained in the Index Register
S:24, then uses the result as the actual address. For example:
 #N7:l0 where S:24= 15, The actual address used by the instruction is N7:25.

Indirect Addressing

 You may specify an address as being indirect by replacing the file number, element
number, or sub-element number with a [Xf:e.s] symbol. The word address inside of the
bracket is queried for a value. The queried value then becomes the file, element, or sub-
element portion of the indirect address. For example: B3:[N 10:2] states that the element
 address of Bit file 3 is contained in address N10:2. Therefore, if N10:2 contains the value
5, B3:[N10:2] indirectly refers to address B3:5. Other examples include:
 N7:[N7:0], N[N7:0]:[N7:1], N7[T4:0.ACC], C5:[N7:0]

Indexed Indirect Addressing

 You may specify a combination of indirect and indexed addressing. The processor first
resolves the indirect portion of the address and then adds the offset from the Index
Register S:24 to come up with the final address. For example:
 #N7:[N10:3] where N10:3= 20 and S:24 =15 The actual address used by the instruction is
N7:35.

Troubleshooting Faults

The major error fault code, indicates the probable causes of faults, and recommends
corrective action. The following section describes the different ways to automatically clear
a fault using your programming software.

AutomaticalIy Clearing Faults: SLC Processors

 Set the Fault Override at Power up Bit S:1/8 in the status file to clear the fault when
power is cycled, assuming the user program is not corrupt.

 Set one of the auto load bits S:1/10, S:1/11, or S:1/12 in the status file of the program in
an EEPROM to automatically transfer a new non-faulted program from the memory
module to RAM when power is cycled.

 Refer to Status Bits for more information on bits S:1/13, S:1/8, S:1/10, S:1/11, S:1/12,
S:5/0-7, and S:36/0-7. You can declare your own application specific major fault by
writing your own unique value to S:6 and then setting hit S:1/I3.

Manually Clearing Faults: SLC Processors

 Manually clear the major fault bit S:1/13, and the minor and major error bits S:5/0-7 in
the status file, using a programming device or a Data Table Access Module. Place the
processor in the REM Program mode. Correct the condition causing the fault, then return
the processor to either REM Run or any of the REM Test modes.

 SLC 5/03 and SLC 5/04 specific - Toggle the key switch from RUN to Progrram and then
back to RUN.
  SLC 5/03 and SLC 5/04 specific - Clearing these bits with the keys witch in the RUN
position causes the processor to immediately enter the Run mode.

 If you are online with a SLC 5/03 or SLC 5/04 processor with the keys witch position is
in RUN and you press the clear major fault function key, you are warned that the
processor will enter the Run mode once you clear the fault

Using the Fault Routine

 When designating a subroutine file, the occurrence of recoverable or non-recoverable

user faults causes the designated subroutine to be executed for one scan. If the fault is
recoverable, the subroutine can be used to correct the problem and clear the fault bit
S:1/13. The processor then continues in the run mode. If the fault is non-recoverable, the
subroutine can send a message via the Message instruction to another DH-485 node with
error code information and/or does an orderly shutdown of the process. The subroutine
does not execute for non-user faults.

Just A "Guide" To Wiring

Wire colors are a combination of actual standards, plus additions:

Voltages AC Color
AC(-) Neutral White
120 or 220v AC(+) (Hot Wire, Line In) Black
120v AC (Control Circuits, Power) Red (common practice)
Ground Green or Green / Yellow
Black with the ends taped:
480v 3-Phase (The wires could be the actual colors:) Red/Yellow/Orange
or Red/Brown/Blue
Foreign Voltage (Outside the panel) Yellow
Temporary Jumpers Purple (easy to see)
Oddball voltages (Speed Control potentiometer wiring) Violet
Unspecified voltages (relay contact for customer connections) Gray
 Voltages DC Color
24v DC(+) Brown
24v DC(-) Blue
DC grounded circuits White / Blue stripe
Foreign Voltage (Outside the panel) Yellow
Temporary Jumpers Purple (easy to see)
Oddball voltages (Speed Control potentiometer wiring) Violet
Unspecified voltages (relay contact for customer connections) Gray

Inside the panel UL-508 allows the following

18 AWG = 7 Amps max
16 AWG = 10 Amps max
14 AWG = 20 Amps max
12 AWG = 25 Amps max
10 AWG = 40 Amps max

The allowable Current is Lower than the above stated values when the wire is in conduit,
wireway or ductbank. Go to the NEC for these requirements.

 Most places use 14 AWG minimum for 120 VAC field wiring, regardless of amps.
 Typically, 16 AWG minimum for 24 VDC field control circuits, and 18 AWG shielded
twisted pair for 4-20 mA wires (Belden 1032A or eq.)
 Avoid using 14 or 12 AWG shielded twisted pair for 4-20 mA wiring - it adds nothing in
function, costs more, and is a pain to work with inside instrument enclosures.
 Do not allow wire nuts on 4-20 mA or other analog signal wires - they get loose, they
pick up EMI/RFI, and are just no good. Field splices should only be made at terminal
strips in junction boxes!
 It's important to note any "foreign voltage" on the panel, since "foreign" wires may still
be hot after the panel is powered down and there isn't really a standard.